TMS320R2811 TMS320R2812
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Literature Number: SPRS257B June 2004 Revised Febrtuary 2005
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Revision History
REVISION HISTORY This data sheet revision history highlights technical changes made SPRS257A device-specific data sheet make SPRS257B revision.
PAGE ADDITIONS/CHANGES/DELETIONS Added temperature options Table Replaced Table Modified Table PARTID DEVICEID Added Absolute Maximum Ratings table Modified Note Figure Modfied second note Table Modified value Table 6-12 Modified location td(WAKE-STBY) Figure 6-12 Modified numbers field names Table 6-43
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Revision History
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Contents
Contents
Section Page Features Introduction Description Device Summary Assignments 2.3.1 Terminal Assignments Packages 2.3.2 Assignments Package 2.3.3 Assignments Package Signal Descriptions Functional Overview Memory Brief Descriptions 3.2.1 C28x 3.2.2 Memory (Harvard Architecture) 3.2.3 Peripheral 3.2.4 Real-Time JTAG Analysis 3.2.5 External Interface (XINTF) (2812 Only) 3.2.6 SARAMs 3.2.7 SARAMs 3.2.8 Boot 3.2.9 Security 3.2.10 Peripheral Interrupt Expansion (PIE) Block 3.2.11 External Interrupts (XINT1, XNMI) 3.2.12 Oscillator 3.2.13 Watchdog 3.2.14 Peripheral Clocking 3.2.15 Low-Power Modes 3.2.16 Peripheral Frames (PFn) 3.2.17 General-Purpose Input/Output (GPIO) Multiplexer 3.2.18 32-Bit CPU-Timers 3.2.19 Control Peripherals 3.2.20 Serial Port Peripherals Register Device Emulation Registers External Interface, XINTF (2812 Only) 3.5.1 Timing Registers 3.5.2 XREVISION Register Interrupts 3.6.1 External Interrupts System Control 3.7.1 Block 3.7.2 Loss Input Clock 3.7.3 PLL-Based Clock Module 3.7.4 External Reference Oscillator Clock Option 3.7.5 Watchdog Block 3.7.6 Low-Power Modes Block Peripherals 32-Bit CPU-Timers 0/1/2
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Contents
Event Manager Modules (EVA, EVB) 4.2.1 General-Purpose (GP) Timers 4.2.2 Full-Compare Units 4.2.3 Programmable Deadband Generator 4.2.4 Waveform Generation 4.2.5 Double Update Mode 4.2.6 Characteristics 4.2.7 Capture Unit 4.2.8 Quadrature-Encoder Pulse (QEP) Circuit 4.2.9 External Start-of-Conversion Enhanced Analog-to-Digital Converter (ADC) Module Enhanced Controller Area Network (eCAN) Module Multichannel Buffered Serial Port (McBSP) Module Serial Communications Interface (SCI) Module Serial Peripheral Interface (SPI) Module GPIO Development Support Device Development Support Tool Nomenclature Documentation Support Electrical Specifications Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Noted) Current Consumption Power-Supply Pins Over Recommended Operating Conditions During Low-Power Modes 150-MHz SYSCLKOUT (TMS320R281x) Current Consumption Graphs Reducing Current Consumption Power Sequencing Requirements Signal Transition Levels Timing Parameter Symbology 6.10 General Notes Timing Parameters 6.11 Test Load Circuit 6.12 Device Clock Table 6.13 Clock Requirements Characteristics 6.13.1 Input Clock Requirements 6.13.2 Output Clock Characteristics 6.14 Reset Timing 6.15 Low-Power Mode Wakeup Timing 6.16 Event Manager Interface 6.16.1 Timing 6.16.2 Interrupt Timing 6.17 General-Purpose Input/Output (GPIO) Output Timing 6.18 General-Purpose Input/Output (GPIO) Input Timing 6.19 Master Mode Timing 6.20 Slave Mode Timing 6.21 External Interface (XINTF) Timing 6.22 XINTF Signal Alignment XCLKOUT 6.23 External Interface Read Timing 6.24 External Interface Write Timing
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Contents
6.25 6.26 6.27 6.28 6.29
External Interface Ready-on-Read Timing With External Wait State External Interface Ready-on-Write Timing With External Wait State XHOLD XHOLDA XHOLD/XHOLDA Timing On-Chip Analog-to-Digital Converter 6.29.1 Absolute Maximum Ratings 6.29.2 Electrical Characteristics Over Recommended Operating Conditions 6.29.3 Current Consumption Different Configurations 25-MHz ADCCLK) 6.29.4 Power-Up Control Timing 6.29.5 Detailed Description 6.29.5.1 Reference Voltage 6.29.5.2 Analog Inputs 6.29.5.3 Converter 6.29.5.4 Conversion Modes 6.29.6 Sequential Sampling Mode (Single-Channel) (SMODE 6.29.7 Simultaneous Sampling Mode (Dual-Channel) (SMODE 6.29.8 Definitions Specifications Terminology 6.30 Multichannel Buffered Serial Port (McBSP) Timing 6.30.1 McBSP Transmit Receive Timing 6.30.2 McBSP Master Slave Timing Migration From F281x Devices Mechanical Data
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SPRS257B
Figures
List Figures
Figure Page 2-1. TMS320R2812 179-Ball MicroStar (Bottom View) 2-2. TMS320R2812 176-Pin LQFP (Top View) 2-3. TMS320R2811 128-Pin LQFP (Top View) 3-1. Functional Block Diagram 3-2. R2812 Memory 3-3. R2811 Memory 3-4. External Interface Block Diagram 3-5. Interrupt Sources 3-6. Multiplexing Interrupts Using Block 3-7. Clock Reset Domains 3-8. Block 3-9. Recommended Crystal/ Clock Connection 3-10. Watchdog Module 4-1. CPU-Timers 4-2. CPU-Timer Interrupts Signals Output Signal 4-3. Event Manager Functional Block Diagram 4-4. Block Diagram R281x Module 4-5. Connections With Internal Reference 4-6. Connections With External Reference 4-7. eCAN Block Diagram Interface Circuit 4-8. eCAN Memory 4-9. McBSP Module With FIFO 4-10. Serial Communications Interface (SCI) Module Block Diagram 4-11. Serial Peripheral Interface Module Block Diagram (Slave Mode) 4-12. GPIO/Peripheral MUXing 5-1. TMS320x28x Device Nomenclature 6-1. Typical Current Consumption Over Frequency 6-2. Typical Power Consumption Over Frequency 6-3. Output Levels 6-4. Input Levels 6-5. 3.3-V Test Load Circuit 6-6. Clock Timing 6-7. Power-on Reset Microcomputer Mode (XMP/MC 6-8. Power-on Reset Microprocessor Mode (XMP/MC 6-9. Warm Reset Microcomputer Mode 6-10. Effect Writing Into PLLCR Register 6-11. IDLE Entry Exit Timing 6-12. STANDBY Entry Exit Timing 6-13. HALT Wakeup Using XNMI 6-14. Output Timing
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Figures
6-15. 6-16. 6-17. 6-18. 6-19. 6-20. 6-21. 6-22. 6-23. 6-24. 6-25. 6-26. 6-27. 6-28. 6-29. 6-30. 6-31. 6-32. 6-33. 6-34. 6-35. 6-36. 6-37. 6-38. 6-39. 6-40. 6-41. 6-42. 6-43. 6-44.
TDIRx Timing EVASOC Timing EVBSOC Timing External Interrupt Timing General-Purpose Output Timing GPIO Input Qualifier Example Diagram QUALPRD General-Purpose Input Timing Master Mode External Timing (Clock Phase Master External Timing (Clock Phase Slave Mode External Timing (Clock Phase Slave Mode External Timing (Clock Phase Relationship Between XTIMCLK SYSCLKOUT Example Read Access Example Write Access Example Read With Synchronous XREADY Access Example Read With Asynchronous XREADY Access Write With Synchronous XREADY Access Write With Asynchronous XREADY Access External Interface Hold Waveform XHOLD/XHOLDA Timing Requirements (XCLKOUT XTIMCLK) Analog Input Impedance Model Power-Up Control Timing Sequential Sampling Mode (Single-Channel) Timing Simultaneous Sampling Mode Timing McBSP Receive Timing McBSP Transmit Timing McBSP Timing Master Slave: CLKSTP 10b, CLKXP McBSP Timing Master Slave: CLKSTP 11b, CLKXP McBSP Timing Master Slave: CLKSTP 10b, CLKXP McBSP Timing Master Slave: CLKSTP 11b, CLKXP
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Tables
List Tables
Table Page 2-1. Hardware Features 2-2. Signal Descriptions 3-1. Wait States 3-2. Boot Mode Selection 3-3. Peripheral Frame Registers 3-4. Peripheral Frame Register 3-5. Peripheral Frame Registers 3-6. Device Emulation Registers 3-7. XINTF Configuration Control Register Mappings 3-8. XREVISION Register Definitions 3-9. Peripheral Interrupts 3-10. Configuration Control Registers 3-11. External Interrupt Registers 3-12. PLL, Clocking, Watchdog, Low-Power Mode Registers 3-13. PLLCR Register Definitions 3-14. Possible Configuration Modes 3-15. R281x Low-Power Modes 4-1. CPU-Timers Configuration Control Registers 4-2. Module Signal Names 4-3. Registers 4-4. Registers 4-5. 3.3-V eCAN Transceivers R281x DSPs 4-6. Registers 4-7. McBSP Register Summary 4-8. SCI-A Registers 4-9. SCI-B Registers 4-10. Registers 4-11. GPIO Registers 4-12. GPIO Data Registers 6-1. Typical Current Consumption Various Peripherals MHz) 6-2. TMS320R281x Clock Table Nomenclature 6-3. Input Clock Frequency 6-4. XCLKIN Timing Requirements Bypassed Enabled 6-5. XCLKIN Timing Requirements Disabled 6-6. Possible Configuration Modes 6-7. XCLKOUT Switching Characteristics (PLL Bypassed Enabled) 6-8. Reset (XRS) Timing Requirements 6-9. IDLE Mode Timing Requirements 6-10. IDLE Mode Switching Characteristics 6-11. STANDBY Mode Timing Requirements 6-12. STANDBY Mode Switching Characteristics 6-13. HALT Mode Timing Requirements 6-14. HALT Mode Switching Characteristics 6-15. Switching Characteristics 6-16. Timer Capture Unit Timing Requirements 6-17. External Start-of-Conversion Switching Characteristics
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Tables
6-18. External Start-of-Conversion Switching Characteristics 6-19. Interrupt Switching Characteristics 6-20. Interrupt Timing Requirements 6-21. General-Purpose Output Switching Characteristics 6-22. General-Purpose Input Timing Requirements 6-23. Master Mode External Timing (Clock Phase 6-24. Master Mode External Timing (Clock Phase 6-25. Slave Mode External Timing (Clock Phase 6-26. Slave Mode External Timing (Clock Phase 6-27. Relationship Between Parameters Configured XTIMING Duration Pulse 6-28. XINTF Clock Configurations 6-29. External Memory Interface Read Switching Characteristics 6-30. External Memory Interface Read Timing Requirements 6-31. External Memory Interface Write Switching Characteristics 6-32. External Memory Interface Read Switching Characteristics (Ready-on-Read, Wait State) 6-33. External Memory Interface Read Timing Requirements (Ready-on-Read, Wait State) 6-34. Synchronous XREADY Timing Requirements (Ready-on-Read, Wait State) 6-35. Asynchronous XREADY Timing Requirements (Ready-on-Read, Wait State) 6-36. External Memory Interface Write Switching Characteristics (Ready-on-Write, Wait State) 6-37. Synchronous XREADY Timing Requirements (Ready-on-Write, Wait State) 6-38. Asynchronous XREADY Timing Requirements (Ready-on-Write, Wait State) 6-39. XHOLD/XHOLDA Timing Requirements (XCLKOUT XTIMCLK) 6-40. XHOLD/XHOLDA Timing Requirements (XCLKOUT XTIMCLK) 6-41. Specifications 6-42. Specifications 6-43. Power-Up Delays 6-44. Sequential Sampling Mode Timing 6-45. Simultaneous Sampling Mode Timing 6-46. McBSP Timing Requirements 6-47. McBSP Switching Characteristics 6-48. McBSP Master Slave Timing Requirements (CLKSTP 10b, CLKXP 6-49. McBSP Master Slave Switching Characteristics (CLKSTP 10b, CLKXP 6-50. McBSP Master Slave Timing Requirements (CLKSTP 11b, CLKXP 6-51. McBSP Master Slave Switching Characteristics (CLKSTP 11b, CLKXP 6-52. McBSP Master Slave Timing Requirements (CLKSTP 10b, CLKXP 6-53. McBSP Master Slave Switching Characteristics (CLKSTP 10b, CLKXP 6-54. McBSP Master Slave Timing Requirements (CLKSTP 11b, CLKXP 6-55. McBSP Master Slave Switching Characteristics (CLKSTP 11b, CLKXP 6-56. Feature Comparison Between F281x R281x Devices 7-1. Thermal Resistance Characteristics 179-GHH 7-2. Thermal Resistance Characteristics 179-ZHH 7-3. Thermal Resistance Characteristics 176-PGF 7-4. Thermal Resistance Characteristics 128-PBK
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Tables
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Features
Features High-Performance Static CMOS Technology
(6.67-ns Cycle Time) Low-Power (1.8-V Core @135 MHz, 1.9-V Core @150 MHz, 3.3-V I/O) Design JTAG Boundary Scan Support High-Performance 32-Bit (TMS320C28x) Operations Dual Harvard Architecture Atomic Operations Fast Interrupt Response Processing Unified Memory Programming Model Linear Program/Data Address Reach Code-Efficient C/C++ Assembly) Code Compatible F2810, F2811, F2812 devices TMS320F24x/LF240x Processor Source Code Compatible On-Chip Memory Total Single-Access (SARAM) Blocks Each SARAM Blocks SARAM Block SARAM Blocks Each SARAM SPI, SCI, GPIO Boot Loader Modes Support Loading Code From Off-chip Sources On-chip RAM. Boot Mode Supports Loading From External Serial EEPROM. Boot With Software Boot Modes Standard Math Tables External Interface (2812) Total Memory Programmable Wait States Programmable Read/Write Strobe Timing Three Individual Chip Selects Clock System Control Dynamic Ratio Changes Supported On-Chip Oscillator Watchdog Timer Module
Three External Interrupts Peripheral Interrupt Expansion (PIE) Block
That Supports Peripheral Interrupts Three 32-Bit CPU-Timers Motor Control Peripherals Event Managers (EVA, EVB) Compatible 240xA Devices Serial Port Peripherals Serial Peripheral Interface (SPI) Serial Communications Interfaces (SCIs), Standard UART Enhanced Controller Area Network (eCAN) Multichannel Buffered Serial Port (McBSP) 12-Bit ADC, Channels Channel Input Multiplexer Sample-and-Hold Single/Simultaneous Conversions Fast Conversion Rate: ns/12.5 MSPS General Purpose (GPIO) Pins Advanced Emulation Features Analysis Breakpoint Functions Real-Time Debug Hardware Development Tools Include ANSI C/C++ Compiler/Assembler/Linker Code Composer Studio DSP/BIOS JTAG Scan Controllers Low-Power Modes Power Savings IDLE, STANDBY, HALT Modes Supported Disable Individual Peripheral Clocks Package Options 179-Ball MicroStar With External Memory Interface (GHH), (ZHH) (2812) 176-Pin Low-Profile Quad Flatpack (LQFP) With External Memory Interface (PGF) (2812) 128-Pin LQFP Without External Memory Interface (PBK) (2811) Temperature Options: -40°C 85°C (GHH, ZHH, PGF, PBK) S/Q: -40°C 125°C (GHH, ZHH, PGF, PBK)
TMS320C24x, Code Composer Studio, DSP/BIOS, MicroStar trademarks Texas Instruments. IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port
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Introduction
Introduction
This section provides summary each device's features, lists assignments, describes function each pin. This document also provides detailed descriptions peripherals, electrical specifications, parameter measurement information, mechanical data about available packaging.
Description
TMS320R2811 TMS320R2812 devices, members TMS320C28x generation, highly integrated, high-performance solutions demanding control applications. functional blocks memory maps described Section Functional Overview. Throughout this document, TMS320R2811 TMS320R2812 abbreviated R2811 R2812, respectively.
TMS320C28x trademark Texas Instruments. trademarks property their respective owners.
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Introduction
Device Summary
Table provides summary each device's features. Table 2-1. Hardware Features
FEATURE R2811 6.67 EVA, SCIA, SCIB R2812 6.67 EVA, SCIA, SCIB 179-ball 179-ball 176-pin
Instruction Cycle MHz) Single-Access (SARAM) (16-bit word) Boot External Memory Interface Event Managers (EVA EVB) General-Purpose (GP) Timers Compare (CMP)/PWM Capture (CAP)/QEP Channels
Watchdog Timer 12-Bit SCIA, SCIB McBSP Digital Pins (Shared) External Interrupts Supply Voltage Packaging -40°C 85°C Temperature Options S/Q: -40°C 125°C Channels 32-Bit Timers
1.8-V Core, (135 MHz) 1.9-V Core (150 MHz), 3.3-V 128-pin
Product Status Section 5.1, Device Development Support Nomenclature descriptions product development stages.
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Introduction
Assignments
Figure illustrates ball locations 179-ball ball grid array (BGA) packages. Figure shows assignments 176-pin low-profile quad flatpack (LQFP) Figure shows assignments 128-pin LQFP. Table describes function(s) each pin.
2.3.1
Terminal Assignments Packages
Table description each terminal's function(s).
XZCS0AND1 PWM8
PWM10
CAP6 _QEPI2
XD[8]
T3CTRIP T4CTRIP/ _PDPINTB EVBSOC
XZCS2
SCITXDB
SPISOMIA
PWM7
PWM9
XR/W
T4PWM _T4CMP
C4TRIP
TEST2
VDDIO
XD[11]
XA[2]
CANTXA CANRXA
VDDIO
SPISIMOA
XA[1]
PWM12
CAP4 _QEP3
CAP5 _QEP4
TEST1
XD[9]
XA[3]
PWM1
SCIRXDB
PWM2
XD[6]
PWM11
XD[7]
C5TRIP
VDDIO
TDIRB
XD[10]
VDDIO
PWM3
PWM4
XD[12]
SPICLKA
XD[4]
SPISTEA
T3PWM _T3CMP
C6TRIP
TCLKINB
XCLKIN
XHOLDA
PWM5
PWM6
MCLKXA
MFSRA
XD[3]
VDDIO
XD[5]
XD[13]
T1PWM _T1CMP
XA[4]
T2PWM _T2CMP
MCLKRA
XD[1]
MFSXA
XD[2]
CAP1 _QEP1
CAP2 _QEP2
CAP3 _QEPI1
XA[5]
T1CTRIP _PDPINTA
MDXA
MDRA
XD[0]
XA[0]
T2CTRIP/ EVASOC
VDDIO
XA[6]
XMP/MC
ADCRESEXT
VSSA1
VDDA1
ADCINB7
C3TRIP XCLKOUT
XA[7]
TCLKINA
TDIRA
AVDDAVSSADCREFP ADCREFM ADCINA5 ADCXHOLD REFBG REFBG BGREFIN
XNMI _XINT13
VDDIO
XA[13]
C2TRIP
XA[8]
C1TRIP
ADCINB6 ADCINB5 ADCINB4 ADCINA1 ADCINA6
XA[18]
XINT2 _ADCSOC
XINT1 _XBIO
EMU0
XA[9]
ADCINB3 ADCINB0 ADCINB1 ADCINA2
VSSA2
VSS1
SCITXDA
EMU1
XA[12]
XA[10]
ADCINB2 VDDAIO
ADCLO ADCINA3 ADCINA7 XREADY
XA[17]
XA[15]
XD[14]
TRST
XZCS6AND7
VSSAIO ADCINA0 ADCINA4
VDDA2
VDD1
SCIRXDA
XA[16]
XD[15]
XA[14]
_XPLLDIS
TESTSEL
XA[11]
Figure 2-1. TMS320R2812 179-Ball MicroStar (Bottom View)
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Introduction
2.3.2
Assignments Package
TMS320R2812 176-pin low-profile quad flatpack (LQFP) assignments shown Figure 2-2. Table description each pin's function(s).
XA[11] XA[10] XA[9] C3TRIP C2TRIP C1TRIP XA[8] XCLKOUT XA[7] TCLKINA TDIRA T2CTRIP EVASOC DDIO XA[6] T1CTRIP_PDPINTA CAP3_QEPI1 XA[5] CAP2_QEP2 CAP1_QEP1 T2PWM_T2CMP XA[4] T1PWM_T1CMP PWM6 PWM5 XD[13] XD[12] PWM4 PWM3 PWM2 PWM1 SCIRXDB SCITXDB CANRXA XZCS2 CANTXA XA[3] T4CTRIP/EVBSOC XHOLDA VDDIO XA[2] T3CTRIP_PDPINTB X1/XCLKIN XD[11] XD[10] TCLKINB TDIRB VDDIO XD[9] TEST1 TEST2 XD[8] VDDIO C6TRIP C5TRIP C4TRIP CAP6_QEPI2 CAP5_QEP4 CAP4_QEP3 T4PWM_T4CMP XD[7] T3PWM_T3CMP XR/W PWM12 PWM11 PWM10 PWM9 PWM8 PWM7
XZCS6AND7 TESTSEL TRST EMU0 XA[12] XD[14] XF_XPLLDIS XA[13] XA[14] VDDIO EMU1 XD[15] XA[15] XINT1_XBIO XNMI_XINT13 XINT2_ADCSOC XA[16] SCITXDA XA[17] SCIRXDA XA[18] XHOLD XREADY VDD1 VSS1 ADCBGREFIN VSSA2 VDDA2 ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2 ADCINA1 ADCINA0 ADCLO VSSAIO
DDAIO ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 ADCREFM ADCREFP AVSSREFBG AVDDREFBG DDA1 SSA1 ADCRESEXT XMP/ XA[0] MDRA XD[0] MDXA XD[1] MCLKRA MFSXA XD[2] MCLKXA MFSRA XD[3] DDIO XD[4] SPICLKA SPISTEA XD[5] XD[6] SPISIMOA SPISOMIA XA[1] XZCS0AND1
Figure 2-2. TMS320R2812 176-Pin LQFP (Top View)
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Introduction
2.3.3
Assignments Package
TMS320R2811 128-pin low-profile quad flatpack (LQFP) assignments shown Figure 2-3. Table description each pin's function(s).
C3TRIP C2TRIP C1TRIP XCLKOUT TCLKINA TDIRA T2CTRIP/ EVASOC VDDIO T1CTRIP_PDPINTA CAP3_QEPI1 CAP2_QEP2 CAP1_QEP1 T2PWM_T2CMP T1PWM_T1CMP PWM6 PWM5 PWM4 PWM3 PWM2 PWM1 SCIRXDB SCITXDB CANRXA
TESTSEL TRST EMU0 XF_XPLLDIS VDDIO EMU1 XINT1_XBIO XNMI_XINT13 XINT2_ADCSOC SCITXDA SCIRXDA VDD1 VSS1 ADCBGREFIN VSSA2 VDDA2 ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2 ADCINA1 ADCINA0 ADCLO VSSAIO
CANTXA T4CTRIP/EVBSOC T3CTRIP_PDPINTB X1/XCLKIN TCLKINB TDIRB VDDIO TEST1 TEST2 VDDIO C6TRIP C5TRIP C4TRIP CAP6_QEPI2 CAP5_QEP4 CAP4_QEP3 T4PWM_T4CMP T3PWM_T3CMP PWM12 PWM11 PWM10 PWM9 PWM8 PWM7
VDDAIO ADCINB0 ADCINB1 ADCINB2 ADCINB3 ADCINB4 ADCINB5 ADCINB6 ADCINB7 ADCREFM ADCREFP AVSSREFBG AVDDREFBG VDDA1 VSSA1 ADCRESEXT MDRA MDXA MCLKRA MFSXA MCLKXA MFSRA VDDIO SPICLKA SPISTEA SPISIMOA SPISOMIA
Figure 2-3. TMS320R2811 128-Pin LQFP (Top View)
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Introduction
Signal Descriptions
Table specifies signals R281x devices. digital inputs TTL-compatible. outputs with CMOS levels. Inputs tolerant. Table 2-2. Signal Descriptions
NAME 179-PIN 176-PIN 128-PIN I/O/Z DESCRIPTION
XINTF SIGNALS (2812 ONLY) XA[18] XA[17] XA[16] XA[15] XA[14] XA[13] XA[12] XA[11] XA[10] XA[9] XA[8] XA[7] XA[6] XA[5] XA[4] XA[3] XA[2] XA[1] XA[0] XD[15] XD[14] XD[13] XD[12] XD[11] XD[10] XD[9] XD[8] XD[7] XD[6] XD[5] XD[4] XD[3] XD[2] I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z 16-bit XINTF Data 19-bit XINTF Address
XD[1] I/O/Z Typical drive strength output buffer pins except TDO, XCLKOUT, XINTF, EMU0, EMU1 pins, which Input, Output, High impedance internal pullup; internal pulldown. Pullup/pulldown strength given Section 6.3.
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Introduction
Table 2-2. Signal Descriptions (Continued)
NAME 179-PIN 176-PIN 128-PIN I/O/Z DESCRIPTION
XINTF SIGNALS (2812 ONLY) (CONTINUED) XD[0] I/O/Z 16-bit XINTF Data Microprocessor/Microcomputer Mode Select. Switches between microprocessor microcomputer mode. When high, Zone enabled external interface. When low, Zone disabled from external interface, on-chip boot accessed instead. This signal latched into XINTCNF2 register reset user modify this software. state XMP/MC ignored after reset. External Hold Request. XHOLD, when active (low), requests XINTF release external place buses strobes into high-impedance state. XINTF will release when current access complete there pending accesses XINTF. External Hold Acknowledge. XHOLDA driven active (low) when XINTF granted XHOLD request. XINTF buses strobe signals will high-impedance state. XHOLDA released when XHOLD signal released. External devices should only drive external when XHOLDA active (low). XINTF Zone Zone Chip Select. XZCS0AND1 active (low) when access XINTF Zone Zone performed. XINTF Zone Chip Select. XZCS2 active (low) when access XINTF Zone performed. XINTF Zone Zone Chip Select. XZCS6AND7 active (low) when access XINTF Zone Zone performed. Write Enable. Active-low write strobe. write strobe waveform specified, zone basis, Lead, Active, Trail periods XTIMINGx registers. Read Enable. Active-low read strobe. read strobe waveform specified, zone basis, Lead, Active, Trail periods XTIMINGx registers. NOTE: signals mutually exclusive. Read Write Strobe. Normally held high. When low, XR/W indicates write cycle active; when high, XR/W indicates read cycle active. Ready Signal. Indicates peripheral ready complete access when asserted XREADY configured synchronous asynchronous input. timing diagrams more details.
XMP/MC
XHOLD
XHOLDA
XZCS0AND1
XZCS2
XZCS6AND7
XR/W
XREADY
Typical drive strength output buffer pins except TDO, XCLKOUT, XINTF, EMU0, EMU1 pins, which Input, Output, High impedance internal pullup; internal pulldown. Pullup/pulldown strength given Section 6.3.
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Table 2-2. Signal Descriptions (Continued)
NAME 179-PIN 176-PIN 128-PIN I/O/Z DESCRIPTION
JTAG MISCELLANEOUS SIGNALS Oscillator Input input internal oscillator. This also used feed external clock. operated with external clock source, provided that proper voltage levels driven X1/XCLKIN pin. should noted that X1/XCLKIN referenced 1.8-V 1.9-V) core digital power supply (VDD), rather than 3.3-V supply (VDDIO). clamping diode used clamp buffered clock signal ensure that logic-high level does exceed (1.8 1.8-V oscillator used. Oscillator Output Output clock derived from SYSCLKOUT used external wait-state generation general-purpose clock source. XCLKOUT either same frequency, frequency, frequency SYSCLKOUT. reset, XCLKOUT SYSCLKOUT/4. XCLKOUT signal turned setting (CLKOFF) XINTCNF2 register Unlike other GPIO pins, XCLKOUT placed high impedance state during reset. Test Pin. Reserved Must connected ground. Device Reset (in) Watchdog Reset (out). Device reset. causes device terminate execution. will point address contained location 0x3FFFC0. When brought high level, execution begins location pointed This driven when watchdog reset occurs. During watchdog reset, will driven watchdog reset duration XCLKIN cycles. output buffer this open-drain with internal pullup (100 typical). recommended that this driven open-drain device. TEST1 TEST2 This connect (NC)" (i.e., this connected circuitry internal device). This connect (NC)" (i.e., this connected circuitry internal device).
X1/XCLKIN
XCLKOUT
TESTSEL
Typical drive strength output buffer pins except TDO, XCLKOUT, XINTF, EMU0, EMU1 pins, which Input, Output, High impedance internal pullup; internal pulldown. Pullup/pulldown strength given Section 6.3.
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Table 2-2. Signal Descriptions (Continued)
NAME 179-PIN 176-PIN 128-PIN I/O/Z DESCRIPTION
JTAG JTAG test reset with internal pulldown. TRST, when driven high, gives scan system control operations device. this signal connected driven low, device operates functional mode, test reset signals ignored. NOTE: pullup resistors TRST; internal pulldown device. low-noise environment, TRST left floating. high-noise environment, additional pulldown resistor needed. value this resistor should based drive strength debugger pods applicable design. 2.2-k resistor generally offers adequate protection. Since this application-specific, recommended that each target board validated proper operation debugger application. JTAG test clock with internal pullup JTAG test-mode select (TMS) with internal pullup. This serial control input clocked into controller rising edge TCK. JTAG test data input (TDI) with internal pullup. clocked into selected register (instruction data) rising edge TCK. JTAG scan out, test data output (TDO). contents selected register (instruction data) shifted falling edge TCK. Emulator When TRST driven high, this used interrupt from emulator system defined input/output through JTAG scan. Emulator When TRST driven high, this used interrupt from emulator system defined input/output through JTAG scan.
TRST
EMU0
I/O/Z
EMU1
I/O/Z
ANALOG INPUT SIGNALS ADCINA7 ADCINA6 ADCINA5 ADCINA4 ADCINA3 ADCINA2 ADCINA1 8-Channel analog inputs Sample-and-Hold pins should driven before VDDA1, VDDA2, VDDAIO pins have been fully powered
ADCINA0 Typical drive strength output buffer pins except TDO, XCLKOUT, XINTF, EMU0, EMU1 pins, which Input, Output, High impedance internal pullup; internal pulldown. Pullup/pulldown strength given Section 6.3.
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Table 2-2. Signal Descriptions (Continued)
NAME 179-PIN 176-PIN 128-PIN I/O/Z DESCRIPTION
ANALOG INPUT SIGNALS (CONTINUED) ADCINB7 ADCINB6 ADCINB5 ADCINB4 ADCINB3 ADCINB2 ADCINB1 ADCINB0 Voltage Reference Output Requires ceramic bypass capacitor analog ground. (Can accept external reference input software enabled this mode. 1-10 capacitor used external reference mode.) Voltage Reference Output Requires ceramic bypass capacitor analog ground. (Can accept external reference input software enabled this mode. 1-10 capacitor used external reference mode.) External Current Bias Resistor (24.9 ±5%) Test Pin. Reserved Must left unconnected. Analog Analog Power (3.3-V) Common Side Analog Input. Connect analog ground. 8-Channel Analog Inputs Sample-and-Hold pins should driven before VDDA1, VDDA2, VDDAIO pins have been fully powered
ADCREFP
ADCREFM
ADCRESEXT ADCBGREFIN AVSSREFBG AVDDREFBG ADCLO
ANALOG INPUT SIGNALS (CONTINUED) VSSA1 VSSA2 VDDA1 VDDA2 VSS1 VDD1 Analog Analog Analog 3.3-V Supply Analog 3.3-V Supply Digital Digital 1.8-V 1.9-V) Supply
VDDAIO 3.3-V Analog Power VSSAIO Analog Ground Typical drive strength output buffer pins except TDO, XCLKOUT, XINTF, EMU0, EMU1 pins, which Input, Output, High impedance internal pullup; internal pulldown. Pullup/pulldown strength given Section 6.3.
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Introduction
Table 2-2. Signal Descriptions (Continued)
NAME 179-PIN 176-PIN 128-PIN I/O/Z DESCRIPTION
POWER SIGNALS VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO 3.3-V Digital Power Pins Core Digital Ground Pins 1.8-V 1.9-V Core Digital Power Pins. Section 6.2, Recommended Operating Conditions, voltage requirements.
VDDIO Typical drive strength output buffer pins except TDO, XCLKOUT, XINTF, EMU0, EMU1 pins, which Input, Output, High impedance internal pullup; internal pulldown. Pullup/pulldown strength given Section 6.3.
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Table 2-2. Signal Descriptions (Continued)
NAME 179-PIN 176-PIN 128-PIN I/O/Z DESCRIPTION
GPIO SIGNALS GPIOA0 PWM1 GPIOA1 PWM2 GPIOA2 PWM3 GPIOA3 PWM4 GPIOA4/PWM5 GPIOA5 PWM6 GPIOA6 T1PWM_T1CMP GPIOA7 T2PWM_T2CMP GPIOA8 CAP1_QEP1 GPIOA9 CAP2_QEP2 GPIOA10/ CAP3_QEPI1 GPIOA11 TDIRA GPIOA12 TCLKINA GPIOA13 C1TRIP GPIOA14 C2TRIP GPIOA15 C3TRIP I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z GPIO Output GPIO Output GPIO Output GPIO Output GPIO Output GPIO Output GPIO Timer Output GPIO Timer Output GPIO Capture Input GPIO Capture Input GPIO Capture Input GPIO Timer Direction GPIO Timer Clock Input GPIO Compare Output Trip GPIO Compare Output Trip GPIO Compare Output Trip
GPIOB SIGNALS GPIOB0 PWM7 GPIOB1 PWM8 GPIOB2 PWM9 GPIOB3 PWM10 I/O/Z I/O/Z I/O/Z I/O/Z GPIO Output GPIO Output GPIO Output GPIO Output
Typical drive strength output buffer pins except TDO, XCLKOUT, XINTF, EMU0, EMU1 pins, which Input, Output, High impedance internal pullup; internal pulldown. Pullup/pulldown strength given Section 6.3.
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Introduction
Table 2-2. Signal Descriptions (Continued)
NAME 179-PIN 176-PIN 128-PIN I/O/Z DESCRIPTION
GPIOB PWM11 GPIOB5 PWM12 GPIOB6/ T3PWM_T3CMP GPIOB7/ T4PWM_T4CMP GPIOB8/CAP4_QEP3 GPIOB9/CAP5_QEP4 GPIOB10/CAP6_QEPI2 GPIOB11/TDIRB GPIOB12/TCLKINB GPIOB13/C4TRIP GPIOB14/C5TRIP GPIOB15/C6TRIP
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
GPIO Output GPIO Output GPIO Timer Output GPIO Timer Output GPIO Capture Input GPIO Capture Input GPIO Capture Input GPIO Timer Direction GPIO Timer Clock Input GPIO Compare Output Trip GPIO Compare Output Trip GPIO Compare Output Trip
GPIOD SIGNALS GPIOD0/ T1CTRIP_PDPINTA GPIOD1/ T2CTRIP/EVASOC I/O/Z I/O/Z Timer Compare Output Trip Timer Compare Output Start-of-Conversion EV-A Trip External
GPIOD SIGNALS GPIOD5/ T3CTRIP_PDPINTB GPIOD6/ T4CTRIP/EVBSOC I/O/Z I/O/Z Timer Compare Output Trip Timer Compare Output Start-of-Conversion EV-B Trip External
GPIOE INTERRUPT SIGNALS GPIOE0/XINT1_XBIO GPIOE1/ XINT2_ADCSOC GPIOE2 XNMI_XINT13 I/O/Z I/O/Z I/O/Z GPIO XINT1 XBIO input GPIO XINT2 start conversion GPIO XNMI XINT13
GPIOF SIGNALS GPIOF0 SPISIMOA GPIOF1 SPISOMIA GPIOF2 SPICLKA (I/O) GPIOF3 SPISTEA (I/O) I/O/Z I/O/Z I/O/Z I/O/Z GPIO slave master GPIO slave out, master GPIO clock GPIO slave transmit enable
Typical drive strength output buffer pins except TDO, XCLKOUT, XINTF, EMU0, EMU1 pins, which Input, Output, High impedance internal pullup; internal pulldown. Pullup/pulldown strength given Section 6.3.
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Table 2-2. Signal Descriptions (Continued)
NAME 179-PIN 176-PIN 128-PIN I/O/Z DESCRIPTION
GPIOF SCI-A SIGNALS GPIOF4 SCITXDA GPIOF5 SCIRXDA I/O/Z I/O/Z GPIO asynchronous serial port data GPIO asynchronous serial port data
GPIOF SIGNALS GPIOF6 CANTXA GPIOF7 CANRXA I/O/Z I/O/Z GPIO eCAN transmit data GPIO eCAN receive data
GPIOF McBSP SIGNALS GPIOF8 MCLKXA (I/O) GPIOF9 MCLKRA (I/O) GPIOF10 MFSXA (I/O) GPIOF11 MFSRA (I/O) GPIOF12 MDXA GPIOF13 MDRA I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z GPIO transmit clock GPIO receive clock GPIO transmit frame synch GPIO receive frame synch GPIO transmitted serial data GPIO received serial data
GPIOF OUTPUT SIGNAL This three functions: GPIOF14 XF_XPLLDIS I/O/Z General-purpose output pin. XPLLDIS This will sampled during reset check needs disabled. will disabled this sensed low. HALT STANDBY modes cannot used when disabled. GPIO GPIO function
GPIOG SCI-B SIGNALS GPIOG4/SCITXDB GPIOG5/SCIRXDB I/O/Z I/O/Z
GPIO asynchronous serial port transmit data GPIO asynchronous serial port receive data
Typical drive strength output buffer pins except TDO, XCLKOUT, XINTF, EMU0, EMU1 pins, which Input, Output, High impedance internal pullup; internal pulldown. Pullup/pulldown strength given Section 6.3.
NOTE: Other than power supply pins, should driven before 3.3-V rail reached recommended operating conditions. However, acceptable ramp along with 3.3-V supply.
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Functional Overview
Memory TINT0 CPU-Timer CPU-Timer CPU-Timer TINT2 interrupts) INT14 Control TINT1 INT[12:1] External Interface (XINTF) Address(19) Data(16) XINT13 XNMI GPIO Pins eCAN SCIA/SCIB McBSP FIFO FIFO FIFO C28x SARAM SARAM External Interrupt Control (XINT1/2/13, XNMI) INT13 SARAM SARAM Real-Time JTAG
EVA/EVB
SARAM SARAM
Channels
12-Bit
X1/XCLKIN XF_XPLLDIS
System Control (Oscillator Peripheral Clocking Low-Power Modes WatchDog)
CLKIN SARAM
Memory
Boot
Peripheral
possible interrupts used devices. XINTF available R2812 devices only.
Figure 3-1. Functional Block Diagram
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Memory
Block Start Address On-Chip Memory External Memory XINTF
0x00 0000
0x00 0040 0x00 0400 (24x/240x Equivalent Data Space) 0x00 0800 0x00 0D00
0x00 0E00 0x00 2000 0x00 6000 0x00 7000 0x00 8000 0x00 9000 0x00 A000 0x00 A400 0x00 A800
0x3F7FF8 High (24x/240x Equivalent Program Space) 0x3F 8000 0x3F A000
0x3F F000
0x3F FFC0
LEGEND: Only these vector maps-M0 vector, vector, BROM vector, XINTF vector-should enabled time. NOTES: Memory blocks scale. Reserved locations reserved future expansion. Application should access these areas. Boot Zone memory maps active either on-chip XINTF zone depending MP/MC, both. Peripheral Frame Peripheral Frame Peripheral Frame memory maps restricted data memory only. User program cannot access these memory maps program space. "Protected" means order Write followed Read operations preserved rather than pipeline order. Certain memory ranges EALLOW protected against spurious writes after configuration. Zones Zones share same chip select; hence, these memory blocks have mirrored locations. passwords ones.
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Vector (Enabled VMAP SARAM SARAM Peripheral Frame Vector (256 (Enabled VMAP ENPIE Reserved Reserved Reserved Reserved XINTF Zone XZCS0AND1) XINTF Zone XZCS0AND1) (Protected) Peripheral Frame Protected) Peripheral Frame Protected) Reserved Reserved SARAM SARAM SARAM SARAM XINTF Zone (0.5M XZCS2) XINTF Zone (0.5M XZCS6AND7) Reserved Reserved 128-bit Password (see Note SARAM Reserved Boot (Enabled MP/MC XINTF Zone (16K XZCS6AND7) (Enabled MP/MC BROM Vector (Enabled VMAP MP/MC ENPIE XINTF Vector (Enabled VMAP MP/MC ENPIE
Data Space
Prog Space
Data Space
Prog Space
0x00 2000 0x00 4000
0x08 0000 0x10 0000 0x18 0000
0x3F C000
Figure 3-2. R2812 Memory (See Notes through
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Block Start Address On-Chip Memory
Data Space 0x00 0000
Prog Space
Vector (Enabled VMAP SARAM
0x00 0040 0x00 0400 (24x/240x Equivalent Data Space) 0x00 0800 0x00 0D00
0x00 0E00 0x00 2000 0x00 6000 0x00 7000 0x00 8000 0x00 9000 0x00 A000 0x00 A400 0x00 A800
0x3F 7FF8 0x3F 8000 High (24x/240x Equivalent Program Space) 0x3F A000
0x3F F000
0x3F FFC0
LEGEND:
Only these vector maps-M0 vector, vector, BROM vector, XINTF vector-should enabled time. NOTES: Memory blocks scale. Reserved locations reserved future expansion. Application should access these areas. Peripheral Frame Peripheral Frame Peripheral Frame memory maps restricted data memory only. User program cannot access these memory maps program space. "Protected" means order Write followed Read operations preserved rather than pipeline order. Certain memory ranges EALLOW protected against spurious writes after configuration. passwords ones.
Figure 3-3. R2811 Memory (See Notes through
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Peripheral Frame Vector (256 (Enabled VMAP ENPIE Reserved Reserved Reserved Peripheral Frame Protected) Reserved Peripheral Frame Protected) SARAM 16,) SARAM SARAM
SARAM
Reserved 128-bit Password (see Note SARAM Reserved Boot (Enabled MP/MC BROM Vector (Enabled VMAP MP/MC ENPIE
SARAM
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Functional Overview
memory-address range maps into data space 240x. "High 64K" memory address range maps into program space 24x/240x. 24x/240x-compatible code will only execute from "High 64K" memory area. Hence, SARAM block used 24x/240x-compatible code MP/MC mode low) 2812, code executed from XINTF Zone MP/MC mode high). XINTF consists five independent zones. zone chip select remaining four zones share chip selects. Each zone programmed with timing (wait states) either sample ignore external ready signal. This makes interfacing external peripherals easy glueless. NOTE: chip selects XINTF Zone Zone merged together into single chip select (XZCS0AND1); chip selects XINTF Zone Zone merged together into single chip select (XZCS6AND7). Section 3.5, "External Interface, XINTF (2812 only)", details. Peripheral Frame Peripheral Frame XINTF Zone grouped together enable these blocks "write/read peripheral block protected". "protected" mode ensures that accesses these blocks happen written. Because C28x pipeline, write immediately followed read, different memory locations, will appear reverse order memory CPU. This cause problems certain peripheral applications where user expected write occur first written). C28x supports block protection mode where region memory protected make sure that operations occur written (the penalty extra cycles added align operations). This mode programmable default, will protect selected zones. 2812, reset, XINTF Zone accessed XMP/MC pulled high. This signal selects microprocessor microcomputer mode operation. microprocessor mode, Zone mapped high memory such that vector table fetched externally. Boot disabled this mode. microcomputer mode, Zone disabled such that vectors fetched from Boot ROM. This allows user either boot from on-chip memory from off-chip memory. state XMP/MC signal reset stored MP/MC mode XINTCNF2 register. user change this mode software hence control mapping Boot XINTF Zone other memory blocks affected XMP/MC. space supported 2812 XINTF. wait states various spaces memory area listed Table 3-1. Table 3-1. Wait States
AREA SARAMs Peripheral Frame Peripheral Frame Peripheral Frame SARAMs SARAM Boot-ROM XINTF WAIT-STATES 0-wait 0-wait 0-wait (writes) 2-wait (reads) 0-wait (writes) 2-wait (reads) 0-wait 0-wait 1-wait Programmable, 1-wait minimum Fixed Fixed Programmed XINTF registers. Cycles extended external memory peripheral. 0-wait operation possible. Fixed Fixed Fixed Fixed COMMENTS
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3.2.1
Brief Descriptions C28x
C28x generation newest member TMS320C2000 platform. C28x source code compatible 24x/240x devices, hence existing 240x users leverage their significant software investment. Additionally, C28x very efficient C/C++ engine, hence enabling users develop only their system control software high-level language, also enables math algorithms developed using C/C++. C28x efficient math tasks system control tasks that typically handled microcontroller devices. This efficiency removes need second processor many systems. 32-bit capabilities C28x 64-bit processing capabilities, enable C28x efficiently handle higher numerical resolution problems that would otherwise demand more expensive floating-point processor solution. this fast interrupt response with automatic context save critical registers, resulting device that capable servicing many asynchronous events with minimal latency. C28x 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables C28x execute high speeds without resorting expensive high-speed memories. Special branch-look-ahead hardware minimizes latency conditional discontinuities. Special store conditional operations further improve performance.
3.2.2
Memory (Harvard Architecture)
with many type devices, multiple busses used move data between memories peripherals CPU. R28x memory architecture contains program read bus, data read data write bus. program read consists address lines data lines. data read write busses consist address lines data lines each. 32-bit-wide data busses enable single cycle 32-bit operations. multiple-bus architecture, commonly termed "Harvard Bus", enables R28x fetch instruction, read data value, write data value single cycle. peripherals memories attached memory prioritize memory accesses. Generally, priority memory accesses summarized follows: Highest: Data Writes (Simultaneous data program writes cannot occur memory bus.) Program Writes (Simultaneous data program writes cannot occur memory bus.) Data Reads Program Reads (Simultaneous program reads fetches cannot occur memory bus.) Lowest: Fetches (Simultaneous program reads fetches cannot occur memory bus.)
3.2.3
Peripheral
enable migration peripherals between various Texas Instruments (TI) family devices, R281x adopts peripheral standard peripheral interconnect. peripheral bridge multiplexes various busses that make processor "Memory Bus" into single consisting address lines data lines associated control signals. versions peripheral supported R281x. version only supports 16-bit accesses (called peripheral frame this retains compatibility with C240x-compatible peripherals. other version supports both 32-bit accesses (called peripheral frame
C28x TMS320C2000 trademarks Texas Instruments.
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3.2.4
Real-Time JTAG Analysis
R281x implements standard IEEE 1149.1 JTAG interface. Additionally, R281x supports real-time mode operation whereby contents memory, peripheral register locations modified while processor running executing code servicing interrupts. user also single step through non-time critical code while enabling time-critical interrupts serviced without interference. R281x implements real-time mode hardware within CPU. This unique feature R281x, software monitor required. Additionally, special analysis hardware provided which allows user hardware breakpoint data/address watch-points generate various user selectable break events when match occurs.
3.2.5
External Interface (XINTF) (2812 Only)
This asynchronous interface consists address lines, data lines, three chip-select lines. chip-select lines mapped five external zones, Zones Zones share single chip-select; Zones also share single chip-select. Each five zones programmed with different number wait states, strobe signal setup hold timing each zone programmed extending wait states externally not. programmable wait-state, chip-select programmable strobe timing enables glueless interface external memories peripherals.
3.2.6
SARAMs
C28x devices contain these blocks single access memory, each size. stack pointer points beginning block reset. block overlaps 240x device blocks hence mapping data variables 240x devices remain same physical address C28x devices. blocks, like other memory blocks C28x devices, mapped both program data space. Hence, user execute code data variables. partitioning performed within linker. C28x device presents unified memory programmer. This makes easier programming high-level languages.
3.2.7
SARAMs
R281x contains additional single-access (SARAM), divided into blocks +1K+ 8K). Each block independently accessed, minimizing pipeline stalls. Each block mapped both program data space.
3.2.8
Boot
Boot factory-programmed with boot-loading software. Boot program executes after device reset checks several GPIO pins determine which boot mode enter. example, user select download software internal through several serial ports. Other boot modes exist well. Boot also contains standard tables, such SIN/COS waveforms, math-related algorithms. Table shows details various boot modes invoked. TMS320F28x Boot Reference Guide (literature number SPRS095), more information.
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Table 3-2. Boot Mode Selection
BOOT MODE SELECTED (Internal status) Reserved Call SPI_Boot load from external serial EEPROM Call SCI_Boot load from SCI-A Jump SARAM address 0x3F Reserved Call Parallel_Boot load from GPIO Port GPIOF4/ (SCITXDA) GPIOF12/ (MDXA) GPIOF3/ (SPISTEA) GPIOF2/ (SPICLK)
internal pullup does have internal pullup Extra care must taken affect toggling SPICLK select boot mode have external logic. boot mode selected then external code loaded bootloader.
3.2.9
Security
R281x devices contain non-utilizable code security module compatibility with C281x F281x devices. passwords security module hard-wired device 0xFFFF. After device reset, SARAM blocks locked condition until dummy read passwords performed. R281x Boot performs dummy read password locations. execution after reset begins directly external memory R2812 devices (i.e., MP/MC user should perform dummy reads, each from address 0x3F7FF8 through 0x3F7FFF.
3.2.10 Peripheral Interrupt Expansion (PIE) Block
block serves multiplex numerous interrupt sources into smaller interrupt inputs. block support peripheral interrupts. R281x, possible interrupts used peripherals. interrupts grouped into blocks each group into interrupt lines (INT1 INT12). Each interrupts supported vector stored dedicated block that overwritten user. vector automatically fetched servicing interrupt. takes clock cycles fetch vector save critical registers. Hence quickly respond interrupt events. Prioritization interrupts controlled hardware software. Each individual interrupt enabled/disabled within block.
3.2.11
External Interrupts (XINT1, XNMI)
R281x supports three masked external interrupts (XINT1, 13). XINT13 combined with non-masked external interrupt (XNMI). combined signal name XNMI_XINT13. Each interrupts selected negative positive edge triggering also enabled/disabled (including XNMI). masked interrupts also contain 16-bit free running counter, which reset zero when valid interrupt edge detected. This counter used accurately time stamp interrupt.
3.2.12 Oscillator
R281x clocked external oscillator crystal attached on-chip oscillator circuit. provided supporting 10-input clock-scaling ratios. ratios changed on-the-fly software, enabling user scale back operating frequency lower power operation desired. Refer Electrical Specification section timing details. block bypass mode.
3.2.13 Watchdog
R281x supports watchdog timer. user software must regularly reset watchdog counter within certain time frame; otherwise, watchdog will generate reset processor. watchdog disabled necessary.
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3.2.14 Peripheral Clocking
clocks each individual peripheral enabled/disabled reduce power consumption when peripheral use. Additionally, system clock serial ports (except eCAN) event managers, blocks scaled relative clock. This enables timing peripherals decoupled from increasing clock speeds.
3.2.15 Low-Power Modes
R281x devices full static CMOS devices. Three low-power modes provided: IDLE: Place into low-power mode. Peripheral clocks turned selectively only those peripherals that need function during IDLE left operating. enabled interrupt from active peripheral will wake processor from IDLE mode. Turn clock peripherals. This mode leaves oscillator functional. external interrupt event will wake processor peripherals. Execution begins next valid cycle after detection interrupt event. Turn oscillator. This mode basically shuts down device places lowest possible power consumption mode. Only reset XNMI will wake device from this mode.
STANDBY:
HALT:
3.2.16 Peripheral Frames (PFn)
R281x segregates peripherals into three sections. mapping peripherals follows: PF0: XINTF: PIE: Timers: PF1: PF2: eCAN: SYS: GPIO: McBSP: SCI: SPI: ADC: External Interface Configuration Registers (2812 only) Interrupt Enable Control Registers Plus Vector Table CPU-Timers Registers eCAN Mailbox Control Registers System Control Registers GPIO Configuration Control Registers Event Manager (EVA/EVB) Control Registers McBSP Control TX/RX Registers Serial Communications Interface (SCI) Control RX/TX Registers Serial Peripheral Interface (SPI) Control RX/TX Registers 12-Bit Registers
3.2.17 General-Purpose Input/Output (GPIO) Multiplexer
Most peripheral signals multiplexed with general-purpose (GPIO) signals. This enables user GPIO peripheral signal function used. reset, GPIO pins configured inputs. user then individually program each GPIO mode Peripheral Signal mode. specific inputs, user also select number input qualification cycles. This filter unwanted noise glitches.
3.2.18 32-Bit CPU-Timers
CPU-Timers identical 32-bit timers with presettable periods with 16-bit clock prescaling. timers have 32-bit count down register, which generates interrupt when counter reaches zero. counter decremented clock speed divided prescale value setting. When counter reaches zero, automatically reloaded with 32-bit period value. CPU-Timer reserved Real-Time (RTOS)/BIOS applications. CPU-Timer reserved DSP/BIOS real-time operating system (DSP/BIOS RTOS), connected INT14 CPU. CPU-Timer general use, connected INT13 CPU. CPU-Timer also general use, connected block.
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3.2.19 Control Peripherals
R281x supports following peripherals which used embedded control communication: event manager module includes general-purpose timers, full-compare/PWM units, capture inputs (CAP) quadrature-encoder pulse (QEP) circuits. such event managers provided which enable three-phase motors driven four two-phase motors. event managers R281x compatible event managers 240x devices (with some minor enhancements). block 12-bit converter, single ended, 16-channels. contains sample-and-hold units simultaneous sampling.
ADC:
3.2.20 Serial Port Peripherals
R281x supports following serial communication peripherals: eCAN: McBSP: This enhanced version peripheral. supports mailboxes, time stamping messages, 2.0B-compliant. This multichannel buffered serial port that used connect E1/T1 lines, phone-quality codecs modem applications high-quality stereo-quality Audio devices. McBSP receive transmit registers supported 16-level FIFO. This significantly reduces overhead servicing this peripheral. high-speed, synchronous serial port that allows serial stream programmed length (one sixteen bits) shifted into device programmable bit-transfer rate. Normally, used communications between controller external peripherals another processor. Typical applications include external peripheral expansion through devices such shift registers, display drivers, ADCs. Multi-device communications supported master/slave operation SPI. R281x, port supports 16-level, receive transmit FIFO reducing servicing overhead. serial communications interface two-wire asynchronous serial port, commonly known UART. R281x, port supports 16-level, receive transmit FIFO reducing servicing overhead.
SPI:
SCI:
Register
R281x devices contain three peripheral register spaces. spaces categorized follows: Peripheral Frame Peripheral Frame Peripheral Frame These peripherals that mapped directly memory bus. Table 3-3. These peripherals that mapped 32-bit peripheral bus. Table 3-4. These peripherals that mapped 16-bit peripheral bus. Table 3-5.
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Table 3-3. Peripheral Frame Registers
NAME Device Emulation Registers reserved XINTF Registers reserved CPU-TIMER0/1/2 Registers reserved Registers Vector Table Reserved ADDRESS RANGE 0x00 0880 0x00 09FF 0x00 0A00 0x00 0B1F 0x00 0B20 0x00 0B3F 0x00 0B40 0x00 0BFF 0x00 0C00 0x00 0C3F 0x00 0C40 0x00 0CDF 0x00 0CE0 0x00 0CFF 0x00 0D00 0x00 0DFF 0x00 0E00 0x00 0FFF SIZE (x16) EALLOW protected EALLOW protected EALLOW protected EALLOW protected ACCESS TYPE EALLOW protected
Registers Frame support 16-bit 32-bit accesses. registers EALLOW protected, then writes cannot performed until user executes EALLOW instruction. EDIS instruction disables writes. This prevents stray code pointers from corrupting register contents.
Table 3-4. Peripheral Frame
NAME eCAN Registers eCAN Mailbox reserved ADDRESS RANGE 0x00 6000 0x00 60FF 0x00 6100 0x00 61FF 0x00 6200 0x00 6FFF SIZE (x16) (128 (128 3584 ACCESS TYPE Some eCAN control registers (and selected bits other eCAN control registers) EALLOW-protected. EALLOW-protected
eCAN control registers only support 32-bit read/write operations. 32-bit accesses aligned even address boundaries.
Table 3-5. Peripheral Frame Registers
NAME reserved System Control Registers reserved SPI-A Registers ADDRESS RANGE 0x00 7000 0x00 700F 0x00 7010 0x00 702F 0x00 7030 0x00 703F 0x00 7040 0x00 704F SIZE (x16) EALLOW Protected EALLOW Protected ACCESS TYPE
Peripheral Frame only allows 16-bit accesses. 32-bit accesses ignored (invalid data returned written).
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Peripheral Frame Registers (Continued)
NAME SCI-A Registers reserved External Interrupt Registers reserved GPIO Registers GPIO Data Registers Registers reserved EV-A Registers reserved EV-B Registers reserved SCI-B Registers reserved McBSP Registers reserved ADDRESS RANGE 0x00 7050 0x00 705F 0x00 7060 0x00 706F 0x00 7070 0x00 707F 0x00 7080 0x00 70BF 0x00 70C0 0x00 70DF 0x00 70E0 0x00 70FF 0x00 7100 0x00 711F 0x00 7120 0x00 73FF 0x00 7400 0x00 743F 0x00 7440 0x00 74FF 0x00 7500 0x00 753F 0x00 7540 0x00 774F 0x00 7750 0x00 775F 0x00 7760 0x00 77FF 0x00 7800 0x00 783F 0x00 7840 0x00 7FFF SIZE (x16) 1984 EALLOW Protected EALLOW Protected EALLOW Protected EALLOW Protected EALLOW Protected EALLOW Protected EALLOW Protected EALLOW Protected ACCESS TYPE EALLOW Protected
Peripheral Frame only allows 16-bit accesses. 32-bit accesses ignored (invalid data returned written).
Device Emulation Registers
These registers used control protection mode C28x monitor some critical device signals. registers defined Table 3-6.
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Table 3-6. Device Emulation Registers
NAME DEVICECNF PARTID DEVICEID PROTSTART PROTRANGE reserved ADDRESS RANGE 0x00 0880 0x00 0881 0x00 0882 0x00 0883 0x00 0884 0x00 0885 0x00 0886 0x00 09FF SIZE (x16) Device Configuration Register 0x0003 R281x Device Register (0x0001 Silicon Rev. Device Register (0x0002 Silicon Rev. Block Protection Start Address Register Block Protection Range Address Register DESCRIPTION
External Interface, XINTF (2812 Only)
This section gives top-level view external interface (XINTF) that implemented 2812 devices. external interface non-multiplexed asynchronous bus, similar C240x external interface. external interface 2812 mapped into five fixed zones shown Figure 3-4. Figure shows 2812 XINTF signals. operation timing external interface, controlled registers listed Table 3-7. Table 3-7. XINTF Configuration Control Register Mappings
NAME ADDRESS 0x00 0B20 0x00 0B22 0x00 0B24 0x00 0B2C 0x00 0B2E 0x00 0B34 0x00 0B38 0x00 0B3A SIZE (x16) DESCRIPTION XINTF Timing Register, Zone access 16-bit registers 32-bit register XINTF Timing Register, Zone access 16-bit registers 32-bit register XINTF Timing Register, Zone access 16-bit registers 32-bit register XINTF Timing Register, Zone access 16-bit registers 32-bit register XINTF Timing Register, Zone access 16-bit registers 32-bit register XINTF Configuration Register access 16-bit registers 32-bit register XINTF Bank Control Register XINTF Revision Register
XTIMING0 XTIMING1 XTIMING2 XTIMING6 XTIMING7 XINTCNF2 XBANK XREVISION
3.5.1
Timing Registers
XINTF signal timing tuned match specific external device requirements such setup hold times strobe signals contention avoidance maximizing efficiency. timing parameters configured individually each zone. This allows programmer maximize efficiency bus, based type memory peripheral that user needs access. XINTF timing values with respect XTIMCLK, which equal one-half SYSCLKOUT rate, shown Figure 6-26. detailed information XINTF timing configuration register fields, TMS320F28x External Interface (XINTF) Reference Guide (literature number SPRU067).
3.5.2
XREVISION Register
XREVISION register contains unique number identify particular version XINTF used product. 2812, this register will configured described Table 3-8. Table 3-8. XREVISION Register Definitions
BIT(S) 15-0
NAME REVISION
TYPE
RESET 0x0004
DESCRIPTION Current XINTF Revision. internal use/reference. Test purposes only. Subject change.
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Data Space 0x00 0000 XD(15:0) Prog Space
XA(18:0) 0x00 2000 0x00 4000 0x00 6000 0x08 0000 0x10 0000 XINTF Zone (512K 0x18 0000 0x3F C000 XINTF Zone (16K (mapped here MP/MC XZCS6 XZCS6AND7 XINTF Zone (512K XZCS2 XINTF Zone XINTF Zone
XZCS0 XZCS1
XZCS0AND1
XZCS7
0x40 0000
XR/W XREADY XMP/MC XHOLD XHOLDA XCLKOUT (see Note
NOTES: mapping XINTF Zone dependent XMP/MC device input signal MP/MC mode (bit XINTCNF2 register). Zones always enabled. Each zone programmed with different wait states, setup hold timing, supported zone chip selects (XZCS0AND1, XZCS2, XZCS6AND7), which toggle when access particular zone performed. These features enable glueless connection many external memories peripherals. chip selects Zone ANDed internally together form chip select (XZCS0AND1). external memory that connected XZCS0AND1 dually mapped both Zones Zone chip selects Zone ANDed internally together form chip select (XZCS6AND7). external memory that connected XZCS6AND7 dually mapped both Zones Zone This means that Zone disabled (via MP/MC mode) then external memory still accessible Zone address space. XCLKOUT also pinned 2810 2811.
Figure 3-4. External Interface Block Diagram
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Interrupts
Figure shows various interrupt sources multiplexed within R281x devices.
Peripherals (SPI, SCI, McBSP, CAN, ADC) Interrupts)
WAKEINT
WDINT LPMINT
Watchdog Low-Power Modes XINT1
Interrupts
Interrupt Control XINT1CR(15:0) XINT1CTR(15:0)
INT1 INT12
Interrupt Control C28x XINT2CR(15:0) XINT2CTR(15:0)
XINT2
TINT0 INT14 TINT2 TINT1 INT13
TIMER TIMER (for RTOS) TIMER
GPIO
select enable Interrupt Control XNMICR(15:0) XNMICTR(15:0) XNMI_XINT13
possible interrupts, currently used peripherals.
Figure 3-5. Interrupt Sources Figure shows interrupts multiplexed using block. Eight block interrupts grouped into interrupt. total, interrupt groups, with interrupts group equals possible interrupts. R281x, these used peripherals shown Table 3-9.
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IFR(12:1) INT1 INT2 INT11 INT12 (Flag) (Enable) INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 (Enable) (Enable/Flag) PIEIERx(8:1) (Flag) PIEIFRx(8:1) IER(12:1) IN
Global Enable
INTx
From Peripherals External Interrupts
PIEACKx
Figure 3-6. Multiplexing Interrupts Using Block Table 3-9. Peripheral Interrupts
INTERRUPTS INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 INT9 INT10 INT11 INT12 INTERRUPTS INTx.8 WAKEINT (LPM/WD) reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved INTx.7 TINT0 (TIMER T1OFINT (EV-A) CAPINT3 (EV-A) T3OFINT (EV-B) CAPINT6 (EV-B) reserved reserved reserved reserved reserved reserved reserved INTx.6 ADCINT (ADC) T1UFINT (EV-A) CAPINT2 (EV-A) T3UFINT (EV-B) CAPINT5 (EV-B) MXINT (McBSP) reserved reserved ECAN1INT (CAN) reserved reserved reserved INTx.5 XINT2 T1CINT (EV-A) CAPINT1 (EV-A) T3CINT (EV-B) CAPINT4 (EV-B) MRINT (McBSP) reserved reserved ECAN0INT (CAN) reserved reserved reserved INTx.4 XINT1 T1PINT (EV-A) T2OFINT (EV-A) T3PINT (EV-B) T4OFINT (EV-B) reserved reserved reserved SCITXINTB (SCI-B) reserved reserved reserved INTx.3 reserved CMP3INT (EV-A) T2UFINT (EV-A) CMP6INT (EV-B) T4UFINT (EV-B) reserved reserved reserved SCIRXINTB (SCI-B) reserved reserved reserved INTx.2 PDPINTB (EV-B) CMP2INT (EV-A) T2CINT (EV-A) CMP5INT (EV-B) T4CINT (EV-B) SPITXINTA (SPI) reserved reserved SCITXINTA (SCI-A) reserved reserved reserved INTx.1 PDPINTA (EV-A) CMP1INT (EV-A) T2PINT (EV-A) CMP4INT (EV-B) T4PINT (EV-B) SPIRXINTA (SPI) reserved reserved SCIRXINTA (SCI-A) reserved reserved
reserved possible interrupts, interrupts currently used. remaining interrupts reserved future devices. These interrupts used software interrupts they enabled PIEIFRx level, provided none interrupts within group being used peripheral. Otherwise, interrupts coming from peripherals lost accidentally clearing their flag while modifying PIEIFR. summarize, there safe cases when reserved interrupts could used software interrupts: peripheral within group asserting interrupts. peripheral interrupts assigned group (example group 12).
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Table 3-10. Configuration Control Registers
NAME PIECTRL PIEACK PIEIER1 PIEIFR1 PIEIER2 PIEIFR2 PIEIER3 PIEIFR3 PIEIER4 PIEIFR4 PIEIER5 PIEIFR5 PIEIER6 PIEIFR6 PIEIER7 PIEIFR7 PIEIER8 PIEIFR8 PIEIER9 PIEIFR9 PIEIER10 PIEIFR10 PIEIER11 PIEIFR11 PIEIER12 PIEIFR12 Reserved ADDRESS 0x0000-0CE0 0x0000-0CE1 0x0000-0CE2 0x0000-0CE3 0x0000-0CE4 0x0000-0CE5 0x0000-0CE6 0x0000-0CE7 0x0000-0CE8 0x0000-0CE9 0x0000-0CEA 0x0000-0CEB 0x0000-0CEC 0x0000-0CED 0x0000-0CEE 0x0000-0CEF 0x0000-0CF0 0x0000-0CF1 0x0000-0CF2 0x0000-0CF3 0x0000-0CF4 0x0000-0CF5 0x0000-0CF6 0x0000-0CF7 0x0000-0CF8 0x0000-0CF9 0x0000-0CFA 0x0000-0CFF
Size (x16)
PIE, Control Register PIE, Acknowledge Register
DESCRIPTION
PIE, INT1 Group Enable Register PIE, INT1 Group Flag Register PIE, INT2 Group Enable Register PIE, INT2 Group Flag Register PIE, INT3 Group Enable Register PIE, INT3 Group Flag Register PIE, INT4 Group Enable Register PIE, INT4 Group Flag Register PIE, INT5 Group Enable Register PIE, INT5 Group Flag Register PIE, INT6 Group Enable Register PIE, INT6 Group Flag Register PIE, INT7 Group Enable Register PIE, INT7 Group Flag Register PIE, INT8 Group Enable Register PIE, INT8 Group Flag Register PIE, INT9 Group Enable Register PIE, INT9 Group Flag Register PIE, INT10 Group Enable Register PIE, INT10 Group Flag Register PIE, INT11 Group Enable Register PIE, INT11 Group Flag Register PIE, INT12 Group Enable Register PIE, INT12 Group Flag Register Reserved
Note:
configuration control registers protected EALLOW mode. vector table protected.
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3.6.1
External Interrupts
Table 3-11. External Interrupt Registers
NAME ADDRESS 0x00 7070 0x00 7071 0x00 7072 0x00 7076 0x00 7077 0x00 7078 0x00 7079 0x00 707A 0x00 707E 0x00 707F SIZE (x16) XNMI counter register XNMI control register XINT1 counter register XINT2 counter register XINT1 control register XINT2 control register DESCRIPTION
XINT1CR XINT2CR reserved XNMICR XINT1CTR XINT2CTR reserved XNMICTR
Each external interrupt enabled/disabled qualified using positive negative going edge. more information, TMS320F28x System Control Interrupts Reference Guide (literature number SPRU078).
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System Control
This section describes R281x oscillator, clocking mechanisms, watchdog function power modes. Figure shows various clock reset domains R281x devices that will discussed.
Reset SYSCLKOUT Peripheral Reset CLKIN C28x X1/XCLKIN Watchdog Block
Power Modes Control Clock Enables
XF_XPLLDIS
System Control Registers Peripheral Registers
eCAN LSPCLK
Low-Speed Prescaler Peripheral Peripheral Registers
Low-Speed Peripherals SCI-A/B, SPI, McBSP HSPCLK
GPIO
GPIOs
High-Speed Prescaler
Peripheral Registers
High-Speed Peripherals EV-A/B HSPCLK
Registers
12-Bit
Inputs
NOTE CLKIN clock input CPU. SYSCLKOUT output clock CPU. They same frequency.
Figure 3-7. Clock Reset Domains PLL, clocking, watchdog low-power modes controlled registers listed Table 3-12.
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Table 3-12. PLL, Clocking, Watchdog, Low-Power Mode Registers
NAME reserved reserved reserved HISPCP LOSPCP PCLKCR reserved LPMCR0 LPMCR1 reserved PLLCR SCSR WDCNTR reserved WDKEY reserved WDCR reserved ADDRESS 0x00 7010 0x00 7017 0x00 7018 0x00 7019 0x00 701A 0x00 701B 0x00 701C 0x00 701D 0x00 701E 0x00 701F 0x00 7020 0x00 7021 0x00 7022 0x00 7023 0x00 7024 0x00 7025 0x00 7026 0x00 7028 0x00 7029 0x00 702A 0x00 702F SIZE (x16) Watchdog Control Register Watchdog Reset Register Control Register System Control Status Register Watchdog Counter Register Power Mode Control Register Power Mode Control Register High-Speed Peripheral Clock Prescaler Register HSPCLK clock Low-Speed Peripheral Clock Prescaler Register LSPCLK clock Peripheral Clock Control Register DESCRIPTION
above registers only accessed, executing EALLOW instruction. control register (PLLCR) reset known state signal only. Emulation reset (through Code Composer Studio) will reset PLLCR.
3.7.1
Block
Figure shows block R281x.
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Latch OSCCLK (PLL Disabled) XPLLDIS
XF_XPLLDIS
XCLKIN
X1/XCLKIN
CLKIN SYSCLKOUT
On-Chip Oscillator (OSC)
Bypass 4-Bit Select
4-Bit Select
Block
Figure 3-8. Block on-chip oscillator circuit enables crystal attached R281x devices using X1/XCLKIN pins. crystal used, then external oscillator directly connected X1/XCLKIN left unconnected. logic-high level this case should exceed VDD. PLLCR bits [3:0] clocking ratio. Table 3-13. PLLCR Register Definitions
BIT(S) 15:4 NAME reserved TYPE RESET SYSCLKOUT (XCLKIN n)/2, where multiplication factor. Value 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Bypassed SYSCLKOUT XCLKIN/2 XCLKIN/2 XCLKIN XCLKIN XCLKIN XCLKIN XCLKIN XCLKIN XCLKIN XCLKIN XCLKIN Reserved Reserved Reserved Reserved Reserved DESCRIPTION
0,0,0,0
PLLCR register reset known state reset line. reset issued debugger, clocking ratio changed.
3.7.2
Loss Input Clock
enabled mode, input clock XCLKIN oscillator clock removed absent, will still issue "limp-mode" clock. limp-mode clock will continue clock peripherals typical frequency MHz. PLLCR register should have been written with non-zero value this feature work.
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Normally, when input clocks present, watchdog counter will decrement initiate watchdog reset WDINT interrupt. However, when external input clock fails, watchdog counter will stop decrementing (i.e., watchdog counter does change with limp-mode clock). This condition could used application firmware detect input clock failure initiate necessary shut-down procedure system.
3.7.3
PLL-Based Clock Module
R281x on-chip, PLL-based clock module. This module provides necessary clocking signals device, well control low-power mode entry. 4-bit ratio control select different clock rates. watchdog module should disabled before writing PLLCR register. re-enabled need after module stabilized, which takes XCLKIN cycles. PLL-based clock module provides modes operation: Crystal-operation This mode allows external crystal/resonator provide time base device. External clock source operation This mode allows internal oscillator bypassed. device clocks generated from external clock source input X1/XCLKIN pin.
X1/XCLKIN
X1/XCLKIN
(see Note
Crystal
(see Note
External Clock Signal (Toggling -VDD)
NOTE recommends that customers have resonator/crystal vendor characterize operation their device with chip. resonator/crystal vendor equipment expertise tune tank circuit. vendor also advise customer regarding proper tank component values that will ensure start-up stability over entire operating range.
Figure 3-9. Recommended Crystal Clock Connection Table 3-14. Possible Configuration Modes
MODE Disabled REMARKS Invoked tying XPLLDIS upon reset. block completely disabled. Clock input (CLKIN) directly derived from clock signal present X1/XCLKIN pin. Default configuration upon power-up, disabled. itself bypassed. However, module block divides clock input X1/XCLKIN before feeding CPU. Achieved writing non-zero value into PLLCR register. module block divides output before feeding CPU. SYSCLKOUT XCLKIN
Bypassed
XCLKIN/2
Enabled
(XCLKIN
3.7.4
External Reference Oscillator Clock Option
typical specifications external quartz crystal frequency listed below: Fundamental mode, parallel resonant (load capacitance) Cshunt range
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3.7.5
Watchdog Block
watchdog block R281x identical used 240x devices. watchdog module generates output pulse, oscillator clocks wide (OSCCLK), whenever 8-bit watchdog counter reached maximum value. prevent this, user disables counter software must periodically write 0x55 0xAA sequence into watchdog register which will reset watchdog counter. Figure 3-10 shows various functional blocks within watchdog module.
WDCR (WDPS(2:0)) WDCR (WDDIS) WDCNTR(7:0)
OSCCLK /512
Watchdog Prescaler
WDCLK
8-Bit Watchdog Counter Clear Counter
Internal Pullup WDKEY(7:0) Watchdog Detector Core-reset WDCR (WDCHK(2:0)) WDCHK SCSR (WDENINT) Good Generate Output Pulse (512 OSCCLKs) WDRST WDINT
WDRST (See Note
NOTE WDRST signal driven OSCCLK cycles.
Figure 3-10. Watchdog Module WDINT signal enables watchdog used wakeup from IDLE/STANDBY mode timer. STANDBY mode, peripherals turned device. only peripheral that remains functional watchdog. Watchdog module will clock oscillator clock. WDINT signal block that wake device from STANDBY enabled). Section 3.7.6, Low-Power Modes Block, more details. IDLE mode, WDINT signal generate interrupt CPU, PIE, take IDLE mode. HALT mode, this feature cannot used because oscillator (and PLL) turned hence WATCHDOG.
3.7.6
Low-Power Modes Block
low-power modes R281x similar 240x devices. Table 3-15 summarizes various modes.
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Table 3-15. R281x Low-Power Modes
MODE Normal LPM(1:0) OSCCLK CLKIN SYSCLKOUT EXIT XRS, WDINT, Enabled Interrupt, XNMI XRS, WDINT, XINT1, XNMI, T1/2/3/4CTRIP, C1/2/3/4/5/6TRIP, SCIRXDA, SCIRXDB, CANRX, XRS, XNMI,
IDLE
STANDBY (watchdog still running)
HALT (oscillator turned off, watchdog functional)
Exit column lists which signals under what conditions power mode will exited. signal, signals, will exit power condition. This signal must kept long enough interrupt recognized device. Otherwise IDLE mode will exited device will back into indicated power mode. IDLE mode C28x behaves differently than 24x/240x. C28x, clock output from core (SYSCLKOUT) still functional while 24x/240x clock turned off. C28x, JTAG port still function even core clock (CLKIN) turned off.
various low-power modes operate follows: IDLE Mode: This mode exited enabled interrupt XNMI that recognized processor. block performs tasks during this mode long LPMCR0(LPM) bits 0,0. other signals (including XNMI) will wake device from STANDBY mode selected LPMCR1 register. user will need select which signal(s) will wake device. selected signal(s) also qualified OSCCLK before waking device. number OSCCLKs specified LPMCR0 register. Only XNMI external signals wake device from HALT mode. XNMI input core enable/disable bit. Hence, safe XNMI signal this function.
STANDBY Mode:
HALT Mode:
NOTE: low-power modes affect state output pins (PWM pins included). They will whatever state code left them when IDLE instruction executed.
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Peripherals
Peripherals
integrated peripherals R281x described following subsections: Three 32-bit CPU-Timers event-manager modules (EVA, EVB) Enhanced analog-to-digital converter (ADC) module Enhanced controller area network (eCAN) module Multichannel buffered serial port (McBSP) module Serial communications interface modules (SCI-A, SCI-B) Serial peripheral interface (SPI) module Digital shared functions
32-Bit CPU-Timers 0/1/2
There three 32-bit CPU-timers R281x devices (CPU-TIMER0/1/2). CPU-Timer reserved system functions Timer reserved DSP/BIOS. CPU-Timer used user applications. These timers different from general-purpose (GP) timers that present Event Manager modules (EVA, EVB). NOTE: application using DSP/BIOS, then CPU-Timers used application.
Reset Timer Reload
16-Bit Timer Divide-Down TDDRH:TDDR
32-Bit Timer Period PRDH:PRD
SYSCLKOUT TCR.4 (Timer Start Status)
16-Bit Prescale Counter PSCH:PSC Borrow 32-Bit Counter TIMH:TIM Borrow
TINT
Figure 4-1. CPU-Timers
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R281x devices, timer interrupt signals (TINT0, TINT1, TINT2) connected shown Figure 4-2.
INT1 INT12
TINT0
CPU-TIMER
C28x TINT1 CPU-TIMER (Reserved system functions) XINT13 INT14 TINT2 CPU-TIMER (Reserved DSP/BIOS)
INT13
NOTES: timer registers connected Memory C28x processor. timing timers synchronized SYSCLKOUT processor clock.
Figure 4-2. CPU-Timer Interrupts Signals Output Signal (See Notes general operation timer follows: 32-bit counter register "TIMH:TIM" loaded with value period register "PRDH:PRD". counter register, decrements SYSCLKOUT rate C28x. When counter reaches timer interrupt output signal generates interrupt pulse. registers listed Table used configure timers. more information, TMS320F28x System Control Interrupts Reference Guide (literature number SPRU078).
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Table 4-1. CPU-Timers Configuration Control Registers
NAME TIMER0TIM TIMER0TIMH TIMER0PRD TIMER0PRDH TIMER0TCR reserved TIMER0TPR TIMER0TPRH TIMER1TIM TIMER1TIMH TIMER1PRD TIMER1PRDH TIMER1TCR reserved TIMER1TPR TIMER1TPRH TIMER2TIM TIMER2TIMH TIMER2PRD TIMER2PRDH TIMER2TCR reserved TIMER2TPR TIMER2TPRH reserved ADDRESS 0x00 0C00 0x00 0C01 0x00 0C02 0x00 0C03 0x00 0C04 0x00 0C05 0x00 0C06 0x00 0C07 0x00 0C08 0x00 0C09 0x00 0C0A 0x00 0C0B 0x00 0C0C 0x00 0C0D 0x00 0C0E 0x00 0C0F 0x00 0C10 0x00 0C11 0x00 0C12 0x00 0C13 0x00 0C14 0x00 0C15 0x00 0C16 0x00 0C17 0x00 0C18 0x00 0C3F SIZE (x16) CPU-Timer Prescale Register CPU-Timer Prescale Register High CPU-Timer Prescale Register CPU-Timer Prescale Register High CPU-Timer Counter Register CPU-Timer Counter Register High CPU-Timer Period Register CPU-Timer Period Register High CPU-Timer Control Register CPU-Timer Prescale Register CPU-Timer Prescale Register High CPU-Timer Counter Register CPU-Timer Counter Register High CPU-Timer Period Register CPU-Timer Period Register High CPU-Timer Control Register DESCRIPTION CPU-Timer Counter Register CPU-Timer Counter Register High CPU-Timer Period Register CPU-Timer Period Register High CPU-Timer Control Register
Event Manager Modules (EVA, EVB)
event-manager modules include general-purpose (GP) timers, full-compare/PWM units, capture units, quadrature-encoder pulse (QEP) circuits. timers, compare units, capture units function identically. However, timer/unit names differ EVB. Table shows module signal names used. Table shows features functionality available event-manager modules highlights nomenclature. Event managers have identical peripheral register sets with starting 7400h starting 7500h. paragraphs this section describe function timers, compare units, capture units, QEPs using nomenclature. These paragraphs applicable with regard function-however, module/signal names would differ. Table lists registers. more information, TMS320F28x Event Manager (EV) Reference Guide (literature number SPRU065).
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Table 4-2. Module Signal Names
EVENT MANAGER MODULES Timers MODULE Timer Timer Compare Compare Compare Capture Capture Capture QEP1 QEP2 QEPI1 Direction External Clock Compare SIGNAL T1PWM/T1CMP T2PWM/T2CMP PWM1/2 PWM3/4 PWM5/6 CAP1 CAP2 CAP3 QEP1 QEP2 TDIRA TCLKINA C1TRIP C2TRIP C3TRIP T1CTRIP_PDPINTA T2CTRIP/EVASOC MODULE Timer Timer Compare Compare Compare Capture Capture Capture QEP3 QEP4 QEPI2 Direction External Clock Compare SIGNAL T3PWM/T3CMP T4PWM/T4CMP PWM7/8 PWM9/10 PWM11/12 CAP4 CAP5 CAP6 QEP3 QEP4 TDIRB TCLKINB C4TRIP C5TRIP C6TRIP T3CTRIP_PDPINTB T4CTRIP/EVBSOC
Compare Units
Capture Units
Channels
External Clock Inputs
External Trip Inputs
External Trip Inputs
24x/240x-compatible mode, T1CTRIP_PDPINTA functions PDPINTA T3CTRIP_PDPINTB functions PDPINTB.
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Table 4-3. Registers
NAME GPTCONA T1CNT T1CMPR T1PR T1CON T2CNT T2CMPR T2PR T2CON EXTCONA COMCONA ACTRA DBTCONA CMPR1 CMPR2 CMPR3 CAPCONA CAPFIFOA CAP1FIFO CAP2FIFO CAP3FIFO CAP1FBOT CAP2FBOT CAP3FBOT EVAIMRA EVAIMRB EVAIMRC EVAIFRA EVAIFRB ADDRESS 0x00 7400 0x00 7401 0x00 7402 0x00 7403 0x00 7404 0x00 7405 0x00 7406 0x00 7407 0x00 7408 0x00 7409 0x00 7411 0x00 7413 0x00 7415 0x00 7417 0x00 7418 0x00 7419 0x00 7420 0x00 7422 0x00 7423 0x00 7424 0x00 7425 0x00 7427 0x00 7428 0x00 7429 0x00 742C 0x00 742D 0x00 742E 0x00 742F 0x00 7430 SIZE (x16) DESCRIPTION Timer Control Register Timer Counter Register Timer Compare Register Timer Period Register Timer Control Register Timer Counter Register Timer Compare Register Timer Period Register Timer Control Register Extension Control Register Compare Control Register Compare Action Control Register Dead-Band Timer Control Register Compare Register Compare Register Compare Register Capture Control Register Capture FIFO Status Register Two-Level Deep Capture FIFO Stack Two-Level Deep Capture FIFO Stack Two-Level Deep Capture FIFO Stack Bottom Register Capture FIFO Stack Bottom Register Capture FIFO Stack Bottom Register Capture FIFO Stack Interrupt Mask Register Interrupt Mask Register Interrupt Mask Register Interrupt Flag Register Interrupt Flag Register
EVAIFRC 0x00 7431 Interrupt Flag Register EV-B register identical except address range from 0x00-7500 0x00-753F. above registers mapped Zone This space allows only 16-bit accesses. 32-bit accesses produce undefined results. register compared 24x/240x
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Peripheral Write
MXINT Interrupt Logic
FIFO Interrupt
FIFO FIFO
FIFO FIFO FIFO
McBSP Transmit Interrupt Select Logic
FIFO
FIFO Registers DXR1 Transmit Buffer Compand Logic XSR2 XSR1 CLKX
LSPCLK McBSP Registers Control Logic
DXR2 Transmit Buffer
RSR2 RBR2 Register McBSP DRR2 Receive Buffer McBSP Receive Interrupt Select Logic FIFO Interrupt FIFO MRINT Interrupt Logic FIFO FIFO
RSR1 Expand Logic
CLKR
RBR1 Register DRR1 Receive Buffer FIFO FIFO FIFO
FIFO Registers Peripheral Read
Figure 4-3. Event Manager Functional Block Diagram (See Note
4.2.1
General-Purpose (GP) Timers
There timers. timer EVA; EVB) includes: 16-bit timer, up-/down-counter, TxCNT, reads writes 16-bit timer-compare register, TxCMPR (double-buffered with shadow register), reads writes 16-bit timer-period register, TxPR (double-buffered with shadow register), reads writes 16-bit timer-control register,TxCON, reads writes Selectable internal external input clocks
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programmable prescaler internal external clock inputs Control interrupt logic, four maskable interrupts: underflow, overflow, timer compare, period interrupts selectable direction input (TDIRx) count down when directional down-count mode selected)
timers operated independently synchronized with each other. compare register associated with each timer used compare function PWM-waveform generation. There three continuous modes operations each timer down-counting operations. Internal external input clocks with programmable prescaler used each timer. timers also provide time base other event-manager submodules: timer compares circuits, timer capture units quadrature-pulse counting operations. Double-buffering period compare registers allows programmable change timer (PWM) period compare/PWM pulse width needed.
4.2.2
Full-Compare Units
There three full-compare units each event manager. These compare units timer1 time base generate outputs compare PWM-waveform generation using programmable deadband circuit. state each outputs configured independently. compare registers compare units double-buffered, allowing programmable change compare/PWM pulse widths needed.
4.2.3
Programmable Deadband Generator
Deadband generation enabled/disabled each compare unit output individually. deadband-generator circuit produces outputs (with without deadband zone) each compare unit output signal. output states deadband generator configurable changeable needed double-buffered ACTRx register.
4.2.4
Waveform Generation
eight waveforms (outputs) generated simultaneously each event manager: three independent pairs (six outputs) three full-compare units with programmable deadbands, independent PWMs GP-timer compares.
4.2.5
Double Update Mode
R281x Event Manager supports "Double Update Mode." This mode refers operation mode which position leading edge position trailing edge pulse independently modifiable each period. support this mode, compare register that determines position edges pulse must allow (buffered) compare value update once beginning period another time middle period. compare registers R281x Event Managers buffered support three compare value reload/update (value buffer becoming active) modes. These modes have earlier been documented compare value reload conditions. reload condition that supports double update mode reloaded Underflow (beginning period) Period (middle period). Double update mode achieved using this condition compare value reload.
4.2.6
Characteristics
Characteristics PWMs follows: 16-bit registers Wide range programmable deadband output pairs Change carrier frequency frequency wobbling needed
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Change pulse widths within after each period needed External-maskable power drive-protection interrupts Pulse-pattern-generator circuit, programmable generation asymmetric, symmetric, four-space vector waveforms Minimized overhead using auto-reload compare period registers pins driven high-impedance state when PDPINTx driven after PDPINTx signal qualification. PDPINTx (after qualification) reflected COMCONx register. PDPINTA status reflected COMCONA register. PDPINTB status reflected COMCONB register.
EXTCON register bits provide options individually trip control each pair signals
4.2.7
Capture Unit
capture unit provides logging function different events transitions. values selected timer counter captured stored two-level-deep FIFO stacks when selected transitions detected capture input pins, CAPx EVA; EVB). capture unit consists three capture circuits. Capture units include following features: 16-bit capture control register, CAPCONx (R/W) 16-bit capture FIFO status register, CAPFIFOx Selection timer (for EVA) (for EVB) time base Three 16-bit 2-level-deep FIFO stacks, each capture unit Three capture input pins (CAP1/2/3 EVA, CAP4/5/6 EVB)-one input capture unit. [All inputs synchronized with device (CPU) clock. order transition captured, input must hold current level meet input qualification circuitry requirements. input pins CAP1/2 CAP4/5 also used inputs circuit.] User-specified transition (rising edge, falling edge, both edges) detection Three maskable interrupt flags, each capture unit capture pins also used general-purpose interrupt pins, they used capture function.
4.2.8
Quadrature-Encoder Pulse (QEP) Circuit
capture inputs (CAP1 CAP2 EVA; CAP4 CAP5 EVB) used interface on-chip circuit with quadrature encoder pulse. Full synchronization these inputs performed on-chip. Direction leading-quadrature pulse sequence detected, timer incremented decremented rising falling edges input signals (four times frequency either input pulse). With EXTCONA register bits, circuit CAP3 capture index well. Similarly, with EXTCONB register bits, circuit CAP6 capture index pin.
4.2.9
External Start-of-Conversion
EVA/EVB start-of-conversion (SOC) sent external (EVASOC/EVBSOC) external interface. EVASOC EVBSOC MUXed with T2CTRIP T4CTRIP, respectively.
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Enhanced Analog-to-Digital Converter (ADC) Module
simplified functional block diagram module shown Figure 4-4. module consists 12-bit with built-in sample-and-hold circuit. Functions module include: 12-bit core with built-in Analog input: (Voltages above produce full-scale conversion results.) Fast conversion rate: 25-MHz clock, 12.5 MSPS 16-channel, MUXed inputs Autosequencing capability provides "autoconversions" single session. Each conversion programmed select input channels Sequencer operated independent 8-state sequencers large 16-state sequencer (i.e., cascaded 8-state sequencers) Sixteen result registers (individually addressable) store conversion values digital value input analog voltage derived Digital Value Digital Value 4096 4095 Digital Value 4095, Input Analog Voltage ADCLO, when input when input when input
Multiple triggers sources start-of-conversion (SOC) sequence software immediate start Event manager (multiple event sources within EVA) Event manager (multiple event sources within EVB)
Flexible interrupt control allows interrupt request every end-of-sequence (EOS) every other Sequencer operate "start/stop" mode, allowing multiple "time-sequenced triggers" synchronize conversions triggers operate independently dual-sequencer mode Sample-and-hold (S/H) acquisition time window separate prescale control
module R281x been enhanced provide flexible interface event managers interface built around fast, 12-bit module with fast conversion rate 25-MHz clock. module channels, configurable independent 8-channel modules service event managers independent 8-channel modules cascaded form 16-channel module. Although there multiple input channels sequencers, there only converter module. Figure shows block diagram R281x module. 8-channel modules have capability autosequence series conversions, each module choice selecting respective eight channels available through analog MUX. cascaded mode, autosequencer functions single 16-channel sequencer. each sequencer, once conversion complete, selected channel value stored respective RESULT register. Autosequencing allows system convert same channel multiple times, allowing user perform oversampling algorithms. This gives increased resolution over traditional single-sampled conversion results.
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SYSCLKOUT C28x
System Control Block
High-Speed Prescaler
ADCENCLK Analog ADCINA0 ADCINA7 12-Bit Module ADCINB0 ADCINB7
HSPCLK
Result Registers Result Result 70A8h
Result Result
70AFh 70B0h
Result
70B7h
Control Registers ADCSOC Sequencer Sequencer
Figure 4-4. Block Diagram R281x Module obtain specified accuracy ADC, proper board layout very critical. best extent possible, traces leading ADCIN pins should close proximity digital signal paths. This minimize switching noise digital lines from getting coupled inputs. Furthermore, proper isolation techniques must used isolate module power pins (VDDA1/VDDA2 AVDDREFBG from digital supply. Figure shows connections R281x devices. Notes: registers accessed SYSCLKOUT rate. internal timing module controlled high-speed peripheral clock (HSPCLK). behavior module based state ADCENCLK HALT signals follows: ADCENCLK: reset, this signal will low. While reset active-low (XRS) clock register will still function. This necessary make sure registers modes into their default reset state. analog module will however low-power inactive state. soon reset goes high, then clock registers will disabled. When user sets ADCENCLK signal high, then clocks registers will enabled analog module will enabled. There will certain time delay range) before stable used. HALT: This signal only affects analog module. does affect registers. low, module powered. high, module goes into low-power mode. HALT mode will stop clock CPU, which will stop HSPCLK. Therefore register logic will turned indirectly. Figure shows pin-biasing internal reference Figure shows pin-biasing external reference.
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16-Channel Analog Inputs
ADCINA[7:0] ADCINB[7:0] ADCLO Test ADCBGREFIN ADCRESEXT ADCREFP ADCREFM VDDA1 VDDA2 VSSA1 VSSA2 AVDDREFBG AVSSREFBG VDDAIO VSSAIO VDD1 VSS1
Analog input with respect ADCLO Connect Analog Ground 24.9
External Current Bias Resistor Reference Positive Output Reference Medium Output
ADCREFP ADCREFM should loaded external circuitry Analog Analog
Analog Power
Reference Power
Analog
Analog Power
Analog Analog Ground same supply Digital Ground digital core separate with ferrite bead filter
Digital Power
Provide access this layouts. Intended test purposes only. TAIYO YUDEN EMK325F106ZH, EMK325BJ106MD, equivalent 24.9-k resistor applicable full range ADC. NOTES: External decoupling capacitors recommended power pins. Analog inputs must driven from operational amplifier that does degrade performance.
Figure 4-5. Connections With Internal Reference (See Notes NOTE: temperature rating recommended component must match rating product.
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16-Channel Analog Inputs Test External Current Bias Resistor Reference Positive Input Reference Medium Input
ADCINA[7:0] ADCINB[7:0] ADCLO ADCBGREFIN ADCRESEXT ADCREFP ADCREFM
Analog Input With Respect ADCLO Connect Analog Ground 24.9 (See Note
Analog Power
VDDA1 VDDA2 VSSA1 VSSA2 AVDDREFBG AVSSREFBG VDDAIO VSSAIO VDD1 VSS1
Analog Analog
Reference Power
Analog
Analog Power
Analog Analog Ground same 1.8-V 1.9-V) Digital Ground supply digital core separate with ferrite bead filter
Digital Power
NOTES: External decoupling capacitors recommended power pins. Analog inputs must driven from operational amplifier that does degrade performance. recommended that buffered external references provided with voltage difference (ADCREFP-ADCREFM) 0.1% better. External reference enabled using ADCTRL3 Register power this mode, accuracy external reference critical overall gain. voltage ADCREFP-ADCREFM will determine overall accuracy. enable internal references when external references connected ADCREFP ADCREFM. TMS320F28x Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU060) more information.
Figure 4-6. Connections With External Reference
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operation configured, controlled, monitored registers listed Table 4-4. Table 4-4. Registers
NAME ADCTRL1 ADCTRL2 ADCMAXCONV ADCCHSELSEQ1 ADCCHSELSEQ2 ADCCHSELSEQ3 ADCCHSELSEQ4 ADCASEQSR ADCRESULT0 ADCRESULT1 ADCRESULT2 ADCRESULT3 ADCRESULT4 ADCRESULT5 ADCRESULT6 ADCRESULT7 ADCRESULT8 ADCRESULT9 ADCRESULT10 ADCRESULT11 ADCRESULT12 ADCRESULT13 ADCRESULT14 ADCRESULT15 ADCTRL3 ADCST reserved ADDRESS 0x00 7100 0x00 7101 0x00 7102 0x00 7103 0x00 7104 0x00 7105 0x00 7106 0x00 7107 0x00 7108 0x00 7109 0x00 710A 0x00 710B 0x00 710C 0x00 710D 0x00 710E 0x00 710F 0x00 7110 0x00 7111 0x00 7112 0x00 7113 0x00 7114 0x00 7115 0x00 7116 0x00 7117 0x00 7118 0x00 7119 0x00 711C 0x00 711F SIZE (x16) Control Register Control Register Maximum Conversion Channels Register Channel Select Sequencing Control Register Channel Select Sequencing Control Register Channel Select Sequencing Control Register Channel Select Sequencing Control Register Auto-Sequence Status Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Conversion Result Buffer Register Control Register Status Register DESCRIPTION
above registers Peripheral Frame Registers.
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Enhanced Controller Area Network (eCAN) Module
module following features: Fully compliant with protocol, version 2.0B Supports data rates Mbps Thirty-two mailboxes, each with following properties: Configurable receive transmit Configurable with standard extended identifier programmable receive mask Supports data remote frame Composed bytes data Uses 32-bit time stamp receive transmit message Protects against reception message Holds dynamically programmable priority transmit message Employs programmable interrupt scheme with interrupt levels Employs programmable alarm transmission reception time-out
Low-power mode Programmable wake-up activity Automatic reply remote request message Automatic retransmission frame case loss arbitration error 32-bit local network time counter synchronized specific message (communication conjunction with mailbox Self-test mode Operates loopback mode receiving message. "dummy" acknowledge provided, thereby eliminating need another node provide acknowledge bit.
NOTE: SYSCLKOUT MHz, smallest rate possible 23.4 kbps. passed conformance test ISO/DIS 16845. Contact further details.
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eCAN0INT eCAN1INT Controls Address Data
Enhanced Controller
Message Controller Mailbox (512 Bytes) 32-Message Mailbox 32-Bit Words Memory Management Unit Interface, Receive Control Unit, Timer Management Unit
eCAN Memory (512 Bytes) Registers Message Objects Control
eCAN Protocol Kernel Receive Buffer Transmit Buffer Control Buffer Status Buffer
SN65HVD23x 3.3-V Transceiver
Figure 4-7. eCAN Block Diagram Interface Circuit Table 4-5. 3.3-V eCAN Transceivers R281x DSPs
PART NUMBER SUPPLY VOLTAGE LOW-POWER MODE Standby Standby Sleep Sleep None None Standby SLOPE CONTROL Adjustable Adjustable Adjustable Adjustable None None Adjustable VREF OTHER -40°C 85°C -40°C 125°C -40°C 85°C -40°C 125°C -40°C 85°C -40°C 125°C -40°C 125°C
SN65HVD230 SN65HVD230Q SN65HVD231 SN65HVD231Q SN65HVD232 SN65HVD232Q SN65HVD233
None None None
Diagnostic Loopback
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Table 4-5. 3.3-V eCAN Transceivers TMS320R281x DSPs (Continued)
PART NUMBER SUPPLY VOLTAGE LOW-POWER MODE Standby Sleep Standby SLOPE CONTROL Adjustable Adjustable VREF OTHER -40°C 125°C -40°C 125°C
SN65HVD234 SN65HVD235
None None
Autobaud Loopback
eCAN Control Status Registers Mailbox Enable CANME Mailbox Direction CANMD Transmission Request CANTRS Transmission Request Reset CANTRR Transmission Acknowledge CANTA eCAN Memory (512 Bytes) 6000h 603Fh 6040h 607Fh 6080h 60BFh 60C0h 60FFh Local Acceptance Masks (LAM) 32-Bit RAM) Message Object Time Stamps (MOTS) 32-Bit RAM) Message Object Time-Out (MOTO) 32-Bit RAM) Control Status Registers Abort Acknowledge CANAA Received Message Pending CANRMP Received Message Lost CANRML Remote Frame Pending CANRFP Global Acceptance Mask CANGAM Master Control CANMC Bit-Timing Configuration CANBTC Error Status CANES Transmit Error Counter CANTEC Receive Error Counter CANREC Global Interrupt Flag CANGIF0 Global Interrupt Mask CANGIM eCAN Memory (512 Bytes) 6100h-6107h 6108h-610Fh 6110h-6117h 6118h-611Fh 6120h-6127h Mailbox Mailbox Mailbox Mailbox Mailbox Global Interrupt Flag CANGIF1 Mailbox Interrupt Mask CANMIM Mailbox Interrupt Level CANMIL Overwrite Protection Control CANOPC Control CANTIOC Control CANRIOC Time Stamp Counter CANTSC Time-Out Control CANTOC Time-Out Status CANTOS 61E0h-61E7h 61E8h-61EFh 61F0h-61F7h 61F8h-61FFh Mailbox Mailbox Mailbox Mailbox Message Mailbox Bytes) 61E8h-61E9h 61EAh-61EBh 61ECh-61EDh 61EEh-61EFh Message Identifier MSGID Message Control MSGCTRL Message Data Message Data High Reserved
Figure 4-8. eCAN Memory
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Peripherals
registers listed Table used configure control controller message objects. eCAN control registers only support 32-bit read/write operations. Mailbox accessed bits bits. 32-bit accesses aligned even boundary. Table 4-6. Registers
REGISTER NAME CANME CANMD CANTRS CANTRR CANTA CANAA CANRMP CANRML CANRFP CANGAM CANMC CANBTC CANES CANTEC CANREC CANGIF0 CANGIM CANGIF1 CANMIM CANMIL CANOPC CANTIOC CANRIOC CANTSC CANTOC CANTOS ADDRESS 0x00 6000 0x00 6002 0x00 6004 0x00 6006 0x00 6008 0x00 600A 0x00 600C 0x00 600E 0x00 6010 0x00 6012 0x00 6014 0x00 6016 0x00 6018 0x00 601A 0x00 601C 0x00 601E 0x00 6020 0x00 6022 0x00 6024 0x00 6026 0x00 6028 0x00 602A 0x00 602C 0x00 602E 0x00 6030 0x00 6032 SIZE (x32) Mailbox enable Mailbox direction Transmit request Transmit request reset Transmission acknowledge Abort acknowledge Receive message pending Receive message lost Remote frame pending Global acceptance mask Master control Bit-timing configuration Error status Transmit error counter Receive error counter Global interrupt flag Global interrupt mask Global interrupt flag Mailbox interrupt mask Mailbox interrupt level Overwrite protection control control control Time stamp counter (Reserved mode) Time-out control (Reserved mode) Time-out status (Reserved mode) DESCRIPTION
These registers mapped Peripheral Frame
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Multichannel Buffered Serial Port (McBSP) Module
McBSP module following features: Compatible McBSP TMS320C54x /TMS320C55x devices, except features Full-duplex communication Double-buffered data registers which allow continuous data stream Independent framing clocking receive transmit External shift clock generation internal programmable frequency shift clock wide selection data sizes including 12-, 16-, 20-, 24-, 32-bits 8-bit data transfers with first Programmable polarity both frame synchronization data clocks HIghly programmable internal clock frame generation Support A-bis mode Direct interface industry-standard CODECs, Analog Interface Chips (AICs), other serially connected devices Works with SPI-compatible devices 16-level FIFO Transmit channel 16-level FIFO Receive channel
following application interfaces supported McBSP: T1/E1 framers MVIP switching-compatible ST-BUS-compliant devices including: MVIP framers H.100 framers SCSA framers IOM-2 compliant devices AC97-compliant devices (the necessary multiphase frame synchronization capability provided.) IIS-compliant devices CLKSRG where CLKSRG source could LSPCLK, CLKX, CLKR. CLKGDIV)
McBSP clock rate CLKG
Serial port performance limited buffer switching speed. Internal prescalers must adjusted such that peripheral speed less than buffer speed limit-20-MHz maximum. Figure shows block diagram McBSP module with FIFO, interfaced R281x version Peripheral Frame
TMS320C54x TMS320C55x trademarks Texas Instruments. SPRS257B June 2004 Revised Febrtuary 2005
Peripherals
Peripheral Write
MXINT Interrupt Logic
FIFO Interrupt
FIFO FIFO
FIFO FIFO FIFO
McBSP Transmit Interrupt Select Logic
FIFO
FIFO Registers DXR1 Transmit Buffer Compand Logic XSR2 XSR1 CLKX
LSPCLK McBSP Registers Control Logic
DXR2 Transmit Buffer
RSR2 RBR2 Register McBSP DRR2 Receive Buffer McBSP Receive Interrupt Select Logic FIFO Interrupt FIFO MRINT Interrupt Logic FIFO FIFO
RSR1 Expand Logic
CLKR
RBR1 Register DRR1 Receive Buffer FIFO FIFO FIFO
FIFO Registers Peripheral Read
Figure 4-9. McBSP Module With FIFO
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Table provides summary McBSP registers. Table 4-7. McBSP Register Summary
NAME ADDRESS 0x00 78xxh TYPE (R/W) RESET VALUE (HEX) DESCRIPTION
DATA REGISTERS, RECEIVE, TRANSMIT DRR2 0x0000 0x0000 0x0000 0x0000 McBSP Receive Buffer Register McBSP Receive Shift Register McBSP Transmit Shift Register McBSP Data Receive Register Read First word size greater than bits, else ignore DRR2 McBSP Data Receive Register Read Second word size greater than bits, else read DRR1 only McBSP Data Transmit Register Write First word size greater than bits, else ignore DXR2 McBSP Data Transmit Register Write Second word size greater than bits, else write DXR1 only McBSP Serial Port Control Register McBSP Serial Port Control Register McBSP Receive Control Register McBSP Receive Control Register McBSP Transmit Control Register McBSP Transmit Control Register McBSP Sample Rate Generator Register McBSP Sample Rate Generator Register McBSP Multichannel Register McBSP Multichannel Register McBSP Receive Channel Enable Register Partition McBSP Receive Channel Enable Register Partition McBSP Transmit Channel Enable Register Partition McBSP Transmit Channel Enable Register Partition McBSP Control Register McBSP Receive Channel Enable Register Partition McBSP Receive Channel Enable Register Partition McBSP Transmit Channel Enable Register Partition
DRR1
0x0000
DXR2
0x0000
DXR1
0x0000
McBSP CONTROL REGISTERS SPCR2 SPCR1 RCR2 RCR1 XCR2 XCR1 SRGR2 SRGR1 MCR2 MCR1 RCERA RCERB XCERA XCERB RCERC RCERD XCERC XCERD 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000
MULTICHANNEL CONTROL REGISTERS
McBSP Transmit Channel Enable Register Partition DRR2/DRR1 DXR2/DXR1 share same addresses receive transmit FIFO registers FIFO mode. FIFO pointers advancing based order access DRR2/DRR1 DXR2/DXR1 registers.
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Table 4-7. McBSP Register Summary (Continued)
NAME ADDRESS 0x00 78xxh TYPE (R/W) RESET VALUE (HEX) DESCRIPTION
MULTICHANNEL CONTROL REGISTERS (CONTINUED) RCERE RCERF XCERE XCERF RCERG RCERH XCERG XCERH 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 McBSP Receive Channel Enable Register Partition McBSP Receive Channel Enable Register Partition McBSP Transmit Channel Enable Register Partition McBSP Transmit Channel Enable Register Partition McBSP Receive Channel Enable Register Partition McBSP Receive Channel Enable Register Partition McBSP Transmit Channel Enable Register Partition McBSP Transmit Channel Enable Register Partition
FIFO MODE REGISTERS (applicable only FIFO mode) FIFO Data Registers DRR2 DRR1 DXR2 DXR1 0x0000 0x0000 0x0000 0x0000 McBSP Data Receive Register receive FIFO Read First FIFO pointers will advance McBSP Data Receive Register receive FIFO Read Second FIFO pointers advance McBSP Data Transmit Register transmit FIFO Write First FIFO pointers will advance McBSP Data Transmit Register transmit FIFO Write Second FIFO pointers advance
FIFO Control Registers MFFTX MFFRX MFFCT MFFINT 0xA000 0x201F 0x0000 0x0000 McBSP Transmit FIFO Register McBSP Receive FIFO Register McBSP FIFO Control Register McBSP FIFO Interrupt Register
MFFST 0x0000 McBSP FIFO Status Register DRR2/DRR1 DXR2/DXR1 share same addresses receive transmit FIFO registers FIFO mode. FIFO pointers advancing based order access DRR2/DRR1 DXR2/DXR1 registers.
Serial Communications Interface (SCI) Module
R281x devices include serial communications interface (SCI) modules. modules support digital communications between other asynchronous peripherals that standard non-return-to-zero (NRZ) format. receiver transmitter double-buffered, each separate enable interrupt bits. Both operated independently simultaneously full-duplex mode. ensure data integrity, checks received data break detection, parity, overrun, framing errors. rate programmable over different speeds through 16-bit baud-select register. Features each module include: external pins: SCITXD: transmit-output SCIRXD: receive-input Both pins used GPIO used SCI.
NOTE:
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Baud rate programmable different rates Baud rate LSPCLK when (BRR LSPCLK when
Serial port performance limited buffer switching speed. Internal prescalers must adjusted such that peripheral speed less than buffer speed limit-20 maximum. Data-word format start Data-word length programmable from eight bits Optional even/odd/no parity stop bits
Four error-detection flags: parity, overrun, framing, break detection wake-up multiprocessor modes: idle-line address Half- full-duplex operation Double-buffered receive
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