TMS320F28020 TMS320F28021 TMS320F28022 TMS320F28023 TMS320F28026 TMS320F28027 TMS320F2802x

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TMS320F28020 TMS320F28021 TMS320F28022 TMS320F28023 TMS320F28026 TMS320F28027 TMS320F2802x

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TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
TMS320F2802x (PiccoloTM) MCUs
High-Efficiency 32-Bit (TMS320C28xTM) (16.67-ns Cycle Time) (25-ns Cycle Time) Operations Dual Harvard Architecture Atomic Operations Fast Interrupt Response Processing Unified Memory Programming Model Code-Efficient C/C++ Assembly) Device System Cost: Single 3.3-V Supply Power Sequencing Requirement Integrated Power-on Reset Brown-out Reset Small Packaging, 38-Pin Available Power Analog Support Pins Clocking: Internal Zero-pin Oscillators On-chip Crystal Oscillator/External Clock Input Dynamic Ratio Changes Supported Watchdog Timer Module Missing Clock Detection Circuitry Individually Programmable, Multiplexed GPIO Pins With Input Filtering Peripheral Interrupt Expansion (PIE) Block That Supports Peripheral Interrupts Three 32-Bit Timers Independent 16-bit Timer Each ePWM Module On-Chip Memory Flash, SARAM, OTP, Boot Available 128-Bit Security Key/Lock Protects Secure Memory Blocks Prevents Firmware Reverse Engineering Serial Port Peripherals (UART) Module Module Inter-Integrated-Circuit (I2C) Advanced Emulation Features Analysis Breakpoint Functions Real-Time Debug Hardware Enhanced Control Peripherals Enhanced Pulse Width Modulator (ePWM) High-resolution (HRPWM) Enhanced Capture (eCAP) Analog-to-Digital Converter (ADC) On-Chip Temperature Sensor Comparator 2802x Packages 38-Pin Plastic Small-Outline Package (PSOP) 48-Pin Plastic Quad Flatpack (PQFP)
Description
F2802x Piccolofamily microcontrollers provides power C28xcore coupled with highly integrated control peripherals pin-count devices. This family code compatible with previous C28-based code, well providing high level analog integration. internal voltage regulator allows single rail operation. Enhancements have been made HRPWM module allow dual-edge control (frequency modulation). Analog comparators with internal 10-bit references have been added routed directly control outputs. converts from 3.3-V fixed full scale range supports ratio-metric VREFHI/VREFLO references. interface been optimized overhead/latency.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this document. Piccolo, TMS320C28x, C28x, TMS320C2000, Code Composer Studio, XDS510 trademarks Texas Instruments. other trademarks property their respective owners.
ADVANCE INFORMATION concerns products sampling preproduction phase development. Characteristic data other specifications subject change without notice.
Copyright 2008-2009, Texas Instruments Incorporated
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TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
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Getting Started
This section gives brief overview steps take when first developing C28x device. more detail each these steps, following: Getting Started With TMS320C28x Digital Signal Controllers (literature number SPRAAM0). C2000 Getting Started Website TMS320F28x Development Experimenter's Kits (http://www.ti.com/f28xkits)
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Contents
TMS320F2802x (PiccoloTM) MCUs
Features Description Getting Started. High-Resolution (HRPWM) Enhanced Capture Module (eCAP1) JTAG Port GPIO
6.10 6.11 6.12
Thermal Design Considerations Emulator Connection Without Signal Buffering Timing Parameter Symbology Clock Requirements Characteristics
Power Sequencing General-Purpose Input/Output (GPIO) Enhanced Control Peripherals Detailed Descriptions
Revision History Mechanicals
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Contents
ADVANCE INFORMATION
Assignments Signal Descriptions Functional Overview Block Diagram Memory Maps Brief Descriptions. Register Device Emulation Registers Interrupts VREG/BOR/POR System Control Low-power Modes Block Peripherals. Analog Block Serial Peripheral Interface (SPI) Module Serial Communications Interface (SCI) Module Inter-Integrated Circuit (I2C) Enhanced Modules (ePWM1/2/3/4)
Hardware Features
Device Support
Device Development Support Tool Nomenclature Related Documentation Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics
Electrical Specifications
Current Consumption.
TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
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Hardware Features
Table lists features TMS320F2802x devices.
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Table 2-1. Hardware Features
FEATURE Package Type Instruction cycle On-chip flash (16-bit word) On-chip SARAM (16-bit word) Code security on-chip flash/SARAM/OTP blocks Boot One-time programmable (OTP) (16-bit word) ePWM outputs eCAP inputs Watchdog timer MSPS Conversion Time 12-Bit Channels Temperature Sensor 32-Bit timers HiRES ePWM Channels Comparators Integrated DACs Inter-integrated circuit (I2C) Serial Peripheral Interface (SPI) Serial Communications Interface (SCI) pins (shared) Digital (GPIO) Analog (AIO) TYPE
28020 MHz) 38-Pin PSOP (ePWM1/2/3/4) 48-Pin PQFP
28021 MHz) 38-Pin PSOP (ePWM1/2/3/4) 48-Pin PQFP
28022 MHz) 38-Pin PSOP (ePWM1/2/3/4) (ePWM1A/2A/3A/4A) 48-Pin PQFP
28023 MHz) 38-Pin PSOP (ePWM1/2/3/4) (ePWM1A/2A/3A/4A) 48-Pin PQFP
28026 MHz) 38-Pin PSOP 48-Pin PQFP
28027 MHz) 38-Pin PSOP 48-Pin PQFP
16.67 (ePWM1/2/3/4) 216.67 (ePWM1A/2A/3A/4A)
16.67 (ePWM1/2/3/4) 216.67 (ePWM1A/2A/3A/4A)
External interrupts Supply voltage (nominal) Temperature options Product status 40°C 105°C 40°C 125°C
type change represents major functional feature difference peripheral module. Within peripheral type, there minor differences between devices that affect basic functionality module. These device-specific differences listed TMS320x28xx, 28xxx Peripheral Reference Guide (SPRU566) peripheral reference guides. Section 5.1, Device Development Support Nomenclature descriptions device stages. experimental device that necessarily representative final device's electrical specifications. fully qualified production device.
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Hardware Features
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Assignments
Figure shows 48-pin plastic quad flatpack (PQFP) assignments. Figure shows 38-pin plastic small outline package (PSOP) assignments.
GPIO33/SCLA/EPWMSYNCO/ADCSOCBO VDDIO VREGENZ GPIO32/SDAA/EPWMSYNCI/ADCSOCAO TEST GPIO0/EPWM1A GPIO1/EPWM1B/COMP1OUT GPIO16/SPISIMOA/TZ2 GPIO17/SPISOMIA/TZ3
Figure 2-1. 2802x 48-Pin PQFP (Top View)
Hardware Features
GPIO29/SCITXDA/SCLA/TZ3
TRST ADCINA6/AIO6 ADCINA4/COMP2A/AIO4 ADCINA7 ADCINA3 ADCINA1 ADCINA2/COMP1A/AIO2 ADCINA0/VREFHI VDDA VSSA/VREFLO
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GPIO2/EPWM2A GPIO3/EPWM2B/COMP2OUT GPIO4/EPWM3A GPIO5/EPWM3B/ECAP1 GPIO7/EPWM4B/SCIRXDA GPIO12/TZ1/SCITXDA GPIO28/SCIRXDA/SDAA/TZ2
GPIO18/SPICLKA/SCITXDA/XCLKOUT GPIO38/XCLKIN (TCK) GPIO37 (TDO) GPIO36 (TMS) GPIO35 (TDI) GPIO34/COMP2OUT ADCINB7 ADCINB6/AIO14 ADCINB4/COMP2B/AIO12 ADCINB3 ADCINB2/COMP1B/AIO10 ADCINB1
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Figure 2-2. 2802x 38-Pin PSOP (Top View)
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Hardware Features
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VREGENZ VDDIO GPIO2/EPWM2A GPIO3/EPWM2B GPIO4/EPWM3A GPIO5/EPWM3B/ECAP1 GPIO7/EPWM4B/SCIRXDA GPIO12/TZ1/SCITXDA GPIO28/SCIRXDA/SDAA/TZ2 GPIO29/SCITXDA/SCLA/TZ3 TRST ADCINA6/AIO6 ADCINA4/AIO4
TEST GPIO0/EPWM1A GPIO1/EPWM1B/COMP1OUT GPIO16/SPISIMOA/TZ2 GPIO17/SPISOMIA/TZ3 GPIO18/SPICLKA/SCITXDA/XCLKOUT GPIO38/XCLKIN (TCK) GPIO37 (TDO) GPIO36 (TMS) GPIO35 (TDI) GPIO34/COMP2OUT ADCINB6/AIO14 ADCINB4/AIO12 ADCINB2/COMP1B/AIO10 VSSA/VREFLO VDDA ADCINA0/VREFHI ADCINA2/COMP1A/AIO2
TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
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Signal Descriptions
Table 2-2. TERMINAL FUNCTIONS
TERMINAL NAME I/O/Z JTAG JTAG test reset with internal pulldown. TRST, when driven high, gives scan system control operations device. this signal connected driven low, device operates functional mode, test reset signals ignored. NOTE: TRST active high test must maintained times during normal device operation. external pulldown resistor recommended this pin. value this resistor should based drive strength debugger pods applicable design. 2.2-k resistor generally offers adequate protection. Since this application-specific, recommended that each target board validated proper operation debugger application. GPIO38. JTAG test clock with internal pullup GPIO36. JTAG test-mode select (TMS) with internal pullup. This serial control input clocked into controller rising edge TCK. GPIO35. JTAG test data input (TDI) with internal pullup. clocked into selected register (instruction data) rising edge TCK. GPIO37. JTAG scan out, test data output (TDO). contents selected register (instruction data) shifted falling edge TCK. drive) FLASH TEST Test Pin. Reserved Must left unconnected. CLOCK GPIO18. Output clock derived from SYSCLKOUT. XCLKOUT either same frequency, one-half frequency, one-fourth frequency SYSCLKOUT. This controlled bits (XCLKOUTDIV) XCLK register. reset, XCLKOUT SYSCLKOUT/4. XCLKOUT signal turned setting XCLKOUTDIV control GPIO18 must also XCLKOUT this signal propogate pin. GPIO19 GPIO38. External oscillator input. source clock controlled XCLKINSEL XCLK register, GPIO38 default selection. This feeds clock from external 3.3-V oscillator. this case, pin, available, must tied on-chip crystal oscillator must disabled CLKCTL register. crystal/resonator used, XCLKIN path must disabled CLKCTL register. Note: Designs that GPIO38/TCK/XCLKIN supply external clock normal device operation need incorporate some hooks disable this path during debug using JTAG connector. This prevent contention with signal, which active during JTAG debug sessions. zero-pin internal oscillators used during this time clock device. On-chip crystal-oscillator input. this oscillator, quartz crystal ceramic resonator must connected across this case, XCLKIN path must disabled CLKCTL register. this used, must tied GND. On-chip crystal-oscillator output. quartz crystal ceramic resonator must connected across used, must left unconnected. DESCRIPTION
TRST
ADVANCE INFORMATION
GPIO38 GPIO36 GPIO35 GPIO37
XCLKOUT
GPIO18
XCLKIN
GPIO19 GPIO38
Input, Output, High Impedance, Open Drain, Pullup, Pulldown
Hardware Features
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Table 2-2. TERMINAL FUNCTIONS (continued)
TERMINAL NAME I/O/Z RESET Device Reset (in) Watchdog Reset (out). Piccolo devices have built-in power-on-reset (POR) brown-out-reset (BOR) circuitry. such, external circuitry needed generate reset pulse. During power-on brown-out condition, this driven device. electrical section thresholds POR/BOR block. This also driven when watchdog reset occurs. During watchdog reset, driven watchdog reset duration OSCCLK cycles. need external circuitry also drive this assert device reset. this case, recommended that this driven open-drain device circuit must connected this noise immunity reasons. Regardless source, device reset causes device terminate execution. program counter points address contained location 0x3FFFC0. When reset deactivated, execution begins location designated program counter. output buffer this open-drain with internal pullup. (I/OD) ADC, COMPARATOR, ANALOG ADCINA7 ADCINA6 AIO6 ADCINA4 COMP2A AIO4 ADCINA3 ADCINA2 COMP1A AIO2 ADCINA1 ADCINA0 VREFHI ADCINB7 ADCINB6 AIO14 ADCINB4 COMP2B AIO12 ADCINB3 ADCINB2 COMP1B AIO10 ADCINB1 VDDA VSSA VREFLO VDDIO Group Channel input Group Channel input Digital Group Channel input Comparator Input (available 48-pin device only) Digital Group Channel input Group Channel input Comparator Input Digital Group Channel input Group Channel input External Reference only used when external reference mode. Section. Group Channel input Group Channel input Digital Group Channel input Comparator Input (available 48-pin device only) Digital AIO12 Group Channel input Group Channel input Comparator Input Digital Group Channel input POWER Analog Power Analog Ground Reference (always tied ground) Logic Digital Power Pins supply source needed when using internal VREG. with (minimum) ceramic capacitor ground when using internal VREG. Digital Flash Power Single Supply source when VREG enabled Digital Ground Pins DESCRIPTION
I/OD
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Hardware Features
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Table 2-2. TERMINAL FUNCTIONS (continued)
TERMINAL NAME I/O/Z DESCRIPTION
VOLTAGE REGULATOR CONTROL SIGNAL VREGENZ Internal VREG Enable/Disable. Pull enable internal voltage regulator (VREG), pull high disable VREG. GPIO PERIPHERAL SIGNALS GPIO0 EPWM1A GPIO1 EPWM1B COMP1OUT GPIO2 EPWM2A GPIO3 EPWM2B COMP2OUT GPIO4 EPWM3A GPIO5 EPWM3B ECAP1 GPIO6 EPWM4A EPWMSYNCI EPWMSYNCO GPIO7 EPWM4B SCIRXDA GPIO12 SCITXDA GPIO16 SPISIMOA I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Direct output Comparator General purpose input/output Enhanced PWM2 Output HRPWM channel General purpose input/output Enhanced PWM2 Output Direct output Comparator (available 48-pin device only) General purpose input/output Enhanced PWM3 output HRPWM channel General purpose input/output Enhanced PWM3 output Enhanced Capture input/output General purpose input/output Enhanced PWM4 output HRPWM channel External ePWM sync pulse input External ePWM sync pulse output General purpose input/output Enhanced PWM4 output SCI-A receive data General purpose input/output Trip Zone input SCI-A transmit data General purpose input/output slave master Trip Zone input General purpose input/output Enhanced PWM1 Output HRPWM channel General purpose input/output Enhanced PWM1 Output
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Hardware Features
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Table 2-2. TERMINAL FUNCTIONS (continued)
TERMINAL NAME GPIO17 SPISOMIA GPIO18 SPICLKA SCITXDA I/O/Z I/O/Z I/O/Z General purpose input/output SPI-A slave out, master Trip zone input General purpose input/output SPI-A clock input/output SCI-A transmit Output clock derived from SYSCLKOUT. XCLKOUT either same frequency, one-half frequency, one-fourth frequency SYSCLKOUT. This controlled bits (XCLKOUTDIV) XCLK register. reset, XCLKOUT SYSCLKOUT/4. XCLKOUT signal turned setting XCLKOUTDIV control GPIO18 must also XCLKOUT this signal propogate pin. General purpose input/output External Oscillator Input. path from this clock block gated function this pin. Care must taken enable this path clocking being used other periperhal functions I/O/Z I/OC I/O/Z I/OC I/O/Z I/OC I/O/Z I/OC I/O/Z SPI-A slave transmit enable input/output SCI-A receive Enhanced Capture input/output General purpose input/output receive data data open-drain bidirectional port Trip zone input General purpose input/output transmit data clock open-drain bidirectional port Trip zone input General purpose input/output data open-drain bidirectional port Enhanced external sync pulse input start-of-conversion General-Purpose Input/Output clock open-drain bidirectional port Enhanced external synch pulse output start-of-conversion General-Purpose Input/Output Direct output Comparator I/O/Z I/O/Z General-Purpose Input/Output JTAG test data input (TDI) with internal pullup. clocked into selected register (instruction data) rising edge General-Purpose Input/Output JTAG test-mode select (TMS) with internal pullup. This serial control input clocked into controller rising edge TCK. DESCRIPTION
GPIO19 XCLKIN SPISTEA SCIRXDA ECAP1 GPIO28 SCIRXDA SDAA GPIO29 SCITXDA SCLA GPIO32 SDAA EPWMSYNCI ADCSOCAO GPIO33 SCLA EPWMSYNCO ADCSOCBO GPIO34 COMP2OUT GPIO35 GPIO36
I/O/Z
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Hardware Features
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XCLKOUT
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Table 2-2. TERMINAL FUNCTIONS (continued)
TERMINAL NAME GPIO37 GPIO38 XCLKIN I/O/Z I/O/Z I/O/Z General-Purpose Input/Output JTAG scan out, test data output (TDO). contents selected register (instruction data) shifted falling edge drive) General-Purpose Input/Output JTAG test clock with internal pullup External Oscillator Input. path from this clock block gated function this pin. Care must taken enable this path clocking being used other functions. DESCRIPTION
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Functional Overview
Block Diagram
Memory
SARAM (0-wait) SARAM (0-wait) Secure SARAM 1K/3K/4K (0-wait) Secure Code Security Module FLASH 16K/32K Secure
Boot-ROM (0-wait)
Memory
TRST COMP1OUT
32-bit periph eral
GPIO
COMP2OUT
C28x 32-bit
COMP1A COMP1B COMP2A COMP2B
GPIO
COMP
External Interrupts XCLKIN Wakeup
Timer Timer Timer A7:0 Memory
OSC1, OSC2, Ext, PLL, LPM,
B7:0
POR/
VREG
16-bit Peripheral
32-bit Peripheral
32-Bit Peripheral
FIFO)
FIFO)
FIFO)
ePWM eCAP HRPWM
EPWMxA EPWMxB ESYNCO
SPISIMOx
SPISOMIx
SCIRXDx
SCITXDx
SPICLKx
SPISTEx
ESYNCI
From COMP1OUT, COMP2OUT
GPIO
peripheral pins available same time multiplexing.
Figure 3-1. Functional Block Diagram
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SDAx
SCLx
Functional Overview
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PSWD
OTP/Flash Wrapper
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Memory Maps
Figure 3-2, Figure 3-3, Figure 3-4, Figure 3-5, following apply: Memory blocks scale. Peripheral Frame Peripheral Frame Peripheral Frame memory maps restricted data memory only. user program cannot access these memory maps program space. Protected means order Write-followed-by-Read operations preserved rather than pipeline order. Certain memory ranges EALLOW protected against spurious writes after configuration. Locations 0x3D7C80 0x3D7CC0 contain internal oscillator calibration routines. These locations programmable user.
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Data Space 0x00 0000 0x00 0040 0x00 0400 0x00 0800
Prog Space
Vector (Enabled VMAP SARAM 0-Wait) SARAM 0-Wait) Peripheral Frame Vector (256 (Enabled VMAP ENPIE Peripheral Frame Reserved
(24x/240x Equivalent Data Space)
0x00 0D00
Reserved
0x00 0E00 0x00 2000 0x00 6000
0x00 7000
Reserved Peripheral Frame Protected)
0x00 8000
SARAM (0-Wait, Secure Zone ECSL, Dual Mapped) Reserved User Secure Zone ECSL) Reserved Calibration Data
0x00 8400 0x3D 7800 0x3D 7C00 0x3D 7C80 0x3D 7CC0 0x3D 8000
Reserved
High (24x/240x Equivalent Program Space)
0x3F 4000 FLASH (16K Sectors, Secure Zone ECSL) 0x3F 7FF8 0x3F 8000 128-Bit Password SARAM (0-Wait, Secure Zone ECSL, Dual Mapped) Reserved Boot 0-Wait) Vector Vectors, Enabled VMAP
0x3F 8400 0x3F E000 0x3F FFC0
Figure 3-2. 28020 Memory
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Functional Overview
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Peripheral Frame Protected)
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Data Space 0x00 0000 0x00 0040 0x00 0400 0x00 0800
Prog Space
Vector (Enabled VMAP SARAM 0-Wait) SARAM 0-Wait) Peripheral Frame Vector (256 (Enabled VMAP ENPIE Peripheral Frame Reserved Peripheral Frame Protected)
(24x/240x Equivalent Data Space)
0x00 0D00
Reserved
0x00 0E00 0x00 2000 0x00 6000
High (24x/240x Equivalent Program Space)
ADVANCE INFORMATION
0x00 7000
Reserved Peripheral Frame Protected)
0x00 8000
SARAM (0-Wait, Secure Zone ECSL, Dual Mapped) Reserved User Secure Zone ECSL) Reserved Calibration Data
0x00 8C00 0x3D 7800 0x3D 7C00 0x3D 7C80 0x3D 7CC0 0x3D 8000
Reserved
0x3F 0000 FLASH (32K Sectors, Secure Zone ECSL) 0x3F 7FF8 0x3F 8000 128-Bit Password SARAM (0-Wait, Secure Zone ECSL, Dual Mapped) Reserved Boot 0-Wait) Vector Vectors, Enabled VMAP
0x3F 8C00 0x3F E000 0x3F FFC0
Figure 3-3. 28021 Memory
Functional Overview
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Data Space 0x00 0000 0x00 0040 0x00 0400 0x00 0800
Prog Space
Vector (Enabled VMAP SARAM 0-Wait) SARAM 0-Wait) Peripheral Frame Vector (256 (Enabled VMAP ENPIE Peripheral Frame Reserved
(24x/240x Equivalent Data Space)
0x00 0D00
Reserved
0x00 0E00 0x00 2000 0x00 6000
0x00 7000
Reserved Peripheral Frame Protected)
0x00 8000
SARAM (0-Wait, Secure Zone ECSL, Dual Mapped) Reserved User Secure Zone ECSL) Reserved Calibration Data
0x00 9000 0x3D 7800 0x3D 7C00 0x3D 7C80 0x3D 7CC0 0x3D 8000
Reserved
High (24x/240x Equivalent Program Space)
0x3F 4000 FLASH (16K Sectors, Secure Zone ECSL) 0x3F 7FF8 0x3F 8000 128-Bit Password SARAM (0-Wait, Secure Zone ECSL, Dual Mapped) Reserved Boot 0-Wait) Vector Vectors, Enabled VMAP
0x3F 9000 0x3F E000 0x3F FFC0
Figure 3-4. 28022/28026 Memory
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Functional Overview
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Peripheral Frame Protected)
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Data Space 0x00 0000 0x00 0040 0x00 0400 0x00 0800
Prog Space
Vector (Enabled VMAP SARAM 0-Wait) SARAM 0-Wait) Peripheral Frame Vector (256 (Enabled VMAP ENPIE Peripheral Frame Reserved Peripheral Frame Protected)
(24x/240x Equivalent Data Space)
0x00 0D00
Reserved
0x00 0E00 0x00 2000 0x00 6000
High (24x/240x Equivalent Program Space)
ADVANCE INFORMATION
0x00 7000
Reserved Peripheral Frame Protected)
0x00 8000
SARAM (0-Wait, Secure Zone ECSL, Dual Mapped) Reserved User Secure Zone ECSL) Reserved Calibration Data
0x00 9000 0x3D 7800 0x3D 7C00 0x3D 7C80 0x3D 7CC0 0x3D 8000
Reserved
0x3F 0000 FLASH (32K Sectors, Secure Zone ECSL) 0x3F 7FF8 0x3F 8000 128-Bit Password SARAM (0-Wait, Secure Zone ECSL, Dual Mapped) Reserved Boot 0-Wait) Vector Vectors, Enabled VMAP
0x3F 9000 0x3F E000 0x3F FFC0
Figure 3-5. 28023/28027 Memory
Functional Overview
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Table 3-1. Addresses Flash Sectors F28021/28023/28027
ADDRESS RANGE 0x3F 0000 0x3F 1FFF 0x3F 2000 0x3F 3FFF 0x3F 4000 0x3F 5FFF 0x3F 6000 0x3F 7F7F 0x3F 7F80 0x3F 7FF5 0x3F 7FF6 0x3F 7FF7 0x3F 7FF8 0x3F 7FFF PROGRAM DATA SPACE Sector Sector Sector Sector Program 0x0000 when using Code Security Module Boot-to-Flash Entry Point (program branch instruction here) Security Password (128-Bit) program zeros)
Table 3-2. Addresses Flash Sectors F28020/28022/28026
ADDRESS RANGE 0x3F 4000 0x3F 4FFF 0x3F 5000 0x3F 5FFF 0x3F 6000 0x3F 6FFF 0x3F 7000 0x3F 7F7F 0x3F 7F80 0x3F 7FF5 0x3F 7FF6 0x3F 7FF7 0x3F 7FF8 0x3F 7FFF PROGRAM DATA SPACE Sector Sector Sector Sector Program 0x0000 when using Code Security Module Boot-to-Flash Entry Point (program branch instruction here) Security Password (128-Bit) program zeros)
NOTE When code-security passwords programmed, addresses between 0x3F 7F80 0x3F 7FF5 cannot used program code data. These locations must programmed 0x0000. code security feature used, addresses 0x3F 7F80 through 0x3F 7FEF used code data. Addresses 0x3F 7FF0 0x3F 7FF5 reserved data should contain program code. Table shows handle these memory locations.
Table 3-3. Impact Using Code Security Module
ADDRESS 0x3F 7F80 0x3F 7FEF 0x3F 7FF0 0x3F 7FF5 FLASH CODE SECURITY ENABLED Fill with 0x0000 CODE SECURITY DISABLED Application code data Reserved data only
Peripheral Frame Peripheral Frame grouped together enable these blocks write/read peripheral block protected. protected mode makes sure that accesses these blocks happen written. Because pipeline, write immediately followed read different memory locations, will appear reverse order memory CPU. This cause problems certain peripheral applications where user expected write occur first written). supports block protection mode where region memory protected that operations occur written (the penalty extra cycles added align operations). This mode programmable default, protects selected zones. wait-states various spaces memory area listed Table 3-4.
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Table 3-4. Wait-states
AREA SARAMs Peripheral Frame Peripheral Frame Peripheral Frame SARAM FLASH WAIT-STATES (CPU) 0-wait 0-wait 0-wait (writes) 2-wait (reads) 0-wait (writes) 2-wait (reads) 0-wait data program Programmable 1-wait minimum Programmable 0-wait Paged 1-wait Random Random Paged FLASH Password Boot-ROM 16-wait fixed 0-wait Wait states password locations fixed. Assumes conflicts Programmed Flash registers. 1-wait minimum number wait states allowed. Programmed Flash registers. Fixed. Cycles cannot extended peripheral. Cycles extended peripheral generated ready. Fixed COMMENTS
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Brief Descriptions 3.3.1
2802x (C28x) family member TMS320C2000microcontroller (MCU) platform. C28x-based controllers have same 32-bit fixed-point architecture existing C28x MCUs. very efficient C/C++ engine, enabling users develop only their system control software high-level language, also enabling development math algorithms using C/C++. device efficient math tasks system control tasks that typically handled microcontroller devices. This efficiency removes need second processor many systems. 32-bit 64-bit processing capabilities enable controller handle higher numerical resolution problems efficiently. this fast interrupt response with automatic context save critical registers, resulting device that capable servicing many asynchronous events with minimal latency. device 8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables execute high speeds without resorting expensive high-speed memories. Special branch-look-ahead hardware minimizes latency conditional discontinuities. Special store conditional operations further improve performance.
3.3.2
Memory (Harvard Architecture)
with many MCU-type devices, multiple busses used move data between memories peripherals CPU. memory architecture contains program read bus, data read bus, data write bus. program read consists address lines data lines. data read write busses consist address lines data lines each. 32-bit-wide data busses enable single cycle 32-bit operations. multiple architecture, commonly termed Harvard Bus, enables C28x fetch instruction, read data value write data value single cycle. peripherals memories attached memory prioritize memory accesses. Generally, priority memory accesses summarized follows: Highest: Data Writes Program Writes Data Reads Program Reads Lowest: Fetches (Simultaneous program reads fetches cannot occur memory bus.) (Simultaneous program reads fetches cannot occur memory bus.) (Simultaneous data program writes cannot occur memory bus.) (Simultaneous data program writes cannot occur memory bus.)
3.3.3
Peripheral
enable migration peripherals between various Texas Instruments (TI) family devices, devices adopt peripheral standard peripheral interconnect. peripheral bridge multiplexes various busses that make processor Memory into single consisting address lines data lines associated control signals. Three versions peripheral supported. version supports only 16-bit accesses (called peripheral frame Another version supports both 32-bit accesses (called peripheral frame
3.3.4
Real-Time JTAG Analysis
devices implement standard IEEE 1149.1 JTAG interface in-circuit based debug. Additionally, devices support real-time mode operation allowing modification contents memory, peripheral, register locations while processor running executing code servicing interrupts. user also single step through non-time-critical code while enabling time-critical interrupts serviced without interference. device implements real-time mode
IEEE Standard 1149.1-1990 Standard Test Access Port Boundary Scan Architecture Functional Overview
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hardware within CPU. This feature unique family devices, requiring software monitor. Additionally, special analysis hardware provided that allows setting hardware breakpoint data/address watch-points generating various user-selectable break events when match occurs. These devices support boundary scan; however, IDCODE BYPASS features available following considerations taken into account. IDCODE does come default. user needs through sequence SHIFT SHIFT state JTAG IDCODE. BYPASS instruction, first shifted value would
3.3.5
Flash
F28021/23/27 devices contain embedded flash memory, segregated into four sectors. F28020/22/26 devices contain embedded flash memory, segregated into four sectors. devices also contain single memory address range 0x3D 7800 0x3D 7BFF. user individually erase, program, validate flash sector while leaving other sectors untouched. However, possible sector flash execute flash algorithms that erase/program other sectors. Special memory pipelining provided enable flash module achieve higher performance. flash/OTP mapped both program data space; therefore, used execute code store data information. Addresses 0x3F 7FF0 0x3F 7FF5 reserved data variables should contain program code.
NOTE Flash wait-states configured application. This allows applications running slower frequencies configure flash fewer wait-states. Flash effective performance improved enabling flash pipeline mode Flash options register. With this mode enabled, effective performance linear code execution will much faster than performance indicated wait-state configuration alone. exact performance gain when using Flash pipeline mode application-dependent. more information Flash options, Flash wait-state, wait-state registers, TMS320x2802x Piccolo System Control Interrupts Reference Guide (literature number SPRUFN3).
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3.3.6
SARAMs
devices contain these blocks single access memory, each size. stack pointer points beginning block reset. blocks, like other memory blocks C28x devices, mapped both program data space. Hence, user execute code data variables. partitioning performed within linker. C28x device presents unified memory programmer. This makes easier programming high-level languages.
3.3.7
SARAM
device contains 1K/3K/4K single-access memory. This block mapped both program data space.
3.3.8
Boot
Boot factory-programmed with boot-loading software. Boot-mode signals provided tell bootloader software what boot mode power user select boot normally download software from external connection select boot software that programmed internal Flash/ROM. Boot also contains standard tables, such SIN/COS waveforms, math-related algorithms.
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Table 3-5. Boot Mode Selection
MODE GPIO37/TDO GPIO34/COMP2OUT TRST GetMode Wait (see Section 3.3.9 description) Parallel Emulation Boot MODE
3.3.8.1 Emulation Boot When emulator connected, GPIO37/TDO cannot used boot mode selection. this case, boot detects that emulator connected uses contents reserved SARAM locations vector table determine boot mode. content either location invalid, then Wait boot option used. boot mode options accessed emulation boot. 3.3.8.2 GetMode default behavior GetMode option boot flash. This behavior changed another boot option programming locations OTP. following loaders specified: SCI, SPI, I2C, OTP. content either location invalid, then boot flash used
3.3.9
Security
devices support high levels security protect user firmware from being reverse engineered. security features 128-bit password (hardcoded wait-states), which user programs into flash. code security module (CSM) used protect flash/OTP L0/L1 SARAM blocks. security feature prevents unauthorized users from examining memory contents JTAG port, executing code from external memory trying boot-load some undesirable software that would export secure memory contents. enable access secure blocks, user must write correct 128-bit value that matches value stored password locations within Flash. addition CSM, emulation code security logic (ECSL) been implemented prevent unauthorized users from stepping through secure code. code data access flash, user OTP, memory while emulator connected will trip ECSL break emulation connection. allow emulation secure code, while maintaining protection against secure memory reads, user must write correct value into lower bits register, which matches value stored lower bits password locations within flash. Note that dummy reads bits password flash must still performed. lower bits password locations ones (unprogrammed), then value does need match. When initially debugging device with password locations flash programmed (i.e., secured), will start running execute instruction that performs access protected ECSL area. this happens, ECSL will trip cause emulator connection cut. solution Wait boot option. This will loop around software breakpoint allow emulator connected without tripping security. user then exit this mode once emulator connected using emulation boot options described TMS320x2802x Piccolo Boot Reference Guide (SPRUFN6). Piccolo devices support hardware wait-in-reset mode.
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NOTE When code-security passwords programmed, addresses between 0x3F7F80 0x3F7FF5 cannot used program code data. These locations must programmed 0x0000. code security feature used, addresses 0x3F7F80 through 0x3F7FEF used code data. Addresses 0x3F7FF0 0x3F7FF5 reserved data should contain program code. 128-bit password 0x3F 7FF8 0x3F 7FFF) must programmed zeros. Doing would permanently lock device.
Disclaimer Code Security Module Disclaimer
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CODE SECURITY MODULE (CSM) INCLUDED THIS DEVICE DESIGNED PASSWORD PROTECT DATA STORED ASSOCIATED MEMORY (EITHER FLASH) WARRANTED TEXAS INSTRUMENTS (TI), ACCORDANCE WITH STANDARD TERMS CONDITIONS, CONFORM TI'S PUBLISHED SPECIFICATIONS WARRANTY PERIOD APPLICABLE THIS DEVICE. DOES NOT, HOWEVER, WARRANT REPRESENT THAT CANNOT COMPROMISED BREACHED THAT DATA STORED ASSOCIATED MEMORY CANNOT ACCESSED THROUGH OTHER MEANS. MOREOVER, EXCEPT FORTH ABOVE, MAKES WARRANTIES REPRESENTATIONS CONCERNING OPERATION THIS DEVICE, INCLUDING IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. EVENT SHALL LIABLE CONSEQUENTIAL, SPECIAL, INDIRECT, INCIDENTAL, PUNITIVE DAMAGES, HOWEVER CAUSED, ARISING YOUR THIS DEVICE, WHETHER BEEN ADVISED POSSIBILITY SUCH DAMAGES. EXCLUDED DAMAGES INCLUDE, LIMITED LOSS DATA, LOSS GOODWILL, LOSS INTERRUPTION BUSINESS OTHER ECONOMIC LOSS.
3.3.10 Peripheral Interrupt Expansion (PIE) Block
block serves multiplex numerous interrupt sources into smaller interrupt inputs. block support peripheral interrupts. F2802x, possible interrupts used peripherals. interrupts grouped into blocks each group into interrupt lines (INT1 INT12). Each interrupts supported vector stored dedicated block that overwritten user. vector automatically fetched servicing interrupt. takes clock cycles fetch vector save critical registers. Hence quickly respond interrupt events. Prioritization interrupts controlled hardware software. Each individual interrupt enabled/disabled within block.
3.3.11 External Interrupts (XINT1-XINT3)
devices support three masked external interrupts (XINT1-XINT3). Each interrupts selected negative, positive, both negative positive edge triggering also enabled/disabled. These interrupts also contain 16-bit free running counter, which reset zero when valid interrupt edge detected. This counter used accurately time stamp interrupt. There dedicated pins external interrupts. XINT1, XINT2, XINT3 interrupts accept inputs from GPIO0 GPIO31 pins.
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3.3.12 Internal Zero Oscillators, Oscillator,
device clocked either internal zero-pin oscillators, external oscillator, crystal attached on-chip oscillator circuit (48-pin devices only). provided supporting input-clock-scaling ratios. ratios changed on-the-fly software, enabling user scale back operating frequency lower power operation desired. Refer Electrical Specification section timing details. block bypass mode.
3.3.13 Watchdog
Each device contains watchdogs: CPU-Watchdog that monitors core NMI-Watchdog that missing clock-detect circuit. user software must regularly reset CPU-watchdog counter within certain time frame; otherwise, CPU-watchdog generates reset processor. CPU-watchdog disabled necessary. NMI-Watchdog engages only case clock failure either generate interrupt device reset.
3.3.14 Peripheral Clocking
clocks each individual peripheral enabled/disabled reduce power consumption when peripheral use. Additionally, system clock serial ports (except I2C) scaled relative clock.
3.3.15 Low-power Modes
devices full static CMOS devices. Three low-power modes provided: IDLE: Place low-power mode. Peripheral clocks turned selectively only those peripherals that need function during IDLE left operating. enabled interrupt from active peripheral watchdog timer will wake processor from IDLE mode.
STANDBY: Turns clock peripherals. This mode leaves oscillator functional. external interrupt event will wake processor peripherals. Execution begins next valid cycle after detection interrupt event HALT: This mode basically shuts down device places lowest possible power consumption mode. internal zero-pin oscillators used clock source, HALT mode turns them off, default. keep these oscillators from shutting down, INTOSCnHALTI bits CLKCTL register used. zero-pin oscillators thus used clock CPU-watchdog this mode. on-chip crystal oscillator used clock source, shut down this mode. reset external signal (through GPIO pin) CPU-watchdog wake device from this mode.
3.3.16 Peripheral Frames (PFn)
device segregates peripherals into three sections. mapping peripherals follows: PF0: PIE: Flash: Timers: CSM: ADC: PF1: GPIO: ePWM: eCAP: Comparators:
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Interrupt Enable Control Registers Plus Vector Table Flash Waitstate Registers CPU-Timers Registers Code Security Module Registers Result Registers GPIO Configuration Control Registers Enhanced Pulse Width Modulator Module Registers Enhanced Capture Module Registers Comparator Modules
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PF2:
SYS: SCI: SPI: ADC: I2C: XINT:
System Control Registers Serial Communications Interface (SCI) Control RX/TX Registers Serial Port Interface (SPI) Control RX/TX Registers Status, Control, Configuration Registers Inter-Integrated Circuit Module Registers External Interrupt Registers
3.3.17 General-Purpose Input/Output (GPIO) Multiplexer
Most peripheral signals multiplexed with general-purpose input/output (GPIO) signals. This enables user GPIO peripheral signal function used. reset, GPIO pins configured inputs. user individually program each GPIO mode peripheral signal mode. specific inputs, user also select number input qualification cycles. This filter unwanted noise glitches. GPIO signals also used bring device specific low-power modes.
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3.3.18 32-Bit CPU-Timers
CPU-Timers identical 32-bit timers with presettable periods with 16-bit clock prescaling. timers have 32-bit count down register, which generates interrupt when counter reaches zero. counter decremented clock speed divided prescale value setting. When counter reaches zero, automatically reloaded with 32-bit period value. CPU-Timer connected INT14 CPU. clocked following: SYSCLKOUT (default) Internal zero-pin oscillator (INTOSC1) Internal zero-pin oscillator (INTSOC2) External clock source
CPU-Timer general connected INT13 CPU. CPU-Timer also general connected block.
3.3.19 Control Peripherals
devices support following peripherals that used embedded control communication: ePWM: enhanced peripheral supports independent/complementary generation, adjustable dead-band generation leading/trailing edges, latched/cycle-by-cycle trip mechanism. Some pins support HRPWM high resolution duty period features. type module found 2802x devices also supports increased dead-band resolution, enhanced interrupt generation, advanced triggering including trip functions based comparator outputs. enhanced capture peripheral uses 32-bit time base registers four programmable events continuous/one-shot capture modes. This peripheral also configured generate auxiliary signal. block 12-bit converter. single-ended channels pinned out, depending device. contains sample-and-hold units simultaneous sampling. Each comparator block consists analog comparator along with internal 10-bit reference supplying input comparator.
eCAP:
ADC:
Comparator:
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3.3.20 Serial Port Peripherals
devices support following serial communication peripherals: SPI: high-speed, synchronous serial port that allows serial stream programmed length (one sixteen bits) shifted into device programmable bit-transfer rate. Normally, used communications between external peripherals another processor. Typical applications include external peripheral expansion through devices such shift registers, display drivers, ADCs. Multi-device communications supported master/slave operation SPI. contains 4-level receive transmit FIFO reducing interrupt servicing overhead. serial communications interface two-wire asynchronous serial port, commonly known UART. contains 4-level receive transmit FIFO reducing interrupt servicing overhead. inter-integrated circuit (I2C) module provides interface between other devices compliant with Philips Semiconductors Inter-IC (I2C-bus) specification version connected I2C-bus. External components attached this 2-wire serial transmit/receive 8-bit data to/from through module. contains 4-level receive transmit FIFO reducing interrupt servicing overhead.
SCI:
I2C:
Register
devices contain four peripheral register spaces. spaces categorized follows: Peripheral Frame Peripheral Frame Peripheral Frame These peripherals that mapped directly memory bus. Table 3-6. These peripherals that mapped 32-bit peripheral bus. Table 3-7. These peripherals that mapped 16-bit peripheral bus. Table 3-8. Table 3-6. Peripheral Frame Registers
NAME Device Emulation Registers FLASH Registers Code Security Module Registers registers wait read only) CPU-TIMER0/1/2 Registers Registers Vector Table ADDRESS RANGE 0x00 0880 0x00 09FF 0x00 0A80 0x00 0ADF 0x00 0AE0 0x00 0AEF 0x00 0B00 0x00 0B0F 0x00 0C00 0x00 0C3F 0x00 0CE0 0x00 0CFF 0x00 0D00 0x00 0DFF SIZE EALLOW PROTECTED
Registers Frame support 16-bit 32-bit accesses. registers EALLOW protected, then writes cannot performed until EALLOW instruction executed. EDIS instruction disables writes prevent stray code pointers from corrupting register contents. Flash Registers also protected Code Security Module (CSM).
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Table 3-7. Peripheral Frame Registers
NAME Comparator registers Comparator registers ePWM1 HRPWM1 registers ePWM2 HRPWM2 registers ePWM3 HRPWM3 registers ePWM4 HRPWM4 registers eCAP1 registers GPIO registers ADDRESS RANGE 0x00 6400 0x00 641F 0x00 6420 0x00 643F 0x00 6800 0x00 683F 0x00 6840 0x00 687F 0x00 6880 0x00 68BF 0x00 68C0 0x00 68FF 0x00 6A00 0x00 6A1F 0x00 6F80 0x00 6FFF SIZE EALLOW PROTECTED
Some registers EALLOW protected. module reference guide more information.
Table 3-8. Peripheral Frame Registers
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NAME System Control Registers SPI-A Registers SCI-A Registers Watchdog Interrupt Registers External Interrupt Registers Registers I2C-A Registers
ADDRESS RANGE 0x00 7010 0x00 702F 0x00 7040 0x00 704F 0x00 7050 0x00 705F 0x00 7060 0x00 706F 0x00 7070 0x00 707F 0x00 7100 0x00 717F 0x00 7900 0x00 793F
SIZE
EALLOW PROTECTED
Some registers EALLOW protected. module reference guide more information.
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Device Emulation Registers
These registers used control protection mode C28x monitor some critical device signals. registers defined Table 3-9. Table 3-9. Device Emulation Registers
NAME DEVICECNF PARTID ADDRESS RANGE 0x0880 0x0881 0x3D 7FFF SIZE (x16) DESCRIPTION Device Configuration Register Part Register TMS320F28027PT TMS320F28027DA TMS320F28026PT TMS320F28026DA TMS320F28023PT TMS320F28023DA TMS320F28022PT TMS320F28022DA TMS320F28021PT TMS320F28021DA TMS320F28020PT TMS320F28020DA CLASSID 0x0882 Class Register TMS320F28027PT/DA TMS320F28026PT/DA TMS320F28023PT/DA TMS320F28022PT/DA TMS320F28021PT/DA TMS320F28020PT/DA REVID 0x0883 Revision Register 0x00CF 0x00CE 0x00C7 0x00C6 0x00CC 0x00C5 0x00C4 0x00CB 0x00CA 0x00C3 0x00C2 0x00CF 0x00C7 0x00CF 0x00C7 0x00CF 0x00C7 0x00CD EALLOW PROTECTED
0x0000 Silicon Rev.
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Interrupts
Figure shows various interrupt sources multiplexed.
Peripherals (SPI, SCI, ePWM, I2C, HRPWM, eCAP, ADC) WAKEINT WDINT Sync LPMINT Watchdog Low-Power Modes
Interrupt Control XINT1CR(15:0) XINT2CTR(15:0)
XINT1
Interrupts
GPIOXINT1SEL(4:0) XINT2SOC XINT2
Interrupt Control XINT2CR(15:0) XINT3CTR(15:0)
Core
GPIOXINT2SEL(4:0) GPIO0.int
Interrupt Control XINT3CR(15:0) XINT3CTR(15:0)
XINT3
XINT3
INT1 INT12
XINT2
XINT1
SYSCLKOUT
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GPIO GPIO31.int
GPIOXINT3SEL(4:0) TINT0 INT13 INT14 TINT1 TINT2 TIMER TIMER TIMER CPUTMR2CLK System Control (See System Control section.)
interrupt with watchdog function (See Watchdog section.)
CLOCKFAIL NMIRS
Figure 3-6. External Interrupt Sources
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Eight block interrupts grouped into interrupt. total, interrupt groups, with interrupts group equals possible interrupts. Table 3-10 shows interrupts used 2802x devices. TRAP #VectorNumber instruction transfers program control interrupt service routine corresponding vector specified. TRAP attempts transfer program control address pointed reset vector. vector table does not, however, include reset vector. Therefore, TRAP should used when enabled. Doing will result undefined behavior. When enabled, TRAP through TRAP will transfer program control interrupt service routine corresponding first vector within group. example: TRAP fetches vector from INT1.1, TRAP fetches vector from INT2.1, forth.
IFR(12:1) INT1 INT2 INT11 INT12 (Flag) (Enable) INTx.1 INTx.2 INTx.3 INTx.4 INTx.5 INTx.6 INTx.7 INTx.8 (Enable) (Enable/Flag) PIEIERx(8:1) (Flag) PIEIFRx(8:1) IER(12:1) IN
Global Enable
INTx
From Peripherals External Interrupts
PIEACKx
Figure 3-7. Multiplexing Interrupts Using Block
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Table 3-10. MUXed Peripheral Interrupt Vector Table
INTx.8 INT1.y WAKEINT (LPM/WD) 0xD4E INT2.y Reserved 0xD5E INT3.y Reserved 0xD6E INT4.y Reserved 0xD7E INT5.y Reserved 0xD8E INT6.y Reserved 0xD9E INT7.y Reserved 0xDAE INT8.y Reserved 0xDBE INT9.y Reserved 0xDCE INT10.y ADCINT8 (ADC) 0xDDE INT11.y Reserved 0xDEE INT12.y Reserved 0xDFE INTx.7 TINT0 (TIMER 0xD4C Reserved 0xD5C Reserved 0xD6C Reserved 0xD7C Reserved 0xD8C Reserved 0xD9C Reserved 0xDAC Reserved 0xDBC Reserved 0xDCC ADCINT7 (ADC) 0xDDC Reserved 0xDEC Reserved 0xDFC INTx.6 ADCINT9 (ADC) 0xD4A Reserved 0xD5A Reserved 0xD6A Reserved 0xD7A Reserved 0xD8A Reserved 0xD9A Reserved 0xDAA Reserved 0xDBA Reserved 0xDCA ADCINT6 (ADC) 0xDDA Reserved 0xDEA Reserved 0xDFA INTx.5 XINT2 Ext. int. 0xD48 Reserved 0xD58 Reserved 0xD68 Reserved 0xD78 Reserved 0xD88 Reserved 0xD98 Reserved 0xDA8 Reserved 0xDB8 Reserved 0xDC8 ADCINT5 (ADC) 0xDD8 Reserved 0xDE8 Reserved 0xDF8 INTx.4 XINT1 Ext. int. 0xD46 EPWM4_TZINT (ePWM4) 0xD56 EPWM4_INT (ePWM4) 0xD66 Reserved 0xD76 Reserved 0xD86 Reserved 0xD96 Reserved 0xDA6 Reserved 0xDB6 Reserved 0xDC6 ADCINT4 (ADC) 0xDD6 Reserved 0xDE6 Reserved 0xDF6 INTx.3 Reserved 0xD44 EPWM3_TZINT (ePWM3) 0xD54 EPWM3_INT (ePWM3) 0xD64 Reserved 0xD74 Reserved 0xD84 Reserved 0xD94 Reserved 0xDA4 Reserved 0xDB4 Reserved 0xDC4 ADCINT3 (ADC) 0xDD4 Reserved 0xDE4 Reserved 0xDF4 INTx.2 ADCINT2 (ADC) 0xD42 EPWM2_TZINT (ePWM2) 0xD52 EPWM2_INT (ePWM2) 0xD62 Reserved 0xD72 Reserved 0xD82 SPITXINTA (SPI-A) 0xD92 Reserved 0xDA2 I2CINT2A (I2C-A) 0xDB2 SCITXINTA (SCI-A) 0xDC2 ADCINT2 (ADC) 0xDD2 Reserved 0xDE2 Reserved 0xDF2 INTx.1 ADCINT1 (ADC) 0xD40 EPWM1_TZINT (ePWM1) 0xD50 EPWM1_INT (ePWM1) 0xD60 ECAP1_INT (eCAP1) 0xD70 Reserved 0xD80 SPIRXINTA (SPI-A) 0xD90 Reserved 0xDA0 I2CINT1A (I2C-A) 0xDB0 SCIRXINTA (SCI-A) 0xDC0 ADCINT1 (ADC) 0xDD0 Reserved 0xDE0 XINT3 Ext. Int. 0xDF0
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Table 3-11. Configuration Control Registers
NAME PIECTRL PIEACK PIEIER1 PIEIFR1 PIEIER2 PIEIFR2 PIEIER3 PIEIFR3 PIEIER4 PIEIFR4 PIEIER5 PIEIFR5 PIEIER6 PIEIFR6 PIEIER7 PIEIFR7 PIEIER8 PIEIFR8 PIEIER9 PIEIFR9 PIEIER10 PIEIFR10 PIEIER11 PIEIFR11 PIEIER12 PIEIFR12 Reserved ADDRESS 0x0CE0 0x0CE1 0x0CE2 0x0CE3 0x0CE4 0x0CE5 0x0CE6 0x0CE7 0x0CE8 0x0CE9 0x0CEA 0x0CEB 0x0CEC 0x0CED 0x0CEE 0x0CEF 0x0CF0 0x0CF1 0x0CF2 0x0CF3 0x0CF4 0x0CF5 0x0CF6 0x0CF7 0x0CF8 0x0CF9 0x0CFA 0x0CFF SIZE (x16) DESCRIPTION PIE, Control Register PIE, Acknowledge Register PIE, INT1 Group Enable Register PIE, INT1 Group Flag Register PIE, INT2 Group Enable Register PIE, INT2 Group Flag Register PIE, INT3 Group Enable Register PIE, INT3 Group Flag Register PIE, INT4 Group Enable Register PIE, INT4 Group Flag Register PIE, INT5 Group Enable Register PIE, INT5 Group Flag Register PIE, INT6 Group Enable Register PIE, INT6 Group Flag Register PIE, INT7 Group Enable Register PIE, INT7 Group Flag Register PIE, INT8 Group Enable Register PIE, INT8 Group Flag Register PIE, INT9 Group Enable Register PIE, INT9 Group Flag Register PIE, INT10 Group Enable Register PIE, INT10 Group Flag Register PIE, INT11 Group Enable Register PIE, INT11 Group Flag Register PIE, INT12 Group Enable Register PIE, INT12 Group Flag Register Reserved
configuration control registers protected EALLOW mode. vector table protected.
3.6.1
External Interrupts
Table 3-12. External Interrupt Registers
NAME XINT1CR XINT2CR XINT3CR XINT1CTR XINT2CTR XINT3CTR ADDRESS 0x00 7070 0x00 7071 0x00 7072 0x00 7078 0x00 7079 0x00 707A SIZE (x16) DESCRIPTION XINT1 configuration register XINT2 configuration register XINT3 configuration register XINT1 counter register XINT2 counter register XINT3 counter register
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Each external interrupt enabled/disabled qualified using positive, negative, both positive negative edge. more information, TMS320x2802x Piccolo System Control Interrupts Reference Guide (literature number SPRUFN3).
VREG/BOR/POR
Although core circuitry operate different voltages, these devices have on-chip voltage regulator (VREG) generate voltage from VDDIO supply. This eliminates cost space second external regulator application board. Additionally, internal power-on reset (POR) brown-out reset (BOR) circuits monitor both VDDIO rails during power-up mode, eliminating need external voltage supervisory circuits.
3.7.1
On-chip Voltage Regulator (VREG)
linear regulator generates core voltage (VDD) from VDDIO supply. Therefore, although capacitors required each stabilize generated voltage, power need supplied these pins operate device. Conversely, VREG disabled, should power redundancy primary concern application.
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3.7.1.1 Using On-chip VREG utilize on-chip VREG, VREGENZ should pulled appropriate recommended operating voltage should supplied VDDIO VDDA pins. this case, voltage needed core logic will generated VREG. Each requires order (minimum) capacitance proper regulation VREG. These capacitors should located close possible pins. 3.7.1.2 Disabling On-chip VREG conserve power, also possible disable on-chip VREG supply core logic voltage pins with more efficient external regulator. enable this option, VREGENZ must pulled high.
3.7.2
On-chip Power-On Reset (POR) Brown-Out Reset (BOR) Circuit
on-chip supervisory circuits, power-on reset (POR) brown-out reset (BOR) remove burden monitoring VDDIO supply rails from application board. purpose create clean reset throughout device during entire power-up procedure. trip point looser, lower trip point than BOR, which watches dips VDDIO rail during device operation. function present both VDDIO rails times. After initial device power-up, function present VDDIO times, when internal VREG enabled (VREGENZ pulled low). Both functions pull when voltages below their respective trip point. Section various trip points well delay time from voltage rising past trip point release pin. Figure shows VREG, POR, BOR.
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(Force Hi-Z When High)
Input, Output) SYSRS Internal Weak Deglitch Filter
SYSCLKOUT Sync MCLKRS JTAG Detect Logic
Core
Clocking Logic VREGHALT
WDRST PBRS
POR/BOR Generating Module
On-Chip Voltage Regulator (VREG)
VREGENZ
WDRST reset signal from CPU-watchdog. PBRS reset signal from POR/BOR module.
Figure 3-8. VREG Reset Signal Connectivity
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System Control
This section describes oscillator clocking mechanisms, watchdog function power modes. Table 3-13. PLL, Clocking, Watchdog, Low-Power Mode Registers
NAME XCLK PLLSTS CLKCTL PLLLOCKPRD INTOSC1TRIM INTOSC2TRIM LOSPCP PCLKCR0 PCLKCR1 LPMCR0 PCLKCR3 PLLCR SCSR WDCNTR WDKEY WDCR ADDRESS 0x00 7010 0x00 7011 0x00 7012 0x00 7013 0x00 7014 0x00 7016 0x00 701B 0x00 701C 0x00 701D 0x00 701E 0x00 7020 0x00 7021 0x00 7022 0x00 7023 0x00 7025 0x00 7029 SIZE (x16) XCLKOUT Control Status Register Clock Control Register Lock Period Internal Oscillator Trim Register Internal Oscillator Trim Register Low-Speed Peripheral Clock Prescaler Register Peripheral Clock Control Register Peripheral Clock Control Register Power Mode Control Register Peripheral Clock Control Register Control Register System Control Status Register Watchdog Counter Register Watchdog Reset Register Watchdog Control Register DESCRIPTION
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registers this table EALLOW protected.
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Figure shows various clock domains that discussed. Figure 3-10 shows various clock sources (both internal external) that provide clock device operation.
PCLKCR0/1/3 (System Ctrl Regs) Clock Enables SPI-A, SCI-A Clock Enables GPIO eCAP1 Clock Enables ePWM1/./4 Clock Enables I2C-A Clock Enables Peripheral Registers Peripheral Registers Peripheral Registers SYSCLKOUT LOSPCP (System Ctrl Regs) LSPCLK Peripheral Registers
C28x Core
CLKIN
Analog GPIO
12-Bit
Registers
Clock Enables COMP1/2 COMP Registers
CLKIN clock into CPU. passed SYSCLKOUT (that CLKIN same frequency SYSCLKOUT).
Figure 3-9. Clock Reset Domains
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CLKCTL[WDCLKSRCSEL] INTOSC1TRIM
Internal MHz)
OSC1CLK OSCCLKSRC1
WDCLK (OSC1CLK reset) CPU-watchdog
OSCE
CLKCTL[INTOSC1OFF] Turn
CLKCTL[INTOSC1HALT] Ignore HALT INTOSC2TRIM
WAKEOSC Internal OSC2CLK MHz) OSCE
CLKCTL[OSCCLKSRCSEL]
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XCLKIN XTAL
OSCCLK (OSC1CLK reset) CLKCTL[TRM2CLKPRESCALE]
Missing-Clock-Detect Circuit
CLKCTL[TMR2CLKSRCSEL] Turn CLKCTL[INTOSC2OFF] Ignore HALT CLKCTL[INTOSC2HALT] OSCCLKSRC2 XCLK[XCLKINSEL] GPIO38 GPIO19 CLKCTL[OSCCLKSRC2SEL] SYSCLKOUT Prescale SYNC Edge Detect
CPUTMR2CLK
CLKCTL[XCLKINOFF] GPIO19 GPIO38 XCLKIN
(Crystal)
EXTCLK WAKEOSC (Oscillators enabled when this signal high)
CLKCTL[XTALOSCOFF]
(default reset) Turn
Register loaded from OTP-based calibration function. Section 3.8.4 details missing clock detection.
Figure 3-10. Clock Tree
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3.8.1
Internal Zero Oscillators
F2802x devices contain independent internal zero oscillators. default both oscillators turned power internal oscillator default clock source this time. power savings, unused oscillators powered down user. center frequency these oscillators determined their respective oscillator trim registers, written calibration routine part boot execution. electrical section more information these oscillators.
3.8.2
Crystal Oscillator Option
typical specifications external quartz crystal (fundamental mode, parallel resonant) listed Table 3-14. Furthermore, range Table 3-14. Typical Specifications External Quartz Crystal
2200
XCLKIN/GPIO19/38
Turn XCLKIN path CLKCTL register
Rbias
Crystal
X1/X2 pins available 48-pin package only.
Figure 3-11. Using On-chip Crystal Oscillator
NOTE total capacitance circuit board components excluding crystal. value usually approximately twice value crystal's load capacitance. Rbias generally load capacitance crystal described crystal specifications manufacturers. recommends that customers have resonator/crystal vendor characterize operation their device with chip. resonator/crystal vendor equipment expertise tune tank circuit. vendor also advise customer regarding proper tank component values that will produce proper start stability over entire operating range.
XCLKIN/GPIO19/38
External Clock Signal (Toggling 0-VDDIO)
Figure 3-12. Using 3.3-V External Oscillator
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FREQUENCY (MHz)
(pF)
(pF)
(pF)
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3.8.3
PLL-Based Clock Module
devices have on-chip, PLL-based clock module. This module provides necessary clocking signals device, well control low-power mode entry. 4-bit ratio control PLLCR[DIV] select different clock rates. watchdog module should disabled before writing PLLCR register. re-enabled need after module stabilized, which takes input clock PLLCR[DIV] bits should chosen such that output frequency (VCOCLK) least MHz. Table 3-15. Settings
PLLCR[DIV] VALUE 0000 (PLL bypass) 0001
SYSCLKOUT (CLKIN) PLLSTS[DIVSEL] OSCCLK/4 (Default) (OSCCLK 1)/4 (OSCCLK 2)/4 (OSCCLK 3)/4 (OSCCLK 4)/4 (OSCCLK 5)/4 (OSCCLK 6)/4 (OSCCLK 7)/4 (OSCCLK 8)/4 (OSCCLK 9)/4 (OSCCLK 10)/4 (OSCCLK 11)/4 (OSCCLK 12)/4
PLLSTS[DIVSEL] OSCCLK/2 (OSCCLK 1)/2 (OSCCLK 2)/2 (OSCCLK 3)/2 (OSCCLK 4)/2 (OSCCLK 5)/2 (OSCCLK 6)/2 (OSCCLK 7)/2 (OSCCLK 8)/2 (OSCCLK 9)/2 (OSCCLK 10)/2 (OSCCLK 11)/2 (OSCCLK 12)/2
PLLSTS[DIVSEL] OSCCLK
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0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100
control register (PLLCR) Status Register (PLLSTS) reset their default state signal watchdog reset only. reset issued debugger missing clock detect logic effect. This register EALLOW protected. TMS320x2802x Piccolo System Control Interrupts Reference Guide (literature number SPRUFN3 more information. default, PLLSTS[DIVSEL] configured (The boot changes this /1.) PLLSTS[DIVSEL] must before writing PLLCR should changed only after PLLSTS[PLLLOCKS]
Table 3-16. CLKIN Divide Options
PLLSTS [DIVSEL] CLKIN DIVIDE
This mode used only when bypassed off.
PLL-based clock module provides four modes operation: INTOSC1 (Internal Zero-pin Oscillator This on-chip internal oscillator This provide clock Watchdog block, core CPU-Timer INTOSC2 (Internal Zero-pin Oscillator This on-chip internal oscillator This provide clock Watchdog block, core CPU-Timer Both INTOSC1 INTOSC2 independently chosen Watchdog block, core CPU-Timer Crystal/Resonator Operation: on-chip (crystal) oscillator enables external crystal/resonator attached device provide time base. crystal/resonator connected X1/X2 pins. Some devices have X1/X2 pins. Table details. External Clock Source Operation: on-chip (crystal) oscillator used, this mode allows bypassed. device clocks generated from external clock source input XCLKIN pin. Note that XCLKIN multiplexed with GPIO19 GPIO38 pin. XCLKIN input selected GPIO19 GPIO38 XCLKINSEL XCLK register. CLKCTL[XCLKINOFF]
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disables this clock input (forced low). clock source used respective pins used GPIOs, user should disable boot time. Before changing clock sources, ensure that target clock present. clock present, then that clock source must disabled (using CLKCTL register) before switching clocks. Table 3-17. Possible Configuration Modes
MODE REMARKS Invoked user setting PLLOFF PLLSTS register. block disabled this mode. This useful reduce system noise power operation. PLLCR register must first 0x0000 (PLL Bypass) before entering this mode. clock (CLKIN) derived directly from input clock either X1/X2, XCLKIN. PLLSTS[DIVSEL] CLKIN SYSCLKOUT OSCCLK/4 OSCCLK/2 OSCCLK/1 OSCCLK/4 OSCCLK/2 OSCCLK/1 OSCCLK*n/4 OSCCLK*n/2
Enable
Achieved writing non-zero value into PLLCR register. Upon writing PLLCR device will switch Bypass mode until locks.
3.8.4
Loss Input Clock (NMI Watchdog Function)
2802x devices clocked from either internal zero-pin oscillators (INTOSC1/INTOSC2), on-chip crystal oscillator, from external clock input. Regardless clock source, PLL-enabled PLL-bypass mode, input clock vanishes, will issue limp-mode clock output. This limp-mode clock continues clock peripherals typical frequency MHz. When limp mode activated, CLOCKFAIL signal generated that latched interrupt. Depending NMIRESETSEL been configured, reset device fired immediately watchdog counter issue reset when overflows. addition this, Missing Clock Status (MCLKSTS) set. interrupt could used application detect input clock failure initiate necessary corrective action such switching over alternative clock source available) initiate shut-down procedure system. software does respond clock-fail condition, watchdog triggers reset after preprogrammed time interval. Figure 3-13 shows interrupt mechanisms involved.
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Bypass default configuration upon power-up after external reset (XRS). This mode selected when PLLCR register 0x0000 Bypass while locks frequency after PLLCR register been modified. this mode, itself bypassed turned off.
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NMIFLG[NMINT] NMIFLGCLR[NMINT] Clear Latch Clear
NMINT
Generate Interrupt Pulse When Input
NMIFLG[CLOCKFAIL] Clear Latch Clear NMIFLGCLR[CLOCKFAIL] CLOCKFAIL SYNC? SYSCLKOUT NMIFLGFRC[CLOCKFAIL]
NMICFG[CLOCKFAIL]
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SYSCLKOUT SYSRS NMIWDPRD[15:0] NMIWDCNT[15:0] Watchdog NMIRS System Control Section
Figure 3-13. NMI-watchdog
3.8.5
CPU-Watchdog Module
CPU-watchdog module 2802x device similar used 281x/280x/283xx devices. This module generates output pulse, oscillator clocks wide (OSCCLK), whenever 8-bit watchdog counter reached maximum value. prevent this, user must disable counter software must periodically write 0x55 0xAA sequence into watchdog register that resets watchdog counter. Figure 3-14 shows various functional blocks within watchdog module. Normally, when input clocks present, CPU-watchdog counter decrements initiate CPU-watchdog reset WDINT interrupt. However, when external input clock fails, CPU-watchdog counter stops decrementing (i.e., watchdog counter does change with limp-mode clock).
NOTE CPU-watchdog different from watchdog. legacy watchdog that present devices.
NOTE Applications which correct operating frequency absolutely critical should implement mechanism which will held reset, should input clocks ever fail. example, circuit used trigger MCU, should capacitor ever fully charged. used discharge capacitor periodic basis prevent from getting fully charged. Such circuit would also help detecting failure flash memory.
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WDCR (WDPS[2:0]) WDCR (WDDIS) WDCNTR(7:0) WDCLK /512 Watchdog Prescaler WDCLK 8-Bit Watchdog Counter Clear Counter
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Internal Pullup WDKEY(7:0) Watchdog Detector Core-reset WDCR (WDCHK[2:0]) WDCHK SCSR (WDENINT) WDRST Generate Output Pulse WDINT (512 OSCCLKs)
Good
WDRST(A)
WDRST signal driven OSCCLK cycles.
Figure 3-14. CPU-watchdog Module WDINT signal enables watchdog used wakeup from IDLE/STANDBY mode. STANDBY mode, peripherals turned device. only peripheral that remains functional CPU-watchdog. This module will OSCCLK. WDINT signal block that wake device from STANDBY enabled). Section 3.9, Low-power Modes Block, more details. IDLE mode, WDINT signal generate interrupt CPU, PIE, take IDLE mode. HALT mode, CPU-watchdog used wake device through device reset.
Low-power Modes Block
Table 3-18 summarizes various modes. Table 3-18. Low-power Modes
MODE IDLE STANDBY LPMCR0(1:0) OSCCLK (CPU-watchdog still running) (on-chip crystal oscillator turned off, zero-pin oscillator CPU-watchdog state dependent user code.) CLKIN SYSCLKOUT EXIT XRS, CPU-watchdog interrupt, enabled interrupt XRS, CPU-watchdog interrupt, GPIO Port signal, debugger XRS, GPIO Port signal, debugger (2), CPU-watchdog
HALT
Exit column lists which signals under what conditions power mode exited. signal, signals, exits power condition. This signal must kept long enough interrupt recognized device. Otherwise, low-power mode will exited device will back into indicated power mode. JTAG port still function even clock (CLKIN) turned off. WDCLK must active device into HALT mode.
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various low-power modes operate follows: IDLE Mode: This mode exited enabled interrupt that recognized processor. block performs tasks during this mode long LPMCR0(LPM) bits 0,0. GPIO port signal (GPIO[31:0]) wake device from STANDBY mode. user must select which signal(s) will wake device GPIOLPMSEL register. selected signal(s) also qualified OSCCLK before waking device. number OSCCLKs specified LPMCR0 register. CPU-watchdog, XRS, GPIO port signal (GPIO[31:0]) wake device from HALT mode. user selects signal GPIOLPMSEL register.
STANDBY Mode:
HALT Mode:
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NOTE low-power modes affect state output pins (PWM pins included). They will whatever state code left them when IDLE instruction executed. TMS320x2802x Piccolo System Control Interrupts Reference Guide (literature number SPRUFN3) more details.
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Peripherals
Analog Block
12-bit core implemented that different timings than 12-bit used F280x/F2833x. wrapper modified incorporate timings also other enhancements improve timing control start conversions.
38-Pin VDDA 48-Pin VDDA (3.3 VDDA (Agnd) VSSA VREFLO Interface Reference Diff VREFHI
VREFLO VREFLO Tied Tied VSSA VSSA VREFHI VREFHI Tied Tied Signal Pinout
COMP1OUT AIO2 AIO10 10-Bit Comp1
Simultaneous Sampling Channels
COMP2OUT AIO4 AIO12 10-Bit Comp2
Temperature Sensor AIO6 AIO14
Figure 4-1. Analog Configurations Figure shows interaction analog module with rest F2802x system.
4.1.1
Table 4-1. Configuration Control Registers
REGISTER NAME ADDRESS 0x7100 0x7104 0x7105 0x7106 0x7107 0x7108 0x7109 0x710A 0x710B 0x710C 0x7110 0x7112 0x7114 0x7115 SIZE (x16) EALLOW PROTECTED Control Register Interrupt Flag Register Interrupt Flag Clear Register Interrupt Overflow Register Interrupt Overflow Clear Register Interrupt Selection Register Interrupt Selection Register Interrupt Selection Register Interrupt Selection Register Interrupt Selection Register (reserved Interrupt Selection) Priority Control Register Sampling Mode Register Interrupt Selection Register (for channels) Interrupt Selection Register (for channels) DESCRIPTION
ADCCTL1 ADCINTFLG ADCINTFLGCLR ADCINTOVF ADCINTOVFCLR ADCINTSEL1AND2 ADCINTSEL3AND4 ADCINTSEL5AND6 ADCINTSEL7AND8 ADCINTSEL9AND10 ADCSOCPRIORITYCTL ADCSAMPLEMODE ADCINTSOCSEL1 ADCINTSOCSEL2
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Table 4-1. Configuration Control Registers (continued)
REGISTER NAME ADCSOCFLG1 ADCSOCFRC1 ADCSOCOVF1 ADCSOCOVFCLR1 ADCSOC0CTL ADCSOC15CTL ADCREFTRIM ADCOFFTRIM ADCREV ADDRESS 0x7118 0x711A 0x711C 0x711E 0x7120 0x712F 0x7140 0x7141 0x714F SIZE (x16) EALLOW PROTECTED DESCRIPTION Flag Register (for channels) Force Register (for channels) Overflow Register (for channels) Overflow Clear Register (for channels) SOC0 Control Register SOC15 Control Register Reference Trim Register Offset Trim Register Revision Register
Table 4-2. Result Registers (Mapped PF0)
REGISTER NAME ADCRESULT0 ADCRESULT15 ADDRESS 0xB00 0xB0F SIZE (x16) EALLOW PROTECTED DESCRIPTION Result Register Result Register
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0-Wait Result Registers
(CPU)
(CPU) SYSCLKOUT ADCENCLK ADCINT ADCINT Channels Core 12-Bit ADCTRIG ADCTRIG ADCTRIG ADCTRIG ADCTRIG ADCTRIG ADCTRIG ADCTRIG ADCTRIG ADCTRIG ADCTRIG ADCTRIG TINT TINT TINT XINT 2SOC SOCA SOCB SOCA SOCB SOCA SOCB SOCA SOCB CPUTIMER CPUTIMER CPUTIMER XINT ePWM ePWM ePWM ePWM
Figure 4-2. Connections
Peripherals
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4.1.2
COMPy input
Channel
AIOx AIOxIN AIOxINE
Logic implemented GPIO block SYSCLK
AIODAT (Latch)
AIOxDIR Input, Output)
AIOMUX
AIOSET, AIOCLEAR, AIOTOGGLE Regs
Input, Output) IORS
AIODIR (Latch)
Figure 4-3. channel Comparator functions always available. digital function available only when respective AIOMUX1 register this mode, reading AIODAT register reflects actual state. digital function disabled when respective AIOMUX1 register cleared this mode, reading AIODAT register reflects output latch AIODAT register input digital buffer disabled prevent analog signals from generating noise. reset, digital function disabled. used analog input, users should keep function disabled that pin.
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SYNC
AIODAT (Read)
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4.1.3
Comparator Block
Figure shows interaction Comparator modules with rest system.
COMP COMP COMP COMP Wrapper COMPxOUT Core 10-Bit
GPIO
TZ1/2/3
ePWM
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Figure 4-4. Comparator Block Diagram Table 4-3. Comparator Control Registers
REGISTER NAME COMPCTL COMPSTS DACVAL COMP1 ADDRESS 0x6400 0x6402 0x6406 COMP2 ADDRESS 0x6420 0x6422 0x6426 SIZE (x16) EALLOW PROTECTED DESCRIPTION Comparator Control Register Comparator Status Register Value Register
Peripherals
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Serial Peripheral Interface (SPI) Module
device includes four-pin serial peripheral interface (SPI) module. module (SPI-A) available. high-speed, synchronous serial port that allows serial stream programmed length (one sixteen bits) shifted into device programmable bit-transfer rate. Normally, used communications between external peripherals another processor. Typical applications include external peripheral expansion through devices such shift registers, display drivers, ADCs. Multidevice communications supported master/slave operation SPI. module features include: Four external pins: SPISOMI: slave-output/master-input SPISIMO: slave-input/master-output SPISTE: slave transmit-enable SPICLK: serial-clock NOTE: four pins used GPIO module used. operational modes: master slave Baud rate: different programmable rates.
Baud rate Baud rate LSPCLK (SPIBRR LSPCLK when SPIBRR when SPIBRR 0,1,
Data word length: sixteen data bits Four clocking schemes (controlled clock polarity clock phase bits) include: Falling edge without phase delay: SPICLK active-high. transmits data falling edge SPICLK signal receives data rising edge SPICLK signal. Falling edge with phase delay: SPICLK active-high. transmits data half-cycle ahead falling edge SPICLK signal receives data falling edge SPICLK signal. Rising edge without phase delay: SPICLK inactive-low. transmits data rising edge SPICLK signal receives data falling edge SPICLK signal. Rising edge with phase delay: SPICLK inactive-low. transmits data half-cycle ahead falling edge SPICLK signal receives data rising edge SPICLK signal. Simultaneous receive transmit operation (transmit function disabled software) Transmitter receiver operations accomplished through either interrupt-driven polled algorithms. Nine module control registers: Located control register frame beginning address 7040h.
NOTE registers this module 16-bit registers that connected Peripheral Frame When register accessed, register data lower byte (7-0), upper byte (15-8) read zeros. Writing upper byte effect.
Enhanced feature: 4-level transmit/receive FIFO Delayed transmit control Bi-directional wire mode support port operation configured controlled registers listed Table 4-4.
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Table 4-4. SPI-A Registers
NAME SPICCR SPICTL SPISTS SPIBRR SPIRXEMU SPIRXBUF SPITXBUF SPIDAT SPIFFTX SPIFFRX SPIFFCT SPIPRI ADDRESS 0x7040 0x7041 0x7042 0x7044 0x7046 0x7047 0x7048 0x7049 0x704A 0x704B 0x704C 0x704F SIZE (x16) EALLOW PROTECTED DESCRIPTION SPI-A Configuration Control Register SPI-A Operation Control Register SPI-A Status Register SPI-A Baud Rate Register SPI-A Receive Emulation Buffer Register SPI-A Serial Input Buffer Register SPI-A Serial Output Buffer Register SPI-A Serial Data Register SPI-A FIFO Transmit Register SPI-A FIFO Receive Register SPI-A FIFO Control Register SPI-A Priority Control Register
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Registers this table mapped Peripheral Frame This space only allows 16-bit accesses. 32-bit accesses produce undefined results.
Peripherals
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Figure block diagram slave mode.
SPIFFENA SPIFFTX.14 FIFO Registers SPIRXBUF FIFO FIFO FIFO SPIRXBUF Buffer Register
Receiver Overrun Flag SPISTS.7
Overrun
SPICTL.4
FIFO Interrupt
SPIINT Interrupt Logic
SPIFFOVF FLAG SPIFFRX.15
FIFO Registers SPITXBUF FIFO FIFO FIFO SPITXBUF Buffer Register FIFO Interrupt
Interrupt Logic SPITX FLAG SPISTS.6 SPICTL.0 TRIWIRE SPIPRI.0
SPIDAT Data Register Talk SPICTL.1
SPISIMO
SPIDAT.15
SPISOMI
SPISTE State Control Master/Slave Char SPICCR.3 SPICTL.2 Clock Polarity SPICCR.6 Clock Phase SPICTL.3 SPICLK
Rate LSPCLK SPIBRR.6
SPISTE driven master slave device.
Figure 4-5. Module Block Diagram (Slave Mode)
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Serial Communications Interface (SCI) Module
devices include serial communications interface (SCI) module (SCI-A). module supports digital communications between other asynchronous peripherals that standard non-return-to-zero (NRZ) format. receiver transmitter double-buffered, each separate enable interrupt bits. Both operated independently simultaneously full-duplex mode. ensure data integrity, checks received data break detection, parity, overrun, framing errors. rate programmable over 65000 different speeds through 16-bit baud-select register. Features each module include: external pins: SCITXD: transmit-output SCIRXD: receive-input NOTE: Both pins used GPIO used SCI. Baud rate programmable different rates:
Baud rate Baud rate LSPCLK (BRR LSPCLK when when
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Data-word format start Data-word length programmable from eight bits Optional even/odd/no parity stop bits Four error-detection flags: parity, overrun, framing, break detection wake-up multiprocessor modes: idle-line address Half- full-duplex operation Double-buffered receive transmit functions Transmitter receiver operations accomplished through interrupt-driven polled algorithms with status flags. Transmitter: TXRDY flag (transmitter-buffer register ready receive another character) EMPTY flag (transmitter-shift register empty) Receiver: RXRDY flag (receiver-buffer register ready receive another character), BRKDT flag (break condition occurred), ERROR flag (monitoring four interrupt conditions) Separate enable bits transmitter receiver interrupts (except BRKDT) (non-return-to-zero) format
NOTE registers this module 8-bit registers that connected Peripheral Frame When register accessed, register data lower byte (7-0), upper byte (15-8) read zeros. Writing upper byte effect.
Enhanced features: Auto baud-detect hardware logic 4-level transmit/receive FIFO
Peripherals
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port operation configured controlled registers listed Table 4-5. Table 4-5. SCI-A Registers
NAME SCICCRA SCICTL1A SCIHBAUDA SCILBAUDA SCICTL2A SCIRXSTA SCIRXEMUA SCIRXBUFA SCITXBUFA SCIFFTXA SCIFFRXA SCIPRIA
ADDRESS 0x7050 0x7051 0x7052 0x7053 0x7054 0x7055 0x7056 0x7057 0x7059 0x705A 0x705B 0x705C 0x705F
SIZE (x16)
EALLOW PROTECTED
DESCRIPTION SCI-A Communications Control Register SCI-A Control Register SCI-A Baud Register, High Bits SCI-A Baud Register, Bits SCI-A Control Register SCI-A Receive Status Register SCI-A Receive Emulation Data Buffer Register SCI-A Receive Data Buffer Register SCI-A FIFO Transmit Register SCI-A FIFO Receive Register SCI-A FIFO Control Register SCI-A Priority Control Register
SCIFFCTA
Registers this table mapped Peripheral Frame space. This space only allows 16-bit accesses. 32-bit accesses produce undefined results. These registers registers FIFO mode.
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SCI-A Transmit Data Buffer Register
TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
SPRS523B NOVEMBER 2008 REVISED APRIL 2009 www.ti.com
Figure shows module block diagram.
SCICTL1.1 Frame Format Mode Parity Even/Odd Enable SCICCR.6 SCICCR.5 TXSHF Register
Transmitter-Data Buffer Register
SCITXD TXENA EMPTY SCICTL2.6 TXRDY SCICTL2.0
FIFO Interrupts
Interrupt Logic
SCITXD
TXWAKE SCICTL1.3
SCICTL2.7
TXINT
FIFO FIFO
FIFO
Interrupt select logic
AutoBaud Detect logic
SCITXBUF.7-0
FIFO registers
ADVANCE INFORMATION
SCIFFENA SCIFFTX.14
SCIHBAUD. Baud Rate MSbyte Register LSPCLK SCILBAUD. Baud Rate LSbyte Register
Receive Data Buffer register SCIRXBUF.7-0
RXSHF Register
SCIRXD SCIRXD RXWAKE SCIRXST.1
RXENA SCICTL1.0 SCICTL2.1 RXRDY SCIRXST.6 BRKDT
FIFO Interrupts
RX/BK
FIFO FIFO_1
SCIRXST.5
Interrupt Logic
FIFO SCIRXBUF.7-0
RXINT
FIFO registers SCIRXST.7 Error SCIRXST.4 Error SCICTL1.6 Interrupt select logic RXFFOVF SCIFFRX.15
Figure 4-6. Serial Communications Interface (SCI) Module Block Diagram
Peripherals
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Inter-Integrated Circuit (I2C)
device contains Serial Port. Figure shows peripheral module interfaces within device. module following features: Compliance with Philips Semiconductors I2C-bus specification (version 2.1): Support 1-bit 8-bit format transfers 7-bit 10-bit addressing modes General call START byte mode Support multiple master-transmitters slave-receivers Support multiple slave-transmitters master-receivers Combined master transmit/receive receive/transmit mode Data transfer rate from kbps kbps (I2C Fast-mode rate) 4-word receive FIFO 4-word transmit FIFO interrupt that used CPU. This interrupt generated result following conditions: Transmit-data ready Receive-data ready Register-access ready No-acknowledgment received Arbitration lost Stop condition detected Addressed slave additional interrupt that used when FIFO mode Module enable/disable capability Free data format mode
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Peripherals
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TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
SPRS523B NOVEMBER 2008 REVISED APRIL 2009 www.ti.com
module
I2CXSR
I2CDXR
FIFO FIFO Peripheral I2CRSR I2CDRR Control/status registers FIFO Interrupt CPU/PIE
Clock synchronizer
ADVANCE INFORMATION
Prescaler
Noise filters Arbitrator
Interrupt CPU/PIE
registers accessed SYSCLKOUT rate. internal timing signal waveforms port also SYSCLKOUT rate. clock enable (I2CAENCLK) PCLKCRO register turns clock port power operation. Upon reset, I2CAENCLK clear, which indicates peripheral internal clocks off.
Figure 4-7. Peripheral Module Interfaces registers Table configure control port operation. Table 4-6. I2C-A Registers
NAME I2COAR I2CIER I2CSTR I2CCLKL I2CCLKH I2CCNT I2CDRR I2CSAR I2CDXR I2CMDR I2CISRC I2CPSC I2CFFTX I2CFFRX I2CRSR I2CXSR ADDRESS 0x7900 0x7901 0x7902 0x7903 0x7904 0x7905 0x7906 0x7907 0x7908 0x7909 0x790A 0x790C 0x7920 0x7921 EALLOW PROTECTED DESCRIPTION address register interrupt enable register status register clock low-time divider register clock high-time divider register data count register data receive register slave address register data transmit register mode register interrupt source register prescaler register FIFO transmit register FIFO receive register receive shift register (not accessible CPU) transmit shift register (not accessible CPU)
Peripherals
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TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
Enhanced Modules (ePWM1/2/3/4)
devices contain four enhanced Modules (ePWM). Figure shows block diagram multiple ePWM modules. Figure shows signal interconnections with ePWM. TMS320x2802x, 2803x Piccolo Enhanced Pulse Width Modulator (ePWM) Module Reference Guide (literature number SPRUGE9) more details. Table shows complete ePWM register module.
EPWMSYNCI
EPWM1SYNCI EPWM1TZINT EPWM1INT EPWM2TZINT EPWMxTZINT EPWMxINT EMUSTOP EPWM1ENCLK TBCLKSYNC EPWM1SYNCO EPWM1SYNCO COMPOUT1 COMPOUT2 EPWM2SYNCI ePWM2 Module CLOCKFAIL EMUSTOP EPWM2ENCLK TBCLKSYNC EPWM2SYNCO eCAPI EPWM2INT ePWM1 Module
EPWM1B
CLOCKFAIL
EPWM2B
COMP
EPWM1A EPWM2A EPWMxA EPWMxB
SOCA1 SOCB1 SOCA2 SOCB2 SOCAx SOCBx
EPWMxSYNCI ePWMx Module CLOCKFAIL EMUSTOP EPWMxENCLK TBCLKSYNC
System Control C28x SOCA1 SOCA2 SPCAx ADCSOCAO Pulse Stretch SYSCLKOUT Cycles, Active-Low Output)
SOCB1 SOCB2 SPCBx
ADCSOCBO Pulse Stretch SYSCLKOUT Cycles, Active-Low Output)
Figure 4-8. ePWM
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Peripherals
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Peripheral
TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
SPRS523B NOVEMBER 2008 REVISED APRIL 2009 www.ti.com
Table 4-7. ePWM Control Status Registers
NAME TBCTL TBSTS TBPHSHR TBPHS TBCTR TBPRD TBPRDHR CMPCTL CMPAHR CMPA CMPB AQCTLA AQCTLB AQSFRC AQCSFRC DBCTL DBRED DBFED TZSEL TZDCSEL TZCTL TZEINT TZFLG TZCLR TZFRC ETSEL ETPS ETFLG ETCLR ETFRC PCCTL HRCNFG ePWM1 0x6800 0x6801 0x6802 0x6803 0x6804 0x6805 0x6806 0x6807 0x6808 0x6809 0x680A 0x680B 0x680C 0x680D 0x680E 0x680F 0x6810 0x6811 0x6812 0x6813 0x6814 0x6815 0x6816 0x6817 0x6818 0x6819 0x681A 0x681B 0x681C 0x681D 0x681E 0x6820 ePWM2 0x6840 0x6841 0x6842 0x6843 0x6844 0x6845 0x6846 0x6847 0x6848 0x6849 0x684A 0x684B 0x684C 0x684D 0x684E 0x684F 0x6850 0x6851 0x6852 0x6853 0x6854 0x6855 0x6856 0x6857 0x6858 0x6859 0x685A 0x685B 0x685C 0x685D 0x685E 0x6860 ePWM3 0x6880 0x6881 0x6882 0x6883 0x6884 0x6885 0x6886 0x6887 0x6888 0x6889 0x688A 0x688B 0x688C 0x688D 0x688E 0x688F 0x6890 0x6891 0x6892 0x6893 0x6894 0x6895 0x6896 0x6897 0x6898 0x6899 0x689A 0x689B 0x689C 0x689D 0x689E 0x68A0 ePWM4 0x68C0 0x68C1 0x68C2 0x68C3 0x68C4 0x68C5 0x68C6 0x68C7 0x68C8 0x68C9 0x68CA 0x68CB 0x68CC 0x68CD 0x68CE 0x68CF 0x68D0 0x68D1 0x68D2 0x98D3 0x68D4 0x68D5 0x68D6 0x68D7 0x68D8 0x68D9 0x68DA 0x68DB 0x68DC 0x68DD 0x68DE 0x68E0 SIZE (x16) #SHADOW DESCRIPTION Time Base Control Register Time Base Status Register Time Base Phase HRPWM Register Time Base Phase Register Time Base Counter Register Time Base Period Register Time Base Period High Resolution Register Counter Compare Control Register Time Base Compare HRPWM Register Counter Compare Register Counter Compare Register Action Qualifier Control Register Output Action Qualifier Control Register Output Action Qualifier Software Force Register Action Qualifier Continuous Force Register Dead-Band Generator Control Register Dead-Band Generator Rising Edge Delay Count Register Dead-Band Generator Falling Edge Delay Count Register Trip Zone Select Register Trip Zone Digital Compare Register Trip Zone Control Register Trip Zone Enable Interrupt Register Trip Zone Flag Register
Trip Zone Clear Register Trip Zone Force Register Event Trigger Selection Register Event Trigger Prescale Register Event Trigger Flag Register Event Trigger Clear Register Event Trigger Force Register Chopper Control Register HRPWM Configuration Register
Registers that EALLOW protected. Peripherals Submit Documentation Feedback
TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
NAME HRPWR HRMSTEP HRPCTL TBPRDHRM TBPRDM CMPAHRM CMPAM DCTRIPSEL DCACTL DCBCTL DCFCTL DCCAPCT DCFOFFSET DCFOFFSETCNT DCFWINDOW DCFWINDOWCNT DCCAP
ePWM1 0x6821 0x6826 0x6828 0x682A 0x682B 0x682C 0x682D 0x6830 0x6831 0x6832 0x6833 0x6834 0x6835 0x6836 0x6837 0x6838 0x6839
ePWM2 0x6868 0x686A 0x686B 0x686C 0x686D 0x6870 0x6871 0x6872 0x6873 0x6874 0x6875 0x6876 0x6877 0x6878 0x6879
ePWM3 0x68A8 0x68AA 0x68AB 0x68AC 0x68AD 0x68B0 0x68B1 0x68B2 0x68B3 0x68B4 0x68B5 0x68B6 0x68B7 0x68B8 0x68B9
ePWM4 0x68E8 0x68EA 0x68EB 0x68EC 0x68ED 0x68F0 0x68F1 0x68F2 0x68F3 0x68F4 0x68F5 0x68F6 0x68F7 0x68F8 0x68F9
SIZE (x16) #SHADOW
DESCRIPTION HRPWM Power Register HRPWM Step Register High resolution Period Control Register Time Base Period HRPWM Register Mirror Time Base Period Register Mirror Compare HRPWM Register Mirror Compare Register Mirror Digital Compare Trip Select Register Digital Compare Control Register
Digital Compare Control Register Digital Compare Filter Control Register Digital Compare Capture Control Register Digital Compare Filter Offset Register Digital Compare Filter Offset Counter Register Digital Compare Filter Window Register Digital Compare Filter Window Counter Register Digital Compare Counter Capture Register
Write shadow register
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Peripherals
TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
SPRS523B NOVEMBER 2008 REVISED APRIL 2009
Time-Base (TB) CTR=ZERO TBPRD Shadow (24) TBPRD Active (24) TBPRDHR CTR=PRD TBCTL[CNTLDE] Counter Up/Down Bit) CTR=ZERO TCBNT Active (16) Phase Control CTR_Dir TBPHSHR TBCTL[SYNCOSEL] EPWMxSYNCI DCAEVT1.sync DCBEVT1.sync CTR=CMPB Disabled Sync In/Out Select
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EPWMxSYNCO
TBCTL[SWFSYNC] (Software Forced Sync) CTR=PRD CTR=ZERO CTR=PRD ZERO CTR=CMPA CTR=CMPB CTR_Dir DCAEVT1.soc DCBEVT1.soc
EPWMxINT Event Trigger Interrupt (ET) EPWMxSOCA EPWMxSOCB EPWMxSOCA EPWMxSOCB
ADVANCE INFORMATION
TBPHS Active (24)
CTR=CMPA CMPAHR
Action Qualifier (AQ)
HiRes (HRPWM) CMPA Active (24) CMPA Shadow (24) EPWMA Dead Band (DB) Chopper (PC) Trip Zone (TZ) EPWMxA
CTR=CMPB CMPB Active (16) CMPB Shadow (16) EPWMB
EPWMxB EPWMxTZINT CTR=ZERO DCAEVT1.inter DCBEVT1.inter DCAEVT2.inter DCBEVT2.inter EMUSTOP CLOCKFAIL DCAEVT1.force DCAEVT2.force DCBEVT1.force DCBEVT2.force
These events generated Type ePWM digital compare (DC) submodule based levels COMPxOUT signals.
Figure 4-9. ePWM Sub-Modules Showing Critical Internal Signal Interconnections
Peripherals
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High-Resolution (HRPWM)
This module combines multiple delay lines single module simplified calibration system using dedicated calibration delay line. each ePWM module there delay line. HRPWM module offers resolution (time granularity) that significantly better than what achieved using conventionally derived digital methods. points HRPWM module are: Significantly extends time resolution capabilities conventionally derived digital This capability utilized both single edge (duty cycle phase-shift control) well dual edge control frequency/period modulation. Finer time granularity control edge positioning controlled extensions Compare Phase registers ePWM module. HRPWM capabilities, when available particular device, offered only signal path ePWM module (i.e., EPWMxA output). EPWMxB output conventional capabilities.
NOTE SYSCLKOUT frequencies below under worst-case process, voltage, temperature (maximum voltage minimum temperature) conditions, step delay decrease point such that maximum steps cover full SYSCLKOUT cycle. other words, high-resolution edge control will available full range SYSCLKOUT cycle. running calibration software, function will return error code when this occurs. TMS320x2802x, 2803x Piccolo High-Resolution Pulse Width Modulator (HRPWM) Reference Guide (literature number SPRUGE8) more information this error condition.
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Peripherals
ADVANCE INFORMATION
TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
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Enhanced Capture Module (eCAP1)
device contains enhanced capture (eCAP) module. Figure 4-10 shows functional block diagram module.
CTRPHS (phase register-32 bit) TSCTR (counter-32 bit) [0-31] [0-31] CTR=PRD CTR=CMP CTR_OVF Delta-mode
SYNCIn SYNCOut
SYNC
APWM mode [0-31] [0-31] [0-31]
compare logic
ADVANCE INFORMATION
CAP1 (APRD active) APRD shadow
Polarity select
[0-31]
CAP2 (ACMP active)
Polarity select Event qualifier Event Pre-scale Polarity select
ACMP shadow
CAP3 (APRD shadow)
CAP4 (ACMP shadow)
Polarity select
Capture events CEVT[1:4] Interrupt Trigger Flag control
CTR_OVF CTR=PRD CTR=CMP
Continuous Oneshot Capture Control
Figure 4-10. eCAP Functional Block Diagram eCAP module clocked SYSCLKOUT rate. clock enable bits (ECAP1 ENCLK) PCLKCR1 register turn eCAP module individually (for power operation). Upon reset, ECAP1ENCLK low, indicating that peripheral clock off.
Peripherals
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MODE SELECT
eCAPx
TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
Table 4-8. eCAP Control Status Registers
NAME TSCTR CTRPHS CAP1 CAP2 CAP3 CAP4 Reserved ECCTL1 ECCTL2 ECEINT ECFLG ECCLR ECFRC Reserved eCAP1 0x6A00 0x6A02 0x6A04 0x6A06 0x6A08 0x6A0A 0x6A0C- 0x6A12 0x6A14 0x6A15 0x6A16 0x6A17 0x6A18 0x6A19 0x6A1A- 0x6A1F SIZE (x16) EALLOW PROTECTED DESCRIPTION Time-Stamp Counter Counter Phase Offset Value Register Capture Register Capture Register Capture Register Capture Register Reserved Capture Control Register Capture Control Register Capture Interrupt Enable Register Capture Interrupt Clear Register Capture Interrupt Force Register Reserved Capture Interrupt Flag Register
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Peripherals
ADVANCE INFORMATION
TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
SPRS523B NOVEMBER 2008 REVISED APRIL 2009 www.ti.com
JTAG Port
2802x device, JTAG port reduced pins (TRST, TCK, TDI, TMS, TDO). TCK, TDI, pins also GPIO pins. TRST signal selects either JTAG GPIO operating mode pins Figure 4-11. During emulation/debug, GPIO function these pins available. GPIO38/TCK/XCLKIN used provide external clock, alternate clock source should used clock device during emulation/debug since this will needed function.
NOTE 2802x devices, JTAG pins also used GPIO pins. Care should taken board design ensure that circuitry connected these pins affect emulation capabilities JTAG function. circuitry connected these pins should prevent emulator from driving being driven JTAG pins successful debug.
ADVANCE INFORMATION
TRST JTAG Disabled (GPIO Mode) TRST JTAG Mode TRST TRST
XCLKIN GPIO38_in TCK/GPIO38 GPIO38_out
C28x Core
GPIO37_in TDO/GPIO37 GPIO36_in TMS/GPIO36 GPIO36_out GPIO35_in TDI/GPIO35 GPIO35_out GPIO37_out
Figure 4-11. JTAG/GPIO Multiplexing
Peripherals
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GPIO
GPIO multiplex three independent peripheral signals single GPIO addition providing individual bit-banging capability. device supports GPIO pins. GPIO control data registers mapped Peripheral Frame enable 32-bit operations registers (along with 16-bit operations). Table shows GPIO register mapping. Table 4-9. GPIO Registers
NAME GPACTRL GPAQSEL1 GPAQSEL2 GPAMUX1 GPAMUX2 GPADIR GPAPUD GPBCTRL GPBQSEL1 GPBMUX1 GPBDIR GPBPUD AIOMUX1 AIODIR GPADAT GPASET GPACLEAR GPATOGGLE GPBDAT GPBSET GPBCLEAR GPBTOGGLE AIODAT AIOSET AIOCLEAR AIOTOGGLE GPIOXINT1SEL GPIOXINT2SEL GPIOXINT3SEL GPIOLPMSEL ADDRESS 0x6F80 0x6F82 0x6F84 0x6F86 0x6F88 0x6F8A 0x6F8C 0x6F90 0x6F92 0x6F96 0x6F9A 0x6F9C 0x6FB6 0x6FBA 0x6FC0 0x6FC2 0x6FC4 0x6FC6 0x6FC8 0x6FCA 0x6FCC 0x6FCE 0x6FD8 0x6FDA 0x6FDC 0x6FDE 0x6FE0 0x6FE1 0x6FE2 0x6FE8 SIZE (x16) DESCRIPTION GPIO Control Register (GPIO0 GPIO Qualifier Select Register (GPIO0 GPIO Register (GPIO0 GPIO Register (GPIO16 GPIO Direction Register (GPIO0 GPIO Pull Disable Register (GPIO0 GPIO Control Register (GPIO32 GPIO Qualifier Select Register (GPIO32 GPIO Register (GPIO32 GPIO Direction Register (GPIO32 GPIO Pull Disable Register (GPIO32 Analog, register (AIO0 AIO15) Analog, Direction Register (AIO0-AIO15) GPIO Data Register (GPIO0 GPIO Data Register (GPIO0 GPIO Data Clear Register (GPIO0 GPIO Data Toggle Register (GPIO0 GPIO Data Register (GPIO32 GPIO Data Register (GPIO32 GPIO Data Clear Register (GPIO32 GPIO Data Toggle Register (GPIO32 Analog Data Register (AIO0 AIO15) Analog Data Register (AIO0 AIO15) Analog Data Clear Register (AIO0 AIO15) Analog Data Toggle Register (AIO0 AIO15) XINT1 GPIO Input Select Register (GPIO0 XINT2 GPIO Input Select Register (GPIO0 XINT3 GPIO Input Select Register (GPIO0 GPIO Select Register (GPIO0 GPIO Qualifier Select Register (GPIO16-31) GPIO CONTROL REGISTERS (EALLOW PROTECTED)
GPIO DATA REGISTERS (NOT EALLOW PROTECTED)
GPIO INTERRUPT POWER MODES SELECT REGISTERS (EALLOW PROTECTED)
NOTE There two-SYSCLKOUT cycle delay from when write GPxMUXn/AIOMUXn GPxQSELn registers occurs when action valid.
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Peripherals
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TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
SPRS523B NOVEMBER 2008 REVISED APRIL 2009 www.ti.com
Table 4-10. GPIOA
DEFAULT RESET PRIMARY FUNCTION GPAMUX1 REGISTER BITS 11-10 13-12 15-14 17-16 19-18 21-20 23-22 25-24 27-26 29-28 31-30 GPAMUX2 REGISTER BITS 11-10 13-12 15-14 17-16 19-18 21-20 23-22 25-24 27-26 29-28 31-30 (GPAMUX1 BITS GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 Reserved Reserved Reserved Reserved GPIO12 Reserved Reserved Reserved (GPAMUX2 BITS GPIO16 GPIO17 GPIO18 GPIO19/XCLKIN Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved GPIO28 GPIO29 Reserved Reserved PERIPHERAL SELECTION (GPAMUX1 BITS EPWM1A EPWM1B EPWM2A EPWM2B EPWM3A EPWM3B EPWM4A EPWM4B Reserved Reserved Reserved Reserved Reserved Reserved Reserved (GPAMUX2 BITS SPISIMOA (I/O) SPISOMIA (I/O) SPICLKA (I/O) SPISTEA (I/O) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SCIRXDA SCITXDA Reserved Reserved PERIPHERAL SELECTION (GPAMUX1 BITS Reserved Reserved Reserved Reserved Reserved Reserved EPWMSYNCI SCIRXDA Reserved Reserved Reserved Reserved SCITXDA Reserved Reserved Reserved (GPAMUX2 BITS Reserved Reserved SCITXDA SCIRXDA Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SDAA (I/OC) SCLA (I/OC) Reserved Reserved PERIPHERAL SELECTION (GPAMUX1 bits Reserved COMP1OUT Reserved COMP2OUT Reserved ECAP1 (I/O) EPWMSYNCO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved (GPAMUX2 BITS XCLKOUT ECAP1 (I/O) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
ADVANCE INFORMATION
word reserved means that there peripheral assigned this GPxMUX1/2 register setting. Should selected, state will undefined driven. This selection reserved configuration future expansion. These functions available 38-pin package.
Peripherals
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Table 4-11. GPIOB
DEFAULT RESET PRIMARY FUNCTION GPBMUX1 REGISTER BITS 11-10 13-12 15-14 17-16 19-18 21-20 23-22 25-24 27-26 29-28 31-30 (GPBMUX1 BITS GPIO32
PERIPHERAL SELECTION (GPBMUX1 BITS SDAA
PERIPHERAL SELECTION (GPBMUX1 BITS EPWMSYNCI
PERIPHERAL SELECTION (GPBMUX1 BITS ADCSOCAO ADCSOCBO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
(I/OC)
GPIO33 GPIO34 GPIO35 (TDI) GPIO36 (TMS) GPIO37 (TDO) GPIO38/XCLKIN (TCK) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
SCLA (I/OC) COMP2OUT Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
EPWMSYNCO Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
These pins available 38-pin package.
Table 4-12. Analog
DEFAULT RESET AIOx PERIPHERAL SELECTION AIOMUX1 REGISTER BITS 11-10 13-12 15-14 17-16 19-18 21-20 23-22 25-24 27-26 29-28 31-30 These pins available 38-pin package. These functions available 38-pin package. AIOMUX1 BITS ADCINA0 ADCINA1
PERIPHERAL SELECTION PERIPHERAL SELECTION AIOMUX1 BITS ADCINA0 ADCINA1 ADCINA2 (I), COMP1A ADCINA3 ADCINA4 (I), COMP2A ADCINA5 ADCINA6 ADCINA7 ADCINB0 ADCINB1 ADCINB2 (I), COMP1B ADCINB3 ADCINB4 (I), COMP2B ADCINB5 ADCINB6 ADCINB7
AIO2 (I/O) ADCINA3 AIO4 (I/O) ADCINA5 AIO6 (I/O) ADCINA7 ADCINB0 ADCINB1 AIO10 (I/O) ADCINB3
AIO12 (I/O) ADCINB5 AIO14 (I/O) ADCINB7
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Peripherals
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TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
SPRS523B NOVEMBER 2008 REVISED APRIL 2009 www.ti.com
user select type input qualification each GPIO GPxQSEL1/2 registers from four choices: Synchronization SYSCLKOUT Only (GPxQSEL1/2=0, This default mode GPIO pins reset simply synchronizes input signal system clock (SYSCLKOUT). Qualification Using Sampling Window (GPxQSEL1/2=0, this mode input signal, after synchronization system clock (SYSCLKOUT), qualified specified number cycles before input allowed change. sampling period specified QUALPRD bits GPxCTRL register configurable groups signals. specifies multiple SYSCLKOUT cycles sampling input signal. sampling window either 3-samples 6-samples wide output only changed when samples same (all shown Figure 4-18 (for sample mode). Synchronization (GPxQSEL1/2=1,1): This mode used peripherals where synchronization required (synchronization performed within peripheral).
ADVANCE INFORMATION
multi-level multiplexing that required device, there cases where peripheral input signal mapped more then GPIO pin. Also, when input signal selected, input signal will default either state, depending peripheral.
Peripherals
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GPIOXINT1SEL GPIOLMPSEL LPMCR0 GPIOXINT2SEL GPIOXINT3SEL
ower Modes Block
External Interrupt
Asynchronous path GPxQSEL1/2 GPxCTRL GPxPUD Input Qualification Asynchronous path GPIOx
GPxDAT (read)
Internal Pullup
Peripheral Input Peripheral Input GPxTOGGLE GPxCLEAR GPxSET
High Impedance Output Control Input, Output
GPxDAT (latch) Peripheral Output Peripheral Output Peripheral Output
GPxDIR (latch) Peripheral Output Enable Peripheral Output Enable Peripheral Output Enable
Default Reset
GPxMUX1/2
Figure 4-12. GPIO Multiplexing
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Peripherals
ADVANCE INFORMATION
Peripheral Input
TMS320F28020, TMS320F28021, TMS320F28022 TMS320F28023, TMS320F28026, TMS320F28027 Piccolo Microcontrollers
SPRS523B NOVEMBER 2008 REVISED APRIL 2009 www.ti.com
Device Support
Texas Instruments (TI) offers extensive line development tools C28xgeneration MCUs, including tools evaluate performance processors, generate code, develop algorithm implementations, fully integrate debug software hardware modules. following products support development 2802x-based applications: Software Development Tools Code Composer StudioIntegrated Development Environment (IDE) C/C++ Compiler Code generation tools Assembler/Linker Cycle Accurate Simulator Application algorithms Sample applications code Hardware Development Tools Development evaluation boards JTAG-based emulators XDS510Class, XDS100 Flash programming tools Power supply Documentation cables
ADVANCE INFORMATION
Device Development Support Tool Nomenclature
designate stages product development cycle, assigns prefixes part numbers TMS320MCU devices support tools. Each TMS320MCU commercial family member three prefixes: TMX, TMP, (e.g., TMS320F28023). Texas Instruments recommends three possible prefix designators support tools: TMDX TMDS. These prefixes represent evolutionary stages product development from engineering prototypes (TMX/TMDX) thro

TMS320F28020 TMS320F28021 TMS320F28022 TMS320F28023 TMS320F28026 TMS320F28027 TMS320F2802x

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