TMS320F280x TMS320C280x TMS320F2801x
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Silicon Errata
Literature Number: SPRZ171K December 2004 Revised March 2009
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Contents
Introduction Device Development Tool Support Nomenclature Device Markings Silicon Change Overview Known Design Marginality/Exceptions Functional Specifications Documentation Support Appendix Revision History
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Table Contents
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List Figures
Example Device Markings Example Device Nomenclature Difference Between Expected Erroneous Operation START
List Tables
Determining Silicon Revision From Trace Code (F2809) Determining Silicon Revision From Trace Code (C2801 C2802). Determining Silicon Revision From Trace Code (F2801, F2802, F2806, F2808, F28015 F28016) TMS320F2809 Silicon Change Overview TMS320C2802 TMS320C2801 Silicon Change Overview TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320F2801x Silicon Change Overview Advisory List Changes Made This Revision
List Figures
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Silicon Errata
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280x/2801x Silicon Errata
Introduction
This document describes silicon updates functional specifications TMS320C2801, TMS320C2802, TMS320F2801, TMS320F2802, TMS320F2806, TMS320F2808, TMS320F2809, TMS320F28015, TMS320F28016 digital signal processors (DSPs). updates applicable 100-ball MicroStar BGATM, GGM, suffix 100-pin thin quad flatpack, suffix Throughout this document, device names abbreviated follows: F280x TMS320F280x refers TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802 TMS320F2801 silicon C280x TMS320C280x refers TMS320C2802 TMS320C2801 silicon. F2801x TMS320F2801x refers TMS320F28015 TMS320F28016 silicon. Throughout this document, reference F2801 F2802 devices includes both 60-MHz 100-MHz versions.
Device Development Tool Support Nomenclature
designate stages product development cycle, assigns prefixes part numbers [TMS320] devices support tools. Each TMS320DSP commercial family member three prefixes: TMX, TMP, (e.g., TMS320F2808). Texas Instruments recommends three possible prefix designators support tools: TMDX TMDS. These prefixes represent evolutionary stages product development from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS). Experimental device that necessarily representative final device's electrical specifications Final silicon that conforms device's electrical specifications completed quality reliability verification Fully qualified production device
Support tool development evolutionary flow: TMDX Development-support product that completed Texas Instruments internal qualification testing TMDS Fully qualified development-support product devices TMDX development-support tools shipped against following disclaimer: "Developmental product intended internal evaluation purposes." devices TMDS development-support tools have been characterized fully, quality reliability device have been demonstrated fully. TI's standard warranty applies.
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Device Markings
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Predictions show that prototype devices (TMX TMP) have greater failure rate than standard production devices. Texas Instruments recommends that these devices used production system because their expected end-use failure rate still undefined. Only qualified production devices used. device nomenclature also includes suffix with device family name. This suffix indicates package type (for example, PBK) temperature range (for example,
Device Markings
Figure provides example TMS320F280x device markings defines each markings. device revision determined symbols marked package shown Figure Some prototype devices have markings different from those illustrated. Figure shows example device nomenclature.
320F2808GGMA CA-26ACRCW
SILICON REVISION
TRACE CODE
Figure Example Device Markings
PREFIX Experimental Device Prototype Device Qualified Device 28015 Indicates 60-MHz device Absence "-60" indicates 100-MHz device. TEMPERATURE RANGE -405C 855C -405C 1255C -405C 1255C Q100 Fault Grading PACKAGE TYPE 100-Pin Low-Profile Quad Flatpack (LQFP) 100-Ball Ball Grid Array (BGA) 100-Ball Lead-Free DEVICE 2809 2808 2806 2802 2801 28015 28016
DEVICE FAMILY TMS320E Family
TECHNOLOGY Flash EEPROM (1.8-V Core/3.3-V I/O)
Figure Example Device Nomenclature
280x/2801x Silicon Errata
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Device Markings
Table Determining Silicon Revision From Trace Code (F2809)
SECOND LETTER PREFIX TRACE CODE Blank second letter prefix) SILICON REVISION Indicates Revision Indicates Revision REVISION (0x0883) 0x0000 0x0001 F2809 COMMENTS This silicon revision available TMS. This silicon revision available TMS.
Table Determining Silicon Revision From Trace Code (C2801 C2802)
SECOND LETTER PREFIX TRACE CODE Blank second letter prefix) SILICON REVISION Indicates Revision Indicates Revision REVISION (0x0883) 0x0000 0x0001 C2801, C2802 COMMENTS This silicon revision available only. This silicon revision available TMS.
Table Determining Silicon Revision From Trace Code (F2801, F2802, F2806, F2808, F28015 F28016)
SECOND LETTER PREFIX TRACE CODE Blank second letter prefix) REVISION (0x0883) 0x0000 0x0001 0x0002 0x0003 F2801, F2802, F2806, F2808 COMMENTS This silicon revision available only. This silicon revision available only. This silicon revision available TMS. This silicon revision available TMS. F28015 F28016 COMMENTS internal only internal only internal only This silicon revision available TMS.
SILICON REVISION
Indicates Revision Indicates Revision Indicates Revision Indicates Revision
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Silicon Change Overview
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Silicon Change Overview
Table Table list change(s) made each silicon revision. Table TMS320F2809 Silicon Change Overview
REVISION CHANGES MADE following advisory fixed: "Input Clock: Device Startup Using XCLKIN Input". First silicon release. (This functionally equivalent Revision TMS320F280x silicon.)
Table TMS320C2802 TMS320C2801 Silicon Change Overview
REVISION CHANGES MADE silicon (This functionally equivalent Revision TMS320F280x silicon.) First silicon release. (This functionally equivalent Revision TMS320F280x silicon Internal only)
Table TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320F2801x Silicon Change Overview
REVISION following advisories were fixed: Watchdog module limitation crosstalk issue First silicon release. Flash tools: flash tools must updated F280x flash v3.00 (SPRC193) later. This backward-compatible with previous silicon versions. Previous versions will longer work. default state internal pullup resistors pins GPIO0 GPIO11 changed from enabled disabled. These pins correspond ePWM output pins. default state internal pullup resistors pins GPIO12 GPIO34 remains enabled. following advisory fixed: GPIO behavior power-up following advisories were fixed: Boot configuration pins asynchronous eCAN boot mode boot Initial Conversion Latency First silicon release. CHANGES MADE
280x/2801x Silicon Errata
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Known Design Marginality/Exceptions Functional Specifications
Known Design Marginality/Exceptions Functional Specifications
table contents advisories shown Table Table Advisory List
Title
Page
Input Clock: Device Startup Using XCLKIN Input Memory: Flash Prefetch Buffer Overflow Memory: Prefetching Beyond Valid Memory ADC: Simultaneous Sampling Latency ADC: Initial Conversion Latency ADC: Channel Channel Crosstalk Simultaneous Mode SCI: Incorrect Operation Address Mode. Bootloader Does Clear After Auto-Baud Lock. eCAN: When Option Invoked Boot ROM, Code Hang Occasionally eCAN: eCAN-A Boot Mode Boot eCAN: Abort Acknowledge Change Watchdog Module: Writes WDKEY Longer Cause RESET/Interrupt Generated Advisory Limitation Watchdog Module: Corrupted Watchdog Writes Advisory GPIO: Behavior Power-up Advisory GPIO: GPIO Qualification Advisory Advisory Advisory Advisory Advisory Advisory Advisory Advisory Advisory Advisory Advisory Advisory Advisory
Boot ROM: Configuration Change Boot ROM.
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280x/2801x Silicon Errata
Advisory Input Clock: Device Startup Using XCLKIN Input
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Advisory
Revision(s) Affected Details Workaround(s)
Input Clock: Device Startup Using XCLKIN Input applicable only F2809 silicon When clock device supplied using XCLKIN pin, device intermittently fail startup correctly. XCLKIN supply clock device. Instead, either crystal/resonator 1.8-V external oscillator clock device. This been fixed revision silicon.
280x/2801x Silicon Errata
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Advisory Memory: Flash Prefetch Buffer Overflow
Advisory
Revision(s) Affected
Memory: Flash Prefetch Buffer Overflow F2809 silicon C280x silicon F2801, F2802, F2806, F2808, F2801x silicon This advisory applies code executing from flash with flash prefetch buffer enabled. devices this applies that replaces flash OTP. flash prefetch buffer overflow instruction within eight 16-bit words preceding operation using indirect direct program-memory addressing. window which this occur shown below:
Address Offset 0x0000 (32-bit opcode) 0x0001 (16-bit opcode) -0x0002 SBF/BF word 0x0003 SBF/BF words 0x0004 SBF/BF words instruction within this window 0x0005 SBF/BF words uses program-memory addressing, 0x0006 SBF/BF words cause flash prefetch buffer 0x0007 SBF/BF words overflow. 0x0008 SBF/BF words 0x0009 SBF/BF words -0x0010 SBF/BF words
Details
Whether overflow actually occurs depends instruction sequence, flash wait states pipeline stalls. overflow occurs will result execution invalid opcodes. Instructions that program-memory addressing include MAC/XMAC, DMAC/XMACD, QMACL, IMACL, PREAD/XPREAD PWRITE/XPWRITE.
Workaround(s)
Hand-coded assembly: SB/B instructions instead SBF/BF code targeted execute from flash OTP. SB/B instructions more efficient wait-stated memory performance improvement also seen. Compiler-generated assembly: compiler switch force compiler generate SB/B instructions instead SBF/BF instructions. heavily wait stated memory SB/B instructions more efficient than SBF/BF. SARAM SBF/BF instructions more efficient. Therefore, this switch should applied follows: compiler switch source code that runs from flash OTP. compiler switch source code that runs from SARAM. file contains functions that runs from flash well functions that from SARAM. switch available C28x compiler V4.1.4 V5.0 beta3.
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280x/2801x Silicon Errata
Advisory Memory: Prefetching Beyond Valid Memory
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Advisory
Revision(s) Affected
Memory: Prefetching Beyond Valid Memory F2809 silicon C280x silicon F2801, F2802, F2806, F2808, F2801x silicon C28x prefetches instructions beyond those currently active pipeline. prefetch occurs past valid memory, then receive invalid opcode. prefetch queue 8x16 words depth. Therefore, code should come within words valid memory. This restriction applies memory regions memory types (Flash/ROM, OTP, SARAM) device. Prefetching across boundary between valid memory blocks Example ends address 0x7FF followed another memory block. Code should stored farther than address 0x7F7. Addresses 0x7F8-0x7FF should used code. Example ends address 0x3FF valid memory (M1) follows Code stored including address 0x3FF. Code also cross into including address 0x7F7.
Details
Workaround
280x/2801x Silicon Errata
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Advisory ADC: Simultaneous Sampling Latency
Advisory
Revision(s) Affected
ADC: Simultaneous Sampling Latency F2809 silicon C280x silicon F2801, F2802, F2806, F2808, F2801x silicon When conversions initiated simultaneous mode, first sample pair will give correct conversion results. used with sampling window then first sample pair must discarded second sample same pair must taken. instance, sequencer sample channel A0:B0/A1:B1/A2:B2 that order, then load sequencer with A0:B0/A0:B0/A1:B1/A2:B2 only last three conversions. used with sampling window greater than there issue.
Details Workaround(s)
Advisory
Revision(s) Affected Details Workaround(s)
ADC: Initial Conversion Latency F2808, F2806, F2801 silicon When conversions initiated source trigger, first samples correct conversion results. convert mega sample second (MSPS) higher, discard first samples instance, sequencer sample channel A0/A1/A2 that order, then load sequencer with A0/A0/A0/A1/A2 only last three conversions. conversion rates below MSPS, conversion latency will give appropriate time settle first conversion should valid. Each application should validate this acceptable their application. This been fixed revision silicon.
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280x/2801x Silicon Errata
Advisory ADC: Channel Channel Crosstalk Simultaneous Mode
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Advisory
Revision(s) Affected
ADC: Channel Channel Crosstalk Simultaneous Mode TMS320C280x silicon F2801, F2802, F2806, F2808, F2801x silicon When used simultaneous mode, voltage present channel will impact conversion value associated channel. channel unaffected channel. example, A4/B4 being sampled simultaneously, converted value will have error associated with value present Voltages other channels have impact likewise, affects only affects only etc. effect deterministic; from codes artificial increase. example, channel converted channel value will unaffected. then converted value will read counts high.
Details
Workaround(s)
deterministic nature coupling from simple subtraction made from channel based channel result. Formula given /256) Corrected result channel Measured result channel. Since effect pure adder, there impact linearity channel. Gain offset errors only nominally impacted, LSBs. Revision silicon design change address this errata. crosstalk will within datasheet specification channel-to-channel offset. most recent version TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, UCD9501, TMS320C2802, TMS320C2801, TMS320F2801x DSPs Data Manual (literature number SPRS230) more information.
280x/2801x Silicon Errata
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Advisory SCI: Incorrect Operation Address Mode
Advisory
Revision(s) Affected
SCI: Incorrect Operation Address Mode F2809 silicon C280x silicon F2801, F2802, F2806, F2808, F2801x silicon does look STOP after ADDR bit. Instead, starts looking start beginning sub-sample ADDR bit. Slow rise-time from ADDR STOP cause false START occur since sub-sample start sensed low.
Details
Expected Operation:
majority vote SCICLK
majority vote
start consecutive zero bits
SCIRXD ADDR STOP START
Erroneous Operation:
majority vote SCICLK majority vote
SCIRXD
ADDR START
STOP
Figure Difference Between Expected Erroneous Operation START
Workaround(s)
Program baud rate slightly slower than actual. This will cause sub-sample false START delayed time, therefore occur more towards middle STOP (away from signal transition region). amount baud slowing needed depends rise-time signal system. Alternatively, IDLE mode module used, applicable.
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280x/2801x Silicon Errata
Advisory Bootloader Does Clear After Auto-Baud Lock
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Advisory
Revision(s) Affected
Bootloader Does Clear After Auto-Baud Lock F2809 silicon C280x silicon F2801, F2802, F2806, F2808, F2801x silicon Details bootloader code does clear Auto-Baud Detect (ABD) SCIFFCT register after auto-baud process completes. SCI-A port used after bootloader executed, transmit interrupts (SCITXINTA) will able occur, will auto-baud lock feature SCI-A work correctly. bootloader been executed, user's application code should clear writing (bit SCIFFCT register before enabling SCITXINTA interrupt, before using auto-baud feature.
Workaround
280x/2801x Silicon Errata
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Advisory eCAN: When Option Invoked Boot ROM, Code Hang Occasionally
Advisory
Revision(s) Affected
eCAN: When Option Invoked Boot ROM, Code Hang Occasionally F2809 silicon C2801 silicon C280x, F2801, F2802, F2806, F2808, F2801x silicon This happens because 16-bit employed check status boot-ROM code. Since 16-bit returns undefined values, code stuck loop, mistakenly reading value opposite what really power-cycling could this issue; however, since this random phenomenon, work consistently. option would burn boot-load code OTP. eCAN: eCAN-A Boot Mode Boot F2808, F2806, F2801 silicon eCAN-A boot mode boot does work intended. This because bits MSGID1 register initialized boot loader code. Since these bits come frames transmitted host received 2808. This been fixed revision silicon. existing bootloader used developing application, certain that bits before proceeding eCAN-A mode bootloader sure that standard identifier frame with received eCAN-A module.
Details
Workaround(s)
Advisory
Revision(s) Affected Details
Workaround(s)
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280x/2801x Silicon Errata
Advisory eCAN: Abort Acknowledge
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Advisory
Revision(s) Affected
eCAN: Abort Acknowledge F2809 silicon C280x silicon F2801, F2802, F2806, F2808, F2801x silicon After setting Transmission Request Reset (TRR) register abort message, there some rare instances where TRRn TRSn bits will clear without setting Abort Acknowledge (AAn) bit. transmission itself correctly aborted, interrupt asserted there indication pending operation. order this rare condition occur, following conditions must happen: previous message successful, either because lost arbitration because node able acknowledge because error frame resulted from transmission. previous message need from same mailbox which transmit abort currently being attempted. TRRn mailbox should cycle immediately following cycle which TRSn set. TRSn remaining incompletion transmission satisfies this condition well. i.e. TRSn could have been past, transmission remains incomplete. TRRn must exact SYSCLKOUT cycle where module idle state cycle. module said idle state when process receiving/transmitting data. these conditions occur, then TRRn TRSn bits mailbox will clear tclr SYSCLKOUT cycles after where: tclr [(mailbox_number) SYSCLKOUT cycles bits will this condition occurs. Normally, either sets after goes zero.
Details
Workaround(s)
When this problem occurs, TRRn TRSn bits will clear within tclr SYSCLKOUT cycles. check this condition, first disable interrupts. Check TRRn tclr SYSCLKOUT cycles after setting TRRn make sure still set. TRRn indicates that problem occur. TRRn cleared, could because normal message corresponding set. Check both bits. either bits set, then problem occur. they both zero, then problem occur. Handle condition like interrupt service routine would except that does need clearing now. set, then normal interrupt routine will happen when interrupt re-enabled.
280x/2801x Silicon Errata
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Advisory Change Watchdog Module: Writes WDKEY Longer Cause RESET/Interrupt Generated
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Advisory
Revision(s) Affected
Change Watchdog Module: Writes WDKEY Longer Cause RESET/Interrupt Generated F2809 silicon C280x silicon F2801, F2802, F2806, F2808, F2801x silicon "Bad Detect" function WDKEY register been disabled. When using Watchdog (WD) module, write anything other than 0x55 0xAA WDKEY register will have effect. TMS320x280x, 2801x, 2804x System Control Interrupts Reference Guide (literature number SPRU712) more information. trigger immediate reset interrupt, perform invalid write WDCHK bits WDCR register.
Details
Workaround(s)
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280x/2801x Silicon Errata
Advisory Limitation Watchdog Module: Corrupted Watchdog Writes
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Advisory
Revision(s) Affected
Limitation Watchdog Module: Corrupted Watchdog Writes C280x silicon F2801, F2802, F2806, F2808, F2801x silicon When using on-chip (PLLCR writes 0x55/0xAA sequence WDKEY register corrupted. Although watchdog counter will reset correctly, this will cause Watchdog (WD) interrupt reset depending state WDENINT SCSR register. bypass mode (PLLCR mode (PLLOFF PLLSTS register). this case, CLKINDIV PLLSTS register cleared. This valid both interrupt reset cases. Case Applications Using Interrupt Implement software function (ServiceWatchDog) that performs writes 0x55 0xAA WDKEY register, shown below. interrupt (WAKEINT PIE) remapped pseudo interrupt service routine (ISR). ServiceWatchDog routine will deterministically force interrupt each time function called. This forced interrupt will serviced pseudo ISR. pseudo will then acknowledge interrupt remap WAKEINT interrupt back normal ISR.
Note: WDINT signal, once triggered, will stay active Clock cycles. another event (timeout write) comes before this signal gone inactive high, event will captured module. TMS320x280x, 2801x, 2804x System Control Interrupts Reference Guide (literature number SPRU712) section Watchdog Reset Watchdog Interrupt Mode more information
Details
Workaround(s)
Case Applications Using Reset This case uses interrupt feature module work around possible corruption WDKEY register service events that would normally trigger reset. Applications that only used reset feature will need properly enable WAKEINT interrupt PIE. Applications will also need enable interrupt function setting WDENINT SCSR register. reset feature will only enabled inside WatchdogInterrupt interrupt service routine (ISR) triggered when true event occurs, either from timeout incorrect write WDKEY register WDCHK bits WDCR register. Inside incorrect value written WDKEY force reset. Since reset gated servicing interrupt, applications must re-enable interrupts PIEIER INbit inside other ISRs. order service WD(reset counter) during normal operation, implement software function (ServiceWatchDog) that performs writes 0x55 0xAA WDKEY register, shown below. interrupt (WAKEINT PIE) remapped pseudo ISR. ServiceWatchDog routine will deterministically force interrupt each time function called. This forced interrupt will serviced pseudo ISR. pseudo will then acknowledge interrupt remap WAKEINT interrupt back normal ISR.
280x/2801x Silicon Errata
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Advisory Limitation Watchdog Module: Corrupted Watchdog Writes
Code example Case
void ServiceWatchdog (void) EALLOW; DINT; Disable Global Interrupts if(SysCtrlRegs.WDCNTR 254) watchdog counter less then 254, then there enough time service watchdog function; otherwise, assume late watchdog time out. PieVectTable.WAKEINT &PseudoWatchdogInterrupt; Remap vector pseudo routine SysCtrlRegs.WDKEY 0x0000; Force interrupt always SysCtrlRegs.WDKEY 0x0055; SysCtrlRegs.WDKEY 0x00AA; This will clear watchdog counter EINT; Enable global interrupts EDIS; interrupt void PseudoWatchdogInterrupt(void) EALLOW; PieVectTable.WAKEINT &WatchdogInterrupt; This will clear PIEIFR.INT1.8 flag remap back proper service routine PieCtrlRegs.PIEACK.all PIEACK_GROUP1; EDIS; interrupt void WatchdogInterrupt(void) Proper Watchdog Interrupt;
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280x/2801x Silicon Errata
Advisory Limitation Watchdog Module: Corrupted Watchdog Writes
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Code example Case
void ServiceWatchdog (void) EALLOW; DINT; Disable Global Interrupts if(SysCtrlRegs.WDCNTR 254) watchdog counter less then 254, then there enough time service watchdog function; otherwise, assume late watchdog time out. PieVectTable.WAKEINT &PseudoWatchdogInterrupt; Remap vector pseudo routine SysCtrlRegs.WDKEY 0x0000; Force interrupt always SysCtrlRegs.WDKEY 0x0055; SysCtrlRegs.WDKEY 0x00AA; This will clear watchdog counter EINT; Enable global interrupts EDIS; interrupt void PseudoWatchdogInterrupt(void) EALLOW; PieVectTable.WAKEINT &WatchdogInterrupt; This will clear PIEIFR.INT1.8 flag remap back proper service routine PieCtrlRegs.PIEACK.all PIEACK_GROUP1; EDIS; interrupt void WatchdogInterrupt(void) EALLOW; SysCtrlRegs.SCSR 0x0000; generate WDRSTn SysCtrlRegs.WDKEY 0x0000; case WDINTn low, force reset with write EDIS; Proper Watchdog Interrupt;
280x/2801x Silicon Errata
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Advisory GPIO: Behavior Power-up
Advisory
Revision(s) Affected Details
GPIO: Behavior Power-up F2808, F2806, F2801 silicon GPIO0-13, GPIO20-GPIO21, GPIO25-31 potentially drive signal while device VDDIO pins powering prior receiving first valid input clock from XCLKIN pin. Once VDDIO fully powered first clock pulse received, device will place these pins into high impedance state. None. synchronous nature these pins been removed revision silicon.
Workaround(s)
Advisory
Revision(s) Affected
GPIO: GPIO Qualification F2809 silicon C2801 C2802 silicon F2801, F2802, F2806, F2808, F28015, F28016 silicon GPIO configured SYSCLKOUT cycle qualification period (where 510) with qualification samples possible that input pulse width qualified (instead This depends upon alignment asynchronous GPIO input signal with respect phase internal prescaled clock, hence, deterministic. probability this kind wrong qualification occurring "1/n". Worst-case example: 510, GPIO input width 3060 SYSCLKOUT cycles required pass qualification. However, because issue described this advisory, minimum GPIO input width which qualified 3060 2549 SYSCLKOUT cycles.
Details
Workaround(s)
None. Ensure sufficient margin design input qualification.
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280x/2801x Silicon Errata
Advisory Boot ROM: Configuration Change Boot
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Advisory
Revision(s) Affected Details Workaround(s)
Boot ROM: Configuration Change Boot F2808, F2806, F2801 silicon input configuration, GPIO pins come synchronized SYSCLKOUT. This different compared TMS320x281x This been fixed revision silicon. boot will configure peripheral pins used asynchronous mode operation.
280x/2801x Silicon Errata
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Documentation Support
Documentation Support
device-specific data sheets related documentation, visit site http://www.ti.com access documentation site: http://www.ti.com Click Product Tree Click C2000 platform Click C28x DSPs Click device name then click documentation type prefer. further information regarding 280x DSPs, please TMS320F2809, TMS320F2808, TMS320F2806, TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801, TMS320F2801x DSPs Data Manual (literature number SPRS230).
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280x/2801x Silicon Errata
Appendix
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Appendix Revision History
This silicon errata revised from SPRZ171J SPRZ171K. Table lists technical changes made this revision. Table A-1. Changes Made This Revision
Location Global Section Additions, Deletions, Modifications Added silicon revision information F2809 device. Introduction: Deleted "The TMS320F2809 device this silicon errata" from "This document describes silicon updates paragraph Determining Silicon Revision From Trace Code (F2809): Added information about Revision table Updated "TMS320F2809 Silicon Change Overview" table "Input Clock: Device Startup Using XCLKIN Input" advisory: Updated Workaround(s) Added "GPIO: GPIO Qualification" advisory
Table Table Section Section
Revision History
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