TMP92CH21FG
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32bit Micro controller TLCS-900/H1 series
TMP92CH21FG
Rev0.92 11th/Jul./2002
Since this Revision 0.92 still under working, there some mistakes When will start design, please order latest one.
Contents-1. Outline Device Characteristics Assignment Functions Assignment name functions Oepration Memory Clock Function Standby Function Interrupts Function Ports 3.5.1 3.5.2 3.5.3 3.5.4 3.5.5 3.5.6 3.5.7 3.5.8 3.5.9 3.5.10 3.5.11 3.5.12 3.5.13 3.5.14 3.5.15 3.5.16 3.5.17 Port Port Port Port Port Port Port Port 92CH21-1 92CH21-5 92CH21-5 92CH21-6 92CH21-12 92CH21-12 92CH21-14 92CH21-15 92CH21-36 92CH21-56 92CH21-111 92CH21-143 92CH21-177 92CH21-281 92CH21-291 92CH21-296 92CH21-310 92CH21-351 92CH21-357 92CH21-367
Port Port Port Port Port Port Port Port
92CH21-
Port
92CH21-
Memory Controller 8-bit Timers (TMRA) Serial Channel 3.10 Controller 3.11 Analog/Digital Converter 3.12 Watch Timer 3.13 3.14 Controller 3.15 Melody Alarm Generator 3.16 SDRAM Controller 3.17 NAND-Flash Controller
92CH21-132
3.18 16-bit Timers (TMRB) 3.19 Touch Screen interface 3.20 3.21 Boot 3.22 Power Supply Backup
92CH21-385 92CH21-395 92CH21-401 92CH21-408 92CH21-426 92CH21-428 92CH21-449 92CH21-492
Electrical Charactoristics Table Speial function registers (SFRs) Package
DataBook Modification History Rev/Data Page 0.91 /20-Apr-2002 0.92 1,3,6 /10-Jul-2002 4,7,431 (Shown Blue-color) 120,121 145,146 157,158 167,169,171 315,316 404,406 408-425 435,436
Modification item release Product name JTMP92CH21 explanation Modified assignment S0ALEL/H,S1ALEL/H Deleted Port0 assignment Modified attribute(I/O) MX,MY Modified Figure Separated Figure 3.5.11 Deleted PC7F,PC6F explanation Added (Note) sizing Added connection example NOR-Flash Added Note NAND-Flash area setting Modified Table 3.7.2 Modified Figure 3.7.8, 3.7.9 Added explanation Added example Modified Figure 3.9.2 Modified Table 3.9.2 Modified baud rate calculation formula Added (Note) Modified (3)Seirial clock generation circuit Modified Figure 3.9.7, 3.9.8 Modified setting example Added Using IrDA 115.2Kbps with Modified Table 3.14.1 Added (Note) Added (Note) Modified number LD-bus Added page, explanation LD-bus 4096 color Modified diagram example Added program example Added (Note3) SDACR1 Modified SDACR2<SDRS1 explanation Modified Figure 3.16.2(2) Modified comment Note1 Modified Table 3.8.2 Added comment Setting example Modified 3.21 Boot-ROM Modified pins shmitt-level Modified explanation BnCSL-registers
Reason
added Mistake
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added Mistake
Under Development
TMP92CH21
CMOS 32-bit Micro-controller
TMP92CH21FG JTMP92CH21 Outline Device Characteristics
TMP92CH21 high-speed advanced 32-bit equipment which processes mass data. TMP92CH21 micro-controller which high-performance (900/H1 CPU) various built-in I/Os. TMP92CH21FG housed 144-pin flat package. Device characteristics follows: 32-bit CPU(900/H1 CPU) with TLCS-900/L1 instruction code linear address space register register banks 8channels (250ns/4bytes 40MHz, best case) Minimum instruction execution time 50ns(at fc=40MHz) Internal memory 16K-byte (can used program data memory) 8K-byte UART NAND-Flash. External memory expansion 512M bytes (shared program/data area) simultaneously support 8/16/32-bit width external data Dynamic data sizing system Memory controller select output channel 8-bit timers: channels 16-bit timer/event counter channel
980508TBA1
micro-controller developed controlling
JTMP92CH21 chip form product.
(used boot-prgram
Possible downloading user's download-program through either USB,
discussion reliability microcontrollers predicted, please refer Section chapter entitled Quality Reliability Assurance Handling Precautions. TOSHIBA continually working improve quality reliability products. Nevertheless, semiconductor devices general malfunction fail their inherent electrical sensitivity vulnerability physical stress. responsibility buyer, when utilizing TOSHIBA products, observe standards safety, avoid situations which malfunction failure TOSHIBA product could cause loss human life, bodily injury damage property. developing your designs, please ensure that TOSHIBA products used within specified operating ranges forth most recent products specifications. Also, please keep mind precautions conditions forth TOSHIBA Semiconductor Reliability Handbook. products described this document subject foreign exchange foreign trade laws. information contained herein presented only guide applications products. responsibility assumed TOSHIBA CORPORATION infringements intellectual property other rights third parties which result from use. license granted implication otherwise under intellectual property other rights TOSHIBA CORPORATION others. information contained herein subject change without notice.
92CH21
Under Development
TMP92CH21
General-purpose serial interface: channels mode: channels (ch.0 Ver.1.0(115kbps) mode selectable: 1channel (ch.0) USB(Universal Serial Bus) Controller channel with rev1.1 (12MHz) (LOW-spped supported.) spec Endpoint-0 Control 64Bytes*1 -FIFO Endpoint-1 BULK(out) 64Bytes*2 -FIFO Endpoint-2 BULK(in) 64Bytes*2 -FIFO Endpoint-3 Interrupt(in) 8Bytes*1 -FIFO 384Bytes (10) S(Inter-IC Sound) interface: channel Sbus-mode/SIO-mode selectable
(Master, transmittion only)
FIFO buffer (11) controller 4096-color TFT, 256-color,16,8,4Gray-levels register/built-in driver (12) SDRAM Controller: channel 16M,64M,128M,256M even 512Mbit SDR-SDRAM execute instruction SDRAM (13) Timer real-time clock (RTC) (14) Key-on wake (Interrupt input) (15) 10-bit converter: channels (16) Touch screen interface reduce external components (17) Watch timer (18) Melody/alarm generator Output clock 5461Hz Output kinds alarm pattern kinds interval interrupt (19) 512M bytes local area/bank method) bank each Program,Read-data,Write-data LCD-display-data
92CH21
Under Development
TMP92CH21
(21) Interrupts: interrupts interrupts: Software interrupt instruction illegal instruction internal interrupts: Seven selectable priority levels external interrupts: Seven selectable priority levels(6-edge selectable) (22)Input/output ports: pins (23) NAND Flash interface: channel Available connect directly with NAND-Flash calculation (24)Stand-by function Halt modes: Idle2 (programmable), Idle1, Stop Power supply RTCVCC controlled /BE-pin status programmable stand-by mode (25) Triple-clock controller doubler (PLL) supplies 48MHz USB, 36MHz system-clock others gear function: Select High-frequency clock fc/16 (fs=32.768kHz) (26)Operating voltage: 40MHz) 27MHz) (27) Package: (P-LQFP144 -1616 0.40) Chip form also available. details, contact your local Toshiba sales representative.
92CH21
Under Development
TMP92CH21
(AN0 AN1) AN2/MX(PG2) AN3/MY/ADTRG(PG3) AVCC,AVSS VREFH,VREFL (PX,INT4)P96 (PY,INT5)P97
10-bit Converter
Touch Screen I/F(TSI)
900/H1
DVCC[3],RTCVCC DVSS[3]
H-OSC
/RESET INTERRUPT Controller
32bit
Clock Gear
L-OSC
(TXD0,TXD1)PF0 (RXD0,RXD1)PF1 (SCLK0,/SCLK0)PF2
SERIAL SIO0 SERIAL SIO1
PORT0 PORT1 PORT2 PORT3 PORT4
D15) (D16 D23,KO0 KO7) (D24 D31) A15) (A16 A23) P70(/RD) P71(/WRLL,/NDRE) P72(/WRLU,/NDWE) P73(EA24) (EA25) (R/W,NDR/B) (/WAIT)
D(I2SCKO,TXD0)P90 (I2SDO,RXD0)P91 (I2SWS,SCLK0,/CTS0)P92 (LGOE0)P93 (LGOE1)P94 (LGOE2)P95
Controller
WATCH-DOG TIMER
8BIT TIMER (TIMERA0) 8BIT TIMER (TIMERA1) 8BIT TIMER (TIMERA2)
PORT5 PORT6
(TA1OUT,INT0)PC0
PORT7
(TA3OUT,INT1)PC1 (TB0OUT0,INT2)PC2 (INT3)PC3
P30,33
P31,34
8BIT TIMER (TIMERA3)
16BIT TIMER (TIMERB0) NAND-FLASH I/F(2ch)
P32,35
(LCP0)PK0 (LLP)PK1 (LFR)PK2 (LCD)PK3 (LD0 LD7)
(/SDRAS,/SRLLB)PJ0 (/SDCAS,/SRLUB)PJ1 (/SDWE,/SRWR)PJ2 (SDLLDQM)PJ3 (SDLUDQM)PJ4 (NDALE,SDULDQM)PJ5 (NDCLE,SDUUDQM)PJ6 (SDCKE)PJ7 (SDCLK)PF7
Controller 16KB
PORT8
KEY-BOARD
P80(/CS0) P81(CS1,/SDCS) P82(/CS2,/CSZA,/SDCS) P83(/CS3) P84(/CSZB,/WRUL,/ND0CE) P85(/CSZC,/WRUU,/ND1CE) P86(/CSZD,/SRULB) P87(/CSZE,/SRUUB) PC7(/CSZF,LCP1)
SDRAM Controller Masked-ROM (Boot program) Figure TMP92CH21 block diagram
MELODY/ ALARM-OUT
PA7(KI0 KI7, LD11) PC6(KO8,LDIV) PM2(/ALARM,/MLDALM) PM1(MLDALM)
92CH21
TMP92CH21
Assignment Functions
assignment input/output pins TMP92CH21FG, their names functions follows:
Assignment
PF2,SCLK0,/CTS0,SCLK1,/CTS1
PF1,RXD0,RXD1 PF0,TXD0,TXD1 PC7,/CSZF,LCP1 P87,/CSZE,/SRUUB P86,/CSZD,/SRULB P85,/CSZC,/WRUU,/ND1CE P84,/CSZB,/WRUL,/ND0CE P83,/CS3 P82,/CS2,/CSZA,/SDCS P81,/CS1,/SDCS PC6,KO8,LDIV P80,/CS0 P76,/WAIT P75,RW,NDR/B P74,EA25 P73,EA24 P72,/WRLU,/NDWE P71,/WRLL,/NDRE P70,/RD
AVCC AVSS PA2,KI2 PA1,KI1 PA0,KI0 PJ7,SDCKE PJ6,SDUUDQM,NDCLE PJ5,SDULDQM,NDALE PJ4,SDLUDQM PJ3,SDLLDQM
PJ1,/SDCAS,/SRLUB
PJ0,/SDRAS,/SRLLB
PJ2,/SDWE,/SRWR
PF7,SDCLK PC1,TA3OUT,INT1 PC0,TA1OUT,INT0
VREFL VREFH PG0,AN0 PG1,AN1 PG2,AN2,MX PG3,AN3,/ADTRG,MY P96,PX,INT4 P97,PY,INT5 PA3,KI3,LD8 PA4,KI4,LD9 PA5,KI5,LD10 PA6,KI6,LD11 PA7,KI7 P90,TXD0,I2SCKO P91,RXD0,I2SDO
P92,SCLK0,/CTS0,I2SWS
TMP92CH21FG
QFP144
RTCVCC DDVCC1 DVSS1 /RESET PC3,INT3 DVSS2 DVCC2 P10,D8 P11,D9 P12,D10 P13,D11 P14,D12 P15,D13 P16,D14 P17,D15 P20,D16 P21,D17 P22,D18 P23,D19 P24,D20 P25,D21
Figure2.1.1 assignment diagram (144-pin QFP)
92CH21
P93,LGOE0 P94,LGOE1 P95,LGOE2 PC2,TB0OUT0,INT2 PL0,LD0 PL1,LD1 PL2,LD2 PL3,LD3 PL4,LD4 PL5,LD5 PL6,LD6 PL7,LD7 PK0,LCP0 PK1,LLP PK2,LFR PK3,LBCD PM2,/ALARM,/MLDALM PM1,MLDALM
TOPVIEW
P67,A23 P66,A22 P65,A21 P64,A20 DVCC3 P63,A19 P62,A18 P61,A17 P60,A16 P57,A15 P56,A14 P55,A13 P54,A12 P53,A11 P52,A10 P51,A9 P50,A8 P47,A7 P46,A6 P45,A5 P44,A4 P43,A3 P42,A2 P41,A1 P40,A0 P37,D31 P36,D30 DVSS3 P35,D29 P34,D28 P33,D27 P32,D26 P31,D25, P30,D24 P27,D23 P26,D22
TMP92CH21
Assignment
(Chip size 5.98mm 6.42mm)
Table2.2.1 assignment diagram (144-pin chip)
Name
VREFL VREFH
Unit:
Name DVCC3 AVSS AVCC point 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2460 2295 2127 1964 1807 1654 1506 1361 1226 1101 -150 -275 -400 -525 -650 -775 -901 -1026 -1151 -1276 -1401 -1526 -1652 -1777 -1902 -2275 -2400 point 1066 1191 1316 1441 1566 1692 1823 1974 2130 2292 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065 3065
point -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2852 -2465 -2339 -2062 -1875 -1598 -1472 -1347 -1126 -1001 -876 -750 -625
point 2671 2546 2421 2296 2171 2045 1920 1795 1270 1145 1020 -106 -231 -356 -481 -606 -732 -857 -982 -1107 -1232 -1357 -1482 -1608 -1892 -2017 -2142 -2444 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072
RTCVCC DDVCC1 DVSS1 /RESET
Name DVSS2 DVCC2 DVSS3
point -488 -338 -200 1050 1176 1301 1426 1551 1676 1801 1927 2052 2177 2303 2460 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848 2848
point -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -3072 -2279 -2138 -1982 -1831 -1687 -1562 -1437 -1311 -1186 -1061 -936 -811 -686 -560 -435 -310 -185
92CH21
TMP92CH21
names functions following table shows names functions input/output pins Table2.3.1 names functions (1/5)
Name
/WRLL /NDRE /WRLU /NDWE EA24 EA25 NDR/B /WAIT
Number pins
Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Data: Data
Function
Port port Input output specifiable units bits Data: Data Port port Input output specifiable units bits Data: Data Output pins used Key-scan strobe (Open drain-output programmable) Port port Data24: Data Port port Data25: Data Port port Data26: Data Port port Data27: Data Port port Data28: Data Port port Data29: Data Port port Input output specifiable units bits Data: Data Port port Input output specifiable units bits Address: Address Port port Input output specifiable units bits Address: Address Port port Input output specifiable units bits Address: Address Port70: Output port Read: Outputs strobe signal read external memory Port port Write: Output strobe signal writing data pins NAND-Flash read: Outputs strobe signal read external NAND-Flash Port port Write: Output strobe signal writing data pins Write Enable NAND-Flash Port Output port Extended Address Port Output port Extended Address Port Output port Read/Write: represents Read Dummy cycle; represents write cycle NAND-Flash Ready(1)/Busy(0) input Port port Wait: Signal used request wait
92CH21
TMP92CH21
Table2.3.1 names functions (2/5)
Name
/CS0 /CS1 /SDCS /CS2 /CSZA /SDCS /CS3 /WRUL /CSZB /ND0CE /WRUU /CSZC /ND1CE /CSZD /SRULB /CSZE /SRUUB TXD0 I2SCKO RXD0 I2SDO SCLK0 /CTS0 I2SWS LGOE0 LGOE1 LGOE2 INT4 INT5 LD11
Number pins
Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Output Input Output Output Output Output Input Output Input Output Input Input Input Input Output Input Input
Function
Port80:Output port Chip select Outputs "Low" when address within specified address area Port81:Output port Chip select Outputs "Low" when address within specified address area Chip Select SDRAM: Outputs when address within SDRAM -address area Port82:Output port Chip select Outputs "Low" when address within specified address area Expand Chip Select: outputs when address within specified address area Chip Select SDRAM: Outputs when address within SDRAM -address area Port83:Output port Chip select Outputs "Low" when address within specified address area Port84:Output port Write: Output strobe signal writing data pins Expand Chip Select: outputs when address within specified address area Chip select NAND-Flash0: Outputs when NAND-Flash-0 accessed Port85: Output port Write: Output strobe signal writing data pins Expand Chip Select: outputs when address within specified address area Chip select NAND-Flash1: Outputs when NAND-Flash-1 accessed Port86: Output port Expand Chip Select: outputs when address within specified address area Data enable SRAM pins Port87: Output port Expand Chip Select: outputs when address within specified address area Data enable SRAM pins Port90: port Serial send data: Open drain-output programmable Clock Output Port91: port Serial receive data Data Output Port92: port Serial clock Serial data send enable (Clear Send) Word Select Output Port93: port Output Enable-0 external TFT-LCD Driver Port94: port Output Enable-1 external TFT-LCD Driver Port95: Output port Output Enable-2 external TFT-LCD Driver Port Input port Interrupt request pin4:Interrupt request with programmable rising/falling edge X-Plus connectted Touch Screen Panel Port Input port Interrupt request pin5:Interrupt request with programmable rising/falling edge Y-Plus connectted Touch Screen Panel Port: port: used input ports input used wake-up (shummit input, with pull-up register) Port: port: used input ports input used wake-up (shummit input, with pull-up register) Data LCD-driver Port: port: used input ports input used wake-up (shummit input, with pull-up register)
92CH21
TMP92CH21
Table2.3.1 names functions (3/5)
Name
INT0 TA1OUT INT1 TA3OUT INT2 TB0OUT0 INT3 LDIV /CSZF LCP1 TXD0 TXD1 RXD0 RXD1 SCLK0 /CTS0 SCLK1 /CTS1 SDCLK /ADTRG
Number pins
Input Output Input Output Input Output Input Output Output Output Output Output Output Input Input Input Input Output Output Input Input Input Input Output Input Input Output Intput
Function
PortC0: port Interrupt request pin0 Interrupt request with programmable level rising /falling edge 8bit timer output: Timer output PortC1: port Interrupt request pin1 Interrupt request with programmable rising /falling edge 8bit timer output: Timer output PortC2 port Interrupt request pin2: Interrupt request with programmable rising /falling edge Timer output PortC3: port Interrupt request pin3 Interrupt request with programmable rising /falling edge PortC6 port Output used Key-scan strobe (Open drain-output programmable) Data Invert enable external TFT-LCD Driver PortC7 port Expand Chip Select: outputs when address within specified address area Shift-clock-1 external TFT-LCD Driver PortF0: port Serial send data: Open drain-output programmable Serial send data: Open drain-output programmable PortF1: port Serial receive data Serial receive data PortF2: port Serial clock Serial data send enable (Clear Send) Serial clock Serial data send enable (Clear Send) PortF7: Output port Clock SDRAM Port port: used input ports Analog input used Input conveter Port port: used input ports Analog input used Input conveter X-Minus: connectted Touch Screen Panel Port port: used input ports Analog input used Input conveter Y-Minus: connectted Touch Screen Panel trigger: Signal used request start
92CH21
TMP92CH21
Table2.3.1 names functions (4/5)
Name
/SDRAS /SRLLB /SDCAS /SRLUB /SDWE /SRWR SDLLDQM SDLUDQM SDULDQM NDALE SDUUDQM NDCLE SDCKE LCP0 LBCD MLDALM /ALARM /MLDALM
Number pins
Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Output Output Output Output Output PortJ0: Output port Address Storobe SDRAM Data enable SRAM pins PortJ1: Output port Column Address Storobe SDRAM Data enable SRAM pins D8to PortJ2: Output port Write Enable SDRAM Write SRAM: strobe signal writing data PortJ3: Output port Data enable SDRAM pins PortJ4: Output port Data enable SDRAM pins PortJ5: port Data enable SDRAM pins Address Latch Enable NAND-Flash PortJ6: port Data enable SDRAM pins Command Latch Enable NAND-Flash PortJ7: Output port Clock Enable SDRAM PortK0: Output port driver output PortK1: Output port driver output PortK2: Output port driver output PortK3: Output port driver output Port Output port Data LCD-driver Port port Data LCD-driver Back-up enable PortM1: Output port Melody Alarm output PortM2: Output port alarm output Melody Alarm output (inverted)
Function
92CH21
TMP92CH21
Table2.3.1 names functions (5/5)
Name
DAM0,AM1 X1/X2 XT1/XT2 /RESET VREFH VREFL AVCC AVSS DVCC DVSS RTCVCC
Number pins
USB-data Connecting
Function
Operation mode: AM1="0",AM0="1" 16-bit external starting AM1="1",AM0="0" 32-bit external starting AM1="1",AM0="1" BOOT(32-bit internal-MROM starting High-frequency oscillator connection pins Low-frequency oscillator connection pins Reset: initializes TMP92CH21 (With pull-up resistor) reference voltage input converter reference voltage input converter Power supply converter converter Power supply pins (All pins should connected with power Supply pin) pins (All pins shuold connected with GND(0V) Power supply RTC, low-frequency oscillator portM
92CH21
TMP92CH21
OPERATION
This section describes basic components, functions operation TMP92CH21.
TMP92CH21 contains advanced high-speed 32-bit CPU(900/H1 CPU)
3.1.1
Outline
900/H1 high-speed high-performance based 900/L1 CPU. 900/H1 expanded 32-bit internal data process Instructions more quickly. Outline 900/H1 follows: Parameter Width Address Width Data Internal Operating Frequency Minimum Cycle Internal Internal Boot-ROM Internal External Device Minimum Instruction Execution Cycle Conditional Jump Instruction Queue Buffer Instruction 900/H1 24-bit 32-bit max.20MHz fc=40MHz) 1-clock access(50ns) 32-bit 1-clock access 32-bit 2-clock access 8/16-bit 2-clock access 8/16-bit 6-clock access 8/16/32-bit 2-clock access (can insert some waits) 1-clock(50ns) 2-clock(100ns) 12-byte Compatible with TLCS-900/L1,TLCS-900/H2 (LDX instruction deleted) Only maximum mode 8-channel
mode Micro
3.1.2
Reset Operation
When resetting TMP92CH21 microcontroller, ensure that power supply voltage within operating voltage range, that internal high-frequency oscillator stabilized. Then hold /RESET input least system clocks(16µs 40MHz). reset, since clock doubler(PLL) bypassed clock-gear 1/16, system clock operates 1.25MHz(fc=40MHz). When Reset been accepted, performs following: Sets Program Counter (PC) follows accordance with Reset Vector stored address FFFF00H~FFFF02H: PC<0~7> data location FFFF00H PC<8~15> data location FFFF01H PC<16~23> data location FFFF02H Sets Stack Pointer (XSP) 00000000H. Sets bits <IFF0 IFF2> Status Register (SR) (thereby setting Interrupt Level Mask Register level Clears bits <RFP0 RFP1> Status Register (thereby selecting Register
92CH21
TMP92CH21
Bank When Reset released, starts executing instructions according Program Counter settings. internal registers mentioned above change when Reset released. When Reset accepted, sets internal I/O, ports other pins follows. Initializes internal registers table "Special Function Register" Section Sets port pins, including pins that also internal I/O, General-Purpose Input Output Port Mode. Internal reset released soon external reset released. operation memory controller cannot insured until power supply becomes stable after power-on reset. external data provided before turning TMP92CH21 spoiled because control signals unstable until power supply becomes stable after power reset.
VCC(3.3V)
/RESET High frequency oscillation warming time system clock
Min.0s
Figure Power Reset Timing Example
3.1.3
Setting
pins like Table3.1 according system usage. Table Operation Mode Setup Table
Operation Mode 16-bit external starting 32-bit external starting BOOT(32-bit internal-MROM starting /RESET Mode Setup input
92CH21
TMP92CH21
Memory
Figure memory TMP92CH21.
000000H
Internal KByte)
Direct area
000100H 001D00H 002000H Internal KByte) 006000H
64Kbyte area (nn)
010000H 3FE000H 400000H BOOT(Internal MROM) KByte)
(Note1)
External memory 16Mbyte area F00000H F10000H Provisional Emulator Control Area (64K Byte) (-R) (R+) R8/16) External memory d8/16) (nnn)
(Note2)
FFFF00H FFFFFFH
Vector table (256 Byte)
(Note3)
Internal area)
Figure Memory
Note1: BOOT-prgram(Internal MROM) mapped only BOOT-mode. another starting mode, area(3FE000H 3FFFFFH) mapped external-memory. Note2: Provisional emulator control area emulator, mapped F00000H F0FFFFH after reset. Note3: Don't last 16-byte area (FFFFF0H FFFFFFH). This area reserved emulator. Note4: emulator signal signal asserted, when provisional emulator control area accessed. carefull external memory.
92CH21
TMP92CH21
Clock Function Standby Function
TMP92CH21 contains (1)clock gear, (2)clock doubler(PLL), standby controller noise-reducing circuit. They used low-power, low-noise systems. This chapter organized follows: 3.3.1 Block diagram system clock 3.3.2 SFRs 3.3.3 System clock controller 3.3.4 Prescaler clock controller 3.3.5 Noise-reducing circuit 3.3.7 Standby controller
92CH21
TMP92CH21
clock operating modes follows: Single Clock Mode (X1, pins only), Dual Clock Mode (X1, pins) Triple Clock Mode (X1, pins PLL). Figure 3.3.1 shows transition figure.
Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) instruction interrupt instruction interrupt release Reset
NORMAL mode (fOSCH/gear value/2)
instruction interrupt
STOP mode (Stops circuits)
Single clock mode transition figure Reset (fOSCH/32)
IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator)
instruction interrupt instruction interrupt instruction interrupt instruction interrupt
release Reset
NORMAL mode (fOSCH/gear value/2)
instruction interrupt
STOP mode (Stops circuits)
SLOW mode (fs/2)
instruction interrupt
STOP mode (Stops circuits)
Dual clock mode transition figure Reset (fOSCH/32)
IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator)
instruction interrupt instruction interrupt
release Reset
NORMAL mode (fOSCH/gear value/2)
instruction *NOTE IDLE2 mode (I/O operate) IDLE1 mode (Operate oscillator PLL)
STOP mode (Stops circuits) instruction
instruction interrupt SLOW mode (fs/2) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator)
NORMAL mode fOSCH/gear value/2)
instruction *NOTE
Using Triple clock mode transition Figure
*NOTE) It's prohibited control SLOW mode when shifting from SLOW mode NORMAL mode with PLL.PLL Start up/Stop/Change Write PLLCR0<PLLON>,PLLCR1<FCSEL> resister shift from NORMAL mode with NORMAL mode, execute following setting same order. Change clock(PLLCR0<FCSEL> 2)Stop circuit(PLLCR1<PLLON><-"0") It's prohibited shift from NORMAL mode with STOP mode directly. should NORMAL mode once, then shift STOP mode.(You should stop high frequency oscillator after stop PLL.)
Figure 3.3.1 System clock block diagram
clock frequency input from pins called clock frequency input from pins called clock frequency selected SYSCR1<SYSCK> called system clock fFPH. system clock fSYS defined divided clock fFPH, cycle fSYS defined state.
92CH21
TMP92CH21 3.3.1 Block diagram system clock
SYSCR0<WUEF> SYSCR2<WUPTM1 Warming timer (High/Low frequency oscillator) Lock timer (PLL) SYSCR0<XTEN Low-Frequency oscillator PLLCR1<PLLON>, PLLCR0<LUPFG> fPLL fOSCH SYSCR0<XEN High-Frequency oscillator fOSCH Clock Doubler (PLL) selector
fFPH
fc/2 fc/4 fc/8
fc/16
fSYS
SYSCR1<SYSCK>
Clock gear PLLCR0<FCSEL>
SYSCR1<GEAR2 Controller RAM,ROM Interrupt controller LCDC Memory Controller NAND-Flash Controller SMROMC,
fUSB (48MHz)= fOSCH 16/3
USBCR1<USB_CLKE>
fSYS
TMRA0 3,TMRB0
prescaler
SIO0
prescaler
ports
MLD/ALM
SDRAMC
Figure 3.3.2 Block Diagram System clock
Table 3.3.1 Selection example fOSCH Selection example fOSCH High-frequency Oscillation fOSCH 9.0MHz max.10.0MHz max.40.0MHz SystemClock fSYS 18MHz max.20MHz max.20MHz USBClock fUSB 48MHz
Needed with No-needed with No-needed without
(Note1) USB, High-frequency Oscillator should 9.0MHz.
92CH21
TMP92CH21 3.3.2
SYSCR0 Symbol (10E0H) Read/Write After reset
XTEN
WUEF
Warm-up Timer Write Don't care Write start timer Read warm-up Read warm-up
High-frequen Low-frequen oscillator oscillator (fc) (fs) Stop Stop Oscillation Oscillation
Function
SYSCR1 (10E1H) Symbol Read/Write After reset
SYSCK
Select system clock. 0:fc 1:fs
GEAR2
GEAR1
GEAR0
Function
Select gear value high frequency (fc) 000: 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (reserved) 110: (reserved) 111: (reserved)
SYSCR2 (10E2H) Symbol Read/Write After reset
Write
WUPTM1
WUPTM0
HALTM1
HALT mode reserved STOP mode IDLE1 mode IDLE2 mode
HALTM0
Function
Warm-Up Timer reserved /inputted frequency 10:2 11:2
Note1:
unassigned register,SYSCR0<bit5 3>,SYSCR0<bit1 0>,SYSCR1<bit SYSCR2<bit6,bit1 read undefined-value.
Note2:
reset, low-frequency oscillator enabled.
Figure 3.3.3 system clock
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TMP92CH21
EMCCR0 (10E3H) symbol Read/Write After reset PROTECT
Protect flag
EXTIN
External clock
DRVOSCH
DRVOSCL
oscillator driverability NORMAL WEAK
oscillator driverability NORMAL WEAK
Function EMCCR1 (10E4H)
symbol Read/Write After reset Function Switching protect ON/OFF write following 1st-KEY,2nd-KEY 1st-KEY: EMCCR1=5AH,EMCCR2=A5H succession write 2nd-KEY: EMCCR1=A5H,EMCCR2=5AH succession write
EMCCR2 (10E5H)
Symbol Read/Write After reset Function
Figure 3.3.4 system clock
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TMP92CH21
PLLCR0 (10E8H) symbol Read/Write After reset
FCSEL
LUPFG
Status flag
Select fc-clock Lock-up timer
OSCH
Function
(Note) carefull that logic PLLCR0<LUPFG> different from 900/L1's DFM.
PLLCR1 (10E9H) symbol Read/Write After reset Function PLLON
Control on/off
Figure 3.3.5
PxDR (xxxxH) symbol Read/Write After reset Function Px7D
Px6D
Px5D
Px4D
Px3D
Px2D
Px1D
Px0D
Output/Input buffer drive-register standby-mode Purpose This register used each pin-status stand-by mode. ports have this format's register. ("x" means port-name.) each register, refer Function Ports. Before "HALT" instruction executed, each register according expected pin-status. They will effective after executed "HALT" instruction. depend stand-by mode(IDLE2,IDLE1 STOP). truth table control Output/Input-buffer below. PxnD Output buffer Input buffer
(Note1) means output enable signal before stand-by mode. Basically, PxCR used (Note2) PxnD means bit-number PORTx.
Figure 3.3.6 drive register
92CH21
TMP92CH21 3.3.3 System clock controller
system clock controller generates system clock signal (fSYS) core internal I/O. contains oscillation circuits clock gear circuit high-frequency (fc) operation. register SYSCR1<SYSCK> changes system clock either SYSCR0<XEN> SYSCR0<XTEN> control enabling disabling each oscillator, SYSCR1<GEAR2 sets high-frequency clock gear either (fc, fc/2, fc/4, fc/8 fc/16). These functions reduce power consumption equipment which device installed. combination settings <XEN> <SYSCK> <GEAR2 will cause system clock (fSYS) fc/32 after reset. example, fSYS 1.25 when 40MHz oscillator connected pins. Switching from Normal Mode Slow Mode When resonator connected pins, pins, warm-up timer used change operation frequency after stable oscillation been attained. warm-up time selected using SYSCR2<WUPTM1 This warm-up timer programmed start stop shown following examples Table 3.3.2 shows warm-up time. Note When using oscillator (other than resonator) with stable oscillation, warm-up timer needed. Note warm-up timer operated oscillation clock. Hence, there some variation warm-up time.
Table 3.3.2 Warming-up times fOSCH 40MHz, 32.768 Warming-up Time SYSCR2 <WUPTM1,WUPTM0>
frequency) (214 frequency) (216 frequency)
Change Normal Mode
(µs) 409.6 (µs) 1.638 (ms)
Change Slow Mode
(ms) (ms) 2000 (ms)
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TMP92CH21
Example 1-Setting clock Changing from high frequency (fc) frequency (fs).
SYSCR0 SYSCR1 SYSCR2 10E0H 10E1H 10E2H (SYSCR2), 0X11-XXB (SYSCR0) (SYSCR0) (SYSCR0) (SYSCR1) (SYSCR0)
WUP:
Sets warm-up time 216/fs. Enables low-frequency oscillation. Clears starts warm-up timer. Detects stopping warm-up timer. Changes fSYS from Disables high-frequency oscillation.
(Note) means don't care means change
<XEN> pins <XTEN> XT1, pins
Warming Timer Warming Timer <SYSCK> System Clock fSYS
Counts fSYS
Counts
Enables Frequency
Clears starts warming-up timer
Chages fsys from warming timer
Disabiles high-frequency
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TMP92CH21
Example 2-Setting clock Changing from frequency (fs) high frequency (fc).
SYSCR0 SYSCR1 SYSCR2 10E0H 10E1H 10E2H (SYSCR2), 0X10-XXB (SYSCR0) (SYSCR0) (SYSCR0) (SYSCR1) (SYSCR0)
WUP:
Sets warm-up time 214/fc. Enables high-frequency oscillation. Clears starts warm-up timer. Detects stopping warm-up timer. Changes fSYS from Disables low-frequency oscillation.
(Note) means don't care means change
<XEN> pins <XTEN> XT1, pins Warming Timer Warming Timer <SYSCK> System Clock fSYS Counts fSYS
Counts
Enables High Frequency
Clears Starts Warming Timer
Chages fsys from Disables low-frequency
warming timer
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TMP92CH21
Clock gear controller fFPH according contents Clock Gear Select Register SYSCR1<GEAR2 either fc/2, fc/4, fc/8 fc/16. Using clock gear select lower value fFPH reduces power consumption. Example Changing high-frequency gear
SYSCR1 10E1H (SYSCR1), XXXX0100B Changes fSYS fc/32.
Don't care (High-speed clock gear changing) change clock gear, write register value SYSCR1<GEAR2 register.It necessary warmming time until changing after writing register value. There possibility that instruction next clock gear changing instruction executed clock gear before changing.To execute instruction next clock gear switching instruction clock gear after changing,input dummy instruction follows (instruction execute write cycle).
(Example) SYSCR1 10E1H (SYSCR1), XXXX0001B (DUMMY),
Changes fSYS fc/4. Dummy instruction
Instruction executed after clock gear changed
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TMP92CH21
3.3.4
Clock doubler (PLL)
outputs fPLL clock signal, which four times fast fOSCH. low-frequency oscillator, even though internal clock high-frequency. Reset initializes Stop status, setting PLLCR0,PLLCR1-register needed before use. Like oscillator, this circuit requires time stabilize. This called lock-up time measured 16-stage binary counter. Lock-up time about 1.6ms fOSCH 10MHz.
(note-1) Input frequency limitation limitation input frequency(High frequency oscillation) following. fOSCH 10MHz (Vcc 3.0~ 3.6V) (note-2) PLLCR0<LUPFG> logic PLLCR0<LUPFG> different from 900/L1's DFM. careful judge lock-up time.
following setting example PLL-starting PLL-stopping. (example-1) PLL-starting
PLLCR0 PLLCR1 LUP: Don't care
<PLLON> <FCSEL> output: fPLL Lockup timer <LUPFG> System clock fSYS Starts operation Starts lock-up. Changes from 10MHz MHz. Ends lock-up
Counts fOSCH
10E8H 10E9H (PLLCR1), 1XXXXXXXXB (PLLCR0) (PLLCR0), X1XXXXXXB
Enables operation starts lock-up. Detects lock-up Changes from MHz.
During lock-up
After lock-up
(example-2) PLL-stopping
PLLCR0 PLLCR1 10E8H 10E9H (PLLCR0), X0XXXXXXB (PLLCR1), 0XXXXXXXB
Changes from to10 MHz. Stop PLL.
Don't care
<FCSEL> <PLLON> output: fPLL System clock fSYS Changes from 40MHz MHz. Stops operation
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TMP92CH21
Limitation point It's prohibited execute enable/disable control SLOW mode(fs) (writing PLLCR0 PLLCR1). should control NORMAL mode. stop operation during using should execute following setting same order. (PLLCR0), Change clock fPLL fOSCH (PLLCR1), stop stop high frequency oscillator during using PLL, should stop before stop high frequency oscillator.
Examples settings below. Start Change Control (OK) frequency oscillator operation mode(fs) (high frequency oscillator STOP) High frequency oscillator start High frequency oscillator operation mode(fOSCH start mode (fPLL (OK) (SYSCR0), 11-1-B 2,(SYSCR0) NZ,WUP (SYSCR1), -0-B (PLLCR1),1-B (PLLCR0) Z,LUP (PLLCR0),-1-B High frequency oscillator start/ Warming start Check flag warming Change system clock fOSCH start lock start Check flag lock Change system clock fOSCH fPLL
WUP:
LUP:
frequency oscillator operation mode(fs) (high frequency oscillator Operate)
High frequency oscillator operation mode(fOSCH )PLL start mode (fPLL (NG) (SYSCR1), -0-B (PLLCR1), (DFMCR0) Z,LUP (PLLCR0),-1-B Change system clock fOSCH start lock start Check flag lock Change system clock fOSCH fPLL
LUP:
frequency oscillator operation mode(fs) (high frequency oscillator STOP)
High frequency oscillator start start mode (fPLL (SYSCR0),11-1-B 2,(SYSCR0) NZ,WUP (PLLCR1),1-B (PLLCR0) Z,LUP (PLLCR0),-1-B (SYSCR1), -0-B High frequency oscillator start/ Warming start Check flag warming start lock start Check flag lock Change internal clock fOSCH fPLL Change system clock fPLL
WUP: LUP:
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TMP92CH21
Change Stop Control (OK) mode (fPLL High frequency oscillator operation mode(fOSCH Stop frequency oscillator operation mode(fs)High frequency oscillator stop (NG) (PLLCR0),-0-B (PLLCR1),0-B (SYSCR1), -1-B (SYSCR0), Change system clock fPLL fOSCH stop Change system clock fOSCH High frequency oscillator stop
mode (fPLL frequency oscillator operation mode(fs) stop High frequency oscillator stop
(OK)
(SYSCR1), (PLLCR0), (PLLCR1), (SYSCR0),
-1-B -0-B
Change system clock fPLL Change internal clock (fC) fPLL fOSCH stop High frequency oscillator stop
mode (fPLL )Set STOP mode High frequency oscillator operation mode (fOSCH) stop HALT(High frequency oscillator stop)
HALT (NG) HALT
(SYSCR2), -01-B (PLLCR0),-0-B (PLLCR1),
STOP mode (This command execute before PLL) Change system clock fPLL fOSCH stop Shift STOP mode
mode (fPLL)Set STOP mode HALT(High frequency oscillator stop) (SYSCR2), -01-B STOP mode (This command execute before PLL) Shift STOP mode
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TMP92CH21
3.3.5
Noise reduction circuits
Noise reduction circuits built allowing implementation following features. Reduced drivability high-frequency oscillator Reduced drivability low-frequency oscillator Single drive high-frequency oscillator protection register contents
Reduced drivability high-frequency oscillator (Purpose) Reduces noise power oscillator when resonator used. (Block diagram)
fOSCH resonator Enable oscillation EMCCR0<DRVOSCH>
(Setting method) drivability oscillator reduced writing"0" EMCCR0<DRVOSCH> register. reset, <DRVOSCH> initialized oscillator starts oscillation normal-drivability when power-supply
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TMP92CH21
Reduced drivability low-frequency oscillator (Purpose) Reduces noise power oscillator when resonator used. (Block diagram)
Resonator
Enable oscillation EMCCR0<DRVOSCL>
(Setting method) drivability oscillator reduced writing EMCCR0<DRVOSCL> register. Reset, <DRVOSCL> initialized "1". Single drive high-frequency oscillator (Purpose) need twin-drive protect mistake-operation inputted noise when external-oscillator used. (Block diagram)
fOSCH Enable oscillation
EMCCR0<DRVOSCH>
(Setting method) oscillator disabled starts operation buffer writing EMCCR0<EXTIN> register.X2-pin always outputted"1". reset,<EXTIN> initialized "0".
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TMP92CH21
Runaway provision with protection register (Purpose) Provision runaway program noise mixing. Write operation specified prohibited that provision program runaway prevents that state which fetch impossibility stopping clock, memory control register (Memory controller, MMU) changed. error handling runaway becomes easy INTP0 interruption. Specified list Memory controller B0CSL/H, B1CSL/H, B2CSL/H, B3CSL/H, BECSL/H MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3, PMEMCR, BROMCR LOCALPX/PY/PZ, LOCALLX/LY/LZ, LOCALRX/RY/RZ, LOCALWX/WY/WZ, Clock gear SYSCR0, SYSCR1, SYSCR2, EMCCR0 PLLCR0,PLLCR1 (Operation explanation) Execute release protection (write operation specified SFR) become possible setting double EMCCR1 EMCCR2 register. Double key) -KEY -KEY
Succession writes EMCCR1 EMCCR2 Succession writes EMCCR1 EMCCR2
state protection confirmed reading EMCCR0<PROTECT>. reset, protection becomes OFF. INTP0 interruption occurs when write operation specified executed with protection state.
92CH21
TMP92CH21 3.3.6 Standby controller
Halt Modes Port Drive-register When HALT instruction executed, operating mode switches IDLE2, IDLE1 STOP Mode, depending contents SYSCR2<HALTM1 register each pin-status according PxDR-register.
PxDR (xxxxH) symbol Read/Write After reset Function Px7D
Px6D
Px5D
Px4D
Px3D
Px2D
Px1D
Px0D
Output/Input buffer drive-register standby-mode Purpose This register used each pin-status stand-by mode. ports have this format's register. ("x" means port-name.) each register, refer Function Ports. Before "HALT" instruction executed, each register according expected pin-status. They will effective after executed "HALT" instruction. depend stand-by mode(IDLE2,IDLE1 STOP). truth table control Output/Input-buffer below. PxnD Output buffer Input buffer
(Note1) means output enable signal before stand-by mode. Basically, PxCR used (Note2) PxnD means bit-number PORTx.
subsequent actions performed each mode follows: IDLE2: Only halts. internal available select operation during IDLE2 mode setting following register. Table Shows registers setting operation during IDLE2 mode. Table 3.3.3 seting operation during IDLE2 mode Internal
TMRA01 TMRA23 TMRB0 SIO0 SIO1 converter
TA01RUN<I2TA01> TA23RUN<I2TA23> TB0RUN<I2TB0> SC0MOD1<I2S0> SC1MOD1<I2S1> ADMOD1<I2AD> WDMOD<I2WDT>
IDLE1: Only oscillator,RTC (real-time clock) ,USBC continue operate. STOP: internal circuits stop operating.
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TMP92CH21
operation each different Halt Modes described Table 3.3.3.
Table 3.3.4 operation during Halt Modes Halt Mode SYSCR2 <HALTM1
ports TMRA,TMRB Block converter I2S,LCDC,SDRAMC, Interrupt controller USBC,RTC,MLD Operate Operate Available select operation block
IDLE2
Stop
IDLE1
Depend PxDR-register setting
STOP
Stop
release Halt mode These HALT states released resetting requesting interrupt. halt release sources determined combination between states interrupt mask register <IFF2 halt modes. details releasing HALT status shown Table Released requesting interrupt operating released from halt mode depends interrupt enabled status.When interrupt request level before executing HALT instruction exceeds value interrupt mask register,the interrupt source processed after releasing halt mode,and status executing instruction that follows HALT instruction. When interrupt request level before executing HALT instruction less than value interrupt mask register,releasing halt mode executed.(in non-maskable interrupts,interrupt processing processed after releasing halt mode regardless value mask register.) However only INT0~INT3, INTKEY interrupts,even interrupt request level before executing HALT instruction less than value interrupt mask register, releasing halt mode executed. this case,interrupt processing, starts executing instruction next HALT instruction,but interrupt request flag held "1". Releasing resetting Releasing halt status executed resetting. When STOP mode released RESET,it necessry enough resetting time (see table 3.3.5) operation oscillator stable. When releasing halt mode resetting, internal data keeps state before "HALT" instruction executed. However other settings contents initialized. (Releasing interrupts keeps state before "HALT" instruction executed.)
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TMP92CH21
Table 3.3.5 Source Halt state clearance Halt clearance operation Status Received Interrupt Halt mode
INTWDT INT0 (Note1) INTALM0 INTTA0 3,INTTB00 INTRX0 1,TX0 INTTBO0,INTI2S INTAD INTKEY INTRTC INTUSB INTLCD RESET
Interrupt Enabled
(interrupt level) (interrupt mask)
Interrupt Disabled
(interrupt level) (interrupt mask)
IDLE2
IDLE1
STOP
IDLE2
IDLE1
STOP
Source Halt state clearance
After clearing Halt mode, starts interrupt processing. (RESET initializes microcont.) After clearing Halt mode, resumes executing starting from instruction following HALT instruction. used release halt mode. priority level (interrupt request level) non-maskable interrupts fixed highest priority level. There this combination type. Releasing halt mode executed after passing warmming-up time. Note When Halt mode cleared INT0 interrupt level mode interrupt enabled status, hold level until starting interrupt processing. level before holding level interrupt processing correctly started. (Example releasing IDLE1 Mode) INT0 interrupt clears Halt state when device IDLE1 Mode.
Interrupt
Address 8203H 8206H 8209H 820BH 820EH INT0
HALT
(IIMC), (INTE0AD), (SYSCR2),
Selects INT0 interrupt rising edge. Sets INT0 interrupt level Sets interrupt level CPU. Sets Halt mode Idle1 Mode. Halts CPU. INT0 interrupt routine RETI
820FH
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TMP92CH21
Operation IDLE2 Mode IDLE2 Mode only specific internal operations, designated IDLE2 Setting Register, take place. Instruction execution stops. Figure 3.3.5 illustrates example timing clearance IDLE2 Mode Halt state interrupt.
Next Next+2
Data
Data
Interrupt release
IDLE2 mode
Figure 3.3.7 Timing chart IDLE2 Mode Halt state cleared interrupt IDLE1 Mode IDLE1 Mode, only internal oscillator RTC,USBC continue operate. system clock stops. Halt state, interrupt request sampled asynchronously with system clock; however, clearance Halt state (i.e. restart operation) synchronous with Figure 3.3.6 illustrates timing clearance IDLE1 Mode Halt state interrupt.
Next Next+2
Data
Data
Interrupt release
IDLE1 mode
Figure 3.3.8 Timing chart IDLE1 Mode Halt state cleared interrupt
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TMP92CH21
STOP Mode When STOP Mode selected, internal circuits stop, including internal oscillator. After STOP Mode been cleared system clock output starts when warm-up time elapsed, order allow oscillation stabilize. Figure 3.3.7 illustrates timing clearance STOP Mode Halt state interrupt.
Warming time
Next Next+2
Data
Data
Interrupt release STOP mode
Figure 3.3.9 Timing chart STOP Mode Halt state cleared interrupt
Table 3.3.6 Example warming-up time after releasing STOP-mode
@fOSCH MHz, =32.768
SYSCR1 <SYSCK>
(fc) (fs)
SYSCR2<WUPTM1,0>
1.024
4.096 2000
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TMP92CH21
Interrupts
Interrupts controlled Interrupt Mask Register <IFF2 (bits Status Register) built-in interrupt controller. TMP92CH21 total interrupts divided into following five types:
Interrupts generated CPU: sources Software interrupts: sources Illegal Instruction interrupt: source Internal interrupts: sources Internal interrupts: sources Micro Transfer interrupts: sources External interrupts: sources Interrupts external pins (INT0 INT5, INTKEY) fixed individual interrupt vector number assigned each interrupt source. seven levels priority also assigned each maskable interrupt. Non-maskable interrupts have fixed priority level highest level. When interrupt generated, interrupt controller sends priority that interrupt CPU. When more than interrupt generated simultaneously, interrupt controller sends priority value interrupt with highest priority CPU. (The highest priority level level used non-maskable interrupts.) compares interrupt priority level which receives with value held Interrupt Mask Register <IFF2 priority level interrupt greater than equal value Interrupt Mask Register, accepts interrupt. However, software interrupts Illegal Instruction interrupts generated processed irrespective value <IFF2 value Interrupt Mask Register <IFF2 changed using instruction sets <IFF2 num). example, command enables acceptance non-maskable interrupts maskable interrupts whose priority level, interrupt controller, higher. commands enable acceptance non-maskable interrupts maskable interrupts with priority level above (hence both equivalent command instruction (sets <IFF2 exactly equivalent instruction. instruction used disable maskable interrupts (since priority level maskable interrupts ranges from instruction takes effect soon executed.
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TMP92CH21
addition general-purpose Interrupt Processing Mode described above, there also Micro Processing Mode. Micro Mode automatically transfers data one-byte, two-byte four-byte blocks; this mode allows high-speed data transfer from internal external memory internal ports. addition, TMP92CH21 also software start function which micro processing requested software rather than interrupt. Figure 3.4.1 flowchart showing overall interrupt processing.
Interrupt processing Micro soft start request
Interrupt apecified micro start vector?
Clear interrupt request flag
Interrupt vector calue read Interrupt request clear
Data transfer micro
General-purpose interrupt processing
PUSH PUSH SR<IFF2:0> Level accepted interrupt INTNEST INTNEST
Count Count-1
Micro processing
Count
Clear vector register generating micro transfer interrupt (INTTC0
(FFFF00H
Interrupt processing program
RETI instruction INTNESTINTNEST
Figure 3.4.1 Interrupt micro processing sequence
92CH21
TMP92CH21 3.4.1 General-purpose interrupt processing
When accepts interrupt, usually performs following sequence operations. However, case software interrupts Illegal Instruction interrupts generated CPU, skips steps executes only steps reads interrupt vector from interrupt controller. When more than interrupt with same priority level have been generated simultaneously, interrupt controller generates interrupt vector accordance with default priority clears interrupt requests. (The default priority determined follows: smaller vector value, higher priority.) pushes Program Counter (PC) Status Register (SR) onto stack (pointed XSP). sets value CPU's Interrupt Mask Register <IFF2 priority level accepted interrupt plus However, priority level accepted interrupt register's value increments interrupt nesting counter INTNEST jumps address given adding contents address FFFF00H interrupt vector, then starts interrupt processing routine.
completion interrupt processing, RETI instruction used return control main routine. RETI restores contents Program Counter Status Register from stack decrements Interrupt Nesting counter INTNEST Non-maskable interrupts cannot disabled user program. Maskable interrupts, however, enabled disabled user program. program priority level each interrupt source. priority level setting will disable interrupt request.) interrupt request received interrupt with priority level equal greater than value Interrupt Mask Register <IFF2 will accept interrupt. Interrupt Mask Register <IFF2 then value priority level accepted interrupt plus during interrupt processing, interrupt generated with higher priority than interrupt currently being processed, during processing non-maskable interrupt processing, non-maskable interrupt request generated from another source, will suspend routine which currently executing accept interrupt. When processing interrupt been completed, will resume processing suspended interrupt. receives another interrupt request while performing processing steps interrupt will sampled immediately after execution first instruction interrupt processing routine. Specifying start instruction disables nesting maskable interrupts. After reset, initializes Interrupt Mask Register <IFF2 111, disabling maskable interrupts. Table 3.4.1 shows TMP92CH21 interrupt vectors micro start vectors. FFFF00H~FFFFFFH (256 bytes) designated interrupt vector area.
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TMP92CH21
Table 3.4.1 TMP92CH21 interrupt vectors micro start vectors
Default Priority Maskable maskable Type Interrupt Source Source Micro Request Reset [SWI0] instruction [SWI1] instruction Illegal instruction [SWI2] instruction [SWI3] instruction [SWI4] instruction [SWI5] instruction [SWI6] instruction [SWI7] instruction (reserved) INTWD: Watchdog Timer Micro INT0: INT0 input INT1: INT1 input INT2: INT2 input INT3: INT3 input INT4: INT4 input(TSI) INTALM0: ALM0(8KHz) INTALM1: ALM1(512Hz) INTALM2: ALM2(64Hz) INTALM3: ALM3(2Hz) INTALM4: ALM4(1Hz) INTP0: Protect0 special SFR) (reserved) INTTA0: 8-bit timer INTTA1: 8-bit timer INTTA2: 8-bit timer INTTA3: 8-bit timer INTTB0: 16-bit timer INTTB1: 16-bit timer INTKEY: wake INTRTC: RTC(alarm interrupt) INTTBO0: 16-bit timer (overflow) INTLCD: LCDC/LP INTRX0: Serial receive (Channel INTTX0: Serial transmission (Channel INTRX1: Serial receive (Channel INTTX1: Serial transmission (Channel (reserved) (reserved) INT5: INT5 input INTI2S: I2S(Channel INTNDF0(NAND Flash Controller Channel INTNDF1(NAND Flash Controller Channel (reserved) (reserved) (reserved) (reserved) (reserved) INTUSB: (reserved) (reserved) 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H 00B4H 00B8H 00BCH 00C0H 00C4H Vector Value Address Vector FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H FFFFB4H FFFFB8H FFFFBCH FFFFC0H FFFFC4H (Note1) (Note1) (Note1) (Note1) refer Micro
Start Vector
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TMP92CH21
Maskable
(reserved) INTAD: conversion INTTC0: Micro (Channel INTTC1: Micro (Channel INTTC2: Micro (Channel INTTC3: Micro (Channel INTTC4: Micro (Channel INTTC5: Micro (Channel INTTC6: Micro (Channel INTTC7: Micro (Channel
00C8H 00CCH 00D0H 00D4H 00D8H 00DCH 00E0H 00E4H 00E8H 00ECH 00F0H
FFFFC8H FFFFCCH FFFFD0H FFFFD4H FFFFD8H FFFFDCH FFFFE0H FFFFE4H FFFFE8H FFFFECH FFFFF0H FFFFFCH
(reserved)
00FCH
Note: Micro default priority interrupt request generated micro DMA, interrupt higher priority than other maskable interrupt (irrespective default channel priority). Note1 When standing-up micro DMA, edge detect mode. Note2 Micro processing cannot applied.
92CH21
TMP92CH21 3.4.2 Micro processing
addition general-purpose interrupt processing, TMP92CH21 also includes micro function. Micro processing interrupt requests micro performed highest priority level maskable interrupts (level regardless priority level interrupt source. Because micro function been implemented with cooperative operation CPU, when state stand-by HALT instruction, requirement micro will ignored (pending). Micro suppoted channels transferred continuously specifying micro burst function following. (1)Micro operation When interrupt request generated interrupt source specified Micro Start Vector Register, micro triggers micro request interrupt priority level starts processing request. eight micro channels allow micro processing eight types interrupt once. When micro accepted, interrupt request flip-flop assigned that channel cleared. Data one-byte two-byte four-byte blocks, automatically transferred once from transfer source address transfer destination address control register, transfer counter decremented value counter after been decremented processing ends with change value micro start vector register. value decremented counter Micro Transfer interrupt (INTTC0 INTTC7) sent from interrupt controller. addition, micro start vector register cleared next micro operation disabled micro processing terminates. micro requests simultaneously more than channel, priority based interrupt priority level channel number: lower channel number, higher priority (Channel thus highest priority Channel lowest). interrupt request triggered interrupt source during interval between time which micro start vector cleared next setting, general-purpose interrupt processing performed interrupt level set. Therefore, interrupt only being used initiate micro (and general-purpose interrupt), interrupt level should first (i.e. interrupt requests should disabled). micro general-purpose interrupts being used together described above, level interrupt which being used initiate micro processing should first lower value than other interrupt levels. this case, edge-triggered interrupts only kinds general interrupts which accepted.
92CH21
TMP92CH21
Although control registers used setting transfer source transfer destination addresses bits wide, this type register only output 24-bit addresses. Accordingly, micro only access Mbytes (the upper eight bits 32-bit address valid). Three micro transfer modes supported: one-byte transfers, two-byte (one-word) transfer four-byte transfer. After transfer mode, transfer source transfer destination addresses will either incremented decremented, will remain unchanged. This simplifies transfer data from memory, from memory I/O, from I/O. details various transfer modes, Section 3.4.2 (1), Detailed description Transfer Mode Register. Since transfer counter 16-bit counter, 65536 micro processing operations performed interrupt source (provided that transfer counter source initially 0000H). Micro processing initiated different interrupts interrupts shown micro start vectors Table 3.4.1 micro soft start. Figure 3.4.2 shows 2-byte transfer carried using micro cycle Transfer Destination Address Mode (micro transfers same every mode except Counter Mode). (The conditions this cycle follows: external 8-bit bus, waits, even-numbered transfer source transfer destination addresses).
state
fSYS A023
Figure 3.4.2 Timing micro cycle State (1),(2): State State State Instruction fetch cycle (prefetches next instruction code) Micro read cycle Micro write cycle (The same state (1),
92CH21
TMP92CH21
(2)Soft start function TMP92CH21 initiate micro either with interrupt using micro soft start function, which micro initiated Write cycle which writes register DMAR. Writing register DMAR causes micro performed once. completion transfer, bits DMAR which support channel automatically cleared When burst specified register DMAB, data transferred continuously from initiation micro until value micro transfer counter
Symbol
NAME
Address 109h RMW)
DREQ7
DREQ6
DREQ5
DREQ4
DREQ3
DREQ2
DREQ1
DREQ0
DMAR
Request
(3)Transfer control registers transfer source address transfer destination address following registers. instruction form cr,r used these registers.
Channel DMAS0 DMAD0 DMAC0 DMAM0 Source address register Destination address register Counter register Mode register
Channel DMAS7 DMAD7 DMAC7 DMAM7 bits bits bits Source address register Destination address register Counter register Mode register
92CH21
TMP92CH21
(4)Detailed description Transfer Mode Register Mode
DMAM0
DMAMn[4:0] 000zz
Mode Description Destination mode (DMADn (DMASn) DMACn DMACn DMACn then INTTCn Destination mode (DMADn (DMASn) DMACn DMACn DMACn then INTTCn Source mode (DMADn) (DMASn DMACn DMACn DMACn then INTTCn Source mode (DMADn) (DMASn DMACn DMACn DMACn then INTTCn Source Destination mode (DMADn (DMASn DMACn DMACn DMACn then INTTCn Source Destination mode (DMADn (DMASn DMACn DMACn DMACn then INTTCn Source Destination Fixed mode (DMADn) (DMASn) DMACn DMACn DMACn then INTTCn Counter mode DMASn DMASn DMACn DMACn DMACn then INTTCn
Execution State number
5states
001zz
5states
010zz
5states
011zz
5states
100zz
6states
101zz
6states
110zz
5states
111zz
5states
1-byte transfer 2-byte transfer 4-byte transfer (reserved)
Note: stands micro channel number DMADn+/DMASn+: Post-increment (register value incremented after transfer) DMADn-/DMASn-: Post-decrement (register value decremented after transfer) "I/O" signifies fixed memory addresses; "memory" signifies incremented decremented memory addresses. Transfer Mode Register should value other than those listed above.
92CH21
TMP92CH21 3.4.3 Interrupt controller operation
block diagram Figure 3.4.3 shows interrupt circuits. left-hand side diagram shows interrupt controller circuit. right-hand side shows interrupt request signal circuit halt release circuit. each interrupt channels there interrupt request flag (consisting flip-flop), interrupt priority setting register micro start vector register. interrupt request flag latches interrupt requests from peripherals. flag cleared zero following cases: when Reset occurs, when reads channel vector interrupt received, when receives micro request (when micro set), when micro burst transfer terminated, when instruction that clears interrupt that channel executed writting micro start vector INTCLR register). interrupt priority independently each interrupt source writing priority interrupt priority setting register (e.g. INTE0AD INTE12). interrupt priorities levels provided. Setting interrupt source's priority level disables interrupt requests from that source. priority non-maskable interrupt (Watchdog Timer interrupts) fixed more than interrupt request with given priority level generated simultaneously, default priority (the interrupt with lowest priority other words, interrupt with lowest vector value) used determine which interrupt request accepted first. bits interrupt priority setting register indicate state interrupt request flag thus whether interrupt request given channel occurred. several interrupts generated simultaneously, interrupt controller sends interrupt request interrupt with highest priority interrupt's vector address CPU. compares mask value <IFF2 Status Register (SR) with priority level requested interrupt; latter higher, interrupt accepted. Then sets <IFF2 priority level accepted interrupt Hence, during processing accepted interrupt, interrupt requests with priority value equal higher than value <IFF2 (i.e. interrupts with priority higher than interrupt being processed) will accepted. When interrupt processing been completed (i.e. after execution RETI instruction), restores SR<IFF2 priority value which saved stack before interrupt generated. interrupt controller also includes eight registers which used store micro start vector. Writing start vector interrupt source micro processing (see Table 3.4.1), enables corresponding interrupt processed micro processing. values must micro parameter registers (e.g. DMAS DMAD) prior micro processing.
92CH21
Interrupt controller Interrupt request RESET interrupt vector read
INTWD
Interrupt mask
Interrupt request
RESET Interrupt level detect Interrupt request signal
Priority setting register
Decoder
Priority encoder signal
Highest Priority interrupt level select
IFF2
INTRQ2
Interrupt request
INT0 Reset
Figure 3.4.3 Block Diagram Interrupt Controller
Interrupt request
INTRQ20 then
Interrupt vector read Micro acknowledge
INT1 INT2 INT3 INT4 INTALM0 INTALM1 INTALM2 INTALM3 INTALM4 INTTC0 INTTC1 INTTC2 INTTC3 INTTC4 INTTC5 INTTC6 INTTC7 Micro start vector setting register
Interrupt vector generator
During IDLE1 During STOP
92CH21
Interrupt vector read
HALT release
Micro Counter Zero Interrupt
RESET INT0,1,2,3,,4KEY,RTC,ALM,USB input
Soft start
INTTC0
then
Micro request
Selector
RESET
DMA0V DMA1V DMA7V
Micro channel specification
TMP92CH21
Micro channel priority dncoder
TMP92CH21
Interrupt level setting registers
Symbol NAME INT0 INTAD Enable
Address
IADC
IADM0
INT0 I0M2 INT1
I0M1
I0M0
INTE0AD
INTAD IADM2 IADM1 INT2 I2M2 INT4 I2M1
INTE12
INT1 INT2 Enable
I2M0
I1M2 INT3
I1M1
I1M0
INTE34
INT3 INT4 Enable
I4M2
I4M1
I4M0
I3M2 INT5
I3M1
I3M0
INTE5I2S
INT5 INTI2S Enable
II2SC
INTI2S II2SM2 II2SM1 INTTA1(Timer1) ITA1M2 ITA1M1 INTAT3(Timer3) ITA3M2 ITA3M1 INTTB1(Timer4) ITB1M2 ITB1M1
II2SM0
I5M2
I5M1
I5M0
INTETA0
INTTA0 INTTA1 Enable INTTA2 INTTA3 Enable INTTB0 INTTB1 Enable INTTBO0
(Overflow)
ITA1C
ITA1M0
ITA0C
INTTA0(Timer0) ITA0M2 ITA0M1 INTAT2(Timer2) ITA2M2 ITA2M1 INTTB0(Timer4) ITB0M2 ITB0M1 INTTBO0
ITBO0M2 ITBO0M1
ITA0M0
INTETA2
ITA3C
ITA3M0
ITA2C
ITA2M0
INTETB0
ITB1C
ITB1M0
ITB0C
ITB0M0
INTETBO
ITBO0C
ITBO0M0
Enable INTRX0 INTTX0 Enable INTRX1 INTTX1 Enable
Note: Always fixed ITX0C INTTX0 ITX0M2 ITX0M1 INTTX1 ITX1M2 ITX1M1 ITX0M0 IRX0C
INTRX0 IRX0M2 IRX0M1 INTRX1 IRX1M2 IRX1M1 INTUSB
IUSBM2 IUSBM1
INTES0
IRX0M0
INTES1
ITX1C
ITX1M0
IRX1C
IRX1M0
INTEUSB
INTUSB Enable
IUSB0C
IUSBM0
Note: Always fixed IA1M0 IA0C INTALM1 IA1M2 IA1M1 INTALM3 IA3M2 IA3M1
INTALM0 IA0M2 IA0M1 INTALM2 IA2M2 IA2M1
INTEALM
INTALM0 INTALM1 Enable INTALM2 INTALM3 Enable
IA1C
IA0M0
INTEALM
IA3C
IA3M0
IA2C
IA2M0
92CH21
TMP92CH21
Symbol
NAME
Address
IA4C
INTEALM INTALM4 Enable
Note: Always fixed INTRTC INTERTC Enable
INTALM4 IA4M2 IA4M1 INTRTC IRM2 IRM1 INTKEY IKM2 IKM1
IA4M0
IRM0
Note: Always fixed INTEC INTKEY Enable
IKM0
Note: Always fixed INTLCD INTLCD Enable
Note: Always fixed INTE ND01 INTNDF0 INTNDF1 Enable IN1C INTNDF1 IN1M2 IN1M1 INTEP0 INTP0 Enable IN1M0
INTLCD ILCD1C ILCDM2 ILCDM1 ILCDM0 IN0C INTNDF0 IN0M2 IN0M1 INTP0 IP0M2 IP0M1 IN0M0
IP0C
IP0M0
Note: Always fixed
Interrupt request flag
lxxM2
lxxM1
lxxM0
Function write Disables interrupt requests Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Disables interrupt requests
92CH21
TMP92CH21
Symbol
NAME
INTTC0 INTTC1 Enable
Address
ITC1C
ITC1M2
ITC1M1
ITC1M0
ITC0C
ITC0M2
ITC0M1
ITC0M0
INTTC1(DMA1)
INTETC01
INTTC0(DMA0) INTTC2(DMA2)
ITC3M0 ITC2C ITC2M2 ITC2M1 ITC2M0
INTTC3(DMA3)
INTETC23
INTTC2& INTTC3 Enable
ITC3C
ITC3M2
ITC3M1
INTTC5(DMA5)
INTTC4(DMA4)
INTETC45
INTTC4 INTTC5 Enable
ITC5C
ITC5M2
ITC5M1
ITC5M0
ITC4C
ITC4M2
ITC4M1
ITC4M0
INTTC7(DMA7)
INTTC6(DMA6)
INTETC67
INTTC6 INTTC7 Enable
ITC7C
ITC7M2
ITC7M1
ITC7M0
ITC6C
ITC6M2
ITC6M1
ITC6M0
INTWD
INTWDT
INTWD Enable
Note: Always fixed
ITCWD
Interrupt request flag
lxxM2
lxxM1
lxxM0
Function write Disables interrupt requests Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Sets interrupt priority level Disables interrupt requests
92CH21
TMP92CH21
Symbol
External interrupt control
NAME Address
I5EDGE
I4EDGE
INT4EDGE Rising Falling
I3EDGE
INT3EDGE Rising Falling
I2EDGE
INT2EDGE Rising Falling
I1EDGE
INT1EDGE Rising Falling
I0EDGE
INT0EDGE Rising Falling
I0LE
0:INT0 edge mode 1:INT0 level mode
Write
Interrupt
IIMC
Input Mode Control
RMW)
INT5EDGE Rising Falling
Note: INT0 Level Enable Rising edge detect "H"level Note Disable INT0 request before changing INT0 mode from level-sense edge-sense.
Setting example:
(IIMC), XXXXXX0-B Switches from level edge. (INTCLR), Clears interrupt request flag. Note: Don't care; change.
Note electrical characteristics section external interrupt input pulse width.
Settings External interrupt Function Interrupt name Mode Setting method
Rising Edge <I0LE> ,<I0EDGE> INT0 Falling Edge <I0LE> <I0EDGE> High Level INT1 INT2 <I0LE>
Rising Edge <I1EDGE> Falling Edge <I1EDGE> Rising Edge <I2EDGE> Falling Edge <I2EDGE>
INT3 INT4 INT5
Rising Edge <I3EDGE> Falling Edge <I3EDGE> Rising Edge <I4EDGE> Falling Edge <I4EDGE> Rising Edge <I5EDGE> Falling Edge <I5EDGE>
92CH21
TMP92CH21
Symbol
Receive interrupt control
NAME Address RMW) Write IR1LE 0:INTRX1 edge mode 1:INTRX1 level mode IR0LE 0:INTRX0 edge mode 1:INTRX0 level mode
SIMC
Interrupt Mode Control
INTRX1 Level Enable Rising edge detect INTRX1 "H"level INTRX1
INTRX0 rising edge Enable Rising edge detect INTRX0 "H"level INTRX0
92CH21
TMP92CH21
Interrupt request flag clear register interrupt request flag cleared writing appropriate micro start vector, given Table (1), register INTCLR. example, clear interrupt flag INT0, perform following register operation after execution instruction. INTCLR Clears interrupt request flag INT0. Symbol INTCLR NAME Interrupt Clear control Address
RMW)
Interrupt Vector
(5)Micro start vector registers These registers assign micro processing sets which source corresponds DMA. interrupt source whose micro start vector value matches vector these registers designated micro start source. When micro transfer counter value reaches zero, micro transfer interrupt corresponding channel sent interrupt controller, micro start vector register cleared, micro start source channel cleared. Therefore, order micro processing continue, micro start vector register must again during processing micro transfer interrupt. same vector micro start vector registers more than channel, lowest numbered channel takes priority. Accordingly, same vector micro start vector registers different channels, interrupt generated lower-numbered channel executed until micro transfer complete. micro start vector this channel been channel's micro start vector register again, micro transfer higher-numbered channel will commenced. (This process known micro chaining.)
92CH21
TMP92CH21
Symbol DMA0V
NAME DMA0 Start Vector DMA1 Start Vector DMA2 Start Vector DMA3 Start Vector DMA4 Start Vector
Address 100h
DMA0V5
DMA0V4
DMA0V3
DMA0V2
DMA0V1
DMA0V0
DMA0 Start Vector
DMA1V5
DMA1V4
DMA1 Start Vector
DMA1V3 DMA1V2
DMA1V1
DMA1V0
DMA1V
101h
DMA2V5
DMA2V4
DMA2 Start Vector
DMA2V3 DMA2V2
DMA2V1
DMA2V0
DMA2V
102h
DMA3V5
DMA3V4
DMA3 Start Vector
DMA3V3 DMA3V2
DMA3V1
DMA3V0
DMA3V
103h
DMA4V5
DMA4V4
DMA4 Start Vector
DMA4V DMA4V2
DMA4V1
DMA4V0
DMA4V
104h
DMA5V5
DMA5V4
DMA5 Start Vector
DMA5V DMA5V2
DMA5V1
DMA5V0
DMA5V
DMA5 Start Vector
105h
DMA6V5
DMA6V4
DMA6 Start Vector
DMA6V DMA6V2
DMA6V1
DMA6V0
DMA6V
DMA6 Start Vector
106h
DMA7V5
DMA7V4
DMA7 Start Vector
DMA7V DMA7V2
DMA7V1
DMA7V0
DMA7V
DMA7 Start Vector
107h
92CH21
TMP92CH21
Specification micro burst Specifying micro burst function causes micro transfer, once started, continue until value Transfer Counter Register reaches zero. Setting bits register DMAB which correspond micro channel shown below) specifies that micro transfer that channel will burst transfer. Symbol DMAB NAME Burst Address 108h DBST7 DBST6 DBST5 DBST4 DBST3 DBST2 DBST1 DBST0
92CH21
TMP92CH21
(7)Notes instruction execution unit interface unit this operate independently. Therefore immediately before interrupt generated, fetches instruction which clears corresponding interrupt request flag, execute this instruction between accepting interrupt reading interrupt vector. this case, will read default vector 0004H jump interrupt vector address FFFF04H. avoid this, instruction which clears interrupt request flag should always preceded instruction. addition, please note that following circuits exceptional demand special attention.
INT0 Level Mode
Level Mode INT0 edge-triggered interrupt. Hence, Level Mode interrupt request flip-flop INT0 does function. peripheral interrupt request passes through input flip-flop becomes output. interrupt input mode changed from Edge Mode Level Mode, interrupt request flag cleared automatically. enters interrupt response sequence result INT0 going from INT0 must then held until interrupt response sequence been completed. INT0 Level Mode release Halt state, INT0 must held from time INT0 changes from until Halt state released. (Hence, necessary ensure that input noise interpreted causing INT0 revert before Halt state been released.) When mode changes from Level Mode Edge Mode, interrupt request flags which were Level Mode will cleared. Interrupt request flags must cleared using following sequence. (IIMC), 00H; Switches from level edge. (INTCLR), 0AH; Clears interrupt request flag.
INTRX
edge mode(the register SIMC<IRxLE> "0"),the interrupt request flip-flop only cleared Reset reading Serial Channel Receive Buffer. cannot cleared instruction.
Note: following instructions input state changes equivalent instructions which clear interrupt request flag. INT0: Instructions which switch Level Mode after interrupt request been generated Edge Mode. input changes from High after interrupt request been generated Level Mode. ("H" "L") INTRX: Instructions which read Receive Buffer
92CH21
TMP92CH21
Function Ports
TMP92CH21 port pins that shown table 3.5.1 addition functioning general-purpose ports, these pins also used internal functions. Table 3.5.2 lists registers their specifications.
Table 3.5.1 Port Functions (1/2)
with programmable pull-up resistor, with programmable pull-down resistor,U= with pull-up resistor) Number Setting Name built-in function Port Name Name Pins Port Port D23,KO0 Port D31, Port (Fixed) Port (Fixed) Port Port Output (Fixed) /WRLL,/NDRE /WRLU,/NDWE Output (Fixed) EA24 Output (Fixed) EA25 R/W,NDR/B /WAIT Port Output (Fixed) /CS0 Output (Fixed) /CS1,/SDCS Output (Fixed) /CS2,/CSZA,/SDCS Output (Fixed) /CS3 Output (Fixed) /CSZB,/WRUL,/ND0CE Output (Fixed) /CSZC,/WRUU,/ND1CE Output (Fixed) /CSZD,/SRULB Output (Fixed) /CSZE,/SRUUB Port TXD0,I2SCKO RXD0,I2SDO SCLK0,/CTS0,I2SWS LGOE0 LGOE1 Output (Fixed) LGOE2 Port Input Input Input Input Output (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) INT4,PX INT5,PY LD11, INT0,TA1OUT INT1,TA3OUT INT2,TB0OUT0 INT3 KO8,LDIV /CSZF,LCP1 TXD0,TXD1 RXD0,RXD1 SCLK0,/CTS0, SCLK1,/CTS1 SDCLK
Port
Port
92CH21
TMP92CH21
Table 3.5.1 Port Functions (2/2)
with programmable pull-up resistor, with programmable pull-down resistor,U= with pull-up resistor) Port Name Port Port Name Number Pins Input Input Input Output Output Output Output Output Output Output Output Output Output Output Output Output Setting (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Name built-in function toAN1 AN2,MX AN3, /ADTRG,MY /SDRAS,/SRLLB /SDCAS,SRLUB /SDWE,/SRWR SDLLDQM SDLUDQM SDULDQM,NDALE SDUUDQM,NDCLE SDCKE LCP0 LBCD MLDALM /ALARM,/MLDALM
Port
Port Port
92CH21
TMP92CH21
Table 3.5.2 Registers Specifications (1/3)
Port Port name Specification Input port Output port Input port Output port Input port Output port Output port output Output port output Input port Output port output Output port Input port output /WRLL output /NDRE output /WRLU output /NDWE output EA24 output EA25 output output NDR/B input /WAIT input Output Port /CS0 output /CS1 output /SDCS output /CS2 output /CSZA Output /SDCS output /CS3 output /CSZB output /WRUL output /ND0CE output /CSZC output /WRUU output /ND1CE output /CSZD output /SRULB output /CSZE output /SRUUB output None register PnCR PnFC None None None None
Don't care
PnFC2 None
Port
None
Port
Port Port Port
None
None
Port
None
Port
92CH21
TMP92CH21
Table 3.5.2 Registers Specifications (2/3)
Port Port name Input port Output port TXD0 output I2SCKO output TXD0 output(Open Drain) RXD0 input I2SDO output SCLK0 output I2SWS output SCLK0,/CTS0 input (note1) LGOE0 output LGOE1 output LGOE2 output INT4 input INT5 input Input port input LD11 output Input port Output port INT0 input TA1OUT output INT1 input TA3OUT output INT2 input TB0OUT0 output INT3 input LDIV output output (Open drain) LCP1 output /CSZF output Input port Output port TXD0 output TXD1 output TXD0/TXD1 output (Open Drain) RXD0 input RXD1 input SCLK0 output SCLK1 output SCLK0,/CTS0 input SCLK1,/CTS1 input SDCLK output Specification None register PnCR PnFC None None None
Don't care
PnFC2
None
Port
None None None None None None None
Port
None
Port
PF2,PF7
None
(note1) P92-pin SCLK0-input /CTS0-input, PF<PF2>.
92CH21
TMP92CH21
Table 3.5.2 Registers Specifications (3/3)
Port Port name Specification Input port input /ADTRG input output outout Output port Input port /SDRAS,/SRLLB output /SDCAS,/SRLUB output /SDWE,/SRWR output SDLLDQM output SDLUDQM output SDULDQM output NDALE output SDUUDQM output NDCLE output SDCKE output Output port LCP0 output output output LBCD output Input Port Output Port output Output Port MLDALM output /MLDALM output /ALARM output register PnCR PnFC
Don't care
PnFC2
None
None
None
Port
None
None
None
Port
None
Port
Port
None
None
None
None
After Reset, port pins listed below function general-purpose port pins. Reset sets pins, which programmed either input, output input ports pins. Setting port pins internal function must done software.
92CH21
TMP92CH21
3.5.1 Port (P10 P17)
Port1 8-bit general-purpose port. Bits individually either inputs outputs control register P1CR function register P1FC. addition functioning general-purpose port, port1 also function data D15).
P1CR register
Function Setting after reset released Don't this setting Data D15) Data D15) Input port
P1FC register External write strobe register External write data Port read data Selector Selector
D15)
External read data
External read strobe
Figure 3.5.1 Port1
Table 3.5.3 Port1 Registers SYMBOL NAME PORT1 Address 0004H P17C 0006H 0007H P17D 0081H P16D 0:PORT 1:Data Bus(D8 D15) P14D P13D P12D Output/Input buffer drive-register standby-mode P15D P11D P16C P15C P12C P11C P10C P10D
P1CR
PORT1 Control Register PORT1 Function Register PORT1 Drive Register
Input/Output P14C P13C 0:Input 1:Output
P1FC
P1DR
92CH21
TMP92CH21
3.5.2 Port (P20 P27)
Port2 8-bit general-purpose port. Bits individually either inputs outputs control register P2CR function register P2FC. addition functioning general-purpose port, port2 also function either data (D16 D23) key-board interface which open drain output buffer. Function Setting after reset released Don't this setting Input port Data (D16 D23) Input port
P2CR register P2FC register
External write strobe
P2FC2 register
register
(D16 D23,
Open drain enable
KO7)
External write data
Selector
Selector
Port read data External read data External read strobe
Figure 3.5.2 Port2
Table 3.5.4 Port2 Registers SYMBOL NAME PORT2 Address 0008H P27C 000AH 000BH P27F2 0009H P27D 0082H P26D P26F2 0:PORT 1:Data Bus(D16 D23) P24F2 P23F2 P22F2 0:CMOS output, 1:Open drain output P25D P24D P23D P22D Output/Input buffer drive-register standby-mode P25F2 P21F2 P26C P25C P22C P21C P20C P20F2
P2CR
PORT2 Control Register PORT2 Function Register PORT2 Function Register2 PORT2 Drive Register
Input/Output P24C P23C 0:Input 1:Output
P2FC
P2FC2
P21D
P20D
P2DR
92CH21
TMP92CH21
3.5.3
Port (P30 P37)
Port3 8-bit general-purpose port. Bits individually either inputs outputs control register P3CR function register P3FC. addition functioning general-purpose port, port3 also function either data (D24 D31) Function Setting after reset released Don't this setting Input port Data (D24 D31) Input port
P3CR register P3FC register
External write strobe
register
(D24 D31)
External write data
Selector
Selector
Port read data External read data External read strobe
Table 3.5.5 Port3 Registers
SYMBOL NAME PORT3 Address 000CH P37C 000EH 000FH P37D 0083H P36D P36C
Figure 3.5.3 Port3
P31C P31D P30C P30D
P3CR
PORT3 Control Register PORT3 Function Register PORT3 Drive Register
P3FC
P3DR
Input/Output P35C P34C P33C P32C 0:Input 1:Output <P3F> 0:PORT, 1:Data Bus(D24 D31) P35D P34D P33D P32D Output/Input buffer drive-register standby-mode
92CH21
TMP92CH21
3.5.4 Port (P40 P47)
Port4 8-bit general-purpose Output ports. addition functioning general-purpose Output port, port4 also function address A7). Function Setting after reset released Don't this setting Address Bus(A0 Address Bus(A0 Output port
P4FC register register
External address Port read data
Selector
Figure 3.5.4 Port4
Table 3.5.6 Port4 Registers
SYMBOL NAME PORT4 Address 0010H P47F 0013H P47D 0084H P46D P46F P41F P40F Input/Output P45F P44F P43F P42F 0:PORT 1:Address Bus(A0 P45D P44D P43D P42D Output/Input buffer drive-register standby-mode
P4FC
PORT4 Function Register PORT4 Drive Register
P41D
P40D
P4DR
92CH21
TMP92CH21
3.5.5 Port (P50 P57)
Port5 8-bit general-purpose Output ports. addition functioning general-purpose port, port5 also function address A15). Function Setting after reset released Don't this setting Address Bus(A8 A15) Address Bus(A8 A15) Output port
P5FC register register
A15)
External address Port read data
Selector
Figure 3.5.5 Port5
Table 3.5.7 Port5 Registers
SYMBOL NAME PORT5 Address 0014H P57F 0017H P57D 0085H P56D P56F P51F P50F Input/Output P55F P54F P53F P52F 0:PORT 1:Address Bus(A8 A15) P55D P54D P53D P52D Output/Input buffer drive-register standby-mode
P5FC
PORT5 Function Register PORT5 Drive Register
P51D
P50D
P5DR
92CH21
TMP92CH21
3.5.6
Port (P60 P67)
Port6 8-bit general-purpose ports. Bits individually either inputs outputs control register P6CR function register P6FC. addition functioning general-purpose port, port6 also function address (A16 A23). Function Setting after reset released Don't this setting Address Bus(A16 A23) Address Bus(A16 A23) Input port
P6CR register P6FC register
(reserved)
register
(A16 A23)
External write data
Selector
Selector
Port read data
Figure 3.5.6 Port6
Table 3.5.8 Port6 Registers
SYMBOL NAME PORT6 Address 0018H P67C 001AH P67F 001BH P67D 0086H P66D P66C P66F P61C P61F P60C P60F Input/Output P65C P64C P63C P62C 0:Input 1:Output P65F P64F P63F P62F 0:PORT 1:Address Bus(A16 A23) P65D P64D P63D P62D Output/Input buffer drive-register standby-mode
P6CR
PORT6 Control Register PORT6 Function Register PORT6 Drive Register
P6FC
P61D
P60D
P6DR
92CH21
TMP92CH21
3.5.7 Port (P70 P76)
Port7 7-bit general-purpose port(P70,P73 used output only). Bits individually either inputs outputs control register P7CR function register P7FC. addition functioning general-purpose port, pins also function interface-pin external memory. reset initializes P70,P73 pins output port mode, P71,P72,P75 input port mode.
Function Setting after reset released Don't this setting Output port
P7FC register
register
Read strobe, EA24,EA25 Port read data
P70(/RD) P73(EA24) P74(EA25)
Selector
P7CR register P7FC register register
Write strobe,
P71(/WRLL,/NDRE) P72(/WRLU,/NDWE) P75(R/W,NDR/B) P76(/WAIT) P7FC
Selector
Port read data
Wait request NDR/B
Selector
Figure 3.5.7 Port7
92CH21
TMP92CH21
Table 3.5.9 Port7 Registers
SYMBOL NAME PORT7 Address 001CH 001EH PORT7 Function Register 001FH In/Out P7CR PORT7 Control Register P76C P76F 0:PORT 1:/WAIT P75C P75F 0:PORT 1:R/W, NDR/B Output P72C In/Out P71C P71F 0:PORT
/NDRE <P71>=0 /WRLL <P71>=1
Output P70F 0:PORT 1:/RD
P7FC
0:Input 1:Output P74F P73F P72F 0:PORT 0:PORT 0:PORT 1:EA25 1:EA24
/NDWE <P72>=0 /WRLU <P72>=1
P7DR
PORT7 Drive Register
0087H
P76D
P75D
P73D P72D P71D Output/Input buffer drive-register standby-mode
P74D
P70D
setting
<P72C> <P72F>
setting
<P71C>
Input port (reserved)
Output port /NDWE <P72>=0) /WRLH <P72>=1)
<P71F>
Input port (reserved)
Output port /NDRE <P71>=0) /WRLL <P71>=1)
setting
<P76C> <P76F>
setting
<P75C>
Input port /WAIT input
Output port (reserved)
<P75F>
Input port NDR/B input
Output port
92CH21
TMP92CH21
3.5.8
Port (P80 P87)
Port80 8-bit output ports. Resetting sets output latch output latches P81, "1". Port8 also function interface-pin external memory. Above setting used function register P8FC. Writing corresponding P8FC, P8FC2 enables respective functions. Resetting resets P80F P87F P8FC P8FC2 "0", sets bits output ports. Port82 initial state Function Setting after reset released Don't this setting Output port Output port Output port
Reset
Function control basis) P8FC2 write Funtion control basis) P8FC write Output lacth write
"1", "1", /SDCS, "1", /ND0CE,/ND1CE,"1", "1",
(/CS0) (/CS1, /SDCS) (/CS2, /CSZA,/SDCS) (/CS3) (/CSZB,/WRUL,/ND0CE) (/CSZC,/WRUU,/ND1CE) (/CSZD,/SRULB) (/CSZE,/SRUUB)
Selector
read
"1", /SDCS, /CSZA, "1", /WRUL,/WRUU,/SRULB,/SRUUB /CS0, /CS1, /CS2, /CS3, /CSZB,/CSZC,/CSZD,/CSZE
Figure 3.5.9 Port
92CH21
TMP92CH21
Port Register
(0020H)
Symbol Read/Write After reset
Port Function Register
P8FC (0023H)
Symbol Read/Write After reset Function PORT /CSZE
P86F
P85F
P84F
P83F
P82F
P81F
P80F
P87F
PORT /CSZD
Refer below table
Refer below table
PORT /CS3
PORT /CS2
PORT /CS1
PORT /CS0
Port Function Register
P8FC2 (0021H)
Symbol Read/Write After reset Function <P87F> 1:/SRUUB
P86F2
P85F2
P84F2
P83F2
P82F2
P81F2
P80F2
P87F2
<P86F> 1:/SRULB
Refer below table
Refer below table
Write
<P82F> 1:/CSZA
<P81F> 1:/SDCS
Write
Port Drive register
P8DR (0088H)
Symbol Read/Write After reset Function
P86D
P85D
P84D
P83D
P82D
P81D
P80D
P87D
Output/Input buffer drive-register standby-mode setting
<P84F>
setting
<P85F> <P85F2>
setting
<P82F>
Output port /WRUU
/CSZC /ND1CE
<P84F2>
Output port /WRUL
/CSZB /ND0CE
<P82F2>
Output port /CSZA
/CS2 /SDCS
(Note) Read-modify-write prohibited P8FC P8FC2
Figure 3.5.10 Register Port
92CH21
TMP92CH21
3.5.9
Port9 (P90 P97)
5-bit general-purpose port. basis using control register. Resetting sets input port bits output latch to"1". 1-bit general-purpose output port 2-bit general-purpose input port. Writing corresponding P9FC enables respective functions. Resetting resets P9FC "0", sets bits input ports.
Port90 (TXD0,I2SCKO), Port91 (RXD0,I2SDO), Port (SCLK0,/CTS0,I2SWS) Port90 general-purpose port. They also used either SIO0 I2S. Each pins below.
SIO-mode (SIO0 module) TXD0 (data output) RXD0 (data input) SCLK0 (clock input output) UART,IrDA-mode (SIO0 module) TXD0 (data output) RXD0 (data input) /CTS0 (Clear send) I2S-mode (I2S module) I2SCKO (clock output) I2SDO (data output) I2SWS (word-select output) SIO-mode (I2S module) I2SCKO (clock output) I2SDO (data output) use)
Reset Direction control basis) P9CR write Internal data Function control basis) P9FC write Output latch write TXD0, I2SCKO output Selector read
(TXD0,I2SCKO)
Selector
Open drain possible P9ODE<P90ODE>
Figure 3.5.11(1)
92CH21
TMP92CH21
Reset Direction control basis) P9CR write Internal data Function control basis) P9FC write Output latch write I2SDO output SCLK0,I2SWS output P91(RXD0,I2SDO) P92(SCLK0,/CTS0,I2SWS)
Selector Selector read PortF1) P91RXD0 PortF2) P92SCLK0
Figure 3.5.11(2)
(LGOE0), P94(LGOE1), P95(LGOE2)
Reset Direction control basis) P9CR write Funtcion control basis) P93(LGOE0), P9FC write Output latch write LGOE0,LGOE1 P94(LGOE1)
Internal data
Selector
Selector
read
Figure
3.5.12
Port
92CH21
TMP92CH21
Reset Direction control basis) P9CR write Funtcion control basis) P9FC write Output latch write LGOE2 P95(LGOE2)
Internal data
Selector
read
Figure
3.5.13
Port95
Reset
Function control bits basis)
Internal data
AVCC TSICR0<PXEN> <PYEN> TSICR0<TSI7> P-ch
P9FC write
read
(INT4,PX) (INT5,PY)
TSICR1<DBC7>
Only
INT4 INT5 Rising/Falling edge-detection
De-bounce Circuit
Selector
IIMC<I4EDGE, I5EDGE
TSICR0<TWIEN TSI7>
TSICR0<PXEN> TSICR0<TSI7>
N-ch Pull-down Resistor
Figure
3.5.14
Port96,97
92CH21
TMP92CH21
Port Register
(0024H) Symbol Read/Write After reset
Input mode Port Control Register
P9CR (0026H) Symbol Read/Write After reset Function
P95C
P94C
P93C
P92C
P91C
P90C
Port Function Register
P9FC (0027H) Symbol Read/Write After reset Function
Input port INT5
P96F
P95F
P94F
P93F
P92F
P91F
P90F
P97F
Input port INT4
setting
<P92C> <P92F>
setting
<P91C>
setting
<P90C>
input port
SCLK0,/CTS0
output port SCLK0
<P91F>
input port RXD0 I2SDO setting
output port (reserved)
<P90F>
input port I2SCKO setting
output port TXD0
I2SWS setting
<P95C> <P95F>
<P94C>
<P93C>
output port LGOE2
<P94F>
input port LGOE1
output port
<P93F>
input port LGOE0
output port
Port Function Register
P9FC2 (0025H) Symbol Read/Write After reset Function
P90F2 0:CMOS 1:OpenDrain
Port Drive Register
P9DR (0089H) Symbol Read/Write After reset Function P97D
P96D
P95D
P94D
P93D
P92D
P91D
P90D
Output/Input buffer drive-register standby-mode
Note Read-modify-write prohibited P9CR,P9FC P9FC2.
Figure
3.5.14
Register Port
92CH21
TMP92CH21
3.5.10
Port (PA0 PA7)
Port 8-bit input ports with pull-up resistor. addition functioning general-purpose ports, port also Key-on wake-up function Keyboard interface. various functions each enabled writing corresponding Port Function Register (PAFC). Resetting resets bits register PAFC sets pins input port.
INTKEY
Start Edge detection
8-OR
Internal data
Reset KEY-ON ENABLE basis) PAFC write read Reset LD11 PACR basis) PACR write Only Pull-up register
PA0(KI0) PA1(KI1) PA2(KI2) PA3(KI3,LD8) PA4(KI4,LD9) PA5(KI5,LD10) PA6(KI6,LD11) PA7(KI7)
Figure 3.5.15 Port When PAFC="1", either input KI0-KI7 pins falls down, INTKEY interrupt generated. INTKEY interrupt used release HALT mode.
92CH21
TMP92CH21
Port Register
(0028H) Symbol Read/Write After reset
Input Mode Port Function Register
PAFC (002BH) Symbol Read/Write After reset
disable Port Control Register
enable
PACR (002AH) Symbol Read/Write After reset
PA6C
PA5C
PA4C
PA3C
input port LD11-LD8 output Port Drive Register
PADR (008AH) Symbol Read/Write After reset Function PA7D
PA6D
PA5D
PA4D
PA3D
PA2D
PA1D
PA0D
Output/Input buffer drive-register standby-mode
Note Read-Modify-Write prohibited registers PACR PAFC
Figure 3.5.16 Port register
92CH21
TMP92CH21
3.5.11
Port (PC0 PC3,PC6 PC7)
PC3,PC6 6-bit general-purpose port. Each individually input output. Resetting sets Port input port. addition functioning general-purpose port, Port also function output timers (TA1OUT, TA3OUT TB0OUT0), input external interruption (INT0 INT3) output memory(/CSZF) output Key(KO8) output Driver(LDIV,LCP1). Above setting used
function register PCFC. Edge select external interruption establishes with IIMC register, which there interruption controller. PC0(INT0,TA1OUT)
Reset
Direction Control bits basis)
PCCR write Internal data
Function control bits basis)
PCFC write Output latch write TA1OUT Selecter read Level edge select Raising/Falling select IIMC<I0LE, I0EDGE> (INT0, TA1OUT)
Selecter
INT0
Figure 3.5.17 Port
92CH21
TMP92CH21
Reset
PC1(INT1,TA3OUT), PC2(INT2,TB0OUT0) PC3(INT3,TB0OUT1)
Direction Control bits basis)
PCCR write Function control basis)
Internal data
PCFC write Output latch write TA3OUT TB0OUT0
Selecter
PC1(INT1,TA3OUT) PC2(INT2,TB0OUT0) PC3(INT3)
Selecter read INT1 INT3
Rising/Falling edge-detection IIMC< I1EDGE, I2EDGE, I3EDGE
Figure 3.5.18 Port (KO8,LDIV)
Reset Direction control basis) PCCR write Funtcion control basis) PCFC write Output latch write LDIV Selector (KO8,LDIV)
Internal data
Open drain possible
Selector
read
Figure 3.5.19 Port
92CH21
TMP92CH21 (/CSZF,LCP1)
Reset Direction control basis) PCCR write Funtcion control basis) PCFC write Output latch write /CSZF LCP1 Selector Selector read (/CSZF,LCP1)
Internal data
Figure 3.5.19 Port
92CH21
TMP92CH21
Port Register
(0030H) Symbol Read/Write After Reset
Input Mode Port Control Register
Input Mode
PCCR (0032H) Symbol Read/Write After Reset PC7C
PC6C
PC3C
PC2C
PC1C
PC0C
Port Function Register
PCFC (0033H) Symbol Read/Write After Reset Function setting
<PC2C> <PC2F>
PC6F
PC3F
PC2F
PC1F
PC0F
PC7F
setting
<PC1C> <PC0C>
setting output port TA3OUT input port INT0 setting
<PC3C>
input port INT2 setting
output port TB0OUT0
<PC1F>
input port INT1 setting
<PC0F>
output port TA1OUT
<PC7C> <PC7F>
<PC6C>
input port /CSZF
<PC6F>
input port
KO8(open drain)
output port LDIV
<PC3F>
input port INT3
output port (reserved)
output port LCP1
Port Drive Register
PCDR (008CH) Symbol Read/Write After reset Function PC7D
PC6D
PC3D
PC2D
PC1D
PC0D
Output/Input buffer drive-register standby-mode
Note Read-Modify-Write prohibited registers PCCR, PCFC.
Figure 3.5.20 Register Port
92CH21
TMP92CH21
3.5.12
Port (PF0 PF2,PF7)
Port 3-bit general-purpose ports. Each individually input output. Resetting sets input ports. also sets bits output latch register "1". addition functioning general-purpose port pins, also function serial channels enabled writing corresponding Port Function Register (PFFC). PortF7 1-bit general-purpose output port. addition functioning general-purpose output port also function SDCLK output. Resetting sets SDCLK output port.
(1)Port (TXD0,TXD1), F1(RXD0,RXD1), F2(SCLK0,/CTS0,SCLK1,/CTS1) PortF0 general-purpose port. They also used either SIO0 SIO1. Each pins below.
SIO-mode (SIO0 module) TXD0 (data output) RXD0 (data input) SCLK0 (clock input output) UART,IrDA-mode (SIO0 module) TXD0 (data output) RXD0 (data input) /CTS0 (Clear send) SIO-mode (SIO1 module) TXD1 (data output) RXD1 (data input) SCLK1 (clock input output) UART -mode (SIO1 module) TXD1 (data output) RXD1 (data input) /CTS1 (Clear send)
Reset Direction control basis) PFCR write Internal data Function control basis) PFFC write Output latch write
TXD0 TXD1
Selecter
Open-drain possible PFFC2<PF0F2>
(TXD0,TXD1)
Selecter Read
Figure 3.5.21 Port
92CH21
TMP92CH21
Reset
Ditection control basis) Internal data PFCR write Output latch write (RXD0,RXD1)
Selecter
read PFFC<PF1F> RXD0
Selecter
P91RXD0
RXD1
Figure 3.5.22 Port
Reset
Ditection control basis) (SCLK0,/CTS0, SCLK1,/CTS1) SCLK0 SCLK1
Internal data
PFCR write Output latch write Selecter
Function control basis) PFFC write
read
Selecter
PFFC<PF2F>
SCLK0in,/CTS0in SCLK1in,/CTS1in
Selecter
P92SCLK0in
Figure 3.5.23 Port
92CH21
TMP92CH21
Reset
Internal data
Funtcion control basis) PFFC write Output latch write SDCLK Selector PF7(SDCLK)
read
Figure 3.5.26 Port
92CH21
TMP92CH21
Port Register
(003CH) Symbol Read/Write After Reset
Port Control Register
PFCR (003EH) Symbol Read/Write After Reset
PF2C
PF1C
PF0C
Port Functon Register
PFFC (003FH) Symbol Read/Write After Reset PF7F
PF2F
PF1F RXD0 Selection PortF1 Port91 setting
PF0F
Function
setting
<PF2C> <PF2F> <PF1C>
setting
<PF0C>
input port SCLK1,/CTS1 SCLK0,/CTS0 From PF2-pin <PF2>=0 From P92-pin <PF2>=1
output port
<PF1F>
input port RXD0/RXD1
output port
<PF0F>
input port TXD1 setting
output port TXD0
SCLK1
SCLK0
<PF7F>
output port SDCLK
Port Functon Register2
PFFC2 (003DH) Symbol Read/Write After Reset Function
PF0F2
Output buffer CMOS OpenDrain
Port Drive Register
PFDR (008FH) Symbol Read/Write After reset Function PF7D
PF2D
PF1D
PF0D
Output/Input buffer drive-register standby-mode
Note Read-Modify-Write prohibited registers PFCR,PFFC PFFC2.
Figure 3.5.24 Register Port
92CH21
TMP92CH21
3.5.13
Port (PG0 PG3)
4-bit input port also used analog input pins internal converter. also used ADTRG converter. PG2,PG3 also used Touch screen interface.
Internal data
Port read
PG0(AN0), PG1(AN1), PG2(AN2,MX), PG3(AN3,MY,/ADTRG)
Conversion Result Register
Converter
Channel Selector
Read
ADTRG (Only PG3) (Only PG2,PG3) TSICR0<MXEN, MYEN
TSICR0<TSI7
Figure 3.5.25 Port
Port Register
(0040H) Symbol Read/Write After reset
Input mode
Note: input channel selection Converter permission ADTRG input Converter mode register ADMOD1. Port Drive Register
PGDR (0090H) Symbol Read/Write After reset Function
PG3D
PG2D
Output/Input buffer drive-register standby-mode
Figure 3.5.26 Register Port
92CH21
TMP92CH21
3.5.14
Port (PJ0 PJ7)
6-bit output port. Resetting sets output latch "1", they output "1". 2-bit input/output port.
addition functioning port, Port also functions output pins SDRAM (/SDRAS, /SDCAS, /SDWE, SDLLDQM, SDLUDQM, SDULDQM, SDUUDQM SDCKE) ,SRAM(/SRWR, /SRLLB /SRLUB) NANDFlash(NDALE NDCLE). Above setting used function register PJFC. Output signal either SDRAM SRAM selected automatically according setting memory controller.
Reset Function control basis) PJFC2 write Funtion control basis) PJFC write Selector Output lacth write
/SRLLB, /SRLUB /SRWR
PJ0(/SDRAS,/SRLLB) PJ1(/SDCAS,/SRLUB) PJ2(/SDWE, /SRWR) PJ3(SDLLDQM,) PJ4(SDLUDQM) PJ7(SDCKE)
read
/SDRAS, /SDCAS,/SDWE, SDLLDQM, SDLUDQM, SDCKE
Figure3.5.27 Port J0,J1,J2,J3,J4
Reset Direction control basis) PJCR write Internal data Function control basis) PJFC write Output latch write
SDULDQM,SDUUDQM NDALE,NDCLE
Selecter
PJ5(SDULDQM,NDALE), PJ6(SDUUDQM,NDCLE)
Selecter Read
Figure3.5.28 Port
92CH21
TMP92CH21
Port register
(004CH) Symbol Read/W rite After Reset
Port control register
PJCR (004EH) Symbol Read/W rite After Reset Function
PJ6C
PJ5C
Port function register
PJFC (004FH) Symbol Read/W rite After Reset
PORT SDCKE
PJ6F
PJ5F
PJ4F
PJ3F
PJ2F
PJ1F
PJ0F
PJ7F
PORT NDCLE <PJ6>=0,
SDUUDQM
PORT NDALE <PJ5>=0,
SDULDQM
PORT SDLUDQM
PORT SDLLDQM
PORT /SDW /SRW
PORT /SDCAS, /SRLUB
PORT /SDRAS, /SRLLB
Function
<PJ6>=1
<PJ5>=1
Port Drive register
PJDR (0093H)
Symbol Read/W rite After reset Function
PJ6D
PJ5D
PJ4D
PJ3D
PJ2D
PJ1D
PJ0D
PJ7D
Output/Input buffer drive-register standby-mode
Note Read-Modify-W rite prohibited registers PJCR PJFC.
Figure3.5.28 Register PortJ
92CH21
TMP92CH21
3.5.15
Port (PK0 PK3)
PortK 4-bit output ports. Resetting sets output latch "0", pins output "0". addition functioning output ports, PortK also function output pins controller (LCP0, LLP, LBCD). Above setting used function register PKFC.
Reset Function control basis) Internal data PKFC write Output latch Selecter write LCP0, LLP, LFR, LBCD (LCP0) PK1(LLP) (LFR) (LBCD)
Output buffer
read
Figure3.5.29 Port
Port register
(0050H) Symbol Read/Write After Reset
Port function register
PKFC (0053H) Symbol Read/Write After Reset Function
PK3F
PK2F
PK1F
PK0F
PORT LBCD
PORT
PORT
PORT LCP0
Port Drive register
PKDR (0094H)
Symbol Read/Write After reset Function
PK3D
PK2D
PK1D
PK0D
Output/Input buffer drive-register standby-mode
Note Read-Modify-Write prohibited registers PKFC.
Figure3.5.31 Register Port
92CH21
TMP92CH21
3.5.16
Port (PL0 PL7)
4-bit output ports. Resetting sets output latch "0", pins output "0". 4-bit general-purpose ports. Each individually input output using control register PLCR. Resetting, control register PLCR sets input ports. addition functioning general-purpose port, Port also function data controller (LD0 LD7). Above setting used function register PLFC.
Reset Function control basis) Internal data PLFC write Output latch write read
(LD0 LD3)
Selector
Figure3.5.32 Register Port
Reset Direction control basis) PLCR write Function control basis) PLFC write Output latch write
Internal data
(LD4 LD7)
Selector
Selector read
Figure3.5.33 Register Port
92CH21
TMP92CH21
Port register
(0054H) Symbol Read/Write After Reset
Port Control Register
PLCR (0056H) Symbol Read/Write After Reset Function PL7C
PL6C
PL5C
PL4C
Port Function Register
PLFC (0057H) Symbol Read/Write After Reset Function PL7F
PL6F
PL5F
PL4F
PL3F
PL2F
PL1F
PL0F
Port
data LCDC (LD7 LD0)
Port Drive register
PLDR (0095H)
Symbol Read/Write After reset Function
PL6D
PL5D
PL4D
PL3D
PL2D
PL1D
PL0D
PL7D
Output/Input buffer drive-register standby-mode
Note Read-Modify-Write prohibited registers PLCR PLFC.
Figure3.5.33 Port register
92CH21
TMP92CH21
3.5.17
Port M(PM1 PM2)
2-bit output ports. Resetting sets output latch "1", pins output "1". addition functioning ports, PortM also function output pins alarm (/ALARM) output melody/alarm generator (MLDALM, /MLDALM). Above setting used function register PMFC. Only output function which /ALARM /MLDALM. This selection used PM<PM2>.
Reset Function control basis) PMFC write Output latch
Internal data
Selecter (MLDALM)
write read MLDALM
Figure3.5.35 Port
Reset Function control basis) PMFC write Output latch
Internal data
Selecter (/ALARM, /MLDALM)
write read /MLDALM /ALARM Selecter
Figure3.5.36 Port
92CH21
TMP92CH21
Port register
(0058H) Symbol Read/Write After Reset
Port function register
PMFC (005BH) Symbol Read/Write After Reset
PM2F
PORT
PM1F
port MLDALM
Function
/ALARM <PM2>="1" /MLDALM at<PM2>="0"
Port Drive register
PMDR (0096H)
Symbol Read/Write After reset
PM2D
PM1D
Output/Input buffer
Function
drive-register standby-mode
Note Read-Modify-Write prohibited registers PMFC.
Figure3.5.31 Register Port
92CH21
TMP92CH21
Memory Controller
3.6.1 Functions TMP92CH21 memory controller with variable 4-block address area that controls follows. 4-block address area support Specifies start address block size 4-block address area(block0 SRAM SDRAM Page-ROM NAND-Flash CS-blocks(CS0 CS3) supported. Only either CS2-blocks supported. Only CS2-blocks supported. recommended NAND-Flash(ND0/1FDTR, 001D00H-001EFFH), built-in LCD-driver(001FE0H-001FEFH) (About NAND Flash area, refer 3.6.6(2) Connecting memory specifications Specifies SRAM,ROM,SDRAM memories connect with selected address areas. Data width selection Whether 8-bit, 16bit 32bit selected data width respective block address areas. Wait control Wait specification control register WAIT input control number waits external cycle. Read cycle write cycle specify number waits individually. number waits controlled mode mentioned below. wait, 1wait, wait, wait, 4wait wait(controls with /WAIT pin) 3.6.2 Control register Operation after reset release This section describes registers control memory controller, state after reset release necessary settings. Control Register control registers memory controller follows Table3.6(1),(2) Control register: BnCSH/BnCSL(n=0 Sets basic functions memory controller, that connecting memory type, number waits read written. Memory start address register: MSARn(n=0 Sets start address selected address areas. Memory address mask register: MAMR(n=0 Sets block size selected address areas. Page control register: PMEMCR Sets access Page-ROM. Internal-Boot control register: BROMCR Sets access Boot-ROM.
92CH21-93
TMP92CH21
Table 3.6(1) Control Register
B0CS ead/W rite After B0CSH ead/W rite After ead/W rite After MSAR ead/W rite After B1CS ead/W rite After B1CSH ead/W rite After ead/W rite After MSAR ead/W rite After B2CS ead/W rite After B2CSH ead/W rite After ead/W rite After MSAR ead/W rite After B3CS ead/W rite After B3CSH ead/W rite After MSAR ead/W rite After ead/W rite After M3S20
ote)
(Note)
ote)
ote)
B0REC
(Note)
M0V16 M0S19 M1V17 M1S19 M2V18 M2S19 M3V18 M3S19
M0V15 M0S18 M1V16 M1S18 M2V17 M2S18 M3V17 M3S18
B0BU 4-V9 M0S17 B1BU 5-V9 M1S17 B2BU M2V16 M2S17 B3BU M3V16 M3S17
B0BU M0S16 B1BU M1S16 B2BU M2V15 M2S16 B3BU M3V15 M3S16
ote)
M0V17 M0S20 B1REC
(Note)
ote)
M1V18 M1S20 B2REC
(Note)
ote)
M2V19 M2S20 B3REC
(Note)
M3V19
Note: "0".
92CH21-94
TMP92CH21
Table 3.6(2) Control Register
B0CSSH BEXC ead/W rite After B0CSH BEXC ead/W rite After ead/W rite After
XBUS
XBUS
ead/W rite After
Operation after reset release start data width determined depending state AM1/AM0 pins just after reset release. Then, external memory accessed follows Start mode Don't this setting Start with 16-bit data (note) Start with 32-bit data (note)
Start with BOOT(32-bit internal-MROM
(note) memory used starting after reset either NOR-Flash, Masked-ROM. NAND-Flash SDRAM can't used.
AM1/AM0 pins valid only just after reset release. other cases, data width value BnBUS control register. reset, only control register (B2CSH/B2CSL) block address area automatically effective (B2CSH<B2E> reset) data width which specified AM1/AM0 loaded specify width control register block address area block address area address 000000H FFFFFFH reset( B2CSH<B2M> reset "0") After reset release, block address areas specified memory start address register(MSARn) memory address mask register(MAMRn). Then control register (BnCS) set. enable bit(BnE) control register enable setting.
92CH21-95
TMP92CH21
3.6.3 Basic functions register setting
this section, setting block address area, connecting memory number waits memory controller's functions described. Block address area specification block address area specified registers. memory start address register(MSARn) sets start address block address areas. memory controller compares between register value address every cycles. address which masked memory address mask register(MAMRn) compared memory controller. block address area size determined setting memory address mask register. value register compared with block address area bus. compared result match, memory controller sets chip select signal(CSn) "Low". Setting memory start address register MS23 bits memory start address register respectively correspond with addresses A16. lower start address always address 0000H. Therefore start address block address area addresses 000000H FF0000H every bytes. (ii) Setting memory address mask registers memory address mask register sets whether address compared not. register compare, compare. address depended block address area. Block address area Block address area Block address area above-mentioned bits always compared. block address area size determined compared result. size depending block address area follows.
Size (bytes) area
Note: After reset release, only control register block address area valid. control register block address area <B2M> bit. Setting <B2M> sets block address area addresses 000000H FFFFFFH. Setting <B2M> specifies start address address area size other block address area
92CH21-96
TMP92CH21
(iii
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