TMP100 TMP101
|
|
|
Top Searches for this datasheet
T0 R0 SOT23 - T0 R0 SOT23
marking t9 sot-23 - marking t9 sot-23
H7 RF - H7 RF
H6 SOT23-6 - H6 SOT23-6
TMP100 - TMP100
TMP101 - TMP101
TMP100 TMP101
SBOS231G JANUARY 2002 REVISED NOVEMBER 2007
Digital Temperature Sensor with I2Ct Interface
DIGITAL OUTPUT: Serial 2-Wire RESOLUTION: 12-Bits, User-Selectable ACCURACY:
±2.0°C from -25°C +85°C (max) ±3.0°C from -55°C +125°C (max) QUIESCENT CURRENT: 45µA, 0.1µA Standby WIDE SUPPLY RANGE: 2.7V 5.5V TINY SOT23-6 PACKAGE
DESCRIPTION
TMP100 TMP101 two-wire, serial output temperature sensors available SOT23-6 packages. Requiring external components, TMP100 TMP101 capable reading temperatures with resolution 0.0625°C. TMP100 TMP101 feature SMBus interface compatibility, with TMP100 allowing eight devices bus. TMP101 offers SMBus alert function with three devices bus. TMP100 TMP101 ideal extended temperature measurement variety communication, computer, consumer, environmental, industrial, instrumentation applications. TMP100 TMP101 specified operation over temperature range -55°C +125°C.
APPLICATIONS
POWER-SUPPLY TEMPERATURE COMPUTER PERIPHERAL THERMAL
PROTECTION NOTEBOOK COMPUTERS CELL PHONES BATTERY MANAGEMENT OFFICE MACHINES THERMOSTAT CONTROLS ENVIRONMENTAL MONITORING HVAC ELECTROMECHANICAL DEVICE TEMPERATURE MONITORING
Temperature Diode Temp. Sensor Control Logic
Temperature Diode Temp. Sensor Control Logic
Converter
Serial Interface
ADD0
Converter
Serial Interface
ADD0
ADD1
Config Temp Register
ALERT
Config Temp Register
TMP100
TMP101
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. trademark Semiconductors. other trademarks property their respective owners.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2002-2007, Texas Instruments Incorporated
www.ti.com
TMP100 TMP101
www.ti.com SBOS231G JANUARY 2002 REVISED NOVEMBER 2007
ABSOLUTE MAXIMUM RATINGS(1)
Power Supply, 7.5V Input Voltage(2) -0.5V 7.5V Operating Temperature Range -55°C +125°C Storage Temperature Range -60°C +150°C Junction Temperature max) +150°C Rating, Human Body Model 2000V Machine Model 200V Stresses above these ratings cause permanent damage. Exposure absolute maximum conditions extended periods degrade device reliability. These stress ratings only, functional operation device these other conditions beyond those specified supported. Input voltage rating applies TMP100 TMP101 input voltages.
This integrated circuit damaged ESD. Texas Instruments recommends that integrated circuits handled with appropriate precautions. Failure observe proper handling installation procedures cause damage. damage range from subtle performance degradation complete device failure. Precision integrated circuits more susceptible damage because very small parametric changes could cause device meet published specifications.
ORDERING INFORMATION(1)
PRODUCT TMP100 PACKAGE-LEAD SOT23-6 PACKAGE DESIGNATOR PACKAGE MARKING T100
TMP101 SOT23-6 T101 most current package ordering information, Package Option Addendum this document, site www.ti.com.
CONFIGURATION
View SOT23 View SOT23
T100
TMP100
T101
ADD1
ADD0
ALERT
ADD0
TMP101
TMP100 TMP101
www.ti.com SBOS231G JANUARY 2002 REVISED NOVEMBER 2007
ELECTRICAL CHARACTERISTICS
-55°C +125°C 2.7V 5.5V, unless otherwise noted. TMP100, TMP101 PARAMETER TEMPERATURE INPUT Range Accuracy (temperature error) Resolution DIGITAL INPUT/OUTPUT Input Logic Levels: Input Current, Output Logic Levels: ALERT Resolution Conversion Time Selectable 9-Bit 10-Bit 11-Bit 12-Bit Conversion Rate 9-Bit 10-Bit 11-Bit 12-Bit POWER SUPPLY Operating Range Quiescent Current Serial Inactive Serial Active, Frequency 400kHz Serial Active, Frequency 3.4MHz Shutdown Current Serial Inactive Serial Active, Frequency 400kHz Serial Active, Frequency 3.4MHz TEMPERATURE RANGE Specified Range Storage Range Thermal Resistance SOT23-6 Surface-Mount +125 +150 °C/W 0.15 0.15 Bits 0.7(V+) -0.5 0.3(V+) -25°C +85°C -55°C +125°C Selectable ±0.5 ±1.0 ±0.0625 +125 ±2.0 ±3.0 TEST CONDITIONS UNIT
TMP100 TMP101
www.ti.com SBOS231G JANUARY 2002 REVISED NOVEMBER 2007
TYPICAL CHARACTERISTICS
+25°C 5.0V, unless otherwise noted.
QUIESCENT CURRENT TEMPERATURE (µA) (µA) 2.7V Serial Inactive Temperature CONVERSION TIME TEMPERATURE Temperature Error (_C) Conversion Time (ms) -0.5 -1.0 -1.5 NOTE: 12-bit resolution. Temperature Typical Units -2.0 NOTE: 12-bit resolution. -0.1 SHUTDOWN CURRENT TEMPERATURE
Temperature TEMPERATURE ACCURACY TEMPERATURE
2.7V
Temperature
QUIESCENT CURRENT WITH ACTIVITY TEMPERATURE (µA) 100k Frequency (Hz) -55_ FAST MODE MODE 125_ 25_C -55_ 125_C
TMP100 TMP101
www.ti.com SBOS231G JANUARY 2002 REVISED NOVEMBER 2007
APPLICATIONS INFORMATION
TMP100 TMP101 digital temperature sensors optimal thermal management thermal protection applications. TMP100 TMP101 SMBus interface-compatible specified over temperature range -55°C +125°C. TMP100 TMP101 require external components operation except pull-up resistors SCL, SDA, ALERT, although 0.1µF bypass capacitor recommended, shown Figure Figure
maintain accuracy applications requiring surface temperature measurement, care should taken isolate package leads from ambient temperature. thermally-conductive adhesive will assist achieving accurate surface temperature measurement.
POINTER REGISTER
Figure shows internal register structure TMP100 TMP101. 8-bit Pointer Register TMP100 TMP101 used address given data register. Pointer Register uses LSBs identify which data registers should respond read write command. Table identifies bits Pointer Register byte. Table describes pointer address registers available TMP100 TMP101. Power-up Reset value P1/P0
0.1µF Controller TMP101 NOTE: SCL, ALERT require pull-up resistors applications. ADD0 (Input) Temperature Register ALERT (Output) Pointer Register
Configuration Register
Control Interface
Figure Typical Connections TMP101
TLOW Register
THIGH Register 0.1µF ADD1 (Input) ADD0 (Input)
Controller TMP100
Figure Internal Register Structure TMP100 TMP101 Table Pointer Register Type
Register Bits
NOTE: require pull-up resistors applications.
Table Pointer Addresses TMP100 TMP101 Registers
REGISTER Temperature Register (READ Only) Configuration Register (READ/WRITE) TLOW Register (READ/WRITE) THIGH Register (READ/WRITE)
Figure Typical Connections TMP100
flag lead frame connected sensing device TMP100 TMP101 chip itself. Thermal paths through package leads well plastic package. lower thermal resistance metal causes leads provide primary thermal path. TMP100 TMP101 directly connected metal lead frame, best choice thermal input.
TEMPERATURE REGISTER
Temperature Register TMP100 TMP101 12-bit read-only register that stores output most recent conversion. bytes must read obtain data described Table Table first bits used indicate temperature with remaining bits
TMP100 TMP101
www.ti.com SBOS231G JANUARY 2002 REVISED NOVEMBER 2007
equal zero. Data format temperature summarized Table Following power-up reset, Temperature Register will read until first conversion complete.
device will shutdown once current conversion completed. equal device will maintain continuous conversion.
Table Byte Temperature Register
THERMOSTAT MODE (TM)
Thermostat Mode TMP101 indicates device whether operate Comparator Mode Interrupt Mode more information comparator interrupt modes, HIGH Limit Registers section.
Table Byte Temperature Register
POLARITY (POL)
Polarity TMP101 allows user adjust polarity ALERT output. ALERT will active LOW, shown Figure ALERT will active HIGH, state ALERT inverted.
Table Temperature Data Format
TEMPERATURE (°C) 127.9375 0.25 -0.25 -128 DIGITAL OUTPUT (BINARY) 0111 1111 1111 0111 1111 1111 0110 0100 0000 0101 0000 0000 0100 1011 0000 0011 0010 0000 0001 1001 0000 0000 0000 0100 0000 0000 0000 1111 1111 1100 1110 0111 0000 1100 1001 0000 1000 0000 0000
Measured Temperature
THIGH
TLOW
TMP101 ALERT (Comparator Mode) TMP101 ALERT (Interrupt Mode) TMP101 ALERT (Comparator Mode) TMP101 ALERT (Interrupt Mode)
user obtain bits resolution addressing Configuration Register setting resolution bits accordingly. 10-, 11-bit resolution, most significant bits Temperature Register used with unused LSBs zero.
CONFIGURATION REGISTER
Configuration Register 8-bit read/write register used store bits that control operational modes temperature sensor. Read/write operations performed first. format Configuration Register TMP100 TMP101 shown Table followed breakdown register bits. power-up/reset value Configuration Register bits equal OS/ALERT will read after power-up/reset.
Read
Read Time
Read
Figure Output Transfer Function Diagrams
FAULT QUEUE (F1/F0)
fault condition occurs when measured temperature exceeds user-defined limits THIGH TLOW Registers. Additionally, number fault conditions required generate alert programmed using Fault Queue. Fault Queue provided prevent false alert environmental noise. Fault Queue requires consecutive fault measurements order trigger alert function. temperature falls below TLOW, prior reaching number programmed consecutive faults limit, count reset Table defines number measured faults that programmed trigger alert condition device.
Table Configuration Register Format
BYTE OS/ALERT
SHUTDOWN MODE (SD)
Shutdown Mode TMP100 TMP101 allows user save maximum power shutting down device circuitry other than serial interface, which reduces current consumption less than 1µA. TMP100 TMP101, Shutdown Mode enabled when
TMP100 TMP101
www.ti.com SBOS231G JANUARY 2002 REVISED NOVEMBER 2007
Table Fault Settings TMP100 TMP101
CONSECUTIVE FAULTS
CONVERTER RESOLUTION (R1/R0)
Converter Resolution Bits control resolution internal Analog-to-Digital (A/D) converter. This allows user maximize efficiency programming higher resolution faster conversion time. Table identifies Resolution Bits relationship between resolution conversion time.
Table Resolution TMP100 TMP101
RESOLUTION Bits (0.5°C) Bits (0.25°C) Bits (0.125°C) Bits (0.0625°C) CONVERSION TIME (typical) 40ms 80ms 160ms 320ms
Interrupt Mode ALERT becomes active when temperature equals exceeds THIGH consecutive number fault conditions. ALERT remains active until read operation register occurs device successfully responds SMBus Alert Response Address. ALERT will also cleared device placed Shutdown Mode. Once ALERT cleared, will only become active again temperature falling below TLOW. When temperature falls below TLOW, ALERT will become active remain active until cleared read operation register successful response SMBus Alert Response Address. Once ALERT cleared, above cycle will repeat with ALERT becoming active when temperature equals exceeds THIGH. ALERT also cleared resetting device with General Call Reset command. This will also clear state internal registers device returning device Comparator Mode Both operational modes represented Figure Table Table describe format THIGH TLOW registers. Power-up Reset values THIGH TLOW are: THIGH 80°C TLOW 75°C. format data THIGH TLOW same Temperature Register.
OS/ALERT (OS)
TMP100 TMP101 feature One-Shot Temperature Measurement Mode. When device Shutdown Mode, writing OS/ALERT will start single temperature conversion. device will return shutdown state completion single conversion. This useful reduce power consumption TMP100 TMP101 when continuous monitoring temperature required. Reading OS/ALERT will provide information about Comparator Mode status. state will invert polarity data returned from OS/ALERT bit. OS/ALERT will read until temperature equals exceeds THIGH programmed number consecutive faults, causing OS/ALERT read OS/ALERT will continue read until temperature falls below TLOW programmed number consecutive faults when will again read status does affect status OS/ALERT bit.
Table Bytes THIGH Register
BYTE BYTE
Table Bytes TLOW Register
BYTE BYTE
bits Temperature, THIGH, TLOW registers used comparisons ALERT function converter resolutions. three LSBs THIGH TLOW affect ALERT output even converter configured 9-bit resolution.
SERIAL INTERFACE HIGH LIMIT REGISTERS
Comparator Mode ALERT TMP101 becomes active when temperature equals exceeds value THIGH generates consecutive number faults according fault bits ALERT will remain active until temperature falls below indicated TLOW value same number faults. TMP100 TMP101 operate only slave devices SMBus. Connections made open-drain lines SCL. TMP100 TMP101 support transmission protocol fast 400kHz) high-speed 3.4MHz) modes. data bytes transmitted most significant first.
TMP100 TMP101
www.ti.com SBOS231G JANUARY 2002 REVISED NOVEMBER 2007
SERIAL ADDRESS
program TMP100 TMP101, master must first address slave devices slave address byte. slave address byte consists seven address bits, direction indicating intent executing read write operation. TMP100 features address pins allow eight devices addressed single interface. Table describes logic levels used properly connect eight devices. Float indicates left unconnected. state pins ADD0 ADD1 sampled first communication should prior activity interface.
Data transfer then initiated sent over eight clock pulses followed Acknowledge Bit. During data transfer must remain stable while HIGH, change while HIGH will interpreted control signal. Once data have been transferred, master generates STOP condition indicated pulling from HIGH, while HIGH.
WRITING/READING TMP100 TMP101
Accessing particular register TMP100 TMP101 accomplished writing appropriate value Pointer Register. value Pointer Register first byte transferred after slave address byte with LOW. Every write operation TMP100 TMP101 requires value Pointer Register. (Refer Figure When reading from TMP100 TMP101, last value stored Pointer Register write operation used determine which register read read operation. change register pointer read operation, value must written Pointer Register. This accomplished issuing slave address byte with LOW, followed Pointer Register Byte. additional data required. master then generate START condition send slave address byte with HIGH initiate read command. Figure details this sequence. repeated reads from same register desired, necessary continually send Pointer Register bytes TMP100 TMP101 will remember Pointer Register value until changed next write operation.
Table Address Pins Slave Addresses TMP100
ADD1 Float Float ADD0 Float Float SLAVE ADDRESS 1001000 1001001 1001010 1001100 1001101 1001110 1001011 1001111
TMP101 features address ALERT pin, allowing three devices connected bus. logic levels described Table address pins TMP100 TMP101 read after reset response address acquire request. Following reading, state address pins latched minimize power dissipation associated with detection.
Table Address Pins Slave Addresses TMP101
ADD0 Float SLAVE ADDRESS 1001000 1001001 1001010
SLAVE MODE OPERATIONS
TMP100 TMP101 operate slave receivers slave transmitters.
Slave Receiver Mode:
first byte transmitted master slave address, with LOW. TMP100 TMP101 then acknowledges reception valid address. next byte transmitted master Pointer Register. TMP100 TMP101 then acknowledges reception Pointer Register byte. next byte bytes written register addressed Pointer Register. TMP100 TMP101 will acknowledge reception each data byte. master terminate data transfer generating START STOP condition.
OVERVIEW
device that initiates transfer called master, devices controlled master slaves. must controlled master device that generates serial clock (SCL), controls access, generates START STOP conditions. address specific device, START condition initiated, indicated pulling data-line (SDA) from HIGH logic level while HIGH. slaves shift slave address byte, with last indicating whether read write operation intended. During ninth clock pulse, slave being addressed responds master generating Acknowledge pulling LOW.
Slave Transmitter Mode:
first byte transmitted master slave address, with HIGH. slave acknowledges reception valid slave address. next byte transmitted slave most significant byte register indicated Pointer Register. master
TMP100 TMP101
www.ti.com SBOS231G JANUARY 2002 REVISED NOVEMBER 2007
acknowledges reception data byte. next byte transmitted slave least significant byte. master acknowledges reception data byte. master terminate data transfer generating Not-Acknowledge reception data byte, generating START STOP condition.
GENERAL CALL
TMP100 TMP101 respond General Call address (0000000) eighth device will acknowledge General Call address respond commands second byte. second byte 00000100, TMP100 TMP101 will latch status their address pins, will reset. second byte 00000110, TMP100 TMP101 will latch status their address pins reset their internal registers.
SMBus ALERT FUNCTION
TMP101 supports SMBus Alert function. When TMP101 operating Interrupt Mode ALERT TMP101 connected SMBus Alert signal. When master senses that ALERT condition present ALERT line, master sends SMBus Alert command (00011001) bus. ALERT TMP101 active, TMP101 will acknowledge SMBus Alert command respond returning slave address line. eighth (LSB) slave address byte will indicate temperature exceeding THIGH falling below TLOW caused ALERT condition. this will temperature greater than equal THIGH. This will HIGH temperature less than TLOW. polarity this will inverted Refer Figure details this sequence. multiple devices respond SMBus Alert command, arbitration during slave address portion SMBus alert command will determine which device will clear ALERT status. TMP101 wins arbitration, ALERT will become inactive completion SMBus Alert command. TMP101 loses arbitration, ALERT will remain active. TMP100 will also respond SMBus ALERT command Since does have ALERT pin, master needs periodically poll device issuing SMBus Alert command. TMP100 generated ALERT, will acknowledge SMBus Alert command return slave address next byte.
(POWER-ON RESET)
TMP100 TMP101 both have on-chip power-on reset circuits that reset device default settings when device powered This circuit activates when power supply less than 0.3V more than 100ms. TMP100 TMP101 powered down removing supply voltage from device, supply voltage assured less than 0.3V, recommended issue General Call reset command interface ensure that TMP100 TMP101 completely reset.
HIGH-SPEED MODE
order operate frequencies above 400kHz, master device must issue Hs-mode master code (00001XXX) first byte after START condition switch high-speed operation. TMP100 TMP101 will acknowledge this byte required specification, will switch their input filters their output filters operate Hs-mode, allowing transfers 3.4MHz. After Hs-mode master code been issued, master will transmit slave address initiate data transfer operation. will continue operate Hs-mode until STOP condition occurs bus. Upon receiving STOP condition, TMP100 TMP101 will switch their input output filters back fast-mode operation.
TMP100 TMP101
www.ti.com SBOS231G JANUARY 2002 REVISED NOVEMBER 2007
TIMING DIAGRAMS
TMP100 TMP101 SMBus compatible. Figure Figure describe various operations TMP100 TMP101. definitions given below. Parameters Figure defined Table Idle: Both lines remain HIGH. Start Data Transfer: change state line, from HIGH LOW, while line HIGH, defines START condition. Each data transfer initiated with START condition. Stop Data Transfer: change state line from HIGH while line HIGH defines STOP condition. Each data transfer terminated with repeated START STOP condition.
Data Transfer: number data bytes transferred between START STOP condition limited determined master device. receiver acknowledges transfer data. Acknowledge: Each receiving device, when addressed, obliged generate Acknowledge bit. device that acknowledges must pull down line during Acknowledge clock pulse such that line stable during HIGH period Acknowledge clock pulse. Setup hold times must taken into account. master receive, termination data transfer signaled master generating Not-Acknowledge last byte that been transmitted slave.
Table Timing Diagram Definitions
FAST MODE PARAMETER SCLK Operating Frequency Free TIme Between STOP START Conditions Hold time after repeated START condition. After this period, first clock generated. Repeated START Condition Setup Time STOP Condition Setup Time Data HOLD Time Data Setup Time SCLK Clock Period SCLK Clock HIGH Period Clock/Data Fall Time Clock/Data Rise Time SCLK 100kHz f(SCLK) t(BUF) t(HDSTA) t(SUSTA) t(SUSTO) t(HDDAT) t(SUDAT) t(LOW) t(HIGH) 1300 1000 HIGH-SPEED MODE UNITS
TMP100 TMP101
www.ti.com SBOS231G JANUARY 2002 REVISED NOVEMBER 2007
TIMING DIAGRAMS
t(LOW)
(HDSTA)
(HDSTA) t(HDDAT)
t(BUF
t(HIGH)
(SUSTA) (SUDAT)
(SUSTO)
Figure Timing Diagram
Start Master
TMP100 TMP101 Frame Slave Address Byte
TMP100 TMP101 Frame Pointer Register Byte
(Continued)
(Continued)
TMP100 TMP101 Frame Data Byte Frame Data Byte
Stop TMP100 TMP101 Master
Figure Timing Diagram Write Word Format
TMP100 TMP101
www.ti.com SBOS231G JANUARY 2002 REVISED NOVEMBER 2007
Start Master
TMP100 TMP101 Frame Slave Address Byte
TMP100 TMP101 Frame Pointer Register Byte
(Continued)
Master
(Continued) Start Master
TMP100 TMP101 Frame Slave Address Byte
From TMP100 TMP101 Frame Data Byte Read Register
(Continued)
(Continued)
Master Stop Master
From TMP100 TMP101 Frame Data Byte Read Register
Figure Timing Diagram Read Word Format
ALERT
Start Master
TMP100 TMP101 Frame SMBus ALERT Response Address Byte
From NACK TMP100 TMP101 Master Frame Slave Address From TMP100
Stop Master
Figure Timing Diagram SMBus ALERT
PACKAGE OPTION ADDENDUM
www.ti.com
6-Nov-2007
PACKAGING INFORMATION
Orderable Device SN0312100DBVR TMP100NA/250 TMP100NA/250G4 TMP100NA/3K TMP100NA/3KG4 TMP101NA/250 TMP101NA/250G4 TMP101NA/3K TMP101NA/3KG4
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SOT-23 SOT-23 SOT-23 SOT-23 SOT-23 SOT-23 SOT-23 SOT-23 SOT-23
Package Drawing
Pins Package Plan 3000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR Level-2-260C-1 YEAR
3000 Green (RoHS Sb/Br) 3000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
3000 Green (RoHS Sb/Br) 3000 Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE REEL INFORMATION
*All dimensions nominal
Device
Package Package Pins Type Drawing SOT-23 SOT-23 SOT-23 SOT-23
Reel Reel Diameter Width (mm) (mm) 180.0 180.0 180.0 180.0
(mm)
(mm)
(mm)
(mm)
Pin1 (mm) Quadrant
TMP100NA/250 TMP100NA/3K TMP101NA/250 TMP101NA/3K
3000 3000
1.39 1.39 1.39 1.39
Pack Materials-Page
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions nominal
Device TMP100NA/250 TMP100NA/3K TMP101NA/250 TMP101NA/3K
Package Type SOT-23 SOT-23 SOT-23 SOT-23
Package Drawing
Pins
3000 3000
Length (mm) 190.5 184.0 190.5 184.0
Width (mm) 212.7 184.0 212.7 184.0
Height (mm) 31.8 50.0 31.8 50.0
Pack Materials-Page
IMPORTANT NOTICE
Texas Instruments Incorporated subsidiaries (TI) reserve right make corrections, modifications, enhancements, improvements, other changes products services time discontinue product service without notice. Customers should obtain latest relevant information before placing orders should verify that such information current complete. products sold subject TI's terms conditions sale supplied time order acknowledgment. warrants performance hardware products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques used extent deems necessary support this warranty. Except where mandated government requirements, testing parameters each product necessarily performed. assumes liability applications assistance customer product design. Customers responsible their products applications using components. minimize risks associated with customer products applications, customers should provide adequate design operating safeguards. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right relating combination, machine, process which products services used. Information published regarding third-party products services does constitute license from such products services warranty endorsement thereof. such information require license from third party under patents other intellectual property third party, license from under patents other intellectual property Reproduction information data books data sheets permissible only reproduction without alteration accompanied associated warranties, conditions, limitations, notices. Reproduction this information with alteration unfair deceptive business practice. responsible liable such altered documentation. Information third parties subject additional restrictions. Resale products services with statements different from beyond parameters stated that product service voids express implied warranties associated product service unfair deceptive business practice. responsible liable such statements. products authorized safety-critical applications (such life support) where failure product would reasonably expected cause severe personal injury death, unless officers parties have executed agreement specifically governing such use. Buyers represent that they have necessary expertise safety regulatory ramifications their applications, acknowledge agree that they solely responsible legal, regulatory safety-related requirements concerning their products products such safety-critical applications, notwithstanding applications-related information support that provided Further, Buyers must fully indemnify representatives against damages arising products such safety-critical applications. products neither designed intended military/aerospace applications environments unless products specifically designated military-grade "enhanced plastic." Only products designated military-grade meet military specifications. Buyers acknowledge agree that such products which designated military-grade solely Buyer's risk, that they solely responsible compliance with legal regulatory requirements connection with such use. products neither designed intended automotive applications environments unless specific products designated compliant with ISO/TS 16949 requirements. Buyers acknowledge agree that, they non-designated products automotive applications, will responsible failure meet such requirements. Following URLs where obtain information other Texas Instruments products application solutions: Products Amplifiers Data Converters Clocks Timers Interface Logic Power Mgmt Microcontrollers RFID RF/IF ZigBee® Solutions amplifier.ti.com dataconverter.ti.com dsp.ti.com www.ti.com/clocks interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com www.ti-rfid.com www.ti.com/lprf Applications Audio Automotive Broadband Digital Control Medical Military Optical Networking Security Telephony Video Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/medical www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office 655303, Dallas, Texas 75265 Copyright 2008, Texas Instruments Incorporated
Other recent searches
SN74AHC573 - SN74AHC573 SN74AHC573 Datasheet
SN54AHC573 - SN54AHC573 SN54AHC573 Datasheet
SF10G41A - SF10G41A SF10G41A Datasheet
SF10J41A - SF10J41A SF10J41A Datasheet
PLP2020-8 - PLP2020-8 PLP2020-8 Datasheet
MBD201 - MBD201 MBD201 Datasheet
MBD301 - MBD301 MBD301 Datasheet
2SA1177 - 2SA1177 2SA1177 Datasheet
2N7370 - 2N7370 2N7370 Datasheet
1758102 - 1758102 1758102 Datasheet
Privacy Policy | Disclaimer
© 2013 Datasheets.org.uk