TC1767
|
|
|
Top Searches for this datasheet
TC1767* - TC1767*
SAK-TC1767-256F80HL Ad - SAK-TC1767-256F80HL Ad
SAK-TC1767-256F80HL - SAK-TC1767-256F80HL
in34 - in34
in24 - in24
DSP DTS - DSP DTS
1/TC1767* - 1/TC1767*
TC1767 - TC1767
32-Bit TC1767
32-Bit Single-Chip Microcontroller
V1.2 2009-05
Microcontrollers
Edition 2009-05 Published Infineon Technologies 81726 Munich, Germany
2009 Infineon Technologies
Rights Reserved. Legal Disclaimer information given this document shall event regarded guarantee conditions characteristics. With respect examples hints given herein, typical values stated herein and/or information regarding application device, Infineon Technologies hereby disclaims warranties liabilities kind, including without limitation, warranties non-infringement intellectual property rights third party. Information further information technology, delivery terms conditions prices, please contact nearest Infineon Technologies Office (www.infineon.com). Warnings technical requirements, components contain dangerous substances. information types question, please contact nearest Infineon Technologies Office. Infineon Technologies components used life-support devices systems only with express written approval Infineon Technologies, failure such components reasonably expected cause failure that life-support device system affect safety effectiveness that device system. Life support devices systems intended implanted human body support and/or maintain sustain and/or protect human life. they fail, reasonable assume that health user other persons endangered.
32-Bit TC1767
32-Bit Single-Chip Microcontroller
V1.2 2009-05
Microcontrollers
TC1767
TC1767 Data Sheet Revision History: V1.2, 2009-05 Previous Version: V1.1 Page Trademarks TriCore® trademark Infineon Technologies Listen Your Comments information within this document that feel wrong, unclear missing all? Your feedback will help continuously improve quality this document. Please send your proposal (including reference this document) mcdocu.comments@infineon.com Subjects (major changes since last revision) Typo TTCAN-related text deleted from MultiCAN features. Description added derivatives TC1767. Text which describes endurance PFlash DFlash enhanced. text Data Access Overlay section enhanced. Input spike-filter info added PORST. footnote added VDDMF spike-filters parameters included, tSF1, tSF2. maximum limit IOZ1 updated. Footnote regarding switch capacitance analog input updated. temperature sensor measurement time parameter added. condition HWCFG deleted from hold time from PORST rising edge. power, pad, reset timing figure updated. notes under section updated.
V1.2, 2009-05
TC1767
Table Contents
Table Contents
2.1.1 2.1.2 2.1.3 2.1.4 2.1.5 2.2.1 2.2.2 2.2.3 2.2.3.1 2.2.3.2 2.3.1 2.3.2 2.3.3 2.3.4 2.3.4.1 2.3.4.2 2.3.4.3 2.3.4.4 2.3.4.5 2.3.5 2.3.6 2.3.6.1 2.3.6.2 2.3.6.3 2.3.6.4 2.3.6.5 2.3.7 2.3.8 2.4.1 2.4.2 2.4.3 2.4.4 2.4.5 2.4.6 Summary Features Introduction About this Document Related Documentations Text Conventions Reserved, Undefined, Unimplemented Terminology Register Access Modes Abbreviations Acronyms System Architecture TC1767 TC1767 Block Diagram System Features TC1767 device Chip Cores High-performance 32-bit High-performance 32-bit Peripheral Control Processor Chip System Units Flexible Interrupt System Direct Memory Access Controller System Timer System Control Unit Clock Generation Unit Features Watchdog Timer Reset Operation External Interface Temperature Measurement General Purpose Ports Peripheral Lines Program Memory Unit (PMU) Boot Overlay Data Acquisition Emulation Memory Interface Tuning Protection Program Data Flash Data Access Overlay TC1767 Development Support On-Chip Peripheral Units Asynchronous/Synchronous Serial Interfaces High-Speed Synchronous Serial Interfaces Micro Second Channel Interface MultiCAN Controller Micro Link Interface General Purpose Timer Array (GPTA)
V1.2, 2009-05
TC1767
Table Contents 2.4.6.1 2.4.7 2.4.7.1 2.4.7.2 2.5.1 2.5.2 2.5.3 2.5.4 2.5.5 2.5.6 3.1.1 3.1.2 5.1.1 5.1.2 5.1.3 5.1.4 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 5.3.8 5.3.8.1 5.3.8.2 5.3.8.3 Functionality GPTA0 Analog-to-Digital Converters Block Diagram FADC Short Description On-Chip Debug Support (OCDS) On-Chip Debug Support Real Time Trace Calibration Support Tool Interfaces Self-Test Support Support Pinning TC1767 Definition Functions TC1767 Configuration: PG-LQFP-176-5 Reset Behavior Pins
Identification Registers Electrical Parameters General Parameters Parameter Interpretation Driver Classes Summary Absolute Maximum Ratings Operating Conditions Parameters Input/Output Pins Analog Digital Converters (ADC0/ADC1) Fast Analog Digital Converter (FADC) Oscillator Pins Temperature Sensor Power Supply Current Parameters Testing Waveforms Output Rise/Fall Times Power Sequencing Power, Reset Timing Phase Locked Loop (PLL) JTAG Interface Timing Interface Timing Peripheral Timings Micro Link Interface (MLI) Timing Micro Second Channel (MSC) Interface Timing Master Slave Mode Timing
V1.2, 2009-05
TC1767
Table Contents 5.4.1 5.4.2 5.4.3 5.4.4 Package Reliability Package Parameters Package Outline Flash Memory Parameters Quality Declarations
V1.2, 2009-05
TC1767
Summary Features
Summary Features
High-performance 32-bit super-scalar TriCore V1.3.1 with 4-stage pipeline Superior real-time performance Strong handling Fully integrated capabilities Single precision Floating Point Unit (FPU) operation full temperature range 32-bit Peripheral Control Processor with single cycle instruction (PCP2) Kbyte Parameter Memory (PRAM) Kbyte Code Memory (CMEM) operation full temperature range Multiple on-chip memories Kbyte Data Memory (LDRAM) Kbyte Code Scratchpad Memory (SPRAM) Mbyte Program Flash Memory (PFlash) Kbyte Data Flash Memory (DFlash, represents Kbyte EEPROM) Instruction Cache: Kbyte (ICACHE, configurable) Data Cache: Kbyte (DCACHE, configurable) Kbyte Overlay Memory (OVRAM) Kbyte BootROM (BROM) 8-Channel Controller Sophisticated interrupt system with hardware priority arbitration levels serviced PCP2 High performing on-chip structure 64-bit Local Memory Buses between CPU, Flash Data Memory 32-bit System Peripheral (SPB) on-chip peripheral functional units bridge (LFI Bridge) Versatile On-chip Peripheral Units Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing overrun error detection High-Speed Synchronous Serial Channels (SSC) with programmable data length shift direction serial Micro Second interface (MSC) serial port expansion external power devices High-Speed Micro Link interface (MLI) serial inter-processor communication MultiCAN Module with nodes free assignable message objects high efficiency data handling FIFO buffering gateway data transfer General Purpose Timer Array Modules (GPTA) with additional Local Timer Cell Array (LTCA2) providing powerful digital signal filtering timer functionality realize autonomous complex Input/Output management analog input lines
V1.2, 2009-05
TC1767
Summary Features independent kernels (ADC0, ADC1) Analog supply voltage range from (single supply) Performance resolution (@fADCI MHz) different FADC input channels Extreme fast conversion, cycles fFADC clock (262.5 fFADC MHz) 10-bit conversion (higher resolution achieved averaging consecutive conversions digital data reduction filter) digital general purpose lines (GPIO), input lines Digital ports with capability On-chip debug support OCDS Level (CPU, PCP, DMA, Chip Bus) Dedicated Emulation Device chip available (TC1767ED) multi-core debugging, real time tracing, calibration four/five wire JTAG (IEEE 1149.1) wire (Device Access Port) interface Power Management System Clock Generation Unit with Core supply voltage voltage Full automotive temperature range: -40° +125°C Package variant: PG-LQFP-176-5
V1.2, 2009-05
TC1767
Summary Features Ordering Information ordering code Infineon microcontrollers provides exact reference required product. This ordering code identifies: derivative itself, i.e. function set, temperature range, supply voltage package type delivery.
available ordering codes TC1767 please refer "Product Catalog Microcontrollers", which summarizes available microcontroller variants. This document describes derivatives device.The Table enumerates these derivatives summarizes differences. Table Derivative SAK-TC1767-256F133HL SAK-TC1767-256F80HL TC1767 Derivative Synopsis Ambient Temperature Range -40oC +125oC -40oC +125oC frequency
V1.2, 2009-05
TC1767
Introduction
Introduction
This Data Sheet describes Infineon TC1767, 32-bit microcontroller DSP, based Infineon TriCore Architecture.
About this Document
This document designed read primarily design engineers software engineers need detailed description interactions TC1767 functional units, registers, instructions, exceptions. This TC1767 Data Sheet describes features TC1767 with respect TriCore Architecture. Where TC1767 directly implements TriCore architectural functions, this manual simply refers those functions features TC1767. cases where this manual describes TC1767 feature without referring TriCore Architecture, this means that TC1767 direct implementation TriCore Architecture. Where TC1767 implements subset TriCore architectural features, this manual describes TC1767 implementation, then describes differs from TriCore Architecture. Such differences between TC1767 TriCore Architecture documented section covering each such subject.
2.1.1
Related Documentations
complete description TriCore architecture found document entitled "TriCore Architecture Manual". architecture TC1767 described separately this because configurable nature TriCore specification: Different versions architecture contain different systems components. TriCore architecture, however, remains constant across derivative designs order preserve compatibility. This Data Sheets together with "TriCore Architecture Manual" required understand complete TC1767 micro controller functionality.
2.1.2
Text Conventions
This document uses following text conventions named components TC1767: Functional units TC1767 given plain UPPER CASE. example: "The supports full-duplex half-duplex synchronous communication". Pins using negative logic indicated overline. example: "The external reset pin, ESR0, dual function.". fields bits registers general referenced "Module_Register name.Bit field" "Module_Register name.Bit". example: "The Current Priority Number field CPU_ICR.CCPN cleared". Most
V1.2, 2009-05
TC1767
Introduction register names contain module name prefix, separated underscore character from actual register name (for example, "ASC0_CON", where "ASC0" module name prefix, "CON" kernel register name). chapters describing kernels peripheral modules, registers mainly referenced with their kernel register names. peripheral module implementation sections mainly refer actual register names with module prefixes. Variables used describe sets processing units registers appear mixed upper lower cases. example, register name "MSGCFGn" refers multiple "MSGCFG" registers with variable bounds variables always given where register expression first used (for example, 0-31"), repeated needed rest text. default radix decimal. Hexadecimal constants suffixed with subscript letter "H", 100H. Binary constants suffixed with subscript letter "B", 111B. When extent register fields, groups register bits, groups pins collectively named body document, they represented "NAME[A:B]", which defines range named group from Individual bits, signals, pins given "NAME[C]" where range variable given text. example: CFG[2:0] SRPN[0]. Units abbreviated follows: Megahertz Microseconds kBaud, kbit 1000 characters/bits second MBaud, Mbit 1,000,000 characters/bits second Kbyte, 1024 bytes memory Mbyte, 1048576 bytes memory general, prefix scales unit 1000 whereas prefix scales unit 1024. Hence, Kbyte unit scales expression preceding 1024. kBaud unit scales expression preceding 1000. prefix scales 1,000,000 1048576, scales .000001. example, Kbyte 1024 bytes, Mbyte 1024 1024 bytes, kBaud/kbit 1000 characters/bits second, MBaud/Mbit 1000000 characters/bits second, 1,000,000 Data format quantities defined follows: Byte 8-bit quantity Half-word 16-bit quantity Word 32-bit quantity Double-word 64-bit quantity
V1.2, 2009-05
TC1767
Introduction
2.1.3
Reserved, Undefined, Unimplemented Terminology
tables where register fields defined, following conventions used indicate undefined unimplemented function. Furthermore, types bits fields defined using abbreviations shown Table Table Function Terminology Description Register fields named indicate unimplemented functions with following behavior. Reading these fields returns These fields should written with field defined These fields have written with field defined These fields reserved. detailed description these fields found register descriptions. field read written. field also reset hardware. field only read (read-only). field only written (write-only). read this register will always give default value back. This field modified hardware (read-hardware, typical example: status flags). read this field give actual status this field back. Writing this field effect setting this field. Bits with this attribute "sticky" direction. their reset value once overwritten software, they switched again into their reset state only reset operation. Software cannot switch this type into reset state writing register. This attribute combined "rws" "rwhs". Bits with this attribute readable only when they accessed instruction fetch. Normal data read operations will return other values.
Function Bits Unimplemented, Reserved
2.1.4
Register Access Modes
Read write access registers memory locations sometimes restricted. memory register access tables, terms defined Table used.
V1.2, 2009-05
TC1767
Introduction Table Symbol Access Terms Description Access Mode: Access permitted User Mode Reset Value: Value changed reset operation. Access permitted Supervisor Mode. Read-only register. Only 32-bit word accesses permitted this register/address range. Endinit-protected register/address. Password-protected register/address. change, indicated register changed. Indicates that access this address range generates Error. Indicates that Error generated when accessing this address range, even though either access undefined address access does follow given rules. Indicates that Error generated when accessing this address address range, even though access undefined address address range. True accesses (MTCR/MFCR) undefined addresses CSFR range.
2.1.5
Abbreviations Acronyms
following acronyms terms used this document: AGPR BROM CMEM CISC Analog-to-Digital Converter Address General Purpose Register Arithmetic Logic Unit Asynchronous/Synchronous Serial Controller Control Unit Boot Test Controller Area Network Code Memory Complex Instruction Computing Slave Interface Central Processing Unit
V1.2, 2009-05
TC1767
Introduction CSFR DCACHE DFLASH DGPR FADC GPIO GPTA ICACHE JTAG LBCU LDRAM Context Save Area Core Special Function Register Device Access Port Device Access Server Data Cache Data Flash Memory Data General Purpose Register Direct Memory Access Data Memory Interface External Request Unit Electro-Magnetic Interference Fast Analog-to-Digital Converter Flash Array Module Flash Command State Machine Flash Interface Control Module Flexible Peripheral Interconnect (Bus) Floating Point Unit General Purpose Input/Output General Purpose Register General Purpose Timer Array Instruction Cache Input Output Joint Test Action Group IEEE1149.1 Local Memory Control Unit Local Data Local Memory-to-FPI Interface Local Memory Local Timer Cell Micro Link Interface Memory Management Unit Most Significant Micro Second Channel
V1.2, 2009-05
TC1767
Introduction OCDS OVRAM PFLASH PRAM RISC SBCU SPRAM SRAM SWDT Connect Non-Maskable Interrupt On-Chip Debug Support Overlay Memory Peripheral Control Processor Program Memory Unit Phase Locked Loop Program Flash Memory Program Memory Interface Program Memory Unit Parameter Random Access Memory Reduced Instruction Computing System Peripheral Control Unit System Control Unit Special Function Register System Peripheral Scratch-Pad Static Data Memory Service Request Node Synchronous Serial Controller System Timer Watchdog Timer
V1.2, 2009-05
TC1767
Introduction
System Architecture TC1767
TC1767 combines three powerful technologies within silicon die, achieving levels power, speed, economy embedded applications: Reduced Instruction Computing (RISC) processor architecture Digital Signal Processing (DSP) operations addressing modes On-chip memories peripherals
operations addressing modes provide computational power necessary efficiently analyze complex real-world signals. RISC load/store architecture provides high computational bandwidth with system cost. On-chip memory peripherals designed support even most demanding high-bandwidth real-time embedded control-systems tasks. Additional high-level features TC1767 include: Program Memory Unit instruction memory instruction cache Serial communication interfaces flexible synchronous asynchronous modes Peripheral Control Processor standalone data operations interrupt servicing Controller operations interrupt servicing General-purpose timers High-performance on-chip buses On-chip debugging emulation facilities Flexible interconnections external components Flexible power-management Maximum clock frequency: MHz1) Maximum clock frequency: MHz2) Maximum frequency: MHz3)
TC1767 clock frequencies:
TC1767 high-performance microcontroller with TriCore CPU, program data memories, buses, arbitration, interrupt controller, peripheral control processor, controller several on-chip peripherals. TC1767 designed meet needs most demanding embedded control systems applications where competing issues price/performance, real-time responsiveness, computational power, data bandwidth, power consumption design elements. TC1767 offers several versatile on-chip peripheral units such serial controllers, timer units, Analog-to-Digital converters. Within TC1767, these peripheral units connected TriCore CPU/system Flexible Peripheral Interconnect (FPI) Local Memory (LMB). Several lines TC1767 ports reserved these peripheral units communicate with external world.
frequencies MHz, mode enabled. mode means: fSPB fCPU frequencies MHz, mode enabled. mode means: fSPB fPCP Mode means: fSPB fCPU mode means: fSPB fPCP
V1.2, 2009-05
TC1767
Introduction
2.2.1
TC1767 Block Diagram
Figure shows block diagram TC1767.
Abbreviations: ICACHE: DCACHE SPRAM LDRAM: OVRAM: BROM: PFlash DFlash: PRAM: CMEM: LBCU Local Memory Bus(LMB) PFlash DFlash OVRAM BROM Bridge
SPRAM ICACHE (Configurable
TriCore
LDRAM DCACHE (Configurable)
Instruction Cache Data Cache Scratch-Pad Local Data Overlay Boot Program Flash Data Flash Parameter Code
1,5V, 3.3V Ext. supply
Channels)
OCDS Debug Interface/ JTAG
PRAM FPI-Bus Interface Interrupt System Interrupts
S
Memcheck
PCP2 Core
Ext. supply
ASC0
System Peripheral (SPB)
Ports CMEM ADC0
Channels
ASC1
max)
SBCU
fPLL
SSC0
ADC1
Channels
GTPA0
SSC1 FADC (3.3V) diff (3.3V max)
LTCA2
Ext. Request Unit
Multi
Nodes, uffer)
MSC0
BlockDiagram 1767 LQFP -176
Figure
TC1767 Block Diagram
V1.2, 2009-05
TC1767
Introduction
2.2.2
System Features TC1767 device
TC1767 following features: Packages PG-LQFP-176-5 package, pitch
Clock Frequencies Maximum clock frequency: MHz1) Maximum clock frequency: MHz2) Maximum clock frequency: MHz3)
frequencies MHz, mode enabled. mode means: fSPB fCPU frequencies MHz, mode enabled. mode means: fSPB fPCP Mode means: fSPB fCPU mode means: fSPB fPCP
V1.2, 2009-05
TC1767
Introduction
2.2.3
Chip Cores
TC1767 includes high Performance Peripheral Control Processor.
2.2.3.1
High-performance 32-bit
This chapter gives overview about TriCore architecture. TriCore (TC1.3.1) Architectural Highlights Unified RISC MCU/DSP 32-bit architecture with Gbytes unified data, program, input/output address space Fast automatic context-switching Multiply-accumulate unit Floating point unit Saturating integer arithmetic High-performance on-chip peripheral (FPI Bus) Register based design with multiple variable register banks handling Packed data operations Zero overhead loop Precise exceptions Flexible power management
High-efficiency TriCore Instruction 16/32-bit instructions reduced code size Data types include: Boolean, array bits, character, signed unsigned integer, integer with saturation, signed fraction, double-word integers, IEEE-754 singleprecision floating point Data formats include: Bit, 8-bit byte, 16-bit half-word, 32-bit word, 64-bit doubleword data formats Powerful instruction Flexible efficient addressing mode high code density
Integrated related On-Chip Memories Instruction memory: total. After reset, configured into:1) Kbyte Scratch-Pad (SPRAM) Kbyte Instruction Cache (ICACHE) Data memory: total. After reset, configured into:1)
Software configurable. Available options described chapter.
V1.2, 2009-05
TC1767
Introduction Kbyte Local Data (LDRAM) Kbyte Data Cache (DACHE) On-chip SRAMs with parity error detection High-performance 32-bit Peripheral Control Processor
2.2.3.2
flexible Peripheral Control Processor optimized interrupt handling thus unloading CPU. Features Data move between memory locations Data move with predefined limit supported Read-Modify-Write capabilities Full computation capabilities including basic MUL/DIV Read/move data accumulate previously read data Read data values perform arithmetic logical operation store result Bit-handling capabilities (testing, setting, clearing) Flow control instructions (conditional/unconditional jumps, breakpoint) Dedicated Interrupt System SRAMs with parity error detection PCP/FPI clock mode available
Integrated related On-Chip Memories Kbyte Code Memory (CMEM) Kbyte Parameter Memory (PRAM)
Chip System Units
TC1767 micro controller offers several versatile on-chip system peripheral units such controller, embedded Flash module, interrupt system ports.
2.3.1
Flexible Interrupt System
TC1767 includes programmable interrupt system with following features: Features Fast interrupt response Hardware arbitration Independent interrupt systems Programmable service request nodes (SRNs)
V1.2, 2009-05
TC1767
Introduction Each mapped interrupt system Flexible interrupt-prioritizing scheme with interrupt priority levels choose from Direct Memory Access Controller
2.3.2
TC1767 includes fast flexible controller with independant channels Move engine). Features independent channels selectable request inputs channel 2-level programmable priority channels within Sub-Block Software hardware request Hardware requests selected on-chip peripherals external inputs 3-level programmable priority Sub-Block chip interfaces Buffer capability move actions buses least move buffered) Individually programmable operation modes each channel Single Mode: stops disables channel after predefined number transfers Continuous Mode: channel remains enabled after predefined number transfers; transaction repeated Programmable address modification shadow register modes (with automatic re-set direct write access). Full 32-bit addressing capability each channel Gbyte address range Data block move supports Kbyte moves transaction Circular buffer addressing mode with flexible circular buffer sizes Programmable data width transfer/transaction: 8-bit, 16-bit, 32-bit Register each channel Source destination address register Channel control status register Transfer count register Flexible interrupt generation (the service request node logic channel also implemented module) module working frequency, interface frequency. Dependant target/destination address, Read/write requests from Move Engine directed SPB, LMB, Cerberus.
V1.2, 2009-05
TC1767
Introduction
2.3.3
System Timer
TC1767's designed global system timing applications requiring both high precision long range. Features Free-running 56-bit counter bits read synchronously Different 32-bit portions 56-bit counter read synchronously Flexible interrupt generation based compare match with partial Scontent Driven maximum fSYS, default after reset fSYS/2) Counting starts automatically after reset operation Sregisters reset application reset ARSTDIS.STMDIS cleared. ARSTDIS.STMDIS set, reset. Scan halted debug/suspend mode
Special Sregister semantics provide synchronous views entire 56-bit counter, 32-bit subsets different levels resolution. maximum clock period fSTM. MHz, example, Scounts 28.56 years before overflowing. Thus, capable continuously timing entire expected product life time system without overflowing. case power-on reset, watchdog reset, software reset, reset. After these reset conditions, enabled immediately starts counting possible affect content timer during normal operation TC1767. timer registers only read written Scan optionally disabled power-saving purposes, suspended debugging purposes clock control register. suspend mode TC1767 (initiated writing appropriate value STM_CLC register), Sclock stopped registers still readable. 56-bit width STM, possible read entire content with instruction. needs read with load instructions. Since timer would continue count between load operations, there chance that values read consistent (due possible overflow from part timer high part between read operations). enable synchronous consistent reading Scontent, capture register (STM_CAP) implemented. latches content high part Seach time when registers STM_TIM0 STM_TIM5 read. Thus, STM_CAP holds upper value timer exactly same time when lower part read. second read operation would then read content STM_CAP complete timer value. content 56-bit System Timer compared against content compare values stored STM_CMP0 STM_CMP1 registers. Interrupts
V1.2, 2009-05
TC1767
Introduction generated compare match Swith STM_CMP0 STM_CMP1 registers. Figure provides overview Smodule. shows options reading parts Scontent.
SModule
etc.
STM_CMP0
Compare Register
SIRQ0 Interrupt Control SIRQ1 Enable Disable Clock Control
STM_CMP1
Compare Register1
56-bit System Timer
STM_TIM5
STM_CAP STM_TIM6
fS
Address Decoder
STM_TIM4 STM_TIM3
PORST
STM_TIM2 STM_TIM1 STM_TIM0
MCB06185_mod
Figure
General Block Diagram SModule Registers
V1.2, 2009-05
TC1767
Introduction
2.3.4
System Control Unit
following introduction gives overview about TC1767 System Control Unit (SCU).
2.3.4.1
Clock Generation Unit
Clock Generation Unit (CGU) allows very flexible clock generation TC1767. During user program execution frequency programmed optimal ratio between performance power consumption.
2.3.4.2
Features Watchdog Timer
main features summarized here. 16-bit Watchdog counter Selectable input frequency: fFPI/256 fFPI/16384 16-bit user-definable reload value normal Watchdog operation, fixed reload value Time-Out Prewarning Modes Incorporation ENDINIT monitoring modifications Sophisticated Password Access mechanism with fixed user-definable password fields Access Error Detection: Invalid password (during first access) invalid guard bits (during second access) trigger Watchdog reset generation Overflow Error Detection: overflow counter triggers Watchdog reset generation Watchdog function disabled; access protection ENDINIT monitor function remain enabled Double Reset Detection: Watchdog induced reset occurs twice, severe system malfunction assumed TC1767 held reset until system class reset occurs.
2.3.4.3
Reset Operation
following reset request triggers available: External power-on hardware reset request trigger; PORST, (cold reset) External System Request reset triggers; ESR0 ESR1 (warm reset) Watchdog Timer (WDT) reset request trigger, (warm reset) Software reset (SW), (warm reset) Debug (OCDS) reset request trigger, (warm reset) JTAG reset (special reset) Resets JTAG interface
Note: JTAG OCDS resets described OCDS chapter. There basic types reset request triggers:
Data Sheet V1.2, 2009-05
TC1767
Introduction Trigger sources that depend clock, such PORST. This trigger force device into asynchronous reset assertion independently clock. activation asynchronous reset asynchronous system clock, whereas de-assertion synchronized. Trigger sources that need clock order asserted, such input signals ESR0, ESR1, trigger, parity trigger, trigger.
2.3.4.4
External Interface
provides interface pads system purpose. Various functions covered these pins. different tasks some pads shared with other functions most them shared with other functions. following functions covered controlled pads: Reset request triggers Reset indication Trap request triggers Interrupt request triggers module triggers
first three points covered pads last points pads.
2.3.4.5
Temperature Measurement
Temperature Sensor (DTS) generates measurement result that indicates directly current temperature. result measurement read register.
2.3.5
General Purpose Ports Peripheral Lines
TC1767 includes flexible Ports structure with following features: Features Digital General-Purpose Input/Output (GPIO) port lines Input/output functionality individually programmable each port line Programmable input characteristics (pull-up, pull-down, pull device) Programmable output driver strength minimization (weak, medium, strong) Programmable output characteristics (push-pull, open drain) Programmable alternate output functions Output lines each port updated port-wise set/reset/toggled bit-wise
V1.2, 2009-05
TC1767
Introduction
2.3.6
Program Memory Unit (PMU)
devices AudoF family contain least Program Memory Unit. This named "PMU0". Some devices contain additional PMUs which named "PMU1", TC1767, PMU0 contains following submodules: Flash command fetch control interface Program Flash Data Flash. Overlay interface with Online Data Acquisition (OLDA) support. Boot interface. Emulation Memory interface. Local Memory slave interface. Mbyte Program Flash memory (PFlash) Kbyte Data Flash memory (DFlash, represents Kbyte EEPROM) Kbyte Boot (BROM) Kbyte Overlay (OVRAM)
Following memories controlled belong PMU0:
following figure shows block diagram PMU0:
To/From Local Memory Interface Slave
PMU0
Overlay Interface
Control
Control
OVRAM
Flash Interface Module DFLASH BROM
Emulation Memory Interface
PFLASH
Emulation Memory chip only
PMU0_BasicBlockDiag _generic
Figure
PMU0 Basic Block Diagram
V1.2, 2009-05
TC1767
Introduction
2.3.6.1
Boot
internal Kbyte Boot (BROM) divided into parts, used for: firmware (Boot ROM), factory test routines (Test ROM).
different sections firmware Boot provide startup boot operations after reset. TestROM reserved special routines, which used testing, stressing qualification component.
2.3.6.2
Overlay Data Acquisition
overlay memory OVRAM provided especially redirection data accesses program memory OVRAM using data overlay function. data overlay functionality itself controlled module. online data acquisition (OLDA) application calibration data virtual memory range provided which accessed without error reporting. Accesses this OLDA range also redirected overlay memory.
2.3.6.3
Emulation Memory Interface
TC1767 Emulation Device, Emulation Memory (EMEM) provided, which fully used calibration program memory OLDA overlay. Emulation Memory interface shown Figure 64-bit wide memory interface that controls CPUaccesses Emulation Memory TC1767 Emulation Device. TC1767 production device, EMEM interface always disabled.
2.3.6.4
Tuning Protection
Tuning protection required user absolutely protect control data (e.g. engine control), serial number user software, stored Flash, from being manipulated, safely detect changed disturbed data. internal Flash, these protection requirements excellently fulfilled TC1767 with Flash read write protection with user-specific protection levels, with dedicated firmware, supporting internal Flash read protection, with Alternate Boot Mode.
Special tuning protection support provided external Flash, which must also protected.
2.3.6.5
Program Data Flash
embedded Flash module PMU0 includes Mbyte Flash memory code constant data (called Program Flash) additionally Kbyte Flash memory used emulation EEPROM data (called Data Flash). Program Flash realized
V1.2, 2009-05
TC1767
Introduction independent Flash bank, whereas Data Flash built Flash banks, allowing following combinations concurrent Flash operations: Read code data from Program Flash, while bank Data Flash busy with program erase operation. Read data from bank Data Flash, while other bank Data Flash busy with program erase operation. Program bank Data Flash while erasing other bank Data Flash, read from Program Flash.
Both, Program Flash Data Flash, provide error correction single-bit errors within 64-bit read double-word, resulting extremely failure rate. Read accesses Program Flash executed 256-bit width, Data Flash 64-bit width (both plus ECC). Single-cycle burst transfers double-words sequential prefetching with control prefetch supported Program Flash. minimum programming width page, including bytes Program Flash bytes Data Flash. Concurrent programming erasing Data Flash performed using automatic erase suspend resume function. basic block diagram Flash Module shown following figure.
Control
Flash Command State Machine
Control
SFRs FSRAM
Microcode
Redundancy Control
Voltage Control
Addr
Address
WR_DATA
Write
Page Write Buffers
byte byte
Program Flash
Block
Code RD_DATA
PF-Read Buffer
256+32
Read
DF-Read Buffer
64+8
Bank Data Flash Bank
Bank
Bank
Flash Interface&Control Module
Flash Array Module Flash Array
Flash_BasicBlockDiagram _generic.vsd
Figure
Basic Block Diagram Flash Module
Flash operations controlled simply transferring command sequences Flash which based JEDEC standard. This user interface embedded Flash very comfortable, because operations controlled with high level commands, such "Erase Sector". State transitions, such termination command execution, errors reported user maskable interrupts. Command sequences
V1.2, 2009-05
TC1767
Introduction normally written Flash CPU, also issued controller OCDS). Flash also features advanced read/write protection architecture, including read protection whole Flash array (optionally without Data Flash) separate write protection sectors (only Program Flash). Write protected sectors made reprogrammable (enabled with passwords), they locked ever (ROM function). Each sector assigned three different users write protection. different users organized hierarchically. Program Flash Features Functions Mbyte on-chip Program Flash PMU0. instruction code constant data. read interface (burst transfer operation). Dynamic correction single-bit errors during read access. Transfer rate burst mode: 64-bit double-word clock cycle. Sector architecture: Eight Kbyte, Kbyte seven Kbyte sectors. Each sector separately erasable. Each sector lockable protection against erase program (write protection). additional configuration sector (not accessible user). Optional read protection whole Flash, with sophisticated read access supervision. Combined with whole Flash write protection thus supporting protection against Trojan horse programs. Sector specific write protection with support re-programmability locked forever. Comfortable password checking temporary disable write read protection. User controlled configuration blocks (UCB) configuration sector keywords sector-specific lock bits (one block every user; three users). supply voltage (VDDP) also used program erase pin). Efficient byte page program operation. Flash operations controlled command sequences (unlock sequences) protection against unintended operation. End-of-busy well error reporting with interrupt error trap. Write state machine automatic program erase, including verification operation quality. Support margin check. Delivery erased state (read zeros). Global sector status information. Overlay support with SRAM calibration applications. Configurable wait state selection different frequencies. Endurance 1000; minimum 1000 program/erase cycles physical sector; reduced endurance sector. Operating lifetime (incl. Retention): years with endurance=1000.
V1.2, 2009-05
TC1767
Introduction further operating conditions data sheet section "Flash Memory Parameters".
Data Flash Features Functions Kbyte on-chip Flash, configured independent Flash banks equal size. read interface. Erase/program bank while data read access from other bank. Programming bank while erasing other bank using automatic suspend/resume function. Dynamic correction single-bit errors during read access. Sector architecture: sectors equal size. Each sector separately erasable. byte pages written step. Operational control command sequences (unlock sequences, same those Program Flash) protection against unintended operation. End-of-busy well error reporting with interrupt error trap. Write state machine automatic program erase. Margin check detection problematic Flash bits. Endurance 30000 (can device dependent); i.e. 30000 program/erase cycles sector allowed, with retention min. years. Dedicated DFlash status information. Other characteristics: Same Program Flash.
2.3.7
Data Access Overlay
data overlay functionality provides capability redirect data accesses TriCore program memory (segments called "target memory" different memory called "overlay memory". Depending device following overlay memories available: Overlay SRAM PMU. Emulation Memory1). External memory2).
This functionality makes possible, example, modify application's test calibration parameters (which typically stored program memory) during time program. address translation implemented DMI, affects only data accesses (reads writes) TriCore. Instruction fetches TriCore accesses other master (including debug interface) redirected.
Only available Emulation Device "ED". Only available Emulation Device with EBU.
V1.2, 2009-05
TC1767
Introduction Summary Features Functions overlay ranges ("blocks") configurable. Support Kbyte embedded Overlay SRAM (OVRAM) PMU. Support Kbyte overlay/calibration memory (EMEM)1). Support overlay memory external memory (EBU space)2). Support Online Data Acquisition into range overlay. Support different overlay memory selections every enabled overlay block. Sizes overlay blocks selectable depending overlay memory: OVRAM: from byte Kbyte. EMEM1) external memory2): Kbyte Kbyte. configured overlay ranges enabled with only register write access. Programmable flush (invalidate) control data cache DMI. TC1767 Development Support
2.3.8
Overview about TC1767 development environment: Complete Development Support variety software hardware development tools 32-bit microcontroller TC1767 available from experienced international tool suppliers. development environment Infineon 32-bit microcontroller includes following tools: Embedded Development Environment TriCore Products TC1767 On-chip Debug Support (OCDS) provides JTAG port communication between external hardware system System Timer (STM) with high-precision, long-range timing capabilities TC1767 includes power management system, watchdog timer well reset logic
V1.2, 2009-05
TC1767
Introduction
On-Chip Peripheral Units
TC1767 micro controller offers several versatile on-chip peripheral units such serial controllers, timer units, Analog-to-Digital converters. Several lines TC1767 ports reserved these peripheral units communicate with external world.
On-Chip Peripheral Units Asynchronous/Synchronous Serial Channels (ASC) with baud-rate generator, parity, framing overrun error detection Synchronous Serial Channels (SSC) with programmable data length shift direction Micro Second Interface (MSC) serial communication Module (MultiCAN) high-efficiency data handling FIFO buffering gateway data transfer Micro Link Serial Interfaces (MLI) serial multiprocessor communication General Purpose Timer Array (GPTA) with powerful digital signal filtering timer functionality accomplish autonomous complex Input/Output management Analog-to-Digital Converter Units (ADC0, ADC1) with 8-bit, 10-bit, 12-bit resolution. fast Analog-to-Digital Converter Unit (FADC)
2.4.1
Asynchronous/Synchronous Serial Interfaces
TC1767 includes Asynchronous/Synchronous Serial Interfaces, ASC0 ASC1. Both modules have same functionality. Figure shows global view Asynchronous/Synchronous Serial Interface (ASC).
V1.2, 2009-05
TC1767
Introduction
Clock Control
fASC
Address Decoder TBIR
Module (Kernel) Port Control
Interrupt Control
MCB05762_mod
Figure
General Block Diagram Interface TC1767 other
provides serial communication between microcontrollers, microprocessors, external peripherals.
supports full-duplex asynchronous communication half-duplex synchronous communication. Synchronous Mode, data transmitted received synchronous shift clock that generated internally. Asynchronous Mode, 8-bit 9-bit data transfer, parity generation, number stop bits selected. Parity, framing, overrun error detection provided increase reliability data transfers. Transmission reception data double-buffered. multiprocessor communication, mechanism included distinguish address bytes from data bytes. Testing supported loop-back option. 13-bit baud rate generator provides with separate serial clock signal, which accurately adjusted prescaler implemented fractional divider.
V1.2, 2009-05
TC1767
Introduction Features Full-duplex asynchronous operating modes 8-bit 9-bit data frames, first Parity-bit generation/checking stop bits Baud rate from Mbit/s 1.19 bit/s module clock) Multiprocessor mode automatic address/data byte detection Loop-back capability Half-duplex 8-bit synchronous operating mode Baud rate from 10.0 Mbit/s 813.8 bit/s module clock) Double-buffered transmitter/receiver Interrupt generation transmit buffer empty condition transmit last frame condition receive buffer full condition error condition (frame, parity, overrun error) Implementation features Connections Controller Connections receiver input GPTA (LTC) baud rate detection break signal measuring
2.4.2
High-Speed Synchronous Serial Interfaces
TC1767 includes High-Speed Synchronous Serial Interfaces, SSC0 SSC1. Both modules have same functionality. Figure shows global view Synchronous Serial interface (SSC).
V1.2, 2009-05
TC1767
Introduction
fSSC
Clock Control
Master
MRSTA MRSTB MTSR MTSRA MTSRB MRST SCLKA SCLKB SCLK SLSI[7:1] SLSO[7:0] SLSOANDO[7:0] SLSOANDI[7:0] Enable Select Port Control
fCLC
Slave
MTSR
Address Decoder Interrupt Control
MRST
Module (Kernel)
Slave Master Slave Master
SCLK SLSI[7:1] SLSO[7:0] SLSOANDO[7:0]
Requests
MCB06058_mod
Figure
General Block Diagram Interface
supports full-duplex half-duplex serial synchronous communication Mbit/s module clock, Master Mode). serial clock signal generated itself (Master Mode) received from external master (Slave Mode). Data width, shift direction, clock polarity phase programmable. This allows communication with SPI-compatible devices. Transmission reception data double-buffered. shift clock generator provides with separate serial clock signal. slave select input available slave mode operation. Eight programmable slave select outputs (chip selects) supported Master Mode.
V1.2, 2009-05
TC1767
Introduction Features Master Slave Mode operation Full-duplex half-duplex operation Automatic control possible Flexible data format Programmable number data bits: bits Programmable shift direction: shift first Programmable clock polarity: Idle idle high state shift clock Programmable clock/data phase: Data shift with leading trailing edge shift clock Baud rate generation Master Mode: 40.0 Mbit/s 610.36 bit/s module clock) Slave Mode: Mbit/s 610.36 bit/s module clock) Interrupt generation transmitter empty condition receiver full condition error condition (receive, phase, baud rate, transmit error) Flexible configuration Seven slave select inputs SLSI[7:1] Slave Mode Eight programmable slave select outputs SLSO Master Mode Automatic SLSO generation with programmable timing Programmable active level enable control
V1.2, 2009-05
TC1767
Introduction
2.4.3
Micro Second Channel Interface
Micro Second Channel (MSC) interface provides serial communication links typically used connect power switches other peripheral devices. serial communication link includes fast synchronous downstream channel slow asynchronous upstream channel. Figure shows global view interface signals interface.
fMSC
Clock Control
fCLC
FCLP FCLN Downstream Channel
Address Decoder
Interrupt SR[3:0] Control ALTINL[15:0] ALTINH[15:0] EMGSTOPMSC
Module (Kernel)
Upstream Channel
SDI[7:0]
MCB06059
Figure
General Block Diagram Interface
downstream upstream channels module communicate with external world nine lines. Eight output lines required serial communication downstream channel (clock, data, enable signals). eight input lines SDI[7:0] used serial data input signal upstream channel. source serial data transmitted downstream channel register contents data that provided ALTINL/ALTINH input lines. These input lines typically connected with other on-chip peripheral units (for example with timer unit such GPTA). emergency stop input signal makes possible bits serial data stream dedicated values emergency case. Clock control, address decoding, interrupt service request control managed outside module kernel. Service request outputs able trigger interrupt request.
V1.2, 2009-05
TC1767
Introduction Features Fast synchronous serial interface connect power switches particular, other peripheral devices serial buses High-speed synchronous serial transmission downstream channel Serial output clock frequency: fFCL fMSC/2 Fractional clock divider precise frequency control serial clock fMSC Command, data, passive frame types Start serial frame: Software-controlled, timer-controlled, free-running Programmable upstream data frame length bits) Transmission with without Flexible chip select generation indicates status during serial frame transmission Emergency stop without intervention Low-speed asynchronous serial reception upstream channel Baud rate: fMSC divided 128, Standard asynchronous serial frames Parity error checker 8-to-1 input multiplexer lines Built-in spike filter lines Selectable types downstream channel interface: four LVDS differential output drivers four digital GPIO pins
V1.2, 2009-05
TC1767
Introduction
2.4.4
MultiCAN Controller
MultiCAN module provides independent nodes PG-LQFP-176-5 package, representing serial communication interfaces. number available message objects
MultiCAN Module Kernel
Clock Control
Message Object Buffer Objects
Address Decoder
Linked List Control
Node Node
TXDC1 RXDC1 TXDC0 RXDC0 Port Control
Interrupt Control
Control
MCA06060_N2
Figure
Overview MultiCAN Module
MultiCAN module contains independently operating nodes with Full-CAN functionality that able exchange Data Remote Frames gateway function. Transmission reception frames handled accordance specification V2.0 (active). Each node receive transmit standard frames with 11-bit identifiers well extended frames with 29-bit identifiers. nodes share common message objects. Each message object individually allocated nodes. Besides serving storage container incoming outgoing frames, message objects combined build gateways between nodes FIFO buffer. message objects organized double-chained linked lists, where each node list message objects. node stores frames only into message objects that allocated message object list node, transmits only messages belonging this message object list. powerful, command-driven list controller performs message object list operations.
V1.2, 2009-05
TC1767
Introduction timings nodes derived from module timer clock (fCAN) programmable data rate Mbit/s. External transceivers connected node pair receive transmit pins. Features Compliant with 11898 functionality according specification V2.0 active Dedicated control registers each node Data transfer rates Mbit/s Flexible powerful message transfer control error handling capabilities Advanced timing analysis baud rate detection each node frame counter Full-CAN functionality: message objects individually Allocated (assigned) node Configured transmit receive object Setup handle frames with 11-bit 29-bit identifier Identified timestamp frame counter Configured remote monitoring mode Advanced Acceptance Filtering Each message object provides individual acceptance mask filter incoming frames. message object configured accept standard extended frames accept both standard extended frames. Message objects grouped into four priority classes transmission reception. selection message transmitted first based frame identifier, according arbitration rules, order list. Advanced message object functionality Message objects combined build FIFO message buffers arbitrary size, limited only total number message objects. Message objects linked form gateway that automatically transfers frames between different buses. single gateway link nodes. arbitrary number gateways defined. Advanced data management message objects organized double-chained lists. List reorganizations performed time, even during full operation nodes. powerful, command-driven list controller manages organization list structure ensures consistency list. Message FIFOs based list structure easily scaled size during operation.
V1.2, 2009-05
TC1767
Introduction Static allocation commands offer compatibility with MultiCAN applications that list-based. Advanced interrupt handling interrupt output lines available. Interrupt requests routed individually interrupt output lines. Message post-processing notifications combined flexibly into dedicated register field notification bits.
V1.2, 2009-05
TC1767
Introduction
2.4.5
Micro Link Interface
This TC1767 contains Micro Link Interface, MLI0. Micro Link Interface (MLI) fast synchronous serial interface exchange data between microcontrollers other devices, such stand-alone peripheral components. Figure shows microcontrollers typically connected together their interfaces.
Controller
Controller
Peripheral
Peripheral
Peripheral
Peripheral
Memory System
System
Memory
MCA06061
Figure Features
Typical Micro Link Interface Connection
Synchronous serial communication between transmitter receiver Different system clock speeds supported transmitter receiver full handshake protocol lines between transmitter receiver) Fully transparent read/write access supported remote programming) Complete address range target device available Specific frame protocol transfer commands, addresses data Error detection parity 32-bit, 16-bit, 8-bit data transfers supported Programmable baud rate: fMLI/2 (max. fMLI fSYS) Address range protection scheme block unauthorized accesses Multiple receiving devices supported
V1.2, 2009-05
TC1767
Introduction Figure shows general block diagram module.
TREADY[D:A] TVALID[D:A]
fSYS
TR[3:0]
Fract. Divider
Transmitter
Control
TDATA TCLK
fMLI
BRKOUT Move Engine
Module RCLK[D:A] Receiver Control
Port Control RREADY[D:A]
SR[7:0]
RVALID[D:A] RDATA[D:A]
MCB06062_mod
Figure
General Block Diagram Modules
transmitter receiver communicate with other receivers transmitters four-line serial connection each. Several lines these connections available outside module kernel four-line output input vector with index numbering module internal control blocks define which signal vector actually taken into account also allow polarity inversions adapt different physical interconnection means).
V1.2, 2009-05
TC1767
Introduction
2.4.6
General Purpose Timer Array (GPTA)
TC1767 contains General Purpose Timer Array (GPTA0). Figure shows global view GPTA module. GPTA provides timer, compare, capture functionalities that flexibly combined form signal measurement signal generation units. They optimized tasks typical engine, gearbox, electrical motor control applications, also used generate simple complex signal waveforms required other industrial applications.
GPTA0 Clock Generation Cells FPC0 FPC1 FPC2 FPC3 FPC4 FPC5 PDL1 DCM3 PDL0 DCM1 DCM2 DIGITAL DCM0
fGPTA Clock Distribution Cells
Clock Conn
GTC00 GTC01 GTC02 GTC03 Global Timer Cell Array GTC30 GTC31
Signal Generation Cells LTCA2 LTC00 LTC01 LTC02 LTC03 Local Timer Cell Array LTC62 LTC63 LTC00 LTC01 LTC02 LTC03 Local Timer Cell Array LTC30 LTC31 Line Sharing Block Interrupt Sharing Block
MCB05910_TC1767_LTC
Line Sharing Block Interrupt Sharing Block
Figure
General Block Diagram GPTA Modules TC1767
V1.2, 2009-05
TC1767
Introduction
2.4.6.1
Functionality GPTA0
General Purpose Timer Array (GPTA0) provides hardware modules required high-speed digital signal processing: Filter Prescaler Cells (FPC) support input noise filtering prescaler operation. Phase Discrimination Logic units (PDL) decode direction information output rotation tracking system. Duty Cycle Measurement Cells (DCM) provide pulse-width measurement capabilities. Digital Phase Locked Loop unit (PLL) generates programmable number GPTA module clock ticks during input signal's period. Global Timer units (GT) driven various clock sources implemented operate time base associated Global Timer Cells. Global Timer Cells (GTC) programmed capture contents Global Timer external internal event. also used control external port depending result internal compare operation. GTCs logically concatenated provide common external port with complex signal waveform. Local Timer Cells (LTC) operating Timer, Capture, Compare Mode also logically tied together drive common external port with complex signal waveform. LTCs enabled Timer Mode Capture Mode clocked triggered various external internal events. On-chip Trigger Gating Signals (OTGS) configured provide trigger gating signals integrated peripherals.
Input lines shared trigger their programmed operation simultaneously. following list summarizes specific features GPTA units. Clock Generation Unit Filter Prescaler Cell (FPC) independent units Three basic operating modes: Prescaler, Delayed Debounce Filter, Immediate Debounce Filter Selectable input sources: Port lines, GPTA module clock, output preceding cell Selectable input clocks: GPTA module clock, prescaled GPTA module clock, clock, compensated uncompensated clock. fGPTA/2 maximum input signal frequency Filter Modes Phase Discriminator Logic (PDL) independent units operating modes sensor signals)
V1.2, 2009-05
TC1767
Introduction fGPTA/4 maximum input signal frequency 2-sensor Mode, fGPTA/6 maximum input signal frequency 3-sensor Mode Duty Cycle Measurement (DCM) Four independent units 100% margin time-out handling fGPTA maximum resolution fGPTA/2 maximum input signal frequency Digital Phase Locked Loop (PLL) unit Arbitrary multiplication factor between 65535 fGPTA maximum resolution fGPTA/2 maximum input signal frequency Clock Distribution Unit (CDU) unit Provides nine clock output signals: fGPTA, divided fGPTA clocks, FPC1/FPC4 outputs, clock, prescaler clock
Signal Generation Unit Global Timers (GT) independent units operating modes (Free-Running Timer Reload Timer) 24-bit data width fGPTA maximum resolution fGPTA/2 maximum input signal frequency Global Timer Cell (GTC) units related Global Timers operating modes (Capture, Compare Capture after Compare) 24-bit data width fGPTA maximum resolution fGPTA/2 maximum input signal frequency Local Timer Cell (LTC) independent units Three basic operating modes (Timer, Capture Compare) units Special compare modes unit 16-bit data width fGPTA maximum resolution fGPTA/2 maximum input signal frequency
Interrupt Sharing Unit interrupt sources, generating service requests
V1.2, 2009-05
TC1767
Introduction On-chip Trigger Unit on-chip trigger signals
Sharing Unit Interconnecting inputs outputs from internal clocks, FPC, GTC, LTC, ports, interface
V1.2, 2009-05
TC1767
Introduction
2.4.7
Analog-to-Digital Converters
TC1767 includes Analog Digital Converter modules (ADC0, ADC1) Fast Analog Digital Converter (FADC).
2.4.7.1
Block Diagram
analog digital converter module (ADC) allows conversion analog input values into discrete digital values based successive approximation method. This module contains independent kernels (ADC0, ADC1) that operate autonomously synchronized each other. kernel unit used convert analog input signal (done analog part) provides means triggering conversions, data handling storage (done digital part).
analog part kernel analog inputs converter conversion control analog part kernel analog inputs converter conversion control
digital part kernel data (result) handling request control digital part kernel data (result) handling request control
ADC_2_kernels
interface
Figure
Module with Kernels
Features analog part each kernel: Input voltage range from analog supply voltage Analog supply voltage range from (single supply) nominal supply voltage, performance degradation accepted lower voltages) Input multiplexer width possible analog input channels (not them necessarily available pins) VAREF alternative reference input channel Programmable sample time periods fADCI) Wide range accepted analog clock frequencies fADCI
V1.2, 2009-05
TC1767
Introduction Multiplexer test mode (channel input connected ground resistor test purposes during time specific control bit) Power saving mechanisms Independent result registers independent registers) conversion request sources (e.g. external events, auto-scan, programmable sequence, etc.) Synchronization kernels concurrent conversion starts Control external analog multiplexer, respecting additional time Programmable sampling times different channels Possibility cancel running conversions demand with automatic restart Flexible interrupt generation (possibility support) Limit checking reduce interrupt load Programmable data reduction filter adding conversion results Support conversion data FIFO Support suspend power down modes Individually programmable reference selection each channel (with exception dedicated channels always referring VAREF)
Features digital part each kernel:
V1.2, 2009-05
TC1767
Introduction
2.4.7.2
FADC Short Description
General Features Extreme fast conversion, cycles fFADC clock (262.5 fFADC MHz) 10-bit conversion (higher resolution achieved averaging consecutive conversions digital data reduction filter) Successive approximation conversion method Each differential input channel also used single-ended input Offset calibration support each channel Programmable gain each channel Free-running (Channel Timers) triggered conversion modes Trigger gating control external signals Built-in Channel Timers internal triggering Channel timer request periods independently selectable each channel Selectable, programmable digital anti-aliasing data reduction filter block with four independent filter units
VFAREF VDDAF VDDMF VDDIF VFAGND VSSAF VSSMF Clock Control fFADC fCLC Data Reduction Unit Control
Input Structure
Interrupt Control TS[H:A] GS[H:A]
Converter Stage
FAIN0P FAIN0N FAIN1P FAIN1N FAIN2P FAIN2N FAIN3P FAIN3N
input channel input channel input channel input channel
Channel Trigger Control
Channel Timers
MCB06065_m4
Figure
Block Diagram FADC Module with Input Channels
shown Figure main FADC functional blocks are: Input Structure containing differential inputs impedance control.
V1.2, 2009-05
TC1767
Introduction Converter Stage responsible analog-to-digital conversion including input multiplexer select between channel amplifiers Data Reduction Unit containing programmable anti-aliasing data reduction filters Channel Trigger Control block determining trigger gating conditions FADC channels Channel Timer each channel independently trigger conversions Control block responsible overall FADC functionality
FADC Power Supply References FADC module supplied following power supply reference voltage lines: VDDMF VSSMF: FADC Analog Channel Amplifier Power Supply (3.3 VDDIF VSSMF: FADC Analog Input Stage Power Supply (3.3 VDDIF supply does appear supply pin, because internally connected VDDM supply that sharing FADC input pins. VDDAF VSSAF: FADC Analog Part Power Supply (1.5 externally VFAREF VFAGND: FADC Reference Voltage (3.3 max.) FADC Reference Ground
Input Structure input structure FADC TC1767 contains: differential analog input stage each input channel select input impedance (differential single-ended measurement) decouple FADC input signal from pins. channel amplifier each input channel with settling time (about 5µs) when changing characteristics input stage (changing between unused, differential, single-ended single-ended mode).
V1.2, 2009-05
TC1767
Introduction
FAIN0P FAIN0N
Analog Input Stages
Channel Amplifier Stages VDDMF
Converter Stage
VSSMF FAIN2P FAIN2N VSSMF FAIN1P FAIN1N VSSMF FAIN3P FAIN3N VSSMF VDDIF
Figure
conversion Control control gain
CHNR
VDDMF
VDDMF
VDDAF VSSAF VDDMF
VSSMF
MCA06432_m4n
FADC Input Structure TC1767
On-Chip Debug Support (OCDS)
TC1767 contains resources different kinds "debugging", covering needs from software development real-time-tuning. These resources either embedded specific modules (e.g. breakpoint logic TriCore) part central peripheral (known CERBERUS).
2.5.1
On-Chip Debug Support
classic software debug approach (start/stop, single-stepping) supported several features labelled "OCDS Level Run/stop single-step execution independently TriCore PCP. Means request kinds reset without usage sideband pins. Halt-after-Reset repeatable debug sessions.
V1.2, 2009-05
TC1767
Introduction Different Boot modes application software programmed Flash. total four hardware breakpoints TriCore based instruction address, data address combination both. Unlimited number software breakpoints (DEBUG instruction) TriCore PCP. Debug event generated access specific address system peripheral bus. Tool access SFRs internal memories independent Cores. central Break Switches collect debug events from modules (TriCore, PCP, DMA, BCU, break input pins) distribute them selectively breakable modules (TriCore, PCP, break output pins). Central Suspend Switch suspend parts system (TriCore, PCP, Peripherals) instead breaking them reaction debug event. Dedicated interrupt resources handle debug events inside TriCore (breakpoint trap, software interrupt) Cerberus (can trigger PCP), e.g. implementing Monitor programs. Access OCDS Level resources also TriCore themselvesitself debug tools integrated into application code. Triggered Transfer data response debug event; target programmed device interface simple variable tracing done.
Additionally, depth performance analysis profiling support provided Emulation Device through MCDS Event Counters driven variety trigger signals (e.g. cache hit, wait state, interrupt accepted).
2.5.2
Real Time Trace
detailed tracing system's behavior pin-compatible Emulation Device available.1)
2.5.3
Calibration Support
main cases catered resources addition OCDS Level infrastructure: Overlay non-volatile on-chip memory non-intrusive signaling: SRAM Overlay. split into blocks which overlay independent regions on-chip Data Flash. Changing configuration triggered single access maintain consistency. Overlay configuration switch does require TriCore stopped suspended.
OCDS interface AudoNG available.
V1.2, 2009-05
TC1767
Introduction Invalidation Data Cache (maintaining write-back data) done concurrently with same SFR. additional Overlay Emulation Device. Trace memory Emulation Device optionally used Overlay also. dedicated trigger with independent status bits provided centrally post requests from application code host computer. host notified automatically when trigger updated TriCore PCP. polling system required.
2.5.4
Tool Interfaces
Three options exist communication channel between Tools (e.g. Debugger, Calibration Tool) TC1767: wire (Device Access Port) protocol long connections noisy environments. Four five) wire JTAG (IEEE 1149.1) standardized manufacturing tests. (plus software linked into application code) bandwidth deeply embedded purposes. JTAG clocked tool. clock JTAG, DAP. attach (i.e. physical disconnect/reconnect host connection without reset TC1767) interfaces. Infineon standard (Device Access Server) implementation seamless, transparent tool access over supported interface. Lock mechanism prevent unauthorized tool access critical application code.
2.5.5
Self-Test Support
Some manufacturing tests invoked application (e.g. after power-on) needed: Hardware-accelerated checksum calculation (e.g. Flash content).
2.5.6
Support
efficiently locate identify faults after integration TC1767 into system special functions available: Boundary Scan (IEEE 1149.1) JTAG DAP. SSCM (Single Scan Chain Mode1)) structural scan testing chip itself.
This function requires access some device pins (e.g. TESTMODE) addition those needed OCDS.
V1.2, 2009-05
TC1767
Pinning
Pinning
TC1767 Definition Functions
Figure shows Logic Symbol device.
PORST TESTMODE ESR0 ESR1 TRST DAP0 OCDS JTAG Control BRKIN DAP2 BRKOUT DAP1 AN[35:0] VSSM SSMF VAGN VFAR FAGN Digital Circuitry Power Supply
1767_LogSym_176
Alternate Functions TC1767 PG-LQFP176 Port Port Port Port Port Port Port GPTA, GPTA, SSC1, ADC0, OCDS GPTA, SSC0/1, MSC0 GPTA, ASC0/1, SSC0/1, SCU, GPTA, GPTA, MLI0 GPTA, MSC0
General Control
Analog Inputs
Analog Power Supply
XTAL1 XTAL2 OSC3 SSOSC
Oscillator
Figure
TC1767 Logic Symbol package variant PG-LQFP-176-5.
V1.2, 2009-05
Figure
OUT40/OUT8/IN40/IN26/P5.0 OUT41/OUT9/IN41/IN27/P5.1 OUT42/OUT10/IN42/IN28/P5.2 OUT43/OUT11/IN43/P5.3 OUT44/OUT12/IN44/IN29/P5.4 OUT45/OUT13/IN45/IN30/P5.5 OUT46/OUT14/IN46/IN31/P5.6 OUT47/OUT15/IN47/P5.7 TCLK0/OUT95/P5.15 VDDP RDATA0B/OUT89/P5.8 RVALID0B/OUT90/P5.9 RREADY0B/OUT91/P5.10 RCLK0B/OUT92/P5.11 TDATA0/SLSO07/OUT93/P5.12 TVALID0B/SLSO16/P5.13 TREADY0B/OUT94/P5.14 VDDP VDD(SB) VDDAF VDDM VSSM VFAREF VFAG AN35 AN34 AN33 AN32 AN31 AN30 AN29 AN28 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20
3.1.1
TC1767 PG-LQFP-176-6
TC1767
TC1767 Configuration: PG-LQFP-176-5
This chapter shows configuration package variant PG-LQFP-176-51).
TC1767 Pinning PG-LQFP-176-5
AN19 AN18 AN17 AN16 AN15 AN14 VARE AN13 AN12 AN11 AN10 VDDP D0EMUX2/OUT18/ IN18/ P1.14 D0EMUX1/OUT17/ IN17/ P1.13 D0EMUX0/OUT16/ IN16/ P1.12 TCLK0/OUT28/OUT32/ IN32/P SLSO13/ SLSO03/ OUT33/TREADY0A/ IN33/P ALID0A /OUT29/OUT34/ IN34/P TDAT A0/OUT30/OUT35/ IN35/P OUT31/ OUT36/RCLK0A/ IN36/P 0A/OUT37/OUT110/ IN37/P OUT38/OUT111/RVALI D0A/ IN38/P OUT39/RDA TA0A/ IN39/P VDDP OUT52/OUT28/ IN52/ IN28/P OUT53/OUT29/ IN53/ IN29/P EXTCLK1/OUT54/OUT30/ IN54/ IN30/P P0.15/IN15/ OUT15/ OUT71 P0.14/IN14/ OUT14/ OUT70 P0.7/I N7/HWCFG7/REQ3/ OUT7/OUT63 P0.6/I N6/HWCFG6/REQ2/ OUT6/OUT62 VDDP P0.13/IN13/ OUT13/OUT69 P0.12/IN12/ OUT12/OUT68 P0.5/I N5/HWCFG5/OUT5/ OUT61 P0.4/I N4/HWCFG4/OUT4/ OUT60 P2.13/IN13/ OUT3/S I11/ SDI0 P2.8/SLSO04/SLS O14/E P2.12/IN12/ OUT2/MTS R1A/ SOP0B P2.11/IN11/ OUT1/S CLK1A/ FCLP0B P2.10/IN10/ OUT0/MRST1A P2.9/SLSO05/SLS O15/E P6.3/I N25/OUT7/OUT83/ SOP0A P6.2/I N24/OUT6/OUT82/ SON0 P6.1/I N15/OUT5/OUT81/ FCLP0A P6.0/I N14/OUT4/OUT80/ FCLN0 VDDP P0.11/IN11/ OUT11/OUT67 P0.10/IN10/ OUT10/OUT66 P0.9/I N9/OUT9/ OUT65 P0.8/I N8/OUT8/ OUT64 P0.3/I N3/HWCFG3/OUT3/ OUT59 P0.2/I N2/HWCFG2/OUT2/ OUT58 P0.1/I N1/HWCFG1/OUT1/ OUT57 P0.0/I N0/HWCFG0/OUT0/ OUT56 P3.11/OUT93// REQ1 P3.12/OUT94// RXDCAN0/ RXD0B P3.13/OUT95// TXDCAN0/TXD0 VDDFL VDDP P3.9/OUT91/RXD1A P3.10/OUT92/REQ0 P3.0OUT84//RXD0A P3.1OUT85//TX P3.14/OUT96RX DCAN1/ P3.15/OUT97/TXDCAN1/ TXD1
P3.4/OUT88/MTSR0 P3.3/OUT87/MRST0 P3.2/OUT86/SCLK0 P3.8/SLSO06/OUT90/TXD1 VDDP ESR0 PORST ESR1 P1.1/IN17/OUT17/OUT73 TESTMODE P1.15/BRKIN/BRKOUT TCK/DAP0 TRST TDO/DAP2/BRKIN/BRKOUT TMS/DAP1 TDI/BRKIN/BRKOUT P1.7/IN23/OUT23/OUT79 P1.6/IN22/OUT22/OUT78 P1.5/IN21/OUT21/OUT77 P1.4/IN20/EMGSTOP/OUT20/OUT76 VDDO VDDO VSSO XTAL2 XTAL1 VDDP P1.3/IN19/OUT19/OUT75 P1.2/IN18/OUT18/OUT74 VDDP
MCP06067
V1.2, 2009-05
TC1767
Pinning
TC1767
Pinning Table Port P0.0 HWCFG0 OUT0 OUT56 OUT0 P0.1 HWCFG1 OUT1 OUT57 OUT1 P0.2 HWCFG2 OUT2 OUT58 OUT2 P0.3 HWCFG3 OUT3 OUT59 OUT3 I/O0 I/O0 I/O0 I/O0 Port General Purpose Line GPTA0 Input LTCA2 Input Hardware Configuration Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input Hardware Configuration Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input Hardware Configuration Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input Hardware Configuration Input GPTA0 Output GPTA0 Output LTCA2 Output Definitions Functions (PG-LQFP-176-5 Package1)) Ctrl. Type Function
Symbol
V1.2, 2009-05
TC1767
Pinning Table P0.4 HWCFG4 OUT4 OUT60 OUT4 P0.5 HWCFG5 OUT5 OUT61 OUT5 P0.6 HWCFG6 REQ2 OUT6 OUT62 OUT6 P0.7 HWCFG7 REQ3 OUT7 OUT63 OUT7 Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line GPTA0 Input LTCA2 Input Hardware Configuration Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input Hardware Configuration Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input Hardware Configuration Input External Request Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input Hardware Configuration Input External Request Input GPTA0 Output GPTA0 Output LTCA2 Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table P0.8 OUT8 OUT64 OUT8 P0.9 OUT9 OUT65 OUT9 P0.10 IN10 OUT10 OUT66 OUT10 P0.11 IN11 OUT11 OUT67 OUT11 P0.12 IN12 OUT12 OUT68 OUT12 Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line GPTA0 Input LTCA2 Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input GPTA0 Output GPTA0 Output LTCA2 Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table P0.13 IN13 OUT13 OUT69 OUT13 P0.14 IN14 REQ4 OUT14 OUT70 OUT14 P0.15 IN15 REQ5 OUT15 OUT71 OUT15 Port P1.0 IN16 BRKIN OUT16 OUT72 OUT16 BRKOUT P1.1 IN17 OUT17 OUT73 OUT17 I/O0 I/O0 Port General Purpose Line GPTA0 Input Break Input GPTA0 Output GPTA0 Output LTCA2 Output Break Output (controlled OCDS module) Port General Purpose Line GPTA0 Input GPTA0 Output GPTA0 Output LTCA2 Output Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 Type Function Port General Purpose Line GPTA0 Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input External Request Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input External Request Input GPTA0 Output GPTA0 Output LTCA2 Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table P1.2 IN18 OUT18 OUT74 OUT18 P1.3 IN19 IN19 OUT19 OUT75 OUT19 P1.4 IN20 IN20 EMGSTOP OUT20 OUT76 OUT20 P1.5 IN21 IN21 OUT21 OUT77 OUT21 P1.6 IN22 IN22 OUT22 OUT78 OUT22 Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line GPTA0 Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input Emergency Stop Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input GPTA0 Output GPTA0 Output LTCA2 Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table P1.7 IN23 IN23 OUT23 OUT79 OUT23 P1.8 IN24 IN48 MTSR1B OUT24 OUT48 MTSR1B P1.9 IN25 IN49 MRST1B OUT25 OUT49 MRST1B P1.10 IN26 IN50 OUT26 OUT50 SLSO17 Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line GPTA0 Input LTCA2 Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input GPTA0 Input SSC1 Slave Receive Input (Slave Mode) GPTA0 Output GPTA0 Output SSC1 Master Transmit Output (Master Mode) Port General Purpose Line GPTA0 Input GPTA0 Input SSC1 Master Receive Input (Master Mode) GPTA0 Output GPTA0 Output SSC1 Slave Transmit Output (Slave Mode) Port General Purpose Line GPTA0 Input GPTA0 Input GPTA0 Output GPTA0 Output SSC1 Slave Select Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table P1.11 IN27 IN51 SCLK1B OUT27 OUT51 SCLK1B P1.12 IN16 AD0EMUX0 AD0EMUX0 OUT16 P1.13 IN17 AD0EMUX1 AD0EMUX1 OUT17 P1.14 IN18 AD0EMUX2 AD0EMUX2 OUT18 P1.15 BRKIN Reserved Reserved Reserved BRKOUT Port Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line GPTA0 Input GPTA0 Input SSC1 Clock Input GPTA0 Output GPTA0 Output SSC1 Clock Output Port General Purpose Line LTCA2 Input ADC0 External Multiplexer Control Output ADC0 External Multiplexer Control Output LTCA2 Output Port General Purpose Line LTCA2 Input ADC0 External Multiplexer Control Output ADC0 External Multiplexer Control Output LTCA2 Output Port General Purpose Line LTCA2 Input ADC0 External Multiplexer Control Output ADC0 External Multiplexer Control Output LTCA2 Output Port General Purpose Line Break Input Break Output (controlled OCDS module)
Symbol
V1.2, 2009-05
TC1767
Pinning Table P2.0 IN32 OUT32 TCLK0 OUT28 P2.1 IN33 TREADY0A OUT33 SLSO03 SLSO13 P2.2 IN34 OUT34 TVALID0 OUT29 P2.3 IN35 OUT35 TDATA0 OUT30 P2.4 IN36 RCLK0A OUT36 OUT36 OUT31 Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line GPTA0 Input GPTA0 Output MLI0 Transmitter Clock Output LTCA2 Output Port General Purpose Line GPTA0 Input MLI0 Transmitter Ready Input GPTA0 Output SSC0 Slave Select Output Line SSC1 Slave Select Output Line Port General Purpose Line GPTA0 Input GPTA0 Output MLI0 Transmitter Valid Output LTCA2 Output Port General Purpose Line GPTA0 Input GPTA0 Output MLI0 Transmitter Data Output LTCA2 Output Port General Purpose Line GPTA0 Input Receiver Clock Input GPTA0 Output GPTA0 Output LTCA2 Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table P2.5 IN37 OUT37 RREADY0A OUT110 P2.6 IN38 RVALID0A OUT38 OUT38 OUT111 P2.7 IN39 RDATA0A OUT39 OUT39 Reserved P2.8 SLSO04 SLSO14 EN00 P2.9 SLSO05 SLSO15 EN01 Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line GPTA0 Input GPTA0 Output MLI0 Receiver Ready Output LTCA2 Output Port General Purpose Line GPTA0 Input Receiver Valid Input GPTA0 Output GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input Receiver Data Input GPTA0 Output GPTA0 Output Port General Purpose Line SSC0 Slave Select Output SSC1 Slave Select Output MSC0 Enable Output Port General Purpose Line SSC0 Slave Select Output SSC1 Slave Select Output MSC0 Enable Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table P2.10 MRST1A IN10 MRST1A OUT0 Reserved P2.11 SCLK1A IN11 SCLK1A OUT1 FCLP0B P2.12 MTSR1A IN12 MTSR1A OUT2 SOP0B P2.13 SLSI11 SDI0 IN13 OUT3 Reserved Reserved Port Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line SSC1 Master Receive Input LTCA2 Input SSC1 Slave Transmit Output LTCA2 Output Port General Purpose Line SSC1 Clock Input LTCA2 Input SSC1 Clock Output LTCA2 Output MSC0 Clock Output Positive Port General Purpose Line SSC1 Slave Receive Input LTCA2 Input SSC1 Master Transmit Output LTCA2 Output MSC0 Serial Data Output Positive Port General Purpose Line SSC1 Slave Select Input MSC0 Serial Data Input LTCA2 Input LTCA2 Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table P3.0 RXD0A RXD0A RXD0A OUT84 P3.1 TXD0 TXD0 OUT85 P3.2 SCLK0 SCLK0 SCLK0 OUT86 P3.3 MRST0 MRST0 MRST0 OUT87 P3.4 MTSR0 MTSR0 MTSR0 OUT88 P3.5 SLSO00 SLSO10 Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line ASC0 Receiver Input (Async. Sync. Mode) ASC0 Output (Sync. Mode) ASC0 Output (Sync. Mode) GPTA0 Output Port General Purpose Line ASC0 Output ASC0 Output GPTA0 Output Port General Purpose Line SSC0 Clock Input (Slave Mode) SSC0 Clock Output (Master Mode) SSC0 Clock Input (Master Mode) GPTA0 Output Port General Purpose Line SSC0 Master Receive Input (Master Mode) SSC0 Slave Transmit Output (Slave Mode) SSC0 Slave Transmit Output (Slave Mode) GPTA0 Output Port General Purpose Line SSC0 Slave Receive Input (Slave Mode) SSC0 Master Transmit Output (Master Mode) SSC0 Master Transmit Output (Master Mode) GPTA0 Output Port General Purpose Line SSC0 Slave Select Output SSC1 Slave Select Output SSC0 SSC1 Slave Select Output
Symbol
SLSOANDO0
V1.2, 2009-05
TC1767
Pinning Table P3.6 SLSO01 SLSO11 P3.7 SLSI01 SLSO02 SLSO12 OUT89 P3.8 SLSO06 TXD1 OUT90 P3.9 RXD1A RXD1A RXD1A OUT91 P3.10 REQ0 Reserved Reserved OUT92 P3.11 REQ1 Reserved Reserved OUT93 Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line SSC0 Slave Select Output SSC1 Slave Select Output SSC0 SSC1 Slave Select Output Port General Purpose Line SSC0 Slave Select Input SSC0 Slave Select Output SSC1 Slave Select Output GPTA0 Output Port General Purpose Line SSC0 Slave Select Output ASC1 Transmit Output GPTA0 Output Port General Purpose Line ASC1 Receiver Input ASC1 Receiver Output (Synchronous Mode) ASC1 Receiver Output (Synchronous Mode) GPTA0 Output Port General Purpose Line External Request Input GPTA0 Output Port General Purpose Line External Request Input GPTA0 Output
Symbol
SLSOANDO1
V1.2, 2009-05
TC1767
Pinning Table P3.12 RXDCAN0 RXD0B RXD0B RXD0B OUT94 P3.13 TXDCAN0 TXD0 OUT95 P3.14 RXDCAN1 RXD1B RXD1B RXD1B OUT96 P3.15 TXDCAN1 TXD1 OUT97 Port P4.0 IN28 IN52 OUT28 OUT52 Reserved I/O0 Port General Purpose Line GPTA0 Input GPTA0 Input GPTA0 Output GPTA0 Output Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line Node Receiver Input ASC0 Receiver Input ASC0 Receiver Output (Synchronous Mode) ASC0 Receiver Output (Synchronous Mode) GPTA0 Output Port General Purpose Line Node Transmitter Output ASC0 Transmit Output GPTA0 Output Port General Purpose Line Node Receiver Input ASC1 Receiver Input ASC1 Receiver Output (Synchronous Mode) ASC1 Receiver Output (Synchronous Mode) GPTA0 Output Port General Purpose Line Node Transmitter Output ASC1 Transmit Output GPTA0 Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table P4.1 IN29 IN53 OUT29 OUT53 Reserved P4.2 IN30 IN54 OUT30 OUT54 EXTCLK1 P4.3 IN31 IN55 OUT31 OUT55 EXTCLK0 Port P5.0 IN40 IN26 OUT40 OUT8 Reserved I/O0 Port General Purpose Line GPTA0 Input LTCA2 Input GPTA0 Output LTCA2 Output Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 Type Function Port General Purpose Line GPTA0 Input GPTA0 Input GPTA0 Output GPTA0 Output Port General Purpose Line GPTA0 Input GPTA0 Input GPTA0 Output GPTA0 Output External Clock Output Port General Purpose Line GPTA0 Input GPTA0 Input GPTA0 Output GPTA0 Output External Clock Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table P5.1 IN41 IN27 OUT41 OUT9 Reserved P5.2 IN42 IN28 OUT42 OUT10 Reserved P5.3 IN43 OUT43 OUT11 Reserved P5.4 IN44 IN29 OUT44 OUT12 Reserved P5.5 IN45 IN30 OUT45 OUT13 Reserved Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line GPTA0 Input LTCA2 Input GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input LTCA2 Input GPTA0 Output LTCA2 Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table P5.6 IN46 IN31 OUT46 OUT14 Reserved P5.7 IN47 OUT47 OUT15 Reserved P5.8 RDATA0B Reserved Reserved OUT89 P5.9 RVALID0B Reserved Reserved OUT90 P5.10 RREADY0B Reserved OUT91 P5.11 RCLK0B Reserved Reserved OUT92 Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line GPTA0 Input LTCA2 Input GPTA0 Output LTCA2 Output Port General Purpose Line GPTA0 Input GPTA0 Output LTCA2 Output Port General Purpose Line MLI0 Receiver Data Input LTCA2 Output Port General Purpose Line MLI0 Receiver Data Valid Input LTCA2 Output Port General Purpose Line MLI0 Receiver Ready Input LTCA2 Output Port General Purpose Line MLI0 Receiver Clock Input LTCA2 Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table P5.12 TDATA0 SLSO07 OUT93 P5.13 TVALID0B SLSO16 Reserved P5.14 TREADY0B Reserved Reserved OUT94 P5.15 TCLK0 Reserved OUT95 Port P6.0 IN14 FCLN0 OUT80 OUT4 P6.1 IN15 FCLP0A OUT81 OUT5 I/O0 I/O0 Port General Purpose Line LTCA2 Input MSC0 Clock Output Negative GPTA0 Output LTCA2 Output Port General Purpose Line LTCA2 Input MSC0 Clock Output Positive GPTA0 Output LTCA2 Output Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 I/O0 I/O0 Type Function Port General Purpose Line MLI0 Transmitter Data Output SSC0 Slave Select Output LTCA2 Output Port General Purpose Line MLI0 Transmitter Valid Input SSC1 Slave Select Output Port General Purpose Line MLI0 Transmitter Ready Input LTCA2 Output Port General Purpose Line MLI0 Transmitter Clock Output LTCA2 Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table P6.2 IN24 SON0 OUT82 OUT6 P6.3 IN25 SOP0A OUT83 OUT7 Analog Input Port AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. I/O0 I/O0 Type Function Port General Purpose Line LTCA2 Input MSC0 Serial Data Output Negative GPTA0 Output LTCA2 Output Port General Purpose Line LTCA2 Input MSC0 Serial Data Output Positive GPTA0 Output LTCA2 Output
Symbol
V1.2, 2009-05
TC1767
Pinning Table AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. Type Function Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Part Power Supply (3.3V Analog Part Ground ADC0 Reference Voltage ADC1 Reference Voltage Reference Ground FADC Analog Part Power Supply (3.3V)2) FADC Analog Part Logic Power Supply (1.5V) FADC Analog Part Ground FADC Analog Part Ground FADC Reference Voltage FADC Reference Ground
Symbol
VDDM VSSM VAREF0 VAREF1 VAGND0 VDDMF VDDAF VSSMF VSSAF VFAREF VFAGND
V1.2, 2009-05
TC1767
Pinning Table 213), 123, 153, VDDP 100, 124, 139, 154, 101, 125, 140, 155, Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. Type Function Digital Core Power Supply (1.5V)
Symbol
Port Power Supply (3.3V)
Digital Ground
VDDOSC VDDOSC3 VSSOSC VDDFL3
XTAL1 XTAL2
Main Oscillator Power Supply (1.5V) Main Oscillator Power Supply (3.3V) Main Oscillator Ground Power Supply Flash (3.3V) Main Oscillator Input Main Oscillator Output
V1.2, 2009-05
TC1767
Pinning Table BRKIN BRKOUT DAP1 DAP2 BRKIN BRKOUT TRST DAP0 TESTMODE ESR1 PORST ESR0 Definitions Functions (PG-LQFP-176-5 Package1)) (cont'd) Ctrl. Type Function JTAG Serial Data Input OCDS Break Input Line OCDS Break Output Line JTAG State Machine Control Input Device Access Port Line JTAG Serial Data Output Device Access Port Line OCDS Break Input Line OCDS Break Output Line JTAG Reset Input JTAG Clock Input Device Access Port Line Test Mode Select Input External System Request Reset Input Power Reset Input (input with input spike-filter) External System Request Reset Input Default configuration during after reset open-drain driver, corresponding strong driver, sharp edge. driver drives during power-on reset.
Symbol
TC1767 PG-LQFP-176-6 This also connected analog power supply comparator module. TC1767 emulation device (ED), this bonded VDDSB Stand supply). TC1767 device, this bonded pad.
Legend Table Column "Ctrl.": Input (for GPIO port lines with IOCR field selection 0XXXB) Output Output with IOCR field selection 1X00B Output with IOCR field selection 1X01B (ALT1)
Data Sheet V1.2, 2009-05
TC1767
Pinning Output with IOCR field selection 1X10B(ALT2) Output with IOCR field selection 1X11(ALT3) Column "Type": class (LVTTL) class (LVTTL) class (LVDS/CMOS) class (ADC) with pull-up device connected during reset (PORST with pull-down device connected during reset (PORST tri-state during reset (PORST
3.1.2
Reset Behavior Pins
Table describes pull-up/pull-down behavior System pins during poweron reset. Table Pins GPIOs, TDI, TESTMODE PORST, TRST, TCK, ESR0 ESR1 List Pull-up/Pull-down PORST Reset Behavior Pins PORST Pull-up Pull-down open-drain driver Pull-up2) used drive low.1) Pull-down3) Pull-up High-impedance PORST
Valid additionally after deactivation PORST until internal reset phase finished. chapter details. SCU_IOCR register description. SCU_IOCR register description.
V1.2, 2009-05
TC1767
Identification Registers
Identification Registers
Identification Registers uniquely identify module whole device. Table Short Name ADC0_ID ADC1_ID ASC0_ID ASC1_ID CAN_ID CBS_JDPID CBS_JTAGID CPS_ID CPU_ID DMA_ID DMI_ID FADC_ID FLASH0_ID FPU_ID GPTA0_ID LBCU_ID LFI_ID LTCA2_ID MCHK_ID MLI0_ID MSC0_ID PCP_ID PMI_ID PMU0_ID SBCU_ID SCU_CHIPID SCU_ID TC1767 Identification Registers Value 0058 C000H 0058 C000H 0000 4402H 0000 4402H 002B C061H 0000 6350H 1015 9083H 0015 C007H 000A C006H 001A C004H 0008 C005H 0027 C003H 0053 C001H 0054 C003H 0029 C005H 000F C005H 000C C006H 002A C005H 001B C001H 0025 C007H 0028 C003H 0020 C006H 000B C005H 0050 C001H 0000 6A0CH 0000 9001H 0052 C001H Address F010 1008H F010 1408H F000 0A08H F000 0B08H F000 4008H F000 0408H F000 0464H F7E0 FF08H F7E1 FE18H F000 3C08H F87F FC08H F010 0408H F800 2008H F7E1 A020H F000 1808H F87F FE08H F87F FF08H F000 2808H F010 C208H F010 C008H F000 0808H F004 3F08H F87F FD08H F800 0508H F000 0108H F000 0640H F000 0508H Stepping
V1.2, 2009-05
TC1767
Identification Registers Table Short Name SCU_MANID SCU_RTID SSC0_ID SSC1_ID STM_ID TC1767 Identification Registers (cont'd) Value 0000 1820H 0000 0007H 0000 4511H 0000 4511H 0000 C006H Address F000 0644H F000 0648H F010 0108H F010 0208H F000 0208H Stepping AD-step
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
5.1.1
Electrical Parameters
General Parameters Parameter Interpretation
parameters listed this section partly represent characteristics TC1767 partly requirements system. interpreting parameters easily when evaluating them design, they marked with two-letter abbreviation column "Symbol": Such parameters indicate Controller Characteristics which distinctive feature TC1767 must regarded system design. Such parameters indicate System Requirements which must provided microcontroller system which TC1767 designed
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
5.1.2
Driver Classes Summary
This section gives overview different driver classes basic characteristics. More details (mainly parameters) defined Section 5.2.1. Table Driver Classes Overview Class (e.g. GPIO) (e.g. serial I/Os) Speed Load Grade Leakage1) Termination Series termination recommended Parallel termination2), Table
Class Power Type Supply LVTTL I/O, LVTTL outputs LVDS/ CMOS
Values TJmax applications where LVDSpins used (disabled), these pins must either left unconnected, properly terminated with differential parallel termination 10%.
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
5.1.3
Absolute Maximum Ratings
Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. During absolute maximum rating overload conditions (VIN related VSS) voltage related pins with respect ground (VSS) must exceed values defined absolute maximum ratings. Table Parameter Absolute Maximum Rating Parameters Symbol Values Min. Typ. Max. Unit Note Test dition Under bias Under bias Whatever lower
Storage temperature Junction temperature Voltage power supply pins with respect VSS1) Voltage power supply VDDP pins with respect VSS2) Voltage power supply VDDM pins with respect Voltage Class input
Ambient temperature dedicated input pins with respect Voltage Class analog input with respect VAGND Voltage Class analog input with respect VSSAF, FADC switched through pin.
2.25 3.75
-0.5
VDDP
max.
VAIN VAREFx
-0.5
VDDM
VAINF VFAREF
-0.5
VDDM
Applicable VDD, VDDOSC, VDDPLL, VDDAF. Applicable VDDP, VDDFL3, VDDMF.
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
5.1.4
Operating Conditions
following operating conditions must exceeded order ensure correct operation TC1767. parameters specified following table refer these operating conditions, unless otherwise noted. Table Parameter Digital supply voltage1) Operating Condition Parameters Symbol Min. 1.42 3.13 3.13 3.13 1.42 4.75 Values Typ. Max. 1.582) 3.473) 3.473) 3.473) 1.582) 5.25 +125 Unit Note Test Condition Class pins (3.3 FADC FADC Class pins, separate specification Page 5-88, Page 5-93
VDDOSC VDDP VDDOSC3 VDDFL3 Analog supply voltages VDDMF VDDAF VDDM
Digital ground voltage Ambient temperature under bias
Analog supply voltages
Overload current class pins
overload current |IOV| class pins Overload coupling KOVAP factor analog inputs Frequency Frequency Frequency Short circuit current
single
OVAN
fCPU fPCP fSYS
Derivative dependent Derivative dependent
V1.2, 2009-05
TC1767
CONFIDENTIAL Table Parameter Absolute short circuit currents group (see Table 5-4) Inactive device current Absolute short circuit currents device External load capacitance Operating Condition Parameters Symbol Min. |ISC_PG| Values Typ. Max. Unit Note Test Condition note Electrical Parameters
|ISC_D|
power supply voltages VDDx note4)
Depending class. characteristics
Digital supply voltages applied TC1767 must static regulated voltages which allow typical voltage swing ±5%. Voltage overshoot permissible Power-Up PORST low, provided pulse duration less than cumulated summary pulses does exceed Voltage overshoot permissible Power-Up PORST low, provided pulse duration less than cumulated summary pulses does exceed additional document "TC1767 Reliability Overload" definition overload current digital pins. overload coupling factor (kA) defines worst case relation overload condition (IOV) resulting leakage current (IleakTOT) into adjacent pin: IleakTOT |IOV| IOZ1. Thus under overload conditions additional error leakage voltage (VAEL) will induced onto adjacent analog input resistance analog input source (RAIN). That means VAEL RAIN |IleakTOT|. definition adjacent pins related their order silicon. Injected leakage current always flows opposite direction from causing overload current. Therefore, total leakage current must calculated algebraic both component leakage currents (the leakage current IOZ1 optional injected leakage current). jitter characteristics this value according application settings. jitter parameters. Applicable digital outputs.
Table Group
Groups Overload/Short-Circuit Current Parameter Pins P5.[14:8] P1.[14:12]; P2.[7:0] P4.[3:0] P1.[3:2]; P1.[11:8]
V1.2, 2009-05
TC1767
CONFIDENTIAL Table Group Electrical Parameters
Groups Overload/Short-Circuit Current Parameter Pins P1.[7:4]; TDI/BRKIN/BRKOUT; TRST, TCK/DAP0; P1.[1:0]; P1.15; TESTMODE; ESR0; PORST; ESR1 P3.[10:0]; P3.[15:14] P3.[13:11]; P0.[3:0]; P0.[11:8] P6.[3:0]; P2.[13:8]; P0.[5:4]; P0.[13:12] P0.[7:6]; P0.[15:14]; P5.[7:0]; P5.15
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
5.2.1
Table Parameter
Parameters Input/Output Pins
Input/Output DC-Characteristics (Operating Conditions apply) Symbol Min. Values Typ. Max. Unit Note Test Condition
General Parameters Pull-up current1) Pull-down current1) capacitance1) (Digital I/O) Input voltage |IPUH| |IPDL|
VIHAmin;
class A1/A2/F/Input pads.
>VILAmax;
class A1/A2/F/Input pads.
Whatever lower
Input only Pads (VDDP 3.13 3.47
VILI
-0.3 0.62 VDDP
0.36
Input high voltage VIHI
VDDP VDDP+
max.
Ratio VIL/VIH
0.58
Whatever lower
Input high voltage VIHJ 0.64 TRST, VDDP
VDDP+ max.
±3000 ±6000
Input hysteresis Input leakage current2)
HYSI
VDDP
IOZI
((VDDP/2)-1) ((VDDP/2)+1) Otherwise
Spike filter always tSF1 blocked pulse duration
V1.2, 2009-05
TC1767
CONFIDENTIAL Table Parameter Spike filter passthrough pulse duration Electrical Parameters
Input/Output DC-Characteristics (cont'd)(Operating Conditions apply) Symbol Min. Values Typ. Max. Unit Note Test Condition
tSF2
Class Pads (VDDP 3.13 3.47 3.3V Output voltage VOLA
2)3)
medium
strong driver mode,
weak
driver mode Output high voltage2)
VOHA
medium
strong driver mode, -500 weak driver mode
VDDP
-1.4 medium strong driver mode, -400 weak driver mode
Whatever lower
Input voltage Class A1/2 pins
VILA
-0.3
0.36
Input high voltage VIHA1 0.62 Class pins VDDP
VDDP VDDP+
max.
Ratio VIL/VIH
0.58
Whatever lower
Input high voltage VIHA2 0.60 Class pins VDDP
VDDP+
max.
Ratio VIL/VIH Input hysteresis Input leakage current Class pins
0.60 HYSA VDDP
±3000 ±6000
IOZA2
((VDDP/2)-1) ((VDDP/2)+1) Otherwise2)
V1.2, 2009-05
TC1767
CONFIDENTIAL Table Parameter Input leakage current Class pins Electrical Parameters
Input/Output DC-Characteristics (cont'd)(Operating Conditions apply) Symbol Min. Values Typ. Max. ±500 <VIN VDDP Unit Note Test Condition
IOZA1
Class Pads, LVDS Mode (VDDP 3.13 3.47 3.3V Output voltage Output high voltage 1525 1325 0.36 Parallel termination Parallel termination Parallel termination Parallel termination Whatever lower
Output differential voltage Output offset voltage
1075
-0.3
Output impedance Input voltage Class pins
Class Pads, CMOS Mode (VDDP 3.13 3.47 3.3V
VILF
Input high voltage VIHF Class pins VDDP Input hysteresis Class pins Input leakage current Class pins
VDDP VDDP+
HYSF 0.05 VDDP
±3000 ±6000
((VDDP/2)-1) ((VDDP/2)+1) Otherwise2)
IOZF
Output voltage VOLF Output high voltage2) Class Pads Characteristics
-1.4
VOHF
subject production test, verified design characterization. Only these parameters tested, other verified design characterization
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
Maximum resistance driver RDSON, defined P_MOS N_MOS transistor separately: strong driver mode, medium driver mode, weak driver mode, verified design characterization. Function verified design, value verified design characterization. Hysteresis implemented avoid metastable states switching internal ground bounce. cannot guaranteed that suppresses switching external system noise. following constraint applies LVDS pair used CMOS mode: only pair should used output, other should used input, both pins should used inputs. Using both pins outputs recommended because higher crosstalk between them.
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
5.2.2
Analog Digital Converters (ADC0/ADC1)
parameters optimized valid range VDDM Table Parameter Analog supply voltage Characteristics (Operating Conditions apply) Symbol Min. Values Typ. Max. 5.25 3.471) 1.58
Unit
Note Test Condition Power supply digital part, internal supply
VDDM
4.75 3.13 1.42
Analog ground voltage
VSSM
-0.1
Analog reference VAREFx VAGNDx+1 voltage14) Analog reference VAGNDx VSSMx ground14) 0.05V Analog input voltage range
VDDM VDDM+
0.05
1)3)4)
±1.5 ±1.5 ±0.5
VAREF
VAIN
VAGNDx
VAREFx
Analog reference VAREFxVDDM/2 voltage range5)14) VAGNDx Converter Clock Internal clocks Sample time
VDDM 0.05 ±3.0 ±3.0 ±3.5
fADC fADCI
TADCI
12-bit conversion, without noise7)8) 10-bit conversion8) 8-bit conversion8) 12-bit conversion without noise8)10) 12-bit conversion without noise8)10) 12-bit conversion without noise8)10)
V1.2, 2009-05
Total unadjusted error5)
error9) error9)5) Gain error9)5)
EADNL
EAINL EAGAIN
TC1767
CONFIDENTIAL Table Parameter Offset error9)5) Electrical Parameters
Characteristics (cont'd) (Operating Conditions apply) Symbol Min. Values Typ. ±1.0 Max. ±4.0 ±1.5 -300 -100 -100 Unit Note Test Condition 12-bit conversion without noise8)10) VDDM) VDDM) VDDM) (97% VDDM) (97% VDDM) (100% VDDM) VAREF VDDM, conversion running VAREF
EAOFF
Input leakage IOZ1 current analog inputs ADC0/1
Input leakage current VAREF0/1, module Input current VAREF0/114), module Total capacitance voltage reference inputs16)14) Switched capacitance positive reference voltage input14) Resistance reference voltage input path16) Total capacitance analog inputs16)
IOZ2
IAREF
VDDM15)
CAREFTOT
CAREFSW
8)17)
RAREF
1000
increased AN[1:0] used reference input8)
6)8)
CAINTOT
V1.2, 2009-05
TC1767
CONFIDENTIAL Table Parameter Switched capacitance analog voltage inputs Electrical Parameters
Characteristics (cont'd) (Operating Conditions apply) Symbol Min. Values Typ. Max. Unit Note Test Condition
8)18)
CAINSW
resistance RAIN transmission gates analog voltage path resistance test (pull-down AIN7)
1500
RAIN7T
90019)
Test feature available only AIN7 Test feature available only AIN78)
Current through IAIN7T resistance test (pulldown AIN7)
peak
Voltage overshoot permissible Power-Up PORST low, provided pulse duration less than cumulated summary pulses does exceed Voltage overshoot permissible Power-Up PORST low, provided pulse duration less than cumulated summary pulses does exceed running conversion become inexact case violating normal operating conditions (voltage overshoot).
VAREF increases VDDM decreases, that reference voltage VAREF (VDDM 0.05 VDDM 0.07 then accuracy decreases LSB12. reduced reference voltage range VDDM/2 VDDM used, then converter errors increase.
reference voltage reduced with factor (k<1), then TUE, DNL, Gain Offset errors increase with factor 1/k. reduced reference voltage range VDDM/2 used, then there additional decrease speed accuracy. tested VAREF VAGND VDDM module capability. subject production test, verified design characterization. DNL/INL/Gain/Offset errors does exceed related total unadjusted error. 10-bit conversions DNL/INL/Gain/Offset error values must multiplied with factor 0.25. 8-bit conversions DNL/INL/Gain/Offset error values must multiplied with 0.0625. leakage current definition continuous function, shown Figure 5-3. numerical values defined determine characteristic points given continuous linear approximation they define step function.
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
Only these parameters tested, other verified design characterization. leakage current decreases typically junction temperature decrease 10oC. Applies AINx, when used auxiliary reference inputs. IAREF_MAX valid minimum specified conversion time. current flowing during conversion with duration 25µs calculated with formula IAREF_MAX QCONV/tC. Every conversion needs total charge QCONV 150pC from VAREF. conversions with duration longer than 25µs consume IAREF_MAX 6µA. definition parameters also Figure 5-2. This represents equivalent switched capacitance. This capacitance switched reference voltage once. Instead this smaller capacitances successively switched reference voltage. sampling capacity conversion C-Network pre-charged VAREF/2 before sampling moment. Because parasitic elements voltage measured AINx deviate from VAREF/2, typically 1.35V. RAIN7T 1400 maximum typical VDDM 3.3V± range. current limited operational lifetime.
clock generation kernel interrupts, etc. fADC divider fADCI
analog clock ADCI
divider ADCD
digital clock
fADCD arbiter
ADC_clocking
registers
analog part
Figure
ADC0/ADC1 Clock Circuit
V1.2, 2009-05
TC1767
CONFIDENTIAL Table Parameter Conversion Time (Operating Conditions apply) Symbol Value Unit Note conversion TADC fADC TADCI fADCI TADC TADCI Electrical Parameters
Conversion time with post-calibration
Conversion time without post-calibration
TADC TADCI
REXT
RAIN,
Analog Input Circuitry
VAIN
CEXT CAINTOT CAINSW VAGNDx RAIN7T
CAINSW
Reference Voltage Input Circuitry
VAREFx VAREF VAGNDx
RAREF,
CAREFTOT CAREFSW
CAREFSW
Analog_InpRefDiag
Figure
ADC0/ADC1 Input Circuits
300nA 200nA 100nA 100%
Figure
ADC0/ADC1Analog Inputs Leakage
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
5.2.3
Fast Analog Digital Converter (FADC)
parameters apply FADC used differential mode, which default intended mode operation, which takes advantage many error cancelation effects inherent differential measurements general. Table Parameter error error Gradient error9) FADC Characteristics (Operating Conditions apply) Symbol Min. Values Typ. Max. ±203) ±903) 3.474) 1.585) 3.474)6) Unit Note Test Condition
EFDNL EFINL EFGRAD
Without calibration gain Without calibration gain With calibration1) Without calibration Nominal
Offset error9)1) Reference error internal VFAREF/2 Analog supply voltages Analog ground voltage Analog reference voltage Analog reference ground
EFOFF2) EFREF
VDDMF 3.13 VDDAF 1.42 -0.1 VSSAF
VFAREF
3.13
VFAGND
VSSAF
0.05
VSSAF
0.05
Analog input voltage VAINF range Analog supply currents Input current
VFAGND
VDDMF
±500
IDDMF IDDAF IFAREF
VFAREF
Independent conversion VDDMF VDDMF
Input leakage current IFOZ2 VFAREF Input leakage current IFOZ3 VFAGND
V1.2, 2009-05
TC1767
CONFIDENTIAL Table Parameter Conversion time Electrical Parameters
FADC Characteristics (Operating Conditions apply) (cont'd) Symbol Min. Values Typ. Max. Unit Note Test Condition 10-bit conv.
tC_FADC
fFADC
Converter clock Input resistance analog voltage path (Rn, Channel amplifier cutoff frequency9) Settling time channel amplifier (after changing channel amplifier input)9)
fFADC RFAIN
fCOFF
tSET
Calibration should performed each power-up. case continuous operation, calibration should performed minimum once week, regular basis order compensate temperature changes. offset error voltage drifts over whole temperature range maximum LSB. Applies when gain channel equals one. other gain settings, offset error increases; must multiplied with applied gain. Voltage overshoots permissible, provided pulse duration less than cumulated summary pulses does exceed Voltage overshoots permissible, provided pulse duration less than cumulated pulses does exceed running conversion become inexact case violating normal operating conditions (voltage overshoots). Current peaks with duration max. occur This value applies power-down mode. subject production test, verified design characterization.
calibration procedure should after each power-up, when power supply voltages reference voltage have stabilized.
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
FADC Analog Input Stage FAINxN VFAREF
VFAGND
FAINxP
FADC Reference Voltage Input Circuitry VFAREF VFAREF VFAGND IFAREF
FADC_InpRefDiag
Figure
FADC Input Circuits
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
5.2.4
Table Parameter
Oscillator Pins
Oscillator Pins Characteristics (Operating Conditions apply) Symbol Min. Values Typ. Max. Unit Note Test Condition External Crystal Mode selected VDDOSC3
Frequency range Input voltage XTAL11) Input high voltage XTAL11) Input current XTAL1
fOSC VILX -0.2
VIHX VDDOSC3 IIX1
VDDOSC3 VDDOSC3
XTAL1 driven crystal, reaching minimum amplitude (peak-to-peak) VDDOSC3 sufficient.
Note: strongly recommended measure oscillation allowance (negative resistance) final target system (layout) determine optimal parameters oscillator operation. Refer limits specified crystal supplier.
5.2.5
Table 5-10 Parameter
Temperature Sensor
Temperature Sensor Characteristics (Operating Conditions apply) Symbol Unit Note Test Condition Min. Typ. Max. Junction temperature Calibrated Values
Temperature sensor range Temperature sensor measurement time Start-up time after reset Sensor accuracy
tTSMT tTSST TTSA
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
following formula calculates temperature measured [oC] from RESULT bitfield DTSSTAT register. (5.1) DTSSTAT RESULT
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
5.2.6
Power Supply Current
default test conditions (differences explicitly specified) are: 1.58 VDDP 3.47 Tj=150oC. other operating conditions apply. Table 5-11 Parameter Core active mode supply current Realistic core active mode supply current FADC analog supply current FADC analog supply current Flash memory supply current Power Supply Currents, Maximum Power Consumption Symbol Values Min. Typ. Max. Unit Note Test Condition
fCPU=133 fCPU/fSYS 1.53 150oC
continuously reading Flash memory Flash memory erase-verify6) total pairs
IDDMF IDDAF IDDFL3R
IDDFL3E
Oscillator supply Oscillator supply LVDS supply currents,sum VDDP supplies
IDDOSC IDDOSC3 ILVDS IDDP IDDP_FP
IDDP including Data
Flash programming current
power supply Maximum Average Power Dissipation1)
IDDM
ADC0
worst case 125oC, 25oC
Infineon Power Loop: running, peripherals active. power consumption each custom application will most probably lower than this value, must evaluated separately. decreases typically fCPU decreased MHz, constant 150oC, Infineon Power Loop. dependency this range constant junction temperature, linear.
V1.2, 2009-05
TC1767
CONFIDENTIAL Electrical Parameters
decreases typically fC
Other recent searches
VCO190-768U - VCO190-768U VCO190-768U Datasheet
SOT763-1 - SOT763-1 SOT763-1 Datasheet
QM800HA-24B - QM800HA-24B QM800HA-24B Datasheet
MF0064M-07BTxx - MF0064M-07BTxx MF0064M-07BTxx Datasheet
MF0128M-07BTxx - MF0128M-07BTxx MF0128M-07BTxx Datasheet
MF0256M-07BTxx - MF0256M-07BTxx MF0256M-07BTxx Datasheet
MF0512M-07BTxx - MF0512M-07BTxx MF0512M-07BTxx Datasheet
MF0640M-07BFxx - MF0640M-07BFxx MF0640M-07BFxx Datasheet
LBN140A46 - LBN140A46 LBN140A46 Datasheet
KM2520CGCK03 - KM2520CGCK03 KM2520CGCK03 Datasheet
Privacy Policy | Disclaimer
© 2013 Datasheets.org.uk