TAS5100EVM
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Evaluation Module TAS5100 Digital Audio Power Output Stage
User's Guide
Digital Audio/Application
SLEU009B
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Mailing Address:
Texas Instruments Post Office 655303 Dallas, Texas 75265 Copyright 2003, Texas Instruments Incorporated
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Running Title-Attribute Reference IMPORTANT NOTICE Texas Instruments (TI) provides enclosed product(s) under following conditions: This evaluation being sold intended ENGINEERING DEVELOPMENT EVALUATION PURPOSES ONLY considered commercial use. such, goods being provided complete terms required design-, marketing-, and/or manufacturing-related protective considerations, including product safety measures typically found product incorporating goods. prototype, this product does fall within scope European Union directive electromagnetic compatibility therefore meet technical requirements directive. Should this evaluation meet specifications indicated User's Guide, returned within days from date delivery full refund. FOREGOING WARRANTY EXCLUSIVE WARRANTY MADE SELLER BUYER LIEU OTHER WARRANTIES, EXPRESSED, IMPLIED, STATUTORY, INCLUDING WARRANTY MERCHANTABILITY FITNESS PARTICULAR PURPOSE. user assumes responsibility liability proper safe handling goods. Further, user indemnifies from claims arising from handling goods. Please aware that products received regulatory compliant agency certified (FCC, etc.). open construction product, user's responsibility take appropriate precautions with regard electrostatic discharge. EXCEPT EXTENT INDEMNITY FORTH ABOVE, NEITHER PARTY SHALL LIABLE OTHER INDIRECT, SPECIAL, INCIDENTAL, CONSEQUENTIAL DAMAGES. currently deals with variety customers products, therefore arrangement with user exclusive. assumes liability applications assistance, customer product design, software performance, infringement patents services described herein. Please read User's Guide and, specifically, Warnings Restrictions notice User's Guide prior handling product. This notice contains important safety information about temperatures voltages. further safety concerns, please contact application engineer. Persons handling product must have electronics training observe good laboratory practice standards. license granted under patent right other intellectual property right covering relating machine, process, combination which such products services might used.
Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
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Running Title-Attribute Reference WARNINGS RESTRICTIONS important operate this within specified input output ranges described User's Guide. Exceeding specified input range cause unexpected operation and/or irreversible damage EVM. there questions concerning input range, please contact field representative prior connecting input power. Applying loads outside specified output range result unintended operation and/or possible permanent damage EVM. Please consult User's Guide prior connecting load output. there uncertainty load specification, please contact field representative. During normal operation, some circuit components have case temperatures greater than 60°C. designed operate properly with certain components above 60°C long input output ranges maintained. These components include limited linear regulators, switching transistors, pass transistors, current sense resistors. These types devices identified using schematic located User's Guide. When placing measurement probes near these devices during operation, please aware that these devices very warm touch. Mailing Address: Texas Instruments Post Office 655303 Dallas, Texas 75265
Copyright 2003, Texas Instruments Incorporated
Preface
Read This First
About This Manual
This manual describes operation TAS5100EVM evaluation module from Texas Instruments.
This Manual
This document contains following chapters:
Chapter Introduction Chapter Description Board Chapter Board Operation Overview Chapter Hints Performance Measurements Chapter Electrical Specifications Typical Characteristics Graphs
Information About Cautions Warnings
This book contain cautions warnings.
This example caution statement. caution statement describes situation that could potentially damage your software equipment.
This example warning statement. warning statement describes situation that could potentially cause harm you.
Read This First
information caution warning provided your protection. Please read each caution warning carefully.
Related Documentation From Texas Instruments
following list data manual that have detailed descriptions integrated circuits used design TAS5100 EVM. data manuals obtained http://www.ti.com. Part Number TAS5001PFB TAS5010PFB TAS5100ADAP TAS3002PFB DIR1703E LMV311IDBVR SN74LVU04APWR SN74LVC1GU04DBVR SN74AHC1G08DBVR SN74LVC08APWR SN74LVC1G14DBVR SN74LVC1G32DBVR SN74LV123APWR SN74LV132APWR TPS3705-33DGN TPS75333QPWP TPS76433DBVR Literature Number SLES009 SLAS328 SLES030 SLAS307 SLES007 SLCS136 SCES130 SCES215 SCLS314 SCAS283 SCES218 SCES219 SCLS393 SCLS394 SLVS184 SLVS241 SLVS180
Additional TAS5100EVM Documentation
CD-ROM attached TAS5100EVM package includes following documentation:
TAS5100EVM User's Guide (SLEU009) (this document) TAS5100EVM Design Document (SLEU010) (schematic, parts list,
layout)
TAS5100EVM Data
Report (SLEU011) (audio performance
efficiency)
TAS5100EVM Test Report (SLEU012) TAS5100EVM Gerber Files Audio Precision Test Files (require AES17 filter installed
measurement equipment)
Software User's Guide Application Notes Data Manuals
Photograph TAS5100EVM
Components included TDAA reference design surrounded with white line PCB.
Trademarks
Equibit trademark Texas Instruments
Read This First
Contents
Introduction TAS5100EVM Features Description Board Board Outline With Connectors, Switches, Jumpers, Indicators Description Jumper Settings 2.3.1 JMP160: Controls Double-Speed TAS51010 2.3.2 JMP280: Enable/Disable UNLOCK Signal From S/PDIF Receiver 2.3.3 JMP360: Bypass Equalizer Function Digital Audio Processor 2.3.4 Default Jumper Positions Description Connectors 2.4.1 S/PDIF Digital Audio Coax/RCA Input (J100) 2.4.2 S/PDIF Optical (J100) 2.4.3 Connector (J140) 2.4.4 Analog Input (J150) 2.4.5 Analog Output (J360) 2.4.6 Interface (J300) 2.4.7 Loudspeaker Connectors (J540, J541, J580, J581) 2.4.8 Power Supply Connector (J640) Description Switches Buttons 2.5.1 S/PDIF Input Selector Switch (S100) 2.5.2 Bypass Digital Audio Processor Switch (S320) 2.5.3 Reset Board Button (S680) 2.5.4 Mute Button (S200) 2.5.5 Volume Control (S340 S341) Description Indicators 2-10 2.6.1 Power (LED242) 2-10 2.6.2 S/PDIF Input (LED241) 2-10 2.6.3 Protection (LED240) 2-10 Board Operation Overview Powering TAS5100EVM 3.1.1 Powering With Power Supply 3.1.2 Powering With External Power Supplies 3.1.3 Recommended Power-Up Power-Down Sequence Setting TAS5100EVM With S/PDIF Input 3.2.1 Start-Up Sequence Setting TAS5100EVM With Analog Line Input
Contents
Interfacing Analog Line Output Controlling With Software
Hints Performance Measurements Electrical Specifications Typical Characteristics Graphs TAS5100 Electrical Specifications Physical Specifications Typical Characateristics Graphs
Figures
5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 Simplified TAS5100EVM Block Diagram TAS5100EVM Outline With Reference Designators Connectors, Switches, Jumpers, Indicators Physical Structure TAS5100EVM (Rough Outline) Default Jumper Positions Numbers Interface (J140) Numbers Line Input Connector Line Output Connector Numbers J360 Numbers Parallel Port Interface/I2C Interface (J300) Numbers Connector (J640) (Top View) Recommended Power-Up Power-Down Sequence Board Connected S/PDIF Sources Personal Computer THD+N Frequency Left Channel THD+N Frequency Right Channel THD+N Power Left Channel THD+N Power Right Channel Signal-to-Noise With 1-kHz Signal Left Channel Signal-to-Noise With 1-kHz Signal Right Channel 30-W Output Power Left Channel 30-W Output Power Right Channel Noise Floor Left Channel Noise Floor Right Channel Channel Separation Left Channel Channel Separation Right Channel Channel Separation Left Channel Channel Separation Right Channel Frequency Response Left Channel 5-10 Frequency Response Right Channel 5-10 Peak Current Left Channel 5-11 Amplifier Efficiency Total Delivered Power 5-11 Power Losses Amplifier Total Delivered Power 5-12
Tables
Interface Connections J150 Description J360 Description J300 Description Description Loudspeaker Connectors J640 Description
Tables
Chapter
Introduction
TAS5100 customer evaluation module (EVM) demonstrates integrated circuits: TAS5010 TAS5100 from Texas Instruments (TI). TAS5010 cost-effective, high performance 24-bit stereo digital modulator based Equibit technology. This converts input serial digital audio data pulse width modulated (PWM) audio data stream. TAS5010 modulator accepts sample rates kHz. Maximum sample rate TAS5001 kHz. Pinouts identical both modulators. TAS5010 designed implemented with TAS5100 true digital output stage driving loudspeaker. Together TAS5010 TAS5100s provide complete conversion 3.3-V digital audio input stream into loudspeakers impedance range. chipset ideal applications requiring excellent audio quality, minimum size weight, high power efficiency. chipset used range products such microcomponent systems, home theater box, receivers, sets. TAS5100EVM complete true digital amplifier including S/DIF receiver, audio interface, volume control, interface personal computer through parallel port, required control logic. TDAA reference design surrounded with white line PCB.
Topic
Page
TAS5100EVM Features
Introduction
TAS5100EVM Features
TAS5100EVM Features
TDAA reference design (double-sided plated-through layout) S/PDIF receiver with coaxial optical input (sampling rate:
kHz-96 kHz)
audio interface (sampling rate: kHz-192 kHz) Onboard volume control Auto-mute function Self-contained protection system (short circuit thermal) Digital audio processor (DAP), which includes 24-bit volume control,
digital gain, bass treble control, parametric equalization, dedicated speaker equalization, loudness control, adjustable dynamic range compression/expansion.
control through software (DCT software from Default settings downloaded EEPROM with
software.
Analog line input (use internal analog-to-digital converter DAP)
Figure 1-1. Simplified TAS5100EVM Block Diagram
Software Parallel Port Interface Analog Input Analog Output Optical Input kHz-96 Coaxial Input DIR1703 S/PDIF Receiver TAS3002 Digital Audio Processor TAS5010 Digital Audio Processor Volume Control
TAS5100 Digital Audio Power Output Stage
Input kHz-192
Interface
TAS5100 Digital Audio Power Output Stage
DIR1703 from used S/PDIF receiver system clock generator. DIR1703 digital audio interface receiver (DIR) which receives decodes audio data 96-kHz sampling rate. DIR1703 running configuration where automatically switches between mode crystal mode. When DIR1703 connected active digital source, running mode. System clock (SCKO) frequency depends incoming sampling rate (fs): SCKO When digital source represented, DIR1703 switches crystal mode. system clock crystal mode depends external crystal. TAS5100EVM board, crystal-mode system clock 12.288 MHz.
TAS5100EVM Features
Crystal-mode operation used generate fixed clock when TAS5100EVM board connected analog source. external antialiasing filter converter optimized onboard 48-kHz sampling rate. TAS3002 from Texas Instruments used digital audio processor (DAP). features controlled through interface. Adjustment sound level executed through with push buttons board. During power TAS3002 settings coefficients loaded from external serial EEPROM. TAS3002 coefficients control features DAP. Customized start-up settings downloaded EEPROM. This operation easy execute with personal computer, software, cable between TAS5100EVM computer. TAS5100EVM connected port computer.
Introduction
Chapter
Description Board
This chapter describes TAS5100EVM board layout, jumpers, switches, buttons, connectors.
Topic
Page
Board Outline With Connectors, Switches, Jumpers, Indicators Description Jumper Settings Description Connectors Description Switches Buttons Description Indicators 2-10
Description Board
Board Outline With Connectors, Switches, Jumpers, Indicators
Board Outline With Connectors, Switches, Jumpers, Indicators
Figure 2-1. TAS5100EVM Outline With Reference Designators Connectors, Switches, Jumpers, Indicators
S/PDIF Input Power Protection LED240 Auto Sample-Rate Control J640 S200 Mute Equalizer Enable S680 Reset J540 Connector JMP360 Disable Enable
LED242 Connector J300 D/A-Converter Output J360
S/PDIF Reset Enable
LED241
Optical
A/D-Converter Input
J150 Coax
Speaker Left
J541
S/PDIF Digital Audio Optical Toslink Input
S100 J101 S320 Bypass Active
Switch Between Optical Coax Input Bypass Digital Audio Processor J140 Interface Speaker Right J580
S/PDIF Digital Audio Coax Input
J100
S341
S340
J581
Volume Control
NOTE: Indicates default jumper position.
physical structure TAS5100EVM illustrated Figure 2-2. Block headings refer page headings TAS5100EVM schematic.
Figure 2-2. Physical Structure TAS5100EVM (Rough Outline)
CONTROL SECTION
POWER SUPPLY SECTION
DIGITAL AUDIO PROCESSOR SECTION
TAS5010 TAS5100 REFERENCE DESIGN AUDIO INPUT SECTION MODULATOR SECTION OUTPUT STAGE SECTION
Description Board
Description Jumper Settings
Description Jumper Settings
There tree jumpers board (J140 interface-see description Section 2.4.3).
2.3.1
JMP160: Controls Double-Speed TAS51010
JMP160 used double-speed TAS5010 (DBSPD, 39). DBSPD connected TAS5010 single-speed mode DBSPD connected TAS5010 double-speed mode. Single-speed mode required 32-kHz, 44.1-kHz, 48-kHz, 192-kHz sampling rates. Double-speed mode required 88-kHz 96-kHz sampling rates. S/PDIF receiver automatically controls DBSPD JMP160 shunts (default setting). JMP160 shunts TAS5010 single-speed mode. JMP160 shunts TAS5010 doublespeed mode.
2.3.2
JMP280: Enable/Disable UNLOCK Signal From S/PDIF Receiver
JMP280 used disable UNLOCK warning signal from S/PDIF receiver. UNLOCK signal high until DIR1703 detects locks incoming digital signal. warning signal used shut down output stage (the H-bridge stop switching). obtain click reduced shutdown, necessary mute output stage before reset TAS5010 pulled down. When board connected analog source digital source through interface, necessary disable UNLOCK warning. This done with JMP280 jumper. When JMP280 shunts UNLOCK warning enabled (default setting). shunts warning signal disabled.
2.3.3
JMP360: Bypass Equalizer Function Digital Audio Processor
JMP360 used disable equalizer function DAP. equalizer function enabled JMP360 shunts equalizer disabled when JMP360 shunts Note: Bass treble control bypassed when equalizer bypassed.
2.3.4
Default Jumper Positions
Default jumper positions illustrated Figure 2-3.
Description Connectors
Figure 2-3. Default Jumper Positions
JMP160 J640 J300 JMP280
J360
JMP360
J540
J150 J541
J101 J580 J140 J100 J581
Description Connectors
2.4.1 S/PDIF Digital Audio Coax/RCA Input (J100)
connector connected digital S/PDIF source through coaxial cable with characteristic impedance (e.g. RG59 cable). Maximum sampling rate this input kHz.
2.4.2
S/PDIF Optical (J100)
Toslink connector connected digital S/PDIF signal through optical cable. Maximum sampling rate this input kHz.
2.4.3
Connector (J140)
connector interfaces directly with TAS5010. Jumpers needed normal operation using S/PDIF input signal. When connector used, signal path. Maximum sampling rate this input kHz.
Figure 2-4. Numbers Interface (J140)
J140
Note:
Rectangles indicate default jumper positions.
Description Board
Description Connectors
Table 2-1. Interface Connections
Description System master clock input (256 Audio clock input Left/right clock input (fs) data input Reset output stage input (active low) Name TAS5100EVM Schematic TA50XX-MCLK TA50XX-SCLK TA50XX-LRCLK TA50XX-SDATA RESET-I2S-INTERFACE
serial interface adaptor (SIA-2322) from audio precision connected interface. Note: unlock signal from S/PDIF must disabled (JMP280) when interface connected external source.
2.4.4
Analog Input (J150)
Analog sources connected converter through J150. analog line input optimized input signal with maximum voltage VRMS.
Figure 2-5. Numbers Line Input Connector Line Output Connector (Top View)
J150
Table 2-2. J150 Description
Description Left channel input Ground Right channel input
2.4.5
Analog Output (J360)
Analog output from digital audio processor available connector. maximum output level VRMS.
Figure 2-6. Numbers J360
J360
Description Connectors
Table 2-3. J360 Description
Description Left channel output Ground Right channel output
2.4.6
Interface (J300)
interface, using attached special cable parallel/printer port makes possible control TAS3002 digital audio processor totally from using special EQ-GUI software saved TDAA CD-ROM.
Figure 2-7. Numbers Parallel Port Interface/I Interface (J300)
J300
Table 2-4. J300 Description
Note:
Description Power reset Serial data line (SDA) Serial clock line (SCL) Serial data line Serial clock line used Serial data line Serial clock line
Output Bidirectional Bidirectional Input Output Output Input
Name Schematics POWER-ON-RESET SDA-BI SCL-BI SDA-IN SCL-OUT SDA-OUT SCL-IN
(SDA) (SCL) used communication between external microcontroller digital audio processor.
connector also used control TAS3002 from external microcontroller your choice.
2.4.7
Loudspeaker Connectors (J540, J541, J580, J581)
speaker connectors accept standard plugs. high quality plugs speaker cable recommended. Caution Both positive negative speaker outputs floating connected ground (e.g. through oscilloscope).
Description Board
Description Switches Buttons
Table 2-5. Description Loudspeaker Connectors
J540 J541 J580 J581 Description Left speaker positive output terminal Left speaker negative output terminal Right speaker positive output terminal Right speaker negative output terminal
2.4.8
Power Supply Connector (J640)
Figure 2-8. Numbers Connector (J640) (Top View)
J640
Table 2-6. J640 Description
Description Supply voltage output stage (VHBR) Supply voltage control gate-drive (V+) Ground Ground Name Schematics Power output stage
Description Switches Buttons
2.5.1 S/PDIF Input Selector Switch (S100)
S100 switches between optical coaxial S/PDIF input. When lever pressed direction J101, optical S/PDIF input selected. When lever pressed direction output stage, coaxial S/PDIF input selected.
2.5.2
Bypass Digital Audio Processor Switch (S320)
When lever pressed direction J101, bypassed. When lever pressed direction output stage, signal path. Below S320 label (DAP ON), which indicates position lever inserted signal path. Warning Bypassing equal maximum output power (attenuation dB). This might loud could possibly damage your loudspeakers ears.
Description Switches Buttons
2.5.3
Reset Board Button (S680)
Master reset board. While this button held down, DIR1703, TAS3002, TAS5010, TAS5100 held reset latching errors cleared. Note that while RESET button held down, S/PDIF Input lights even valid S/PDIF input signal present because DIR1703 S/PDIF receiver held reset.
2.5.4
Mute Button (S200)
output stage mutes when mute button pressed down unmutes when mute button released.
2.5.5
Volume Control (S340 S341)
Volume control TAS3002 controlled S340 S341. Press hold S341 button decrease output power level. Press hold S340 button increase output power level. Note: Change listening level slow. takes approximately seconds change attenuation from TAS3002 device implements soft volume control. This feature allows change from volume level another over entire range volume control mute). Above there risk signal clipping. Distortion output signals result signal clipping. Note: Significant signal clipping might result activation current protection system.
Description Board
Description Indicators
Description Indicators
2.6.1 Power (LED242)
green indicates that TAS5100 board control circuit powered
2.6.2
S/PDIF Input (LED241)
yellow indicates that S/PDIF input signal missing. Reasons S/PDIF warning:
lever S/PDIF input selector switch (S100) placed wrong
position.
S/PDIF signal missing. Some players remove S/PDIF
output signal when drawer opened. Note: When UNLOCK signal from S/PDIF receiver disabled (JMP280 shunted yellow disabled.
2.6.3
Protection (LED240)
indicates that protection circuit engaged output shutdown mode. There four reasons shutdown mode.
speaker terminals shorted. amplifier constantly overloaded (decrease volume level). Speaker terminal shorted ground (e.g. through oscilloscope). Output stage thermal shutdown.
Check setup board carefully remove causing failure before pressing RESET (S680) disengage protection mode.
2-10
Chapter
Board Operation Overview
This chapter describes TAS5100EVM board operation.
Topic
Page
Powering TAS5100EVM Setting TAS5100EVM With S/PDIF Input Setting TAS5100EVM With Analog Line Input Interfacing Analog Line Output Controlling With Software
Board Operation Overview
Powering TAS5100EVM
Powering TAS5100EVM
TAS5100EVM powered from external power supplies. High-end audio performance requires stabilized power supply with ripple voltage output impedance. Note: length power supply cable must minimized. Increasing length cable equal increasing distortion amplifier high output levels frequencies.
3.1.1
Powering With Power Supply
single power supply connected TAS5100EVM board. Short VHBR power cable (red white plugs). Voltage connected power supply allowed below Maximum supply voltage depends speaker load resistance. Check recommended maximum supply voltage TAS5100 data sheet (SLLS419).
Supply voltage (VHBR V-20 V-23 V-26
3.1.2
Powering With External Power Supplies
When powering TAS5100EVM with power supplies, possible adjust listening level with level voltage VHBR (pin J640). Minimum VHBR voltage Maximum voltage depends load resistance. Check recommended maximum supply voltage TAS5100 data sheet (SLS419).
Maximum VHBR voltage voltage V-27 V-27 V-27
3.1.3
Recommended Power-Up Power-Down Sequence
Figure shows recommended power-up power-down sequence.
Figure 3-1. Recommended Power-Up Power-Down Sequence
VHBR
Setting TAS5100EVM With S/PDIF Input
Setting TAS5100EVM With S/PDIF Input
Connect board shown Figure 3-2. Select between coaxial optical input signal input selector switch (S100). Press lever S320 direction output stage TAS3002 wanted signal path (recommended during normal listening tests). There attenuation bypassed. signal path, start volume level depends what programmed serial EEPROM board. Default startup volume level initially programmed below full scale, which some speakers still loud. default volume level changed with software
Board Operation Overview
Setting TAS5100EVM With S/PDIF Input
Notes:
Figure 3-2. Board Connected S/PDIF Sources Personal Computer
S/PDIF Input (Yellow)
Power (Green)
Protection (Red)
LED242
LED241
LED240
Disable
J150 Optical Coax
Enable
Bypass
Active
Speakers, power supply, required cable communication initially connected board.
jumpers default position.
with Software Control: Volume Bass, Treble, Loudness Equalizer Loudness -Etc.
Power Supply
Power Supply
Auto Sample-Rate Control
J640 VHBR
J300 Attached cable interface parallel printer port J360
S200 Mute Equalizer Enable S680 Reset
JMP360
J540 Green
J541 Blue
Speaker Left
S/PDIF Optical Toslink Cable J101
S100 S320
Switch Between Optical Coax Input Bypass Digital Audio Processor J140 Interface J580 Green
J100 S/PDIF Coaxial Cable
J581 S341 S340 Blue
Speaker Right
Volume Control
NOTE: Indicates default jumper position.
Setting TAS5100EVM With Analog Line Input
TAS5100EVM powered with either power supplies (see section 3.1). Power supplies initially switched off. Music player initially switched off. connection optional.
3.2.1
Start-Up Sequence
Turn power supply/supplies. Follow power-up power-down sequence described section 3.1. Observe that green power yellow illuminated. software from desktop activated (S320) attached cable connected from J300 Turn CD/DVD player play test Observe that yellow S/PDIF off. Observe digital audio coming from left right speaker.
Setting TAS5100EVM With Analog Line Input
Disable UNLOCK warning from S/PDIF receiver (JMP280: jumper shunts Connect TAS5100EVM board with attached cable. Connect analog source analog input (J150). Power TAS5100EVM board. Enable TAS3002 analog input with software. Disable TAS3002 digital input (both SDIN1 SDIN2) with software. TAS5100EVM board ready play with analog source.
Interfacing Analog Line Output
default analog line output (J360) being active. analog line output connected analog tape recorders analog amplifiers (e.g. subwoofer).
Controlling With Software
Operating instructions software described user's guide Digital Audio Processor (DAP) Configuration Tool Operating Instruction.
Board Operation Overview
Chapter
Hints Performance Measurements
Read Digital Audio Measurements application note, literature number SLAA114, introduction measurements true digital audio amplifiers. audio precision test files available TDAA CD-ROM. Note that AES17 filter required reach shown measurements. Specifications AES17 filter described standard method digital audio engineering-measurement digital audio equipment (the AES17 standard available from Audio Engineering Society- www.aes.org). When evaluating performance digital amplifier section, bypass digital audio processor with S320 adjust settings neutral attenuation Connect TAS5100EVM regulated power supply with cable. length cable must exceed meters.
Hints Performance Measurements
Chapter
Electrical Specifications Typical Characteristics Graphs
This chapter contains electrical specifications typical characteristics graphs.
Topic
Page
Electrical Specifications Physical Specifications Typical Characteristics Graphs
Electrical Specifications Typical Characteristics Graphs
TAS5100EVM Electrical Specifications
TAS5100EVM Electrical Specifications
General Test Conditions PARAMETER Power supply Load impedance S/PDIF sampling frequency Electrical Data Continuous output power Output stage efficiency Total board idle power consumption Rated load impedance Maximum peak current Damping factor Coaxial S/PDIF Input THD+N, THD+N, Dynamic range, A-weighted Channel separation Frequency response Analog Line Input THD+N, THD+N, Dynamic range, A-weighted Channel separation Frequency response Sensitivity Input impedance Analog Line Output Maximum output voltage Output impedance
Note:
TEST CONDITIONS Laboratory power supply (EA-PS 7065-10A)
44.1
UNIT
<0.09% THD+N, kHz, 25°C POUT
1-kHz burst kHz, load Reference: rated power, AES17 filter kHz, POUT
0.034% 0.079% 0.03% 0.08% 2.25 VRMS
Ref: rated power, AES17 filter kHz, POUT ±0.5
0.71
VRMS
electrical audio specifications typical values.
Physical Specifications
dimensions Aluminum plate dimension Board weight Total weight (3.35 5.12") Height Width (4.52 6.3") Height Width 0,15 (0.33 Components 0,25 (0.55 Components Mechanics
Typical Characteristics Graphs
Typical Characteristics Graphs
Figure 5-1. THD+N Frequency Left Channel
Power Supply Load Sample Frequency 44.1 Filter AES17 TAS3002: Bypassed, Coaxial Input
0.05
0.02
0.01
Frequency
Figure 5-2. THD+N Frequency Right Channel
Power Supply Load Sample Frequency 44.1 Filter AES17 TAS3002: Bypassed, Coaxial Input
0.05
0.02
0.01
Frequency
Electrical Specifications Typical Characteristics Graphs
Typical Characteristics Graphs
Figure 5-3. THD+N Power Left Channel
Power Supply Input Signal Load Sample Frequency 44.1 Filter AES17 TAS3002: Bypassed, Coaxial Input
0.05
0.02
0.01 400m 500m
Output Power
Figure 5-4. THD+N Power Right Channel
Power Supply Input Signal Load Sample Frequency 44.1 Filter AES17 TAS3002: Bypassed, Coaxial Input
0.05
0.02
0.01 400m 500m
Output Power
Typical Characteristics Graphs
Figure 5-5. Signal-to-Noise With 1-kHz Signal Left Channel
-100 -110 -120 -130 -140 Frequency Power Supply Input Signal Load Sample Frequency 44.1 Filter AES17 Size Reference: 13.7 Full Scale TAS3002: Bypassed, Coaxial Input
Figure 5-6. Signal-to-Noise With 1-kHz Signal Right Channel
-100 -110 -120 -130 -140 Frequency Power Supply Input Signal Load Sample Frequency 44.1 Filter AES17 Size Reference: 13.7 Full Scale TAS3002: Bypassed, Coaxial Input
Electrical Specifications Typical Characteristics Graphs
Typical Characteristics Graphs
Figure 5-7. 30-W Output Power Left Channel
-100 -110 -120 -130 Frequency Power Supply Input Signal Load Sample Frequency 44.1 Filter AES17 Size Reference: 13.7 Full Scale TAS3002: Bypassed, Coaxial Input
Figure 5-8. 30-W Output Power Right Channel
-100 -110 -120 -130 Frequency Power Supply Input Signal Load Sample Frequency 44.1 Filter AES17 Size Reference: 13.7 Full Scale TAS3002: Bypassed, Coaxial Input
Typical Characteristics Graphs
Figure 5-9. Noise Floor Left Channel
-100 -110 -120 -130 -140 Frequency Power Supply Input Signal Load Sample Frequency 44.1 Size Reference: 13.7 Full Scale TAS3002: Bypassed, Coaxial Input
Figure 5-10. Noise Floor Right Channel
-100 -110 -120 -130 -140 Frequency Power Supply Input Signal Load Sample Frequency 44.1 Size Reference: 13.7 Full Scale TAS3002: Bypassed, Coaxial Input
Electrical Specifications Typical Characteristics Graphs
Typical Characteristics Graphs
Figure 5-11. Channel Separation Left Channel
Right Output Left Output -100 Frequency Power Supply Input Left Channel Input Right Channel Load Sample Frequency 44.1 Filter AES17 Reference: 13.7 Full Scale TAS3002: Bypassed, Coaxial Input
Figure 5-12. Channel Separation Right Channel
Left Output Right Output -100 Frequency Power Supply Input Left Channel Input Right Channel Load Sample Frequency 44.1 Filter AES17 Reference: 13.7 Full Scale TAS3002: Bypassed, Coaxial Input
Typical Characteristics Graphs
Figure 5-13. Channel Separation Left Channel
-100 -110 -120 -130 -140 -150 Frequency Power Supply Input Left Channel Input Right Channel kHz, Load Sample Frequency 44.1 Filter AES17 Reference: 13.7 Full Scale TAS3002: Bypassed, Coaxial Input
Figure 5-14. Channel Separation Right Channel
-100 -110 -120 -130 -140 -150 Frequency Power Supply Input Left Channel kHz, Input Right Channel Load Sample Frequency 44.1 Filter AES17 Reference: 13.7 Full Scale TAS3002: Bypassed, Coaxial Input
Electrical Specifications Typical Characteristics Graphs
Typical Characteristics Graphs
Figure 5-15. Frequency Response Left Channel
-0.5 -1.5 -2.5 Frequency Load Load Load Power Supply Input Signal Output Power Sample Frequency 44.1 TAS3002: Bypassed, Coaxial Input
Figure 5-16. Frequency Response Right Channel
-0.5 -1.5 -2.5 Frequency Load Power Supply Input Signal Output Power Sample Frequency 44.1 TAS3002: Bypassed, Coaxial Input
Load Load
5-10
Typical Characteristics Graphs
Figure 5-17. Peak Current Left Channel
Power Supply Input Signal Load Sample Frequency 44.1 TAS3002: Bypassed, Coaxial Input
38.25 38.5 38.75 39.25 39.5 Time 39.75 40.25 40.5 40.75
Figure 5-18. Amplifier Efficiency Total Delivered Power
Total Delivered Power Into Loads (Both Channels) Power Supply Input Signal Load Sample Frequency 44.1 Output Stage Idle Loss Control Section Idle Loss Total Idle Power Consumption
Electrical Specifications Typical Characteristics Graphs
5-11
Typical Characteristics Graphs
Figure 5-19. Power Losses Amplifier Total Delivered Power
Power Supply Input Signal Load Sample Frequency 44.1 Output Stage Idle Loss Control Section Idle Loss Total Idle Power Consumption
Total Delivered Power Into Loads (Both Channels)
5-12
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