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Si8410/20/21 Si8422/23 (2.5
OWER, INGLE HANNEL IGITA
High-speed operation Mbps startup time Wide Operating Supply Voltage: 2.6-5.5 Ultra power (typical) Operation: mA/channel Mbps mA/channel Mbps 2.70 Operation: mA/channel Mbps mA/channel Mbps 100-year life rated working voltage High electromagnetic immunity
Precise timing (typical) propagation delay pulse width distortion channel-channel skew propagation delay skew minimum pulse width correct 5000 VRMS isolation Transient immunity: kV/µs start-up initialization required Wide temperature range: Mbps RoHS compliant packages SOIC-16 wide body SOIC-8
Assignments
Narrow Body SOIC VDD1 VDD2 GND1 GND2
View (Si842x)
GND1 VDD1
Applications
Industrial automation systems Medical electronics Hybrid electric vehicles Isolated switch mode supplies
Isolated ADC, Motor control Power inverters
GND1
Wide Body SOIC
View (Si842x)
GND2 VDD2 GND2
Safety Regulatory Approvals (Pending)
1577 recognized 5000 VRMS minute component notice approval 60950, 61010, 60601 (reinforced insulation)
certification conformity 60747-5-2 (VDE0884 Part EN60950 (reinforced insulation)
Patents pending
Description
This Silicon Laboratories family ultra-low-power digital isolators comprised CMOS devices that employ couplers transmit digital information across isolation barriers. Very high-speed operation power levels achieved. These devices available 8-pin narrow-body SOIC 16-pin wide body packages. speed grade options Mbps) available achieve worst-case propagation delays less than
Block Diagram
Si8410
Si8420
Si8421
Si8422*
Si8423*
Default High Output
Rev. 6/10
Copyright 2010 Silicon Laboratories
Si8410/20/21 Si8422/23
Si8410/20/21 422/23
Rev.
Si8410/20/21 Si8422/23 (2.5 TABLE ONTENTS
Section Page
Electrical Specifications Typical Performance Characteristics Application Information 3.1. Theory Operation 3.2. Diagram 3.3. Layout Recommendations Descriptions (Wide-Body SOIC) Descriptions (Narrow-Body SOIC) Ordering Guide Package Outline: 16-Pin Wide Body SOIC Landing Pattern: 16-Pin Wide-Body SOIC Package Outline: 8-Pin Narrow Body SOIC Landing Pattern: 8-Pin Narrow Body SOIC Marking: 16-Pin Wide Body SOIC Marking: 8-Pin Narrow-Body SOIC Contact Information
Rev.
Si8410/20/21 422/23
Electrical Specifications
Table Electrical Characteristics
(VDD1 ±10%, VDD2 ±10%,
Parameter Undervoltage Threshold Negative-going Lockout Hysteresis Positive-going input threshold Negative-going input threshold Input hysteresis High Level Input Voltage Level Input Voltage High Level Output Voltage Level Output Voltage Input Leakage Current Output Impedance1 Si8410Ax, VDD1 VDD2 VDD1 VDD2 Si8420Ax, VDD1 VDD2 VDD1 VDD2 Si8421Ax, VDD1 VDD2 VDD1 VDD2 Si8422Ax, VDD1 VDD2 VDD1 VDD2 Si8423Ax, VDD1 VDD2 VDD1 VDD2
Symbol VDDUV+ VDDHYS
Test Condition VDD1, VDD2 rising
2.15
0.45
0.50
Unit
inputs rising inputs falling 0.40 VHYS VDD1,VDD2 Supply Current (All inputs Supply) inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs
Notes: nominal output impedance isolator driver channel approximately ±40%, which combination value on-chip series termination resistor channel resistance output driver FET. When driving loads where transmission line effects will factor, output pins should appropriately terminated with controlled impedance traces. tPSK(P-P) magnitude difference propagation delay times measured between different units operating same supply voltages, load, ambient temperature. Start-up time time period from application power valid data output.
Rev.
Si8410/20/21 Si8422/23 (2.5
Table Electrical Characteristics (Continued)
(VDD1 ±10%, VDD2 ±10%,
Parameter
Symbol Test Condition Mbps Supply Current (All inputs square wave, outputs)
Unit
Si8410Ax, VDD1 VDD2 Si8420Ax, VDD1 VDD2 Si8421Ax, VDD1 VDD2 Si8422Ax, VDD1 VDD2 Si8423Ax, VDD1 VDD2 Mbps Supply Current (All inputs square wave, outputs) Si8410Bx VDD1 VDD2 Si8420Bx VDD1 VDD2 Si8421Bx VDD1 VDD2 Si8422Bx VDD1 VDD2 Si8423Bx VDD1 VDD2
Notes: nominal output impedance isolator driver channel approximately ±40%, which combination value on-chip series termination resistor channel resistance output driver FET. When driving loads where transmission line effects will factor, output pins should appropriately terminated with controlled impedance traces. tPSK(P-P) magnitude difference propagation delay times measured between different units operating same supply voltages, load, ambient temperature. Start-up time time period from application power valid data output.
Rev.
Si8410/20/21 422/23
Table Electrical Characteristics (Continued)
(VDD1 ±10%, VDD2 ±10%,
Parameter Si8410Bx VDD1 VDD2 Si8420Bx VDD1 VDD2 Si8421Bx VDD1 VDD2 Si8422Bx VDD1 VDD2 Si8423Bx VDD1 VDD2
Symbol Test Condition Mbps Supply Current (All inputs square wave, outputs) Timing Characteristics 12.3 11.5
Unit
Si8422Ax, Si8423Ax Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH tPHL| Propagation Delay Skew2 Channel-Channel Skew Si8422Bx, Si8423Bx Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH tPHL| Propagation Delay Skew2 Channel-Channel Skew Models Output Rise Time Output Fall Time Common Mode Transient Immunity Start-up Time3
tPHL, tPLH tPSK(P-P) tPSK
Figure Figure
Mbps Mbps kV/µs
tPHL, tPLH tPSK(P-P) tPSK CMTI
Figure Figure
Notes: nominal output impedance isolator driver channel approximately ±40%, which combination value on-chip series termination resistor channel resistance output driver FET. When driving loads where transmission line effects will factor, output pins should appropriately terminated with controlled impedance traces. tPSK(P-P) magnitude difference propagation delay times measured between different units operating same supply voltages, load, ambient temperature. Start-up time time period from application power valid data output.
Rev.
Si8410/20/21 Si8422/23 (2.5
Typical Input
tPLH
Typical Output
tPHL
Figure Propagation Delay Timing
Rev.
Si8410/20/21 422/23
Table Electrical Characteristics
(VDD1 ±10%, VDD2 ±10%,
Parameter Undervoltage Threshold Negative-going Lockout Hysteresis Positive-going input threshold Negative-going input threshold Input hysteresis High Level Input Voltage Level Input Voltage High Level Output Voltage Level Output Voltage Input Leakage Current Output Impedance Si8410Ax, VDD1 VDD2 VDD1 VDD2 Si8420Ax, VDD1 VDD2 VDD1 VDD2 Si8421Ax, VDD1 VDD2 VDD1 VDD2 Si8422Ax, VDD1 VDD2 VDD1 VDD2 Si8423Ax, VDD1 VDD2 VDD1 VDD2 (Si8410/20)1
Symbol VDDHYS VHYS
Test Condition
2.15
0.45
0.50
Unit
VDDUV+ VDD1, VDD2 rising
inputs rising inputs falling
0.40
VDD1,VDD2
Supply Current (All inputs supply) inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs
Notes: nominal output impedance isolator driver channel approximately ±40%, which combination value on-chip series termination resistor channel resistance output driver FET. When driving loads where transmission line effects will factor, output pins should appropriately terminated with controlled impedance traces. tPSK(P-P) magnitude difference propagation delay times measured between different units operating same supply voltages, load, ambient temperature. Start-up time time period from application power valid data output.
Rev.
Si8410/20/21 Si8422/23 (2.5
Table Electrical Characteristics (Continued)
(VDD1 ±10%, VDD2 ±10%,
Parameter Si8410Ax, VDD1 VDD2 Si8420Ax, VDD1 VDD2 Si8421Ax, VDD1 VDD2 Si8422Ax, VDD1 VDD2 Si8423Ax, VDD1 VDD2 Si8410Bx VDD1 VDD2 Si8420Bx VDD1 VDD2 Si8421Bx VDD1 VDD2 Si8422Bx VDD1 VDD2 Si8423Bx VDD1 VDD2
Symbol
Test Condition
Unit
Mbps Supply Current (All inputs square wave, outputs)
Mbps Supply Current (All inputs square wave, outputs)
Notes: nominal output impedance isolator driver channel approximately ±40%, which combination value on-chip series termination resistor channel resistance output driver FET. When driving loads where transmission line effects will factor, output pins should appropriately terminated with controlled impedance traces. tPSK(P-P) magnitude difference propagation delay times measured between different units operating same supply voltages, load, ambient temperature. Start-up time time period from application power valid data output.
Rev.
Si8410/20/21 422/23
Table Electrical Characteristics (Continued)
(VDD1 ±10%, VDD2 ±10%,
Parameter Si8410Bx VDD1 VDD2 Si8420Bx VDD1 VDD2 Si8421Bx VDD1 VDD2 Si8422Bx VDD1 VDD2 Si8423Bx VDD1 VDD2
Symbol
Test Condition
Unit
Mbps Supply Current (All inputs square wave, outputs) Timing Characteristics Si8422Ax, Si8423Ax Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH tPHL| Propagation Delay Skew2 Channel-Channel Skew Si8422Bx, Si8423Bx Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH tPHL| Propagation Delay Skew2 Channel-Channel Skew tPHL, tPLH tPSK(P-P) tPSK Figure Figure Mbps tPHL, tPLH tPSK(P-P) tPSK Figure Figure Mbps
Notes: nominal output impedance isolator driver channel approximately ±40%, which combination value on-chip series termination resistor channel resistance output driver FET. When driving loads where transmission line effects will factor, output pins should appropriately terminated with controlled impedance traces. tPSK(P-P) magnitude difference propagation delay times measured between different units operating same supply voltages, load, ambient temperature. Start-up time time period from application power valid data output.
Rev.
Si8410/20/21 Si8422/23 (2.5
Table Electrical Characteristics (Continued)
(VDD1 ±10%, VDD2 ±10%,
Parameter Models Output Rise Time Output Fall Time Common Mode Transient Immunity Start-up Time3
Symbol CMTI
Test Condition
Unit kV/µs
Notes: nominal output impedance isolator driver channel approximately ±40%, which combination value on-chip series termination resistor channel resistance output driver FET. When driving loads where transmission line effects will factor, output pins should appropriately terminated with controlled impedance traces. tPSK(P-P) magnitude difference propagation delay times measured between different units operating same supply voltages, load, ambient temperature. Start-up time time period from application power valid data output.
Rev.
Si8410/20/21 422/23
Table Electrical Characteristics1
(VDD1 2.70 VDD2 2.70
Parameter Undervoltage Threshold Negative-going Lockout Hysteresis Positive-going input threshold Negative-going input threshold Input hysteresis High Level Input Voltage Level Input Voltage High Level Output Voltage Level Output Voltage Input Leakage Current Output Impedance2 Si8410Ax, VDD1 VDD2 VDD1 VDD2 Si8420Ax, VDD1 VDD2 VDD1 VDD2 Si8421Ax, VDD1 VDD2 VDD1 VDD2 Si8422Ax, VDD1 VDD2 VDD1 VDD2 Si8423Ax, VDD1 VDD2 VDD1 VDD2
Symbol VDDUV+ VDDHYS VHYS
Test Condition VDD1, VDD2 rising
2.15
0.45
0.50
Unit
0.40 VDD1,VDD2 Supply Current (All inputs supply) inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs inputs
inputs rising inputs falling
Notes: Specifications this table also valid VDD1 VDD2 when operating temperature range constrained nominal output impedance isolator driver channel approximately ±40%, which combination value on-chip series termination resistor channel resistance output driver FET. When driving loads where transmission line effects will factor, output pins should appropriately terminated with controlled impedance traces. tPSK(P-P) magnitude difference propagation delay times measured between different units operating same supply voltages, load, ambient temperature. Start-up time time period from application power valid data output.
Rev.
Si8410/20/21 Si8422/23 (2.5
Table Electrical Characteristics1 (Continued)
(VDD1 2.70 VDD2 2.70
Parameter
Symbol Test Condition Mbps Supply Current (All inputs square wave, outputs)
Unit
Si8410Ax, VDD1 VDD2 Si8420Ax, VDD1 VDD2 Si8421Ax, VDD1 VDD2 Si8422Ax, VDD1 VDD2 Si8423Ax, VDD1 VDD2 Mbps Supply Current (All inputs square wave, outputs) Si8410Bx VDD1 VDD2 Si8420Bx VDD1 VDD2 Si8421Bx VDD1 VDD2 Si8422Bx VDD1 VDD2 Si8423Bx VDD1 VDD2
Notes: Specifications this table also valid VDD1 VDD2 when operating temperature range constrained nominal output impedance isolator driver channel approximately ±40%, which combination value on-chip series termination resistor channel resistance output driver FET. When driving loads where transmission line effects will factor, output pins should appropriately terminated with controlled impedance traces. tPSK(P-P) magnitude difference propagation delay times measured between different units operating same supply voltages, load, ambient temperature. Start-up time time period from application power valid data output.
Rev.
Si8410/20/21 422/23
Table Electrical Characteristics1 (Continued)
(VDD1 2.70 VDD2 2.70
Parameter Si8410Bx VDD1 VDD2 Si8420Bx VDD1 VDD2 Si8421Bx VDD1 VDD2 Si8422Bx VDD1 VDD2 Si8423Bx VDD1 VDD2
Symbol Test Condition Mbps Supply Current (All inputs square wave, outputs) Timing Characteristics
Unit
Si8422Ax, Si8423Ax Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH tPHL| Propagation Delay Skew3 Channel-Channel Skew Si8422Bx, Si8423Bx Maximum Data Rate Minimum Pulse Width Propagation Delay Pulse Width Distortion |tPLH tPHL| Propagation Delay Skew3 Channel-Channel Skew
tPHL, tPLH tPSK(P-P) tPSK
Figure Figure
Mbps Mbps
tPHL, tPLH tPSK(P-P) tPSK
Figure Figure
Notes: Specifications this table also valid VDD1 VDD2 when operating temperature range constrained nominal output impedance isolator driver channel approximately ±40%, which combination value on-chip series termination resistor channel resistance output driver FET. When driving loads where transmission line effects will factor, output pins should appropriately terminated with controlled impedance traces. tPSK(P-P) magnitude difference propagation delay times measured between different units operating same supply voltages, load, ambient temperature. Start-up time time period from application power valid data output.
Rev.
Si8410/20/21 Si8422/23 (2.5
Table Electrical Characteristics1 (Continued)
(VDD1 2.70 VDD2 2.70
Parameter Models Output Rise Time Output Fall Time Common Mode Transient Immunity Start-up Time4
Symbol CMTI
Test Condition
Unit kV/µs
Notes: Specifications this table also valid VDD1 VDD2 when operating temperature range constrained nominal output impedance isolator driver channel approximately ±40%, which combination value on-chip series termination resistor channel resistance output driver FET. When driving loads where transmission line effects will factor, output pins should appropriately terminated with controlled impedance traces. tPSK(P-P) magnitude difference propagation delay times measured between different units operating same supply voltages, load, ambient temperature. Start-up time time period from application power valid data output.
Table Absolute Maximum Ratings1
Parameter Storage Temperature
Symbol TSTG VDD1, VDD2
-0.5 -0.5 -0.5
4500 6500
Unit VRMS VRMS
Operating Temperature Supply Voltage Input Voltage Output Voltage Output Current Drive Channel Lead Solder Temperature Maximum Isolation Voltage SOIC-8 Maximum Isolation Voltage SOIC-16
Notes: Permanent device damage occur above absolute maximum ratings exceeded. Functional operation should restricted conditions specified operational sections this data sheet. certifies storage temperature from
Rev.
Si8410/20/21 422/23
Table Recommended Operating Conditions
Parameter Ambient Operating Temperature* Supply Voltage Symbol VDD1 VDD2 Test Condition Mbps, 2.70 2.70 Unit
*Note: maximum ambient temperature dependent upon data frequency, output loading, number operating channels, supply voltage.
Table Regulatory Information1,2
Si84xx certified under Component Acceptance Notice more details, File 232873. 61010: VRMS reinforced insulation working voltage; VRMS basic insulation working voltage. 60950: VRMS reinforced insulation working voltage; 1000 VRMS basic insulation working voltage. 60601: VRMS reinforced insulation working voltage; VRMS basic insulation working voltage. Si84xx certified according 60747-5-2. more details, File 5006301-4880-0001. 60747-5-2: Vpeak basic insulation working voltage. 60950: VRMS reinforced insulation working voltage; 1000 VRMS basic insulation working voltage. Si84xx certified under UL1577 component recognition program. more details, File E257455. Rated 5000 VRMS isolation voltage basic insulation.
Notes: Pending. Regulatory Certifications apply kVRMS rated devices which production tested kVRMS sec. Regulatory Certifications apply kVRMS rated devices which production tested kVRMS sec. more information, Ordering Guide" page
Rev.
Si8410/20/21 Si8422/23 (2.5
Table Insulation Safety-Related Specifications
Value Parameter Nominal (Clearance)1 Nominal External Tracking (Creepage)1 Minimum Internal (Internal Clearance) Tracking Resistance (Proof Tracking Index) Erosion Depth Resistance (Input-Output)
Symbol L(IO1) L(IO2)
Test Condition
SOIC-16 0.014
SOIC-8 4.01 0.014 0.040 1012
Unit VRMS
IEC60112
0.019 1012
Capacitance (Input-Output)2 Input Capacitance
Notes: values this table correspond nominal creepage clearance values detailed Package Outline: 16-Pin Wide Body SOIC", Package Outline: 8-Pin Narrow Body SOIC". certifies clearance creepage limits minimum SOIC-16 package minimum SOIC-8 package. does impose clearance creepage minimum component level certifications. certifies clearance creepage limits minimum SOIC-8 minimum SOIC-16 package. determine resistance capacitance, Si84xx converted into 2-terminal device. Pins (1-4, SOIC-8) shorted together form first terminal pins 9-16 (5-8, SOIC-8) shorted together form second terminal. parameters then measured between these terminals. Measured from input ground.
Table 60664-1 (VDE 0844 Part Ratings
Parameter Test Conditions Specification SOIC8 Basic isolation group Material Group Rated Mains Voltages VRMS Installation Classification Rated Mains Voltages VRMS Rated Mains Voltages VRMS I-IV I-III I-II SOIC I-IV I-IV I-III
Rev.
Si8410/20/21 422/23
Table 60747-5-2 Insulation Characteristics Si84xxxx*
Characteristic Parameter Maximum Working Insulation Voltage Symbol Test Condition SOIC-16 Method (VIORM 1.875 VPR, 100% Production Test, sec, Partial Discharge SOIC-8 Unit
VIORM
Vpeak
Input Output Test Voltage
1375
1050
Highest Allowable Overvoltage (Transient Overvoltage, sec) Pollution Degree (DIN 0110, Table Insulation Resistance
6000
4000 >109
Vpeak
>109
*Note: This isolator suitable basic electrical isolation only within safety limit data. Maintenance safety data ensured protective circuits. Si84xx provides climate classification 40/125/21.
Table Safety Limiting Values1
Parameter Case Temperature Safety input, output, supply current Device Power Dissipation2 Symbol °C/W SOIC-8), SOIC-16), Test Condition SOIC-16 SOIC-8 Unit
Notes: Maximum value allowed event failure; also thermal derating curve Figures Si84xx tested with VDD1 VDD2 input Mbps duty cycle square wave.
Rev.
Si8410/20/21 Si8422/23 (2.5
Table Thermal Characteristics
Parameter Junction-to-Air Thermal Resistance Symbol SOIC-16 SOIC-8 Unit
Safety-Limiting Values (mA)
VDD1, VDD2 2.70
Case Temperature
VDD1, VDD2
VDD1, VDD2
Figure SOIC-16) Thermal Derating Curve, Dependence Safety Limiting Values with Case Temperature 60747-5-2
Safety-Limiting Values (mA)
VDD1, VDD2 2.70
Case Temperature
VDD1, VDD2
VDD1, VDD2
Figure SOIC-8) Thermal Derating Curve, Dependence Safety Limiting Values with Case Temperature 60747-5-2
Rev.
Si8410/20/21 422/23
Table Si84xx Logic Operation Table
Input1,4 VDDI State1,2,3 VDDO State1,2,3 Output1,4 Normal operation. Comments
(Si8422/23) Upon transition VDDI from unpowered (Si8410/20/21) powered, returns same state less than Undetermined Upon transition VDDO from unpowered powered, returns same state within
Notes: VDDI VDDO input output power supplies. respective input output terminals. Powered state defined 2.70 Unpowered (UP) state defined applicable; Logic High; Logic Low.
Rev.
Si8410/20/21 Si8422/23 (2.5
Typical Performance Characteristics
typical performance characteristics depicted following diagrams information purposes only. Refer Tables actual specification limits.
Current (mA)
Current (mA)
2.70V Data Rate (Mbps) 3.3V
Data Rate (Mbps) 3.3V 2.70V
Figure Si8410 Typical VDD1 Supply Current Data Rate 3.3, 2.70 Operation
Figure Si8410 Typical VDD2 Supply Current Data Rate 3.3, 2.70 Operation Load)
Current (mA)
Current (mA) 2.70V Data Rate (Mbps) 3.3V
3.3V 2.70V
Data Rate (Mbps)
Figure Si8420 Typical VDD1 Supply Current Data Rate 3.3, 2.70 Operation
Figure Si8420 Typical VDD2 Supply Current Data Rate 3.3, 2.70 Operation Load)
Current (mA) Data Rate (Mbps) 2.70V Current (mA) 3.3V Data Rate (Mbps) 2.70V 3.3V
Figure Si8421 Typical VDD1 VDD2 Supply Current Data Rate 3.3, 2.70 Operation Load)
Figure Si8422 Typical VDD1 VDD2 Supply Current Data Rate 3.3, 2.70 Operation Load)
Rev.
Si8410/20/21 422/23
Time Failure, 10ppm (Years)
100000000 10000000 1000000 100000 10000 1000 0.01 0.001 0.0001 0.00001 0.000001
Current (mA) 2.70V Data Rate (Mbps) 3.3V
Si84xx 10ppm (25C) Si84xx 10ppm (150C)
Continous Working Voltage Specification
Working Voltage (Vrms)
Figure Si8423 Typical VDD1 Supply Current Data Rate 3.3, 2.70 Operation
Current (mA) Data Rate (Mbps) 3.3V 2.70V
Magnetic Flux Density(Wb/m2)
Figure Time-Dependent Breakdown Dielectric Breakdown
1.00E+08
1.00E+06 1.00E+04
Si84xx
1.00E+02
1.00E+00
1.00E-02
1.00E-04 1.00E-06 IEC61000-4-8
1.00E-08
1.00E-10
1.00E-12
1.00E-14 1.00E-16
IEC61000-4-9
1.00E-18
0.001 0.01
Frequency (MHz)
Figure Si8423 Typical VDD2 Supply Current Data Rate 3.3, 2.70 Operation Load)
Delay (ns) Rising Edge Temperature (Degrees Falling Edge
Figure Electromagnetic Immunity
Figure Propagation Delay Temperature
Rev.
Si8410/20/21 Si8422/23 (2.5
Application Information
3.1. Theory Operation
operation Si84xx channel analogous that opto coupler, except carrier modulated instead light. This simple architecture provides robust isolated data path requires special considerations initialization start-up. simplified block diagram single Si84xx channel shown Figure
Transmitter
OSCILLATOR
Receiver
MODULATOR
SemiconductorBased Isolation Barrier
DEMODULATOR
Figure Simplified Channel Diagram
channel consists Transmitter Receiver separated semiconductor-based isolation barrier. Referring Transmitter, input modulates carrier provided oscillator using on/off keying. Receiver contains demodulator that decodes input state according energy content applies result output output driver. This on/off keying scheme superior pulse code schemes provides best-in-class noise immunity, power consumption, better immunity magnetic fields. Figure more details.
Input Signal
Modulation Signal
Output Signal
Figure Modulation Scheme
Rev.
Si8410/20/21 422/23
3.2. Diagram
Figure illustrates eye-diagram taken Si8422. data source, test used Anritsu (MP1763C) Pulse Pattern Generator 1000 ns/div. output generator's clock data from Si8422 were captured oscilloscope. results illustrate that data integrity maintained even high data rate Mbps. results also show that pulse width distortion peak jitter were exhibited.
Figure Diagram
Rev.
Si8410/20/21 Si8422/23 (2.5
3.3. Layout Recommendations
ensure safety user application, high voltage circuits (i.e., circuits with VAC) must physically separated from safety extra-low voltage circuits (SELV circuit with VAC) certain distance (creepage/clearance). component, such digital isolator, straddles this isolation barrier, must meet those creepage/clearance requirements also provide sufficiently large high-voltage breakdown protection rating (commonly referred working voltage protection). Table page Table page detail working voltage creepage/clearance capabilities Si84xx. These tables also detail component standards (UL1577, IEC60747, 5A), which readily accepted certification bodies provide proof end-system specifications requirements. Refer end-system specification (61010, 60950, 60601, etc.) requirements before starting design that uses digital isolator. 3.3.1. Supply Bypass Si842x family requires bypass capacitor between VDD1 GND1 VDD2 GND2. capacitor should placed close possible package. enhance robustness design, further recommended that user include resistors series with inputs outputs supply system excessively noisy. 3.3.2. Output Termination nominal output impedance isolator driver channel approximately ±40%, which combination value on-chip series termination resistor channel resistance output driver FET. When driving loads where transmission line effects will factor, output pins should appropriately terminated with controlled impedance traces.
Rev.
Si8410/20/21 422/23
3.3.3. Radiated Emissions Si84xx family uses carrier frequency approximately MHz. This results small amount radiated emissions this frequency harmonics. radiation from chip but, rather, small amount energy driving isolated ground planes, which dipole antenna. unshielded Si84xx evaluation board passes Class (Part requirements. Table shows measured emissions compared requirements. Note that data reflects worst-case conditions where inputs tied logic transmitters fully active. Radiated emissions reduced circuit board enclosed shielded enclosure less efficient antenna.
Table Radiated Emissions
Frequency Measured (MHz) (dBµV/m) 1424 2136 2848 4272 4984 5696 Spec (dBµV/m) Compared Spec (dB)
3.3.4. Magnetic, Common Mode Transient Immunity Si84xx families have very high common mode transient immunity while transmitting data. This typically measured applying square pulse with very fast rise/fall times between isolated grounds. Measurements show failures kV/µs (typical). During high surge event, output glitch output corrects immediately after surge event. Si84xx families pass industrial requirements CISPR24 immunity using unshielded evaluation board. shown Figure isolated ground planes form parasitic dipole antenna. should laid-out efficient antenna frequency interest. susceptibility also significantly reduced when system housed metal enclosure, otherwise shielded. Si84xx digital isolator used close proximity large motors various other magnetic-field producing equipment. theory, data transmission errors occur magnetic field large field close isolator. However, actual use, Si84xx devices provide extremely high immunity external magnetic fields have been independently evaluated withstand magnetic fields least 1000 according 61000-4-8 61000-4-9 specifications.
GND1
Isolator
GND2
Dipole Antenna
Figure Dipole Antenna
Rev.
Si8410/20/21 Si8422/23 (2.5
Descriptions (Wide-Body SOIC)
Si841x
GND1 VDD1 GND1
Si842x
GND2 VDD2 GND2 GND1 VDD1 GND1
View
View
GND2 VDD2 GND2
Name GND1 VDD1 GND1 GND2 VDD2 GND2
SOIC-16 Pin# SOIC-16 Pin# Si8410 Si842x 8,10, 8,10,
Type Ground Connect Supply Digital Digital Ground Ground Digital Digital Supply Ground
Description Side ground. Side power supply. Side digital input output. Side digital input output. Side ground. Side ground. Side digital input output. Side digital input output. Side power supply. Side ground.
*Note: Connect. These pins internally connected. They left floating, tied tied GND.
Rev.
Si8410/20/21 422/23
Descriptions (Narrow-Body SOIC)
Si842x
VDD1 GND1
View
VDD2 GND2
Narrow Body SOIC
Name SOIC-8 Pin# Si842x Type Description
VDD1 GND1 VDD2 GND2
Supply Ground Digital Digital Digital Digital Supply Ground
Side power supply. Side ground. Side digital input output. Side digital input output. Side digital input output. Side digital input output. Side power supply. Side ground.
Rev.
Si8410/20/21 Si8422/23 (2.5
Ordering Guide
possible device configuration options their corresponding ordering part numbers (OPN) included Ordering Guide table. However, there specific device configuration interest that currently listed Ordering Guide table, please contact your local Silicon Labs sales representative, Silicon Labs Technical Support page register submit request your specific device configuration OPN.
Si84XYSV-R-TPn
Isolator Product Data channel count Reverse channel count Data Rate (A=1 Mbps, B=150 Mbps) Insulation Rating (A=1 B=2.5 C=3.75 Product Revision Temp Range (I=-40 +125C) Package Type (S=SOIC) Package Extension (1=Narrow Body 16-pin)
Figure Ordering Part Number (OPN) Convention
Rev.
Si8410/20/21 422/23
Table Ordering Guide1
Ordering Part Number (OPN) Si8422AB-B-IS Si8422BB-B-IS Si8423AB-B-IS Si8423BB-B-IS Si8410AD-A-IS2 Si8410BD-A-IS
Number Number Maximum Inputs Inputs Data Rate Isolation Rating VDD1 Side VDD2 Side (Mbps) kVrms kVrms
Temp Range
Package Type
SOIC-8
Si8420AD-A-IS2 Si8420BD-A-IS2 Si8421AD-B-IS2 Si8421BD-B-IS2 Si8422AD-B-IS Si8422BD-B-IS Si8423AD-B-IS Si8423BD-B-IS
SOIC-16
Notes: packages RoHS-compliant with peak reflow temperatures according JEDEC industry standard classifications peak solder temperatures. Moisture sensitivity level MSL3 wide-body SOIC-16 packages. Moisture sensitivity level MSL2A narrow-body SOIC-8 packages. Refer Si8410/20/21 data sheet information regarding rated versions these products.
Rev.
Si8410/20/21 Si8422/23 (2.5
Package Outline: 16-Pin Wide Body SOIC
Figure illustrates package details Si84xx Digital Isolator. Table lists values dimensions shown illustration.
Figure 16-Pin Wide Body SOIC Table Package Diagram Dimensions
Millimeters Symbol 2.65
10.3 10.3 0.31 0.20 0.25 0.51 0.33 0.75 1.27
1.27
Rev.
Si8410/20/21 422/23
Landing Pattern: 16-Pin Wide-Body SOIC
Figure illustrates recommended landing pattern details Si84xx 16-pin wide-body SOIC. Table lists values dimensions shown illustration.
Figure 16-Pin SOIC Land Pattern Table 16-Pin Wide Body SOIC Landing Pattern Dimensions
Dimension Feature Column Spacing Pitch Width Length (mm) 9.40 1.27 0.60 1.90
Notes: This Land Pattern Design based IPC-7351 pattern SOIC127P1032X265-16AN Density Level (Median Land Protrusion). feature sizes shown Maximum Material Condition (MMC) card fabrication tolerance 0.05 assumed.
Rev.
Si8410/20/21 Si8422/23 (2.5
Package Outline: 8-Pin Narrow Body SOIC
Figure illustrates package details Si84xx. Table lists values dimensions shown illustration.
Figure 8-pin Small Outline Integrated Circuit (SOIC) Package Table Package Diagram Dimensions
Symbol Millimeters 1.35 0.10 1.40 0.33 0.19 4.80 3.80 5.80 0.25 0.40 1.75 0.25 1.55 0.51 0.25 5.00 4.00 6.20 0.50 1.27
1.27
Rev.
Si8410/20/21 422/23
Landing Pattern: 8-Pin Narrow Body SOIC
Figure illustrates recommended landing pattern details Si84xx 8-pin narrow-body SOIC. Table lists values dimensions shown illustration.
Figure Landing Pattern: 8-Pin Narrow Body SOIC Table Landing Pattern Dimensions (8-Pin Narrow Body SOIC)
Dimension Feature Column Spacing Pitch Width Length (mm) 5.40 1.27 0.60 1.55
Notes: This Land Pattern Design based IPC-7351 pattern SOIC127P600X173-8N Density Level (Median Land Protrusion). feature sizes shown Maximum Material Condition (MMC) card fabrication tolerance 0.05 assumed.
Rev.
Si8410/20/21 Si8422/23 (2.5
Marking: 16-Pin Wide Body SOIC
Si84XYSV YYWWTTTTTT
Figure Isolator Marking Table Marking Explanation
Line Marking: Base Part Number Ordering Options Si84 Isolator product series Channel Configuration data channels (See Ordering Guide more reverse channels information). Speed Grade Mbps; Mbps Insulation rating 3.75 Year Workweek TTTTTT Code Line Marking: Circle Diameter (Center-Justified) Country Origin Code Abbreviation Assigned assembly subcontractor. Corresponds year workweek mold date. Manufacturing code from assembly house. "e3" Pb-Free Symbol. Taiwan.
Line Marking:
Rev.
Si8410/20/21 422/23
Marking: 8-Pin Narrow-Body SOIC
Si84XYSV YYWWRF AIXX
Figure Isolator Marking Table Marking Explanations
Line Marking: Base Part Number Ordering Options (See Ordering Guide more information). Si84 Isolator product series Channel Configuration data channels reverse channels Speed Grade Mbps; Mbps Insulation rating 3.75 Assigned assembly subcontractor. Corresponds year workweek mold date.
Line Marking:
Year Workweek Product (OPN) Revision Wafer
Line Marking:
Circle Diameter Left-Justified Assembly Site Internal Code Serial Number
"e3" Pb-Free Symbol. First characters manufacturing code. Last four characters manufacturing code.
Rev.
Si8410/20/21 Si8422/23 (2.5
NOTES:
Rev.
Si8410/20/21 422/23
CONTACT INFORMATION
Silicon Laboratories Inc. West Cesar Chavez Austin, 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit Silicon Labs Technical Support page: register submit technical support request.
information this document believed accurate respects time publication subject change without notice. Silicon Laboratories assumes responsibility errors omissions, disclaims responsibility consequences resulting from information included herein. Additionally, Silicon Laboratories assumes responsibility functioning undescribed features parameters. Silicon Laboratories reserves right make changes without further notice. Silicon Laboratories makes warranty, representation guarantee regarding suitability products particular purpose, does Silicon Laboratories assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. Silicon Laboratories products designed, intended, authorized applications intended support sustain life, other application which failure Silicon Laboratories product could create situation where personal injury death occur. Should Buyer purchase Silicon Laboratories products such unintended unauthorized application, Buyer shall indemnify hold Silicon Laboratories harmless against claims damages. Silicon Laboratories Silicon Labs trademarks Silicon Laboratories Inc. Other products brandnames mentioned herein trademarks registered trademarks their respective holders.
Rev.

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