STR750Fxx STR751Fxx STR752Fxx STR755Fxx
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ARM7TDMI-S32-bit with Flash, SMI, 16-bit timers, timer, fast 10-bit ADC, I2C, UART, SSP,
Core ARM7TDMI-S 32-bit RISC DMIPS Memories Flash program memory (10k cycles, retention 85°C) Read-While-Write Flash data (100k cycles, retention yrs@ 85°C) Flash Data Readout Write Protection 16KBytes embedded high speed SRAM Memory mapped interface (SMI) ext. Serial Flash boot capability Clock, reset supply management Single supply 3.3V ±10% ±10% Embedded 1.8V Voltage Regulators Int. fast start-up backup clock operation using internal with crystal/ceramic osc. Smart Power Modes: SLOW, WFI, STOP STANDBY with backup registers Real-time Clock, driven power internal 32.768 dedicated osc, clock-calendar Auto Wake-up Nested interrupt controller Fast interrupt handling with vectors priorities, maskable sources external interrupt wake-up lines 4-channel controller Circular buffer management Support UART, SSP, Timers, Timers 16-bit watchdog timer (WDG) 16-bit timer system timebase functions synchronizable timers each with input captures output compare/PWMs.
LQFP64 10x10
LQFP100
LFBGA64
LFBGA100
16-bit 6-ch. synchronizable timer Dead time generation, edge/center-aligned waveforms emergency stop Ideal induction/brushless motors Communications interfaces interface HiSpeed UARTs Modem/LIN capability interfaces (SPI SSI) Mb/s interface (2.0B Active) full-speed Mb/s interface with configurable endpoint sizes 10-bit converter 16/11 chan. with prog. Scan Mode FIFO Programmable Analog Watchdog feature Conversion time: min. 3.75 Start conversion triggered timers 72/38 ports 72/38 GPIOs with High Sink capabilities Atomic operations Device summary
Part number
Table
Reference
STR750Fxx STR750FV0, STR750FV1, STR750FV2 STR751Fxx STR751FR0, STR751FR1, STR751FR2 STR752Fxx STR752FR0, STR752FR1, STR752FR2 STR755Fxx STR755FR0, STR755FR1, STR755FR2 STR755FV0, STR755FV1, STR755FV2
February 2009
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Contents
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Contents
Description Device overview Introduction
Functional description Block diagram
description
description table External components
Memory Electrical parameters
Parameter conditions
6.1.1 6.1.2 6.1.3 6.1.4 6.1.5 6.1.6 6.1.7 6.1.8 Minimum maximum values Typical values Typical curves Loading capacitor input voltage Power supply schemes characteristics versus various power schemes (3.3V 5.0V) Current consumption measurements
Absolute maximum ratings
6.2.1 6.2.2 6.2.3 Voltage characteristics Current characteristics Thermal characteristics
Operating conditions
6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 General operating conditions Operating conditions power-up power-down Embedded voltage regulators Supply current characteristics Clock timing characteristics
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx 6.3.6 6.3.7 6.3.8 6.3.9 6.3.10 6.3.11 6.3.12
Contents
Memory characteristics characteristics port characteristics timer characteristics Communication interface characteristics characteristics 10-bit characteristics
Package characteristics
Package mechanical data Thermal characteristics
7.2.1 7.2.2 Reference document Selecting product temperature range
Order codes Revision history
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Description
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Description
STR750 family 32-bit microcontrollers combines industry-standard ARM7TDMI® 32-bit RISC core, featuring high performance, very power, very dense code, with comprehensive peripherals ST's latest 0.18µ embedded Flash technology. STR750 family comprises range devices integrating common peripherals well USB, some innovations like clock failure detection advanced motor control timer. supports both 3.3V also available extended temperature range (-40 +105°C). This makes genuine general purpose microcontroller family, suitable wide range applications:
Appliances, brushless motor drives peripherals, UPS, alarm systems Programmable logic controllers, circuit breakers, inverters Medical portable equipment
Table
Device overview
Device overview
STR755FR0 STR755FR1 STR755FR2 STR751FR0/ STR751FR1/ STR751FR2 STR752FR0/ STR752FR1/ STR752FR2 STR755FV0 STR755FV1/ STR755FV2 STR750FV0/ STR750FV1/ STR750FV2
Features Flash Bank (bytes) Flash Bank (bytes) (bytes) Operating Temperature. Common Peripherals USB/CAN peripherals Operating Voltage Packages
64K/128K/256K Ambient temp.:-40 +85°C +105°C (see Table Junction temp. (see Table UARTs, SSPs, I2C, timers timer, I/Os Wake-up lines, Channels None 3.3V 3.3V UARTs, SSPs, I2C, timers timer, I/Os Wake-up lines, Channels None 3.3V T=LQFP100 14x14, H=LFBGA100 USB+CAN
T=LQFP64 10x10, H=LFBGA64
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Introduction
Introduction
This Datasheet contains description STR750F family features, pinout, Electrical Characteristics, Mechanical Data Ordering information. complete information Microcontroller memory, registers peripherals. Please refer STR750F Reference Manual. information ARM7TDMI-S core please refer ARM7TDMI-S Technical Reference Manual available from Ltd. information programming, erasing protection internal Flash memory please refer STR7 Flash Programming Reference Manual information third-party development tools, please refer http://www.st.com/mcu website.
Functional description
STR750F family includes devices package sizes: 64-pin 100-pin. Both types have following common features:
ARM7TDMI-Score with embedded Flash
STR750F family embedded core therefore compatible with tools software. combines high performance ARM7TDMI-SCPU with extensive range peripheral functions enhanced capabilities. devices have on-chip highspeed single voltage FLASH memory high-speed RAM. Figure shows general block diagram device family.
Embedded Flash memory
KBytes embedded Flash available Bank storing programs data. additional Bank provides Kbytes (Read While Write) memory allowing erased/programmed on-the-fly. This partitioning feature ideal storing application parameters.
When configured burst mode, access Flash memory performed clock speed with wait states sequential accesses wait state random access (maximum MHz). When configured burst mode, access Flash memory performed clock speed with wait states (maximum MHz)
Embedded SRAM
Kbytes embedded SRAM accessed (read/write) clock speed with wait states.
Enhanced interrupt controller (EIC)
addition standard interrupt controller, STR750F embeds nested interrupt controller able handle vectors priority levels. This additional hardware block provides flexible interrupt management features with minimal interrupt latency.
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Introduction
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Serial memory interface (SMI)
Serial Memory interface directly able access serial FLASH devices. used access data, execute code directly boot application from external memory. memory addressed banks Mbytes each.
Clocks start-up
After RESET when exiting from Power Mode, clocked immediately internal oscillator (FREEOSC) frequency centered around MHz, application code start executing without delay. parallel, Oscillator enabled stabilization time monitored using dedicated counter. oscillator failure detection implemented: when clock disappears pin, circuit automatically switches FREEOSC oscillator interrupt generated. mode, clock speeds large number different frequencies thanks various prescalers: when fetching from Flash when fetching from SRAM). SLOW mode, clock significantly decreased reduce power consumption. built-in Clock Controller also provides clock directly without extra oscillators PLL. instance, starting from crystal source, possible obtain parallel clock, clock peripherals.
Boot modes
start-up, boot pins used select five boot options:
Boot from internal flash Boot from external serial Flash memory Boot from internal boot loader Boot from internal SRAM
Booting from memory allows booting from serial flash. This way, specific boot monitor implemented. Alternatively, STR750F boot from internal boot loader that implements boot from UART.
Power supply schemes
connect device following ways depending your application.
Power Scheme Single external 3.3V power source. this configuration VCORE supply required internal logic generated internally main voltage regulator VBACKUP supply generated internally power voltage regulator. This scheme advantage requiring only 3.3V power source. Power Scheme Dual external 3.3V 1.8V power sources. this configuration, internal voltage regulators switched forcing VREG_DIS high level. VCORE provided externally through V18REG power pins VBACKUP through V18_BKP pin. This scheme intended save power consumption applications which already provide 1.8V power supply. Power Scheme Single external 5.0V power source. this configuration VCORE supply required internal logic generated internally main voltage
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Introduction
regulator VBACKUP supply generated internally power voltage regulator. This scheme advantage requiring only 5.0V power source.
Power Scheme Dual external 5.0V 1.8V power sources. this configuration, internal voltage regulators switched off, forcing VREG_DIS high level. VCORE provided externally through V18REG power pins VBACKUP through V18_BKP pin. This scheme intended provide capability.
Caution:
When powered 5.0V, peripheral cannot operate.
power modes
STR750F supports power modes, SLOW, PCG, WFI, STOP STANDBY.
SLOW MODE: system clock speed reduced. Alternatively, main oscillator stopped device driven power clock (fRTC). clock either external 32.768 oscillator internal power oscillator. MODE (Peripheral Clock Gating MODE): When peripherals used, their clocks gated optimize power consumption. MODE (Wait Interrupts): only clock stopped, peripherals continue work wake-up when IRQs occur. STOP MODE: clocks/peripherals disabled. also possible disable oscillators Main Voltage Regulator this case VCORE entirely powered V18_BKP). This mode intended achieve lowest power consumption with SRAM registers contents retained. system woken external interrupts wake-up lines timer which optionally kept running. clocked either 32.768 Crystal Power Oscillator. Alternatively, STOP mode gives flexibility keep either main oscillator, Flash Main Voltage Regulator enabled when fast start after wake-up preferred cost some extra power consumption). STANDBY MODE: This mode (only available single supply power schemes) intended achieve lowest power consumption even when temperature increasing. digital power supply (VCORE) completely removed leakage even high ambient temperature). SRAM register contents lost. Only remains powered V18_BKP. STR750F switched back from STANDBY mode trigger event WKP_STDBY alarm timeout counter.
Caution:
important bear mind that forbidden remove power from VDD_IO power supply Power Modes (even STANDBY MODE).
flexible 4-channel general-purpose able manage memory memory, peripheral memory memory peripheral transfers. controller supports circular buffer management avoiding generation interrupts when controller reaches buffer. used with main peripherals: UART0, SSP0, Motor control timer (PWM), standard timer TIM0 ADC.
(real-time clock)
real-time clock provides continuously running counters which used with suitable software provide clock calendar function, provides alarm interrupt
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Introduction
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
periodic interrupt. clocked external 32.768 oscillator internal power oscillator. typical frequency calibrated.
(watchdog timer)
watchdog timer based 16-bit downcounter 8-bit prescaler. used watchdog reset device when problem occurs, free running timer application time management.
Timebase timer (TB)
timebase timer based 16-bit auto-reload counter connected pins. used software triggering, implement scheduler real-time operating system.
Synchronizable standard timers (TIM2:0)
three standard timers based 16-bit auto-reload counter feature input captures output compares (for external triggering time base time management). They work together with timer Timer Link feature synchronization event chaining. reset state, timer Alternate Function I/Os connected same ports both 64-pin 100-pin devices. optimize timer functions 64-pin devices, timer Alternate Function I/Os connected, "remapped", other ports summarized Table detailed Table This remapping done application control register. Table Standard timer alternate function I/Os
Number alternate function I/Os Standard timer functions 100-pin package Input Capture Output Compare/PWM Input Capture Output Compare/PWM Input Capture Output Compare/PWM 64-pin package Default mapping Remapped
standard timers used generate outputs. timer (TIM0) mapped channel.
Motor control timer (PWM)
Motor Control Timer (PWM) seen three-phase multiplexed channels. 16-bit generator full modulation capability (0.100%), edge centre-aligned patterns supports dead-time insertion. many features common with standard timers which same architecture work together with timers Timer Link feature synchronization event chaining.The timer mapped channel.
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Introduction
interface operate multi-master slave mode. support standard fast modes 400KHz).
High speed universal asynch. receiver transmitter (UART)
three UART interfaces able communicate speeds Mbit/s. They provide hardware management signals have Master capability. optimize data transfer between processor peripheral, FIFOs (receive/transmit) bytes each have been implemented. UART served controller (UART0).
Synchronous serial peripheral (SSP)
SSPs able communicate Mbit/s (SSP1) Mbit/s (SSP0) standard full duplex 4-pin interface mode master device 2.66 Mbit/s slave device. optimize data transfer between processor peripheral, FIFOs (receive/transmit) words have been implemented. SSPs support Motorola protocols. served controller (SSP0).
Controller area network (CAN)
compliant with specification part (active) with rate 1Mbit/s. receive transmit standard frames with 11-bit identifiers well extended frames with 29-bit identifiers. message objects handled through internal buffer. LQFP64 devices, cannot connected simultaneously.
Universal serial (USB)
STR750F embeds device peripheral compatible with Full speed 12Mbs. interface implements full speed Mbit/s) function interface. software configurable endpoint setting suspend/resume support. dedicated clock source generated from internal main PLL. must range 3.3V±10% operation.
(analog digital converter)
10-bit Analog Digital Converter, converts external channels channels 64-pin devices) single-shot scan modes. scan mode, continuous conversion performed selected group analog inputs. minimum conversion time 3.75 (including sampling time). served controller. analog watchdog feature allows very precisely monitor converted voltage four channels. generated when converted voltage outside programmed thresholds. events generated TIM0, TIM2 timers internally connected start trigger, injection trigger, trigger respectively, allow application synchronize conversion timers.
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Introduction
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
GPIOs (general purpose input/output)
Each GPIO pins GPIOs 64-pin devices) configured software output (push-pull open-drain), input (with without pull-up pull-down) Peripheral Alternate Function. Port 1.15 exception, used general-purpose input only wake-up from STANDBY mode (WKP_STDBY). Most GPIO pins shared with digital analog alternate functions.
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Introduction
Block diagram
Figure
BOOT1, BOOT0 TEST NJTRST JTDI JTCK JTMS JTDO
STR750 block diagram
ARM7TDMI-S 60MHz JTAG ICE-RT streams
MATRIX
HRESETN PRESETN SRAM 16KB FLASH 256KB +16KB (RWW) NESTED INTERRUPT CK_RTC CK_SYS HCLK PCLK CLOCK MANAGEMENT VDD_IO VCORE VBACKUP VDDA_PLL VDDA_ADC 32xIRQ 2xFIQ
RESET POWER DC-DC 3.3V 1.8V MAIN POWER
NRSTIN NRSTOUT VDD_IO V18BKP
Arbiter SCLK, MOSI MISO SERIAL MEMORY INTERFACE
LITE 60MHz)
FREE VDDA_PLL VSSA_PLL RTC_XT1 RTC_XT2
BRIDGE
CK_USB Full Speed
15AF P0[31:0] P1[19:0] P2[19:0] 16AF VDDA_ADC VSSA_ADC
EXT.IT WAKEUP GPIO PORT GPIO PORT GPIO PORT 10-bit WATCHDOG
USBDP USBDM RX,TX RX,TX,CTS, RX,TX,CTS, RX,TX,CTS, MOSI,MISO, SCK,NSS MOSI,MISO, SCK,NSS SCL,SDA
2.0B FIFO 2x(16x8bit) UART0 FIFO 2x(16x8bit) UART1 FIFO 2x(16x8bit) UART2 FIFO 2x(8x16bit) SSP0
TIMER 2xICAP, 2xOCMP 2xICAP, 2xOCMP 2xICAP, 2xOCMP PWM1, PWM1N PWM2, PWM2N PWM3, PWM3N PWM_EMERGENCY TIM0 TIMER TIM1 TIMER TIM2 TIMER TIMER MHz) FIFO 2x(8x16bit) SSP1
alternate function port Note: I/Os shown devices. 64-pin devices have shown Figure
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description
Figure
description
ADC_IN13 P1.12 ADC_IN0 TIM2_OC1/ P0.02 TIM0_TI1 P0.01 BOOT0 TIM0_OC1 P0.00 TIM1_TI2 P0.31 TIM1_OC2 P0.30 ADC_IN8 TIM1_TI1 P0.29 TIM1_OC1 P0.28 TEST VSS_IO ADC_IN6 UART1_RTS P0.23 TIM2_OC1/ P2.04 UART1_RTS P2.03 P2.02 ADC_IN5 UART1_CTS P0.22 UART1_TX P0.21 UART1_RX P0.20 JTMS P1.19 JTCK P1.18 JTDO P1.17 JTDI P1.16 NJTRST P2.01 P2.00 UART0_RTS RTCK P0.13
SMI_CS1 ADC_IN2 UART0_CTS P0.12 SMI_CS2 BOOT1 UART0_TX P0.11 SMI_CS3 UART0_RX P0.10 I2C_SDA P0.09 I2C_SCL P0.08 P2.19 P2.18 UART2_RTS P2.17 ADC_IN12 UART0_RTS P1.11 ADC_IN7 /UART2_RTS P0.27 UART2_CTS P0.26 UART2_TX P0.25 UART2_RX P0.24 ADC_IN4 SSP1_NSS USB_CK P0.19 SSP1_MOSI P0.18 ADC_IN3 SSP1_MISO P0.17 SSP1_SCLK P0.16 P2.16 VDD_IO VDDA_PLL VSS_IO VSSA_PLL P2.15
input channels External interrupts Wake-up Lines
LQFP100 pinout
LQFP100
V18BKP I/Os
VREG_DIS VSS_IO VSSA_ADC P2.10 P2.11 VDDA_ADC VDD_IO P1.02 TIM2_OC2 P1.03 TIM2_TI2 USB_DP USB_DN P0.14 CAN_RX P0.15 CAN_TX P2.12 P2.13 P1.15 WKP_STDBY NRSTIN NRSTOUT XRTC2 XRTC1 V18BKP VSSBKP VSS18 V18REG P2.14
P0.03 TIM2_TI1 ADC_IN1 VDD_IO VSS_IO VSS18 P1.00 TIM0_OC2 P1.01 TIM0_TI2 P1.13 ADC_IN14 P1.14/ ADC_IN15 P1.04 PWM3N ADC_IN9 P1.05 PWM3 P1.06 PWM2N/ ADC_IN10 P1.07 PWM2 P1.08 PWM1N/ ADC_IN11 P2.05 PWM3N P2.06 PWM3 P2.07 PWM2N P2.08 PWM2 P2.09 PWM1N P1.09 PWM1 P1.10 PWM_EMERGENCY P0.04 SMI_CS0 SSP0_NSS P0.05 SSP0_SCLK SMI_CK P0.06 SMI_DIN SSP0_MISO P0.07 SMI_DOUT SSP0_MOSI
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure LQFP64 pinout
description
ADC_IN13 P1.12 ADC_IN0 TIM2_OC1 P0.02 TIM0_TI1 P0.01 BOOT0 TIM0_OC1 P0.00 ADC_IN8 TIM1_TI1 P0.29 TIM1_OC1 P0.28 TEST VSS_IO_4 UART1_TX P0.21 UART1_RX P0.20 JTMS P1.19 JTCK P1.18 JTDO P1.17 JTDI P1.16 NJTRST UART2_TX UART0_RTS RTCK P0.13
LQFP64 V18BKP I/Os
P1.09 PWM1 P1.10 PWM_EMERGENCY P0.04 SMI_CS0 /SSP0_NSS P0.05 SSP0_SCLK SMI_CK P0.06 SMI_DIN SSP0_MISO P0.07 SMI_DOUT SSP0_MOSI VREG_DIS VSS_IO_2 VSSA_ADC VDDA_ADC VDD_IO_2 P1.03 TIM2_TI2 P0.14 CAN_RX USB_DP P0.15 CAN_TX USB_DN NRSTIN NRSTOUT XRTC2 XRTC1 V18BKP VSSBKP VSS18 V18REG
P0.03 TIM2_TI1 ADC_IN1 VDD_IO_1 VSS_IO_1 VSS18 P1.04 PWM3N ADC_IN9 P1.05 PWM3 P1.06 PWM2N ADC_IN10 P1.07 PWM2
input channels External interrupts Wake-up Lines
SMI_CS1 ADC_IN2 UART0_CTS UART2_RX /P0.12 SMI_CS2 BOOT1 UART0_TX P0.11 SMI_CS3 UART0_RX P0.10 I2C_SDA/ P0.09 I2C_SCL P0.08 ADC_IN12 UART0_RTS P1.11 ADC_IN4 SSP1_NSS USB_CK P0.19 SSP1_MOSI P0.18 ADC_IN3 SSP1_MISO P0.17 SSP1_SCLK P0.16 VDD_IO_3 VDDA_PLL VSS_IO_3 VSSA_PLL
P1.08 PWM1N ADC_IN11
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description Table
P0.03 P1.12 P0.31 P0.29 P0.28 P2.03
STR750Fxx STR751Fxx STR752Fxx STR755Fxx LFBGA100 ball connections
P1.04 P1.05 VSS18 P0.05 P0.04 VSS_IO VDD_IO P0.06 P2.13 VSSA_ADC VDDA_ADC P0.07 P1.03 P2.11 P2.12 P1.02 P2.10 USB_DP USB_DN P0.14 P0.15 XRTC2 XRTC1 VSS_IO
P1.13 P1.14 P0.02 P0.01 P0.00 VDD_IO P0.30 VSS_IO P0.23 P0.22 P0.21 P0.20
P1.06 P1.08 P1.07 P1.09 P1.10 P2.09 P1.01 P1.15
VSS_IO TEST P1.00 NRSTOUT VREG_DIS NRSTIN P2.02 P2.01 P2.19 P0.27 P0.18 P2.04 P2.05 P2.00 P2.07 P2.18 P2.17 P0.19 P0.26 P0.17 P0.16 P2.06 2.08 P0.24 P0.25 VSS18 V18REG P2.14 P2.15 VSSBKP V18BKP P2.16 VDD_IO
NJTRST P1.18 P1.19 P0.13 P0.11 P0.10 P1.16 P1.17 P0.12 P1.11 P0.09 P0.08
VDDA_PLL VSSA_PLL
Table
LFBGA64 ball connections
VSS_IO VDD_IO P0.02 P0.28 P1.19 NJTRST P0.12 P0.09 P1.04 P1.05 P0.00 TEST P0.20 P1.16 P1.11 P0.08 P1.06 P1.07 VSS_IO P0.21 P1.17 P0.19 P0.17 P1.08 P1.09 VSS18 P0.05 P0.04 VDD_IO P0.06 P1.10 VSS_IO P0.07 P1.03 P0.14 P0.15 XRTC2 XRTC1
P0.03 P1.12 P0.01 P0.29 P1.18 P0.13 P0.11 P0.10
VREG_DIS VDDA_ADC VSSA_ADC NRSTOUT V18REG VDD_IO P0.18 NRSTIN VSS18 VSS_IO P0.16 V18BKP VSSBKP
VDDA_PLL VSSA_PLL
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx
description
description table
Legend abbreviations Table
Type: Input levels: input, output, supply, Inputs LVTTL VDD_IO 3.3V+/-0.3V VDD_IO 0.5V. both cases, means VILmax =0.8V VIHmin=2.0V inputs configured floating with internal weak pull-up pull down (pu/pd) Outputs configured Open Drain (OD) Push-Pull (PP) (see also note below Table There different types Output with different drives speed characteristics: fmax CL=50pF static drive capability VOL=0.4V VOL=1.3V (seeOutput driving current page fmax CL=50pF static drive capability VOL=0.4V (seeOutput driving current page fmax CL=50pF static drive capability VOL=0.4V (seeOutput driving current page
Inputs: Outputs:
External interrupts/wake-up lines: EITx
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description
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Port reset state
reset state ports GPIO input floating. Exceptions P1[19:16] P0.13 which configured JTAG alternate functions:
JTAG inputs (JTDI, JTMS JTDI) configured input floating ready accept JTAG sequences. JTAG output JTDO configured floating when idle JTAG operation) configured output push-pull only when serial JTAG data must output. JTAG output RTCK always configured output push-pull. outputs level during reset phase then outputs JTCK input signal resynchronized times internal clock. GPIO_PCx registers control JTAG selection, reset values GPIO_PCx P1[19:16] same other ports. Refer GPIO section STR750 Reference Manual register description reset values. P0.11 P0.00 sampled boot logic after reset, prior fetching first word user code address 0000 0000h. When booting from (and only this case), reset state following GPIOs "SMI alternate function output enabled": P0.07 (SMI_DOUT) P0.05 (SMI_CLK) P0.04 (SMI_CS0) P0.06 (SMI_DIN)
Note that other pins: SMI_CS1,2,3 (P0.12, P0.11, P0.10) affected. avoid excess power consumption, unused ports must tied ground. Table
LFBGA100(1) LFBGA64(2) Input Level
STR750F description
Usable Standby Input Ext. /Wake-up Output
LQFP100(1)
pu/pd
name
Capability
LQFP64(2)
floating
Main function (after reset)
Type
Alternate function
P1.12 ADC_IN13
EIT12
Port 1.12
ADC: Analog input TIM2: Output Compare 1(4) ADC: Analog input
P0.02 TIM2_OC1 ADC_IN0 P0.01 TIM0_TI1
EIT0
Port 0.02
Port 0.01 Port 0.00 Boot mode selection input Port 0.31 Port 0.30
TIM0: Input Main Clock Capture trigger Output external clock
P0.00 TIM0_OC1 BOOT0 P0.31 TIM1_TI2 P0.30 TIM1_OC2
TIM0: Output Compare
TIM1: Input Capture trigger external clock TIM1: Output Compare
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LFBGA100(1) LFBGA64(2) Input Level
description
STR750F description (continued)
Usable Standby Input Ext. /Wake-up Output
LQFP100(1)
pu/pd
name
Capability
LQFP64(2)
floating
Main function (after reset)
Type
Alternate function
P0.29 TIM1_TI1 ADC_IN8 P0.28 TIM1_OC1
Port 0.29 Port 0.28
TIM1: Input Capture
ADC: Analog input
TIM1: Output Compare
TEST VSS_IO P0.23 UART1_RTS ADC_IN6 P2.04 TIM2_OC1 P2.03 UART1_RTS P2.02 P0.22 UART1_CTS ADC_IN5
Reserved, must tied ground Ground Voltage digital I/Os Port 0.23 UART1: Ready Send output(4) TIM2: Output Compare 1(4) UART1: Ready Send output(4) analog input
Port 2.04
Port 2.03 Port 2.02 Port 0.22
UART1: Clear Send input
ADC: Analog input
P0.21 UART1_TX P0.20 UART1_RX P1.19 JTMS
Port 0.21 Port 0.20 JTAG mode selection input(6) JTAG clock input(6) JTAG data output(6) JTAG data input(6)
UART1: Transmit data output (remappable P0.15)(4) UART1: Receive data input (remappable P0.14)(4) Port 1.19
P1.18 JTCK P1.17 JTDO P1.16 JTDI NJTRST P2.01 P2.00
Port 1.18 Port 1.17 Port 1.16
JTAG reset input(5) Port 2.01 Port 2.00 Port 0.13
P0.13 RTCK UART0_RTS UART2_TX
JTAG return clock output(6)
UART2: Transmit UART0: Ready Send output(4) Data output (when remapped)(8)
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LFBGA100(1) LFBGA64(2) Input Level
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
STR750F description (continued)
Usable Standby Input Ext. /Wake-up Output
LQFP100(1)
pu/pd
name
Capability
LQFP64(2)
floating
Main function (after reset)
Type
Alternate function
P0.12 UART2_RX UART0_CTS ADC_IN2 SMI_CS1
UART0: Clear Send input Port 0.12 Serial Memory Interface: chip select output
ADC: Analog input UART2: Receive Data input (when remapped)(8) Serial Memory Interface: chip select output Serial Memory Interface: chip select output
P0.11 UART0_TX BOOT1 SMI_CS2 P0.10 UART0_RX SMI_CS3 P0.09 I2C_SDA P0.08 I2C_SCL P2.19 P2.18 P2.17 UART2_RTS P1.11 /UART0_RTS ADC_IN12 P0.27 UART2_RTS ADC_IN7 P0.26 UART2_CTS P0.25 UART2_TX P0.24 UART2_RX
Port 0.11/Boot mode selection input Port 0.10 Port 0.09 Port 0.08 Port 2.19 Port 2.18 Port 2.17
UART0: Transmit data output
EIT4
UART0: Receive Data input I2C: Serial Data I2C: Serial clock
EIT3
UART2: Ready Send output(4) UART0: Ready Send output(4) UART2: Ready Send output(8) ADC: Analog input ADC: Analog input
EIT11
Port 1.11
Port 0.27
Port 0.26 Port 0.25 Port 0.24
UART2: Clear Send input UART2: Transmit data output (remappable P0.13)(8) UART2: Receive data input (remappable P0.12)(8) SSP1: Slave select input (remappable P0.11)(8) USB: Clock input ADC: Analog input
P0.19 USB_CK SSP1_NSS ADC_IN4
EIT6
Port 0.19
P0.18 SSP1_MOSI
Port 0.18
SSP1: Master out/slave data (remappable P0.10)(8) SSP1: Master in/slave data (remappable P0.09)(8) ADC: Analog input
P0.17 SSP1_MISO ADC_IN3 P0.16 SSP1_SCLK
Port 0.17
Port 0.16
SSP1: serial clock (remappable P0.08)(8)
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table
LFBGA100(1) LFBGA64(2) Input Level
description
STR750F description (continued)
Usable Standby Input Ext. /Wake-up Output
LQFP100(1)
pu/pd
name
Capability
LQFP64(2)
floating
Main function (after reset)
Type
Alternate function
P2.16 VDD_IO VDDA_PLL
Port 2.16 Supply voltage digital I/Os Supply voltage main oscillator
VSS_IO VSSA_PLL P2.15 P2.14 Ground voltage digital I/Os Ground voltage Port 2.15 Port 2.14 Stabilization main voltage regulator. Requires external capacitors least 10µF between V18REG VSS18. Figure 4.2. connected 1.8V external power supply when embedded regulators used,
V18REG
VSS18 VSSBKP
Ground Voltage main voltage regulator Stabilization power voltage regulator. Ground Voltage power voltage regulator. Requires external capacitors least between V18BKP VSSBKP. Figure 4.2. connected 1.8V external power supply when embedded regulators used, oscillator Realtime Clock
V18BKP
XRTC1 XRTC2 NRSTOUT NRSTIN P1.15 WKP_STDBY P2.13 P2.12 EIT5 EIT15
Reset output Reset input Port 1.15 Port 2.13 Port 2.12 Port 0.15 Port 0.14 CAN: Transmit data output CAN: Receive data input Wake-up from STANDBY input
P0.15 CAN_TX P0.14 CAN_RX USB_DN USB_DP
USB: bidirectional data (data USB: bidirectional data (data TIM2: Input Capture trigger external clock (remappable P0.07)(8)
P1.03 TIM2_TI2
Port 1.03
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description Table
LFBGA100(1) LFBGA64(2) Input Level
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
STR750F description (continued)
Usable Standby Input Ext. /Wake-up Output
LQFP100(1)
pu/pd
name
Capability
LQFP64(2)
floating
Main function (after reset)
Type
Alternate function
P1.02 TIM2_OC2 VDD_IO VDDA_ADC P2.11 P2.10 VSSA_ADC VSS_IO VREG_DIS P0.07 SMI_DOUT SSP0_MOSI P0.06 SMI_DIN SSP0_MISO
Port 1.02
TIM2: Output compare (remappable P0.06)(8)
Supply Voltage digital I/Os Supply Voltage converter Port 2.11 Port 2.10 Ground Voltage converter Ground Voltage digital I/Os EIT2 Voltage Regulator Disable input Port 0.07 Serial Memory Interface: data output Serial Memory Interface: data input SSP0: Serial clock Serial Memory Interface: chip select output SSP0: Master Slave data SSP0: Master Slave data Serial Memory Interface: Serial clock output SSP0: Slave select input
Port 0.06
P0.05 SSP0_SCLK SMI_CK P0.04 SMI_CS0 SSP0_NSS
EIT1
Port 0.05
Port 0.04
P1.10 PWM_EMERGE P1.09 PWM1 P2.09 PWM1N P2.08 PWM2 P2.07 PWM2N P2.06 PWM3 P2.05 PWM3N P1.08 PWM1N ADC_IN11
EIT10 EIT9
Port 1.10 Port 1.09 Port 2.09 Port 2.08 Port 2.07 Port 2.06 Port 2.05
PWM: Emergency input PWM: PWM1 output PWM: PWM1 complementary output(4) PWM: PWM2 output(4) PWM: PWM2 complementary output(4) PWM: PWM3 output(4) PWM: PWM3 complementary output(4) PWM: PWM1 complementary output(8) ADC: analog input
EIT7 EIT8
Port 1.08 Port 1.07 Port 1.06 Port 1.05
P1.07 PWM2 P1.06 PWM2N ADC_IN10
PWM: PWM2 output(4) PWM: PWM2 complementary output(4) ADC: analog input
P1.05 PWM3
PWM: PWM3 output(4)
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table
LFBGA100(1) LFBGA64(2) Input Level
description
STR750F description (continued)
Usable Standby Input Ext. /Wake-up Output
LQFP100(1)
pu/pd
name
Capability
LQFP64(2)
floating
Main function (after reset)
Type
Alternate function
P1.04 PWM3N ADC_IN9 P1.14 ADC_IN15 P1.13 ADC_IN14 P1.01 TIM0_TI2 P1.00 TIM0_OC2
Port 1.04
PWM: PWM3 complementary output(4)
ADC: analog input
EIT13
Port 1.14 Port 1.13
ADC: analog input ADC: analog input TIM0: Input Capture trigger external clock (remappable P0.05)(8) TIM0: Output compare (remappable P0.04)(8)
Port 1.01
Port 1.00
Stabilization main voltage regulator. Requires external capacitors 33nF between VSS18. Figure 4.2. connected 1.8V external power supply when embedded regulators used. Ground Voltage main voltage regulator. Ground Voltage digital I/Os Supply Voltage digital I/Os Port 0.03 TIM2: Input Capture trigger external clock ADC: analog input
VSS18 VSS_IO VDD_IO P0.03 TIM2_TI1 ADC_IN1
STR755FVx part numbers, pins must left unconnected. available pins LQPFP64 LFBGA64 packages internally tied level. None I/Os True Open Drain: when configured Open Drain, there always protection diode between VDD_IO. 100-pin package, this Alternate Function duplicated ports. configure port this other port then free general purpose (GPIO), external interrupt/wake-up lines, analog input (ADC_IN) where these functions listed table. mandatory that NJTRST reset ground during power-up phase. recommended connect this NRSTOUT available) NRSTIN. After reset, these pins enabled JTAG alternate function (Port reset state page 16). these ports general purpose (GPIO), DBGOFF control GPIO_REMAP0R register must software this case, debugging these I/Os JTAG possible). There different TQFP 64-pin packages: first one, pins mapped DN/DP while second one, they mapped P0.15/CAN_TX P0.14/CAN_RX. details remapping these alternate functions, refer GPIO_REMAP0R register description.
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description
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
External components
Figure Required external capacitors when regulators used
VSS18 V18BKP VSSBKP
VSS18
V18BKP VSSBKP
LQFP100
VSS18
LQFP64
VSS18
V18REG VDD_IO
V18REG VDD_IO
VSS18
V18BKP VSSBKP
VSS18
V18BKP VSSBKP
LFBGA100
LFBGA64
VSS18 V18REG
VSS18
V18REG VDD_IO
VDD_IO
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Memory
Memory
Figure Memory
Peripheral Memory Space Kbytes
0xFFFF FFFF 0xFFFF FC00 0xFFFF FBFF 0xFFFF F800 0xFFFF F7FF 0xFFFF F400 0xFFFF F3FF
0xE000 0000 0xDFFF FFFF
Addressable Memory Space Gbytes
0xFFFF FFFF 0xFFFF 8000 ARM7 BRIDGE
Reserved EXTIT
FLASH Memory Space 128/256 Kbytes
0x2010 DFFF 0x2010 C000 0x2010 0017 0x2010 0000
0xFFFF F000 0xFFFF EFFF 0xFFFF EC00 0xFFFF EBFF
Reserved
0xC000 0000 0xBFFF FFFF
SystemMemory Flash registers
0xFFFF E800 0xFFFF E7FF
GPIO Ports
0xFFFF E400 0xFFFF E3FF 0xFFFF E000 0xFFFF DFFF 0xFFFF DC00 0xFFFF DBFF
Reserved UART2 UART1 UART0 Reserved Reserved Reserved SSP1 SSP0 Reserved Reserved Registers Reserved
0xA000 0000 0x9FFF FFFF
0xFFFF D800 0xFFFF D7FF 0x200C 0x200C 0x200C 0x200C 0x200C 4000 3FFF 2000 1FFF 0000 0xFFFF D400 0xFFFF D3FF
B1F1 B1F0
0xFFFF D000 0xFFFF CFFF 0xFFFF CC00 0xFFFF CBFF 0xFFFF C800 0xFFFF C7FF 0xFFFF C400 0xFFFF C3FF
0x9000 0013 0x9000 0000 0x83FF FFFF 0x8000 0000 0x7FFF FFFF
Registers
Ext. Memory
0xFFFF C000 0xFFFF BFFF 0xFFFF BC00 0xFFFF BBFF
0x6000 0047 0x6000 0000 0x5FFF FFFF CONF MRCC
0xFFFF B800 0xFFFF B7FF 0xFFFF B400 0xFFFF B3FF
0x2003 FFFF
0xFFFF B000 0xFFFF AFFF
B0F7(2)
0xFFFF AC00 0xFFFF ABFF 0xFFFF A800 0xFFFF A7FF 0xFFFF 0xFFFF 0xFFFF 0xFFFF 0xFFFF
0x4000 3FFF 0x4000 0000 0x3FFF FFFF Internal SRAM
0x2003 0000 0x2002 FFFF
0x2002 0000 0x2001 FFFF
B0F6(2)
A400 A3FF A200 x16-bit A000 9FFF
Reserved
0xFFFF 9C00 0xFFFF 9BFF
0x2010 0017 0x2000 0000 0x1FFF FFFF Internal Flash
B0F5
0xFFFF 9800 0xFFFF 97FF 0xFFFF 9400 0xFFFF 93FF
TIM2 TIM1
128K/256K+16K+32B
0x2001 0000 0x2000 FFFF
0xFFFF 9000 0xFFFF 8FFF
B0F4
0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 0x2000 8000 7FFF 6000 5FFF 4000 3FFF 2000 1FFF 0000
TIM0 Timer Reserved
0xFFFF 8C00 0xFFFF 8BFF 0xFFFF 8800 0xFFFF 87FF 0xFFFF 8400 0xFFFF 83FF 0xFFFF 8000
0x0000 0000 Boot Memory(1)
B0F3 B0F2 B0F1 B0F0
128K/256K
internal Flash Boot Mode, internal FLASH aliased 0x0000 0000h Only available STR750Fx2 Reserved
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Electrical parameters
Parameter conditions
Unless otherwise specified, voltages referred VSS.
6.1.1
Minimum maximum values
Unless otherwise specified minimum maximum values guaranteed worst conditions ambient temperature, supply voltage frequencies tests production 100% devices with ambient temperature TAmax (given selected temperature range). Data based product characterisation, design simulation and/or technology characteristics indicated table footnotes tested production. Based characterization, minimum maximum values refer sample tests represent mean value plus minus three times standard deviation (mean±3).
6.1.2
Typical values
Unless otherwise specified, typical data based TA=25° VDD_IO=3.3 (for VVDD_IO3.6 voltage range) V18=1.8 They given only design guidelines tested. Typical accuracy values determined characterization batch samples from standard diffusion over full temperature range, where devices have error less than equal value indicated (mean±2).
6.1.3
Typical curves
Unless otherwise specified, typical curves given only design guidelines tested.
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Electrical parameters
6.1.4
Loading capacitor
loading conditions used parameter measurement shown Figure Figure loading conditions
STR7
CL=50pF
6.1.5
input voltage
input voltage measurement device described Figure Figure input voltage
STR7
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
6.1.6
Power supply schemes
When mentioned, some electrical parameters refer dedicated power scheme among four possibilities. four different power schemes described below.
Power supply scheme Single external power source
Figure Power supply scheme
V18_BKP
VSS_BKP
STANDBY MODE THIS BLOCK KEPT POWERED
NORMAL MODE
VBACKUP
VREG_DIS
33nF
POWER LPVREG ~1.4V VOLTAGE REGULATOR POWER SWITCH
BACKUP CIRCUITRY OSC32K, WAKEUP LOGIC, BACKUP REGISTERS)
VSS18 V18REG
10µF
VSS18
VDD_IO 3.3V
+/-0.3V
VSS_IO
MAIN VMVREG 1.8V VOLTAGE REGULATOR VIO=3.3V
VCORE
KERNEL LOGIC (CPU DIGITAL MEMORIES)
I/Os
LOGIC
VDD_PLL VSS_PLL
3.3V
VDD_ADC
3.3V
VSS_ADC ADCIN
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Electrical parameters
Power supply scheme Dual external 1.8V 3.3V supply
Figure Power supply scheme
V18_BKP
VSS_BKP
VDD_IO
VREG_DIS
VBACKUP VLPVREG
V18REG 1.8V VSS18 VDD_IO 3.3V
+/-0.3V
POWER VOLTAGE REGULATOR
BACKUP CIRCUITRY (OSC32K, WAKEUP LOGIC, BACKUP REGISTERS)
POWER SWITCH
MAIN VOLTAGE REGULATOR
VSS_IO
VMVREG
VCORE
KERNEL (CORE DIGITAL MEMORIES)
VIO=3.3V
I/Os LOGIC
VDD_PLL VSS_PLL
3.3V
VDD_ADC
3.3V
VSS_ADC ADCIN
NOTE EXTERNAL POWER SUPPLY MUST ALWAYS KEPT
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Power supply scheme Single external power source
Figure Power supply scheme
V18_BKP
VSS_BKP
STANDBY MODE THIS BLOCK KEPT POWERED
NORMAL MODE
VBACKUP
VREG_DIS
33nF
POWER LPVREG ~1.4V VOLTAGE REGULATOR POWER SWITCH
BACKUP CIRCUITRY OSC32K, WAKEUP LOGIC, BACKUP REGISTERS)
VSS18 V18REG
10µF
VSS18
VDD_IO 5.0V
+/-0.5V
VSS_IO
MAIN VMVREG 1.8V VOLTAGE REGULATOR VIO=5.0V
VCORE
KERNEL LOGIC (CPU DIGITAL MEMORIES)
I/Os
LOGIC
VDD_PLL VSS_PLL
5.0V
VDD_ADC
5.0V
VSS_ADC ADCIN
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Electrical parameters
Power supply scheme Dual external supply
Figure Power supply scheme
V18_BKP
VSS_BKP
VDD_IO
VREG_DIS
VBACKUP
V18REG 1.8V VSS18 VDD_IO 5.0V
+/-0.5V
POWER VLPVREG VOLTAGE REGULATOR POWER SWITCH
BACKUP CIRCUITRY (OSC32K, WAKEUP LOGIC, BACKUP REGISTERS)
MAIN VOLTAGE REGULATOR
VSS_IO
VMVREG
VCORE
KERNEL (CORE DIGITAL MEMORIES)
VIO=5.0V
I/Os LOGIC
VDD_PLL VSS_PLL
5.0V
VDD_ADC
5.0V
VSS_ADC ADCIN
NOTE EXTERNAL 5.0V POWER SUPPLY MUST ALWAYS KEPT
6.1.7
characteristics versus various power schemes (3.3V 5.0V)
Unless otherwise mentioned, characteristics valid both
VDD_IO=3.0 with EN33=1 VDD_IO=4.5 with EN33=0
When VDD_IO=3.0 I/Os tolerant.
6.1.8
Current consumption measurements
current consumption measurements mentioned below refer Power scheme described Figure Figure
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure Power consumption measurements power scheme (regulators enabled)
VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins ballast regulator transistor pins (including V18BKP) 1.8V internal load 3.3V internal load IDDA_ADC load load
3.3V Supply
measured, which corresponds total current consumption IDDA_PLL IDDA_ADC
Figure Power consumption measurements power scheme (regulators disabled)
VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins 3.3V internal load IDDA_ADC load load
IDD_v33 3.3V Supply 1.8V Supply IDD_v18
pins (including V18BKP)
IDD_v33 IDD_v18 measured which correspond IDD_v33 IDDA_PLL IDDA_ADC IDD_v18
1.8V internal load
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Electrical parameters
Figure Power consumption measurements power scheme (regulators enabled)
VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins ballast regulator transistor pins (including V18BKP) 1.8V internal load 5.0V internal load IDDA_ADC load load
5.0V Supply
measured, which corresponds total current consumption IDDA_PLL IDDA_ADC
Figure Power consumption measurements power scheme (regulators disabled)
VDDA_ADC pins VDDA_PLL pins IDDA_PLL VDD_IO pins 5.0V internal load IDDA_ADC load load
IDD_v50 5.0V Supply 1.8V Supply IDD_v18
pins (including V18BKP)
IDD_v50 IDD_v18 measured which correspond IDD_v50= IDDA_PLL IDDA_ADC IDD_v18
1.8V internal load
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Absolute maximum ratings
Stresses above those listed "absolute maximum ratings" cause permanent damage device. This stress rating only functional operation device under these conditions implied. Exposure maximum rating conditions extended periods affect device reliability.
6.2.1
Voltage characteristics
Table
Symbol
Voltage characteristics
Ratings -0.3 -0.3 VSS-0.3 VDD_IO+0.3 VSS-0.3 VDD_IO+0.3 Absolute maximum ratings (electrical sensitivity) page Absolute maximum ratings (electrical sensitivity) page Unit
VDD_x VSS_X(1) Including VDDA_ADC VDDA_PLL VSS18 Digital Supply voltage power pins (when provided externally) Input voltage Variations between different power pins Variations between different power pins(3) Variations between different ground pins Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model)
|VDDx| |V18x| |VSSX VSS| VESD(HBM)
VESD(MM)
power (VDD_IO, VDDA_ADC, VDDA_PLL) ground (VSS_IO, VSSA_ADC, VDDA_ADC) pins must always connected external 3.3V 5.0V supply. When powered 3.3V, I/Os tolerant. IINJ(PIN) must never exceeded. This implicitly insured maximum respected. maximum cannot respected, injection current must limited externally IINJ(PIN) value. positive injection induced VIN>VDD while negative injection induced VIN<VSS. true open-drain pads, there positive injection current, corresponding maximum must always respected Only when using external power supply. power (V18, V18REG, V18BKP) ground (VSS18, VSSBKP) pins must always connected external supply.
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Electrical parameters
6.2.2
Current characteristics
Table
Symbol IVDD_IO(1) IVSS_IO
Current characteristics
Ratings Total current into VDD_IO power lines (source) Total current ground lines (sink)
Maximum value
Unit
Output current sunk control Output current source I/Os control Injected current NRSTIN IINJ(PIN) IINJ(PIN)(3) Injected current pins Injected current other pins)
Total injected current (sum control
user GPIOs source sink high current type High Sink I/Os). this case, user must ensure that these absolute max. values exceeded (taking into account power consumption) must follow rules described Section 6.3.8: port characteristics page power (VDD_IO, VDDA_ADC, VDDA_PLL) ground (VSS_IO, VSSA_ADC, VDDA_ADC) pins must always connected external 3.3V 5.0V supply. IINJ(PIN) must never exceeded. This implicitly insured maximum respected. maximum cannot respected, injection current must limited externally IINJ(PIN) value. positive injection induced VIN>VDD while negative injection induced VIN<VSS. Data based TA=25°C. Negative injection disturbs analog performance device. note Section 6.3.12: 10-bit characteristics page When several inputs submitted current injection, maximum IINJ(PIN) absolute positive negative injected currents (instantaneous values). These results based characterization with IINJ(PIN) maximum current injection four port pins device.
6.2.3
Thermal characteristics
Table
Symbol TSTG
Thermal characteristics
Ratings Storage temperature range Maximum junction temperature Value +150 Unit
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
6.3.1
Operating conditions
General operating conditions
Subject general operating conditions VDD_IO, unless otherwise specified. Table
Symbol
General operating conditions
Parameter Conditions Accessing SRAM with wait states Accessing Flash burst mode, TA85° Accessing Flash burst mode TA>85° Accessing Flash with wait states Write access Flash registers(1) Accessing Flash mode 1.65 LQFP100 Unit
1.95
fHCLK
Internal Clock frequency
fPCLK
Internal Clock frequency Standard Operating Voltage Power Scheme
VDD_IO
Standard Operating Voltage Power Scheme Standard Operating Voltage Power Scheme
Power dissipation suffix 105° suffix 7(2)
LQFP64 LFBGA100 LFBGA64
Ambient temperature suffix Maximum power dissipation version power dissipation(3) Ambient temperature suffix Maximum power dissipation version power dissipation Suffix Version Junction temperature range Suffix Version
Write access Flash registers either program, erase, protection un-set protection operation. lower, higher values allowed long does exceed TJmax (see Section 7.2: Thermal characteristics page 79). power dissipation state, extended this range long does exceed TJmax (see Section 7.2: Thermal characteristics page 79).
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Electrical parameters
6.3.2
Operating conditions power-up power-down
Subject general operating conditions Table
Symbol tVDD_IO
Operating conditions power-up power-down
Parameter VDD_IO rise time rate rise time rate When power supplied externally Conditions Min(1) Max(1) Unit ms/V ms/V
tV18
Data guaranteed characterization, tested production.
6.3.3
Embedded voltage regulators
Subject general operating conditions VDD_IO, Table
Symbol VMVREG VLPVREG
Embedded voltage regulators
Parameter MVREG power supply(1) LPVREG power supply(2) Voltage Regulators start-up time reach final value) VDD_IO power-up(3) Conditions load <150 load VDD_IO rise slope µs/V VDD_IO rise slope ms/V 1.65 1.30 1.80 1.40 1.95 1.50 Unit
tVREG_PWRUP(1)
VMVREG observed V18, V18REG V18BKP pins except following case: STOP mode with MVREG (LP_PARAM13 bit). note STANDBY mode. note STANDBY mode, VLPVREG observed V18BKP STOP mode, VLPVREG observed V18, V18REG V18BKP pins. Once VDD_IO reached (Regulator Startup Monitor) generates internal RESET during this start-up time.
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
6.3.4
Supply current characteristics
current consumption measured described Figure page Figure page Subject general operating conditions VDD_IO,
Maximum power consumption
measurements Table Table placed under following conditions:
pins configured output push-pull peripherals disabled except explicitly mentioned. Embedded Regulators used provide (except explicitly mentioned). Maximum power consumption modes
Parameter Conditions Typ(2) Unit
Table
Symbol
External Clock with multiplication, code running from RAM, peripherals enabled 3.3V Supply current MRCC_PLCKEN register: fHCLK=60 mode MHz, fPCLK=30 range Single supply scheme Figure Figure External Clock, code running from RAM: fHCLK=60 MHz, fPCLK=30 3.3V Supply current Single supply scheme mode Figure 12./ Figure range Parameter setting BURST=1, WFI_FLASHEN=1
conditions these consumption measurements described beginning Section 6.3.4. Typical data based TA=25°C, VDD_IO=3.3V 5.0V V18=1.8V unless otherwise specified. Data based product characterisation, tested production VDD_IO (1.95V dual supply mode regulator output value single supply mode) max.
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table
Symbol
Electrical parameters
Maximum power consumption STOP STANDBY modes
Max(3) Parameter Conditions Typ(2) 25°C 85°C 105°C Unit
LP_PARAM bits: OFF(4) Single supply scheme Figure Supply current STOP mode LP_PARAM bits: Dual supply scheme Figure LP_PARAM bits: OFF(4) Single supply scheme Figure LP_PARAM bits: Dual supply scheme Figure Supply current STANDBY mode
3.3V range IDD_V18 IDD_V33 range IDD_V18 IDD_V50 range
range
conditions these consumption measurements described beginning Section 6.3.4. Typical data based TA=25°C, VDD_IO=3.3V 5.0V V18=1.8V unless otherwise specified. Data based product characterisation, tested production VDD_IO (1.95V dual supply mode regulator output value single supply mode). this mode, whole digital circuitry powered internally LPVREG approximately 1.4V, which significantly reduces leakage currents.
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure Power consumption STOP mode Figure Power consumption STOP mode Single supply scheme (3.3 Single supply scheme range) range)
IStop (uA) Temp (°C) (3.3V) IStop (uA) (3.6V) Temp (°C) (5.0V) (5.5V)
Figure Power consumption STANDBY mode (3.3 range)
Figure Power consumption STANDBY mode range)
IStandby (uA) Temp (°C) (3.3V) IStandby (uA) (3.6V)
Temp (°C) (5.0V) (5.5V)
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Electrical parameters
Typical power consumption
following measurement conditions apply Table Table Table mode:
Program executed from Flash (except especially mentioned). program consists infinite loop. When fHCLK MHz, burst mode activated. standard crystal source used. cases used multiply frequency. measurements done single supply scheme with internal regulators used (see Figure Mode measurement conditions similar mode (OSC4M enabled). addition, Flash disabled depending burst mode activation: frequencies greater than MHz, burst mode activated Flash kept enabled setting WFI_FLASH_EN (this cannot reset when burst mode activated). frequencies less than equal MHz, burst mode deactivated, WFI_FLASH_EN reset LP_PARAM14 (Flash disabled mode).
Mode:
SLOW mode:
same program mode executed from Flash. clocked FREEOSC, OSC4M, LPOSC OSC32K. Only EXTIT peripheral enabled MRCC_PCLKEN register. SLOW-WFI, measurement conditions similar SLOW mode (CPU clocked frequency clock). addition, LP_PARAM14 (FLASH OFF). routine itself executed from SRAM allowed execute from internal FLASH) Several measurements given: single supply scheme with internal regulators used (see Figure 12): dual supply scheme (see Figure 13). Three measurements given: disabled, only consumption LPVREG remain (almost leakage currents) running, clocked standard 32.768 crystal. running, clocked internal Power oscillator (LPOSC)
SLOW-WFI mode:
STOP mode:
STANDBY mode:
STANDBY mode only supported single supply scheme (see Figure
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Subject general operating conditions VDD_IO, Table
Symbol
Single supply typical power consumption Run, WFI, Slow Slow-WFI modes
Para meter Conditions 3.3V typ(1) typ(2) Unit
Clocked OSC4M with multiplication, peripherals enabled MRCC_PLCKEN register: fHCLK=60 MHz, fPCLK=30 fHCLK=56 MHz, fPCLK=28 fHCLK=48 MHz, fPCLK=24 fHCLK=32 MHz, fPCLK=32 fHCLK=16 MHz, fPCLK=16 Supply current fHCLK=8 MHz, fPCLK=8 mode(4) Clocked OSC4M with multiplication, only EXTIT peripheral enabled MRCC_PLCKEN register: fHCLK=60 MHz, fPCLK=30 fHCLK=56 MHz, fPCLK=28 fHCLK=48 MHz, fPCLK=24 fHCLK=32 MHz, fPCLK=32 fHCLK=16 MHz, fPCLK=16 fHCLK=8 MHz, fPCLK=8 Clocked OSC4M with multiplication, only EXTIT peripheral enabled MRCC_PLCKEN register: fHCLK=60 MHz, fPCLK=30 MHz(5) Supply current fHCLK=56 MHz, fPCLK=28 MHz(5) fHCLK=48 MHz, fPCLK=24 MHz(5) mode(4) fHCLK=32 MHz, fPCLK=32 MHz(6) fHCLK=16 MHz, fPCLK= fHCLK= MHz, fPCLK= MHz(6) Clocked FREEOSC: fHCLK=fPCLK=~5 MHz, Supply current Clocked OSC4M: fHCLK=fPCLK=4 Clocked LPOSC: fHCLK=fPCLK=~300 SLOW mode(4) Clocked OSC32K: fHCLK=fPCLK=32.768 Clocked FREEOSC: fHCLK=fPCLK=~5 Supply current Clocked OSC4M: fHCLK=fPCLK=4 SLOW-WFI Clocked LPOSC: fHCLK=fPCLK=~300 (4)(7) mode Clocked OSC32K: fHCLK=fPCLK=32.768
Typical data based TA=25° VDD_IO=3.3V. Typical data based TA=25° VDD_IO=5.0V.
3.65 1.15 0.98
3.75 1.65
conditions these consumption measurements described beginning Section 6.3.4 page Single supply scheme Figure Parameter setting BURST=1, WFI_FLASHEN=1 Parameter setting BURST=0, WFI_FLASHEN=0 Parameter setting WFI_FLASHEN=0, OSC4MOFF=1
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Electrical parameters
Dual supply supply typical power consumption Run, WFI, Slow Slow-WFI modes
calculate power consumption Dual supply mode, refer values given Table consider that this consumption split follows: IDD(single supply)~IDD(dual supply)= IDD_V18 IDD(VDD_IO) 3.3V range: IDD(VDD_IO) range: IDD(VDD_IO) Therefore most consumption sunk power supply This formula does apply STOP STANDBY modes, refer Table
Subject general operating conditions VDD_IO, Table
Symbol
Typical power consumption STOP STANDBY modes
Parameter Conditions LP_PARAM bits: OFF(5) LP_PARAM bits MVREG OSC4M OFF, FLASH OFF(6) LP_PARAM bits: MVREG OSC4M FLASH OFF(6) LP_PARAM bits: MVREG OSC4M OFF, FLASH LP_PARAM bits: MVREG OSC4M FLASH
3.3V Typ(1) 1950 2435 1475 1475
Typ(2) 1930 2425 1435 1445
Unit
Supply current STOP mode(4)
IDD(3) Supply current STOP mode(7)
LPPARAM bits: OFF, with V18=1.8 LP_PARAM bits: OSC4M FLASH LP_PARAM bits: OSC4M OFF, FLASH LP_PARAM bits: OSC4M FLASH Supply current STANDBY mode(4) clocked OSC32K
IDD_V18 IDD_V33 IDD_V18 IDD_V33 IDD_V18 IDD_V33 IDD_V18 IDD_V33
Typical data based TA=25°C, VDD_IO=3.3 V18=1.8 unless otherwise indicated table. Typical data based TA=25°C, VDD_IO=5.0 V18=1.8 unless otherwise indicated table. conditions these consumption measurements described beginning Section 6.3.4 page Single supply scheme Figure this mode, whole digital circuitry powered internally LPVREG approximately which significantly reduces leakage currents. this mode, whole digital circuitry powered internally MVREG Dual supply scheme Figure
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Supply clock manager power consumption
Table
Symbol
Supply clock manager power consumption
Parameter Conditions(1) External components specified crystal ceramic resonator oscillator (XT1/XT2) page 3.3V 1815 1795 Unit
Supply current resonator oscillator IDD(OSC4M) STOP mode (LP_PARAM bit: OSC4M IDD(FLASH) FLASH static current consumption STOP mode (LP_PARAM FLASH
Main Voltage Regulator static current IDD(MVREG) consumption STOP mode (LP_PARAM bit: MVREG STOP mode includes leakage where internally STANDBY mode where V18BKP internally respectively
Power Voltage Regulator IDD(LPVREG) current static current consumption
Measurements performed 3.3V single supply mode Figure
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Electrical parameters
On-Chip peripheral power consumption
Conditions: VDD_IO=VDDA_ADC=VDDA_PLL=3.3 ±10% unless otherwise specified. Clocked OSC4M with multiplication, fCK_SYS=64 MHz, fHCLK=32 MHz, fPCLK=32 On-Chip peripherals
Parameter Timer supply current Timer supply supply current current(2)
Table
Symbol IDD(TIM) IDD(PWM) IDD(SSP) IDD(UART) IDD(I2C) IDD(ADC) IDD(USB) IDD(CAN)
(3.3V 5.0V) 0.90
Unit
UART supply current supply current
supply current when converting supply current Note: VDD_IO must ±10% supply current
Data based differential measurement between reset configuration timer counter running MHz. IC/OC programmed pads toggling) Data based differential measurement between reset configuration running MHz. This measurement does include pads toggling consumption. Data based differential measurement between reset configuration permanent master communication maximum speed MHz. data sent 55h. This measurement does include toggling consumption. Data based differential measurement between reset configuration permanent UART data transmit sequence 1Mbauds. This measurement does include toggling consumption. Data based differential measurement between reset configuration (I2C disabled) permanent master communication 100kHz (data sent equal 55h). This measurement includes toggling consumption external 10kOhm external pull-up clock data lines. Data based differential measurement between reset configuration continuous conversions scan mode inputs configured AIN. Data based differential measurement between reset configuration running generic application. Data based differential measurement between reset configuration (CAN disabled) permanent data transmit sequence loopback mode 1MHz. This measurement does include toggling consumption.
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Electrical parameters
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6.3.5
Clock timing characteristics
external clock source
Subject general operating conditions VDD_IO, Table
Symbol fXT1 VXT1H VXT1L tw(XT1H) tw(XT1L) tr(XT1) tf(XT1) CIN(XT1)
external clock source
Parameter External clock source frequency input high level voltage input level voltage high time rise fall time VDD_IO Figure 0.7xVDD_IO Conditions(1) VDD_IO 0.3xVDD_IO Unit
Input leakage current input capacitance(3)
DuCy(XT1) Duty cycle
Data based typical application software.
Time measured between interrupt event interrupt vector fetch. tc(INST) number tCPU cycles needed finish current instruction execution. Data based design simulation and/or technology characteristics, tested production.
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Electrical parameters
XRTC1 external clock source
Subject general operating conditions VDD_IO, Table
Symbol fXRTC1 VXRTC1H VXRTC1L
XRTC1 external clock source
Parameter External clock source frequency XRTC1 input high level voltage XRTC1 input level voltage Figure 0.7xVDD_IO VSSVINVDD_I
Conditions(1)
32.768
VDD_IO
Unit
0.3xVDD_IO
tw(XRTC1H) XRTC1 high tw(XRTC1L) time(2) tr(XRTC1) tf(XRTC1) CIN(RTC1) XRTC1 rise fall time(2)
XRTCx Input leakage current XRTC1 input capacitance(2)
DuCy(RTC1) Duty cycle
Data based typical application software.
Data based design simulation and/or technology characteristics, tested production.
Figure Typical application with external clock source
VXT1H
VXT1L tr(XT1) tf(XT1) tw(XT1H) tw(XT1L)
TXT1
EXTERNAL CLOCK SOURCE hi-Z
fOSC4M
STR750
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Electrical parameters
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crystal ceramic resonator oscillator (XT1/XT2)
STR750 system clock input supplied OSC4M which clock generated from crystal ceramic resonator. using oscillator, software XTDIV enable divider generate OSC4M clock. information given this paragraph based product characterisation with specified typical external components. application, resonator load capacitors have placed close possible oscillator pins order minimize output distortion start-up stabilization time. Refer crystal/ceramic resonator manufacturer more details (frequency, package, accuracy.). Table
Symbol
crystal ceramic resonator oscillator (XT1/XT2)(1)
Parameter Conditions Crystal/Resonator Oscillator connected XT1/XT2 XTDIV=0 Crystal/Resonator Oscillator connected XT1/XT2 XTDIV=1 Unit
fOSC4M
Oscillator frequency
CL1(2)
Feedback resistor Recommended load capacitance versus equivalent RS=200 serial resistance crystal ceramic resonator (RS) driving current VDD_IO=3.3
tSU(OSC4M)(4) Startup time VDD_IO power-up
Resonator characteristics given crystal/ceramic resonator manufacturer.
recommended high-quality ceramic capacitors 5-pF 25-pF range (typ.) designed high-frequency applications selected match requirements crystal resonator. CL2, usually same size. crystal manufacturer typically specifies load capacitance which series combination CL2. capacitance must included when sizing used rough estimate combined board capacitance). relatively value resistor offers good protection against issues resulting from humid environment, induced leakage bias condition change. However, recommended take this point into account used tough humidity conditions. tSU(OSC4M) typical start-up time measured from moment VDD_IO powered (with quick VDD_IO ramp-up from 3.3V (<50s) stabilized 4MHz oscillation reached. This value measured standard crystal resonator vary significantly with crystal/ceramic resonator manufacturer.
Figure Typical application with crystal ceramic resonator
XTDIV
WHEN RESONATOR WITH INTEGRATED CAPACITORS
LINEAR AMPLIFIER
FEEDBACK LOOP
fOSC4M
RESONATOR
VDD/2
STR75X
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Electrical parameters
OSC32K crystal ceramic resonator oscillator
STR7 clock supplied with 32.768 Crystal/Ceramic resonator oscillator. information given this paragraph based product characterisation with specified typical external components. application, resonator load capacitors have placed close possible oscillator pins order minimize output distortion start-up stabilization time. Refer crystal/ceramic resonator manufacturer more details (frequency, package, accuracy.). Table
Symbol fOSC32K
OSC32K crystal ceramic resonator oscillator
Parameter Oscillator Frequency Feedback resistor VDD_IO=3.3 Conditions 32.768 12.5 Unit
Recommended load capacitance RS=40K versus equivalent serial resistance crystal ceramic resonator (RS)(1) driving current VDD_IO=3.3 VIN=VSS VDD_IO stabilized
tSU(OSC32K)(2) Startup time
oscillator selection optimized terms supply current using high quality resonator with small value. Refer crystal/ceramic resonator manufacturer more details tSU(OSC32K) start-up time measured from moment enabled software) stabilized oscillation reached. This value measured standard crystal resonator vary significantly with crystal/ceramic resonator manufacturer
Figure Typical application with 32.768 crystal ceramic resonator
WHEN RESONATOR WITH INTEGRATED CAPACITORS
FEEDBACK LOOP
XRTC1
fOSC32K
RESONATOR XRTC2
STR750
characteristics
Jitter Terminology
Self-referred single period jitter (period jitter) Period Jitter defined difference maximum period (Tmax) minimum period (Tmin) output where Tmax maximum time difference between consecutive clock rising edges Tmin minimum time difference between consecutive clock rising edges. Figure
Self-referred long term jitter period jitter) Self-referred long term Jitter defined difference maximum period (Tmax) minimum period (Tmin) output where Tmax maximum time
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Electrical parameters
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difference between consecutive clock rising edges Tmin minimum time difference between consecutive clock rising edges. should kept sufficiently large have long term jitter (ex: thousands). N=1, this becomes single period jitter. Figure
Cycle-to-cycle jitter period jitter) This corresponds time variation between adjacent cycles over random sample adjacent clock cycles pairs. Jitter(cycle-to-cycle) Max(Tcycle Tcycle n-1) Figure
Figure Self-referred jitter (single long term)
IDEAL CK_PLL -n+N
ACTUAL CK_PLL single period jitter
trigger point
long term jitter
Figure Cycle-to-cycle jitter
IDEAL CK_PLL -n+N
ACTUAL CK_PLL
Tcycle
Tcycle
Tcycle
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Electrical parameters
characteristics
Subject general operating conditions VDD_IO, Table
Symbol
characteristics
Value Parameter input clock Test Conditions fPLL_INx When operates (locked) fPLL_IN MHz(4) VDD_IO stable fPLL_IN MHz(4) VDD_IO stable +/-250 +/-2.5 +/-500 Max(1) Unit
fPLL_IN fPLL_OUT fVCO tLOCK tJITTER1(2)(3) tJITTER2(2)(3) tJITTER3(2)(3)
input clock duty cycle multiplier output clock frequency range lock time Single period jitter (+/-3 peak peak) Long term jitter (+/-3 peak peak)
Cycle cycle jitter (+/-3 peak fPLL_IN MHz(4) VDD_IO stable peak)
Data based product characterisation, tested production. Refer jitter terminology characteristics page details jitter specified. jitter specification holds true only 50mV (peak-to-peak) noise VDDA_PLL supplies. Jitter will increase noise more than 50mV. addition, assumes that input clock jitter. parameters (MX1, MX0, PRESC1, PRESC2) must respect constraints described characteristics page
Internal oscillators (FREEOSC LPOSC)
Subject general operating conditions VDD_IO, Table
Symbol fCK_FREEOSC fCK_LPOSC
Internal oscillators (FREEOSC LPOSC)
Parameter FREEOSC Oscillator Frequency LPOSC Oscillator Frequency Conditions Unit
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Electrical parameters
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6.3.6
Memory characteristics
Flash memory
Subject general operating conditions VDD_IO V18, unless otherwise specified. Table
Symbol tPDW tPB0 tPB1 tRPD tPSL tESL
Flash memory characteristics
Value Parameter Word Program Double Word Program Bank Program (256K) Bank Program (16K) Sector Erase (64K) Sector Erase (8K) Bank Erase (256K) Bank Erase (16K) Recovery when disabled Program Suspend Latency Erase Suspend Latency Single Word programming checker-board pattern Single Word programming checker-board pattern preprogrammed (all Preprogrammed (all preprogrammed (all Preprogrammed (all preprogrammed (all Preprogrammed (all preprogrammed (all Preprogrammed (all Test Conditions 1.54 1.176 4.9(2) 224(2) 2.94(2) 2.38(2) 560(2) 532(2) 13.7 11.2 Max(1) Unit
Data based characterisation tested production program/erase cycles.
Table
Symbol
Flash memory endurance data retention
Value Parameter Conditions Min(1) TA=85° time from Erase Resume next Erase Suspend Unit kcycles kcycles Years
NEND_B0 Endurance (Bank sectors) NEND_B1 Endurance (Bank sectors) YRET tESR Data Retention Erase Suspend Rate
Data based characterisation tested production.
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Electrical parameters
6.3.7
characteristics
Susceptibility tests performed sample basis during product characterization.
Functional (electro magnetic susceptibility)
Based simple running application product (toggling LEDs through ports), product stressed electro magnetic events until failure occurs (indicated LEDs).
ESD: Electro-Static Discharge (positive negative) applied pins device until functional disturbance occurs. This test conforms with 1000-4-2 standard. FTB: Burst Fast Transient voltage (positive negative) applied through 100pF capacitor, until functional disturbance occurs. This test conforms with 1000-4-4 standard.
device reset allows normal operations resumed. test results given table below based levels classes defined application note AN1709.
Designing hardened software avoid noise problems
characterization optimization performed component level with typical application environment simplified software. should noted that good performance highly dependent user application software particular. Therefore recommended that user applies software optimization prequalification tests relation with level requested application. Software recommendations: software flowchart must include management runaway conditions such
Corrupted program counter Unexpected reset Critical Data corruption (control registers.)
Prequalification trials: Most common failures (unexpected reset program counter corruption) reproduced manually forcing state RESET Oscillator pins second. complete these trials, stress applied directly device, over range specification values. When unexpected behaviour detected, software hardened prevent unrecoverable errors occurring (see application note AN1015). Table
Symbol
characteristics
Parameter Voltage limits applied induce functional disturbance Conditions VDD_IO=3.3 TA=+25° fCK_SYS=32 conforms 1000-4-2 Level/ Class Class
VFESD
VEFTB
Fast transient voltage burst limits applied VDD_IO=3.3 through 100pF pins induce TA=+25° fCK_SYS=32 functional disturbance conforms 1000-4-4
Class
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Electrical parameters
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Electro magnetic interference (EMI)
Based simple application running product (toggling LEDs through ports), product monitored terms emission. This emission test line with norm 1752/3 which specifies board loading each pin. Table characteristics
Conditions Flash devices: VDD_IO=3.3 TA=+25° LQFP64 package conforming 1752/3 Monitored Frequency Band Level [fOSC4M/fHCLK] Unit 4/32MHz 4/60MHz
Symbo Parameter
SEMI
Peak level
Absolute maximum ratings (electrical sensitivity)
Based three different tests (ESD, DLU) using specific measurement methods, product stressed order determine performance terms electrical sensitivity. more details, refer application note AN1181.
Electro-Static discharge (ESD)
Electro-Static Discharges positive then negative pulse separated second) applied pins each sample according each combination. sample size depends number supply pins device parts*(n+1) supply pin). models simulated: Human Body Model Machine Model. This test conforms JESD22-A114A/A115A standard. Table
Symbol VESD(HBM) VESD(MM) VESD(CDM)
Absolute maximum ratings
Ratings Electro-static discharge voltage (Human Body Model) Electro-static discharge voltage (Machine Model) Electro-static discharge voltage (Charge Device Model) TA=+25° Conditions Maximum value(1) 2000 Unit
Data based product characterisation, tested production.
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Electrical parameters
Static dynamic latch-up
complementary static tests required parts assess latch-up performance. supply overvoltage (applied each power supply pin) current injection (applied each input, output configurable pin) performed each sample. This test conforms EIA/JESD latch-up standard. more details, refer application note AN1181. DLU: Electro-Static Discharges (one positive then negative test) applied each samples when micro running assess latch-up performance dynamic mode. Power supplies typical values, oscillator connected near possible pins micro component reset mode. This test conforms IEC1000-4-2 SAEJ1752/3 standards. more details, refer application note AN1181. Electrical sensitivities
Parameter Static latch-up class TA=+25° TA=+85° TA=+105° VDD= fOSC4M=4 MHz, fCK_SYS=32 MHz, TA=+25° Conditions Class(1) Class
Table
Symbol
Dynamic latch-up class
Class
Class description: Class STMicroelectronics internal specification. limits higher than JEDEC specifications, that means when device belongs Class exceeds JEDEC standard. Class strictly covers JEDEC criteria (international standard).
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Electrical parameters
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6.3.8
port characteristics
General characteristics
Subject general operating conditions VDD_IO unless otherwise specified. Table General characteristics
static characteristics Symbol Vhys IINJ(PIN) IINJ(PIN
Parameter Input level voltage Input high level voltage Schmitt trigger voltage hysteresis(1) Injected Current Total injected current (sum control pins) Input leakage current robust pins Input leakage current(3)
Conditions
Unit
ports
Section 6.3.12 page VSSVINVDD_IO Floating input mode VIN=VSS VIN=VDD_IO VDD_IO=3.3 VDD_IO=5 VDD_IO=3.3 VDD_IO=5
Ilkg
Static current consumption(4) Weak pull-up equivalent resistor(5) Weak pull-down equivalent resistor(5) capacitance External interrupt/wake-up lines pulse time(6)
tw(IT)in
Hysteresis voltage between Schmitt trigger switching levels. When current limitation possible, absolute maximum rating must respected, otherwise refer IINJ(PIN) specification. positive injection induced VIN>VDD_IO while negative injection induced VIN<VSS. Refer Section page more details. Leakage could higher than max. negative current injected adjacent pins. Configuration recommended, unused pins must kept fixed voltage: using output mode example external pull-up pull-down resistor (see Figure 25). Data based design simulation and/or technology characteristics, tested production. pull-up pull-down equivalent resistor based resistive transistor. generate external interrupt, minimum pulse width applied port configured external interrupt source.
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure Connecting unused pins
Electrical parameters
STR7XXX
UNUSED PORT
UNUSED PORT
STR7XXX
Output driving current
I/Os have different drive capabilities:
outputs sink source +/-2 outputs sink source +/-4 outputs sink source +/-8 sink (with relaxed VOL).
application, user must limit number pins which drive current respect absolute maximum rating specified Section 6.2.2
current sourced I/Os VDD_IO, plus maximum consumption sourced VDD_IO, exceed absolute maximum rating IVDD_IO. current sunk I/Os VSS_IO plus maximum consumption sunk VSS_IO exceed absolute maximum rating IVSS_IO.
Subject general operating conditions VDD_IO unless otherwise specified.
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Electrical parameters Table Output driving current
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Output drive characteristics VDD_IO EN33 VDD_IO EN33 Symbol Type VOL(1) VOH(2) VOL(1) VOH(2) Parameter Conditions Unit
Output level voltage standard when pins sunk same IIO=+2 time Output high level voltage when pins sourced same time Output level voltage standard when pins sunk same IIO=+4 time Output high level voltage when pins sourced same time Output level voltage standard when pins sunk same IIO=+8 time VDD_IO-0.8 VDD_IO-0.8
VOL(1)
IIO=+20 Output level voltage high sink 85°C when pins sunk same 85°C time IIO=+8 Output high level voltage when pins sourced same time VDD_IO-0.8
VOH(2)
current sunk must always respect absolute maximum rating specified Section 6.2.2 (I/O ports control pins) must exceed IVSS_IO. current sourced must always respect absolute maximum rating specified Section 6.2.2 (I/O ports control pins) must exceed IVDD_IO.
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Electrical parameters
Output speed
Subject general operating conditions VDD_IO unless otherwise specified. Table Output speed
dynamic characteristics VDD_IO 3.6V EN33 VDD_IO 5.5V EN33 Type Symbol Parameter Conditions CL=50 CL=50 Between CL=50 CL=50 Between CL=50pF CL=50 Between Unit
fmax(IO)out Maximum Frequency(1) tf(IO)out tr(IO)out Output high level fall time(2) Output high level rise time(2)
fmax(IO)out Maximum Frequency(1) tf(IO)out tr(IO)out Output high level fall time(2) Output high level rise time(2)
fmax(IO)out Maximum Frequency(1) tf(IO)out tr(IO)out Output high level fall time(2) Output high level rise time(2)
maximum frequency defined described Figure Data based product characterisation, tested production.
Figure output speed definition
EXTERNAL OUTPUT 50pF
tr(IO)out
tr(IO)out
Maximum frequency achieved (2/3)T duty cycle (45-55%) when loaded 50pF
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Electrical parameters
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NRSTIN NRSTOUT pins
NRSTIN Input Driver TTL/LVTTL I/Os. permanent pull-up present which same (see General characteristics page NRSTOUT Output Driver equivalent type driver except that works only open-drain (the P-MOS de-activated). permanent pull-up present which same (see General characteristics page Subject general operating conditions VDD_IO unless otherwise specified.
Table NRSTIN NRSTOUT pins
Symbol VIL(NRSTIN) VIH(NRSTIN) Vhys(NRSTIN) VOL(NRSTIN) RPU(NRSTIN) Parameter NRSTIN Input level voltage(1) NRSTIN Input high level voltage(1) NRSTIN Schmitt trigger voltage hysteresis(2) NRSTOUT Output level voltage(3) NRSTIN Weak pull-up equivalent resistor(4) Generated reset pulse duration (visible NRSTOUT pin)(5) External reset pulse hold time NRSTIN pin(6) IIO=+2 VIN=VSS VDD_IO=3.3 VDD_IO=5 Conditions Unit
tw(RSTL)out
Internal reset source VDD_IO power-up(5) When VDD_IO established(5) time between spikes must higher than spike duration.
th(RSTL)in
tg(RSTL)in
maximum negative spike duration filtered NRSTIN pin(7)
Data based product characterisation, tested production. Hysteresis voltage between Schmitt trigger switching levels. current sunk must always respect absolute maximum rating specified Section 6.2.2 (I/O ports control pins) must exceed IVSS. pull-up equivalent resistor based resistive transistor guarantee reset device, minimum pulse applied internal reset. VDD_IO power-up, built-in reset stretcher generate pulse duration while once VDD_IO established, external reset pulse will internally stretched thanks reset pulse stretcher. reset network (the resistor capacitors) protects device against parasitic resets, especially noisy environments. fact filter made ignore incoming pulses with short duration: negative spikes with duration less than filtered trains negative spikes with ratio filtered. This means that spikes with maximum duration with minimum interval between spikes filtered. Data guaranteed design, tested production.
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure Recommended NRSTIN protection
VDD_IO
Electrical parameters
NRSTOUT RESET OTHER CHIPS
Filter
INTERNAL RESET WATCHDOG RESET SOFTWARE RESET RESET
PULSE GENERATOR
VDD_IO
STR7X
EXTERNAL RESET CIRCUIT 0.01F NRSTIN
Filter
user must ensure that level NRSTIN below VIL(NRSTIN) max. level specified NRSTIN NRSTOUT pins page Otherwise reset will taken into account internally.
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Electrical parameters
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6.3.9
timer characteristics
Subject general operating conditions VDD_IO, fCK_SYS, unless otherwise specified. Refer Section 6.3.8: port characteristics page more details input/output alternate function characteristics (output compare, input capture, external clock, output.).
Table timers
Symbol tw(ICAP)in Parameter Input capture TIM0,1,2 pulse time fCK_TIM(MAX) fCK_SYS tres(TIM) Timer resolution time(1) fCK_TIM fCK_SYS fCK_TIM(MAX) fCK_SYS TIM0,1,2 CK_TIM fCK_SYS 60MHz Timer fCK_TIM(MAX) fCK_SYS external clock TIM0,1,2 CK_TIM fCK_SYS frequency Timer resolution fCK_TIM fCK_SYS 0.0166 fCK_TIM fCK_SYS 0.0166 Conditions 16.6(1) 16.6(1) fCK_TIM/4 65536 1092 65536 1092 Unit tCK_TIM tCK_TIM tCK_TIM tCK_TIM tCK_TIM
fEXT
ResTIM
16-bit Counter clock period when tCOUNTER internal clock selected (16-bit TIM0,1,2 Prescaler)
65536x65536 tCK_TIM Maximum tMAX_COUNT Possible Count fCK_TIM fCK_SYS 71.58
65536x65536 tCK_TIM TIM0,1,2 CK_TIM fCK_SYS 71.58
Take into account frequency limitation speed capability when outputting pin, described Output speed page
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Electrical parameters
Table Timer (PWM)
Symbol Parameter Conditions fCK_TIM(MAX) fCK_SYS tres(PWM) ResPWM VOS(1) resolution time fCK_TIM fCK_SYS 16.6(1) VDD_IO=3.3 Res=16-bits VDD_IO=5.0 Res=16-bits fCK_TIM=60 0.0166 50(1)
Unit tCK_TIM
resolution PWM/DAC output step voltage Timer clock period when internal clock selected
65536 1087
tCK_TIM
tCOUNTER
Maximum Possible tMAX_COUNT Count
65536x 65536 CK_TIM fCK_TIM fCK_SYS 71.58
Take into account frequency limitation speed capability when outputting pin, described Output speed page
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Electrical parameters
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6.3.10
Communication interface characteristics
synchronous serial peripheral master mode (SPI mode)
General operating conditions: V33, 3.0V 3.3V, =1.8V, Table
Symbol fSCK
master mode characteristics(1)
Parameter clock frequency(2) Conditions SSP0 SSP1 SSP0 clock rise time SSP1 SSP0 clock fall time SSP1 SSP0 high time SSP1 Data Output MOSI valid time CPHA SSP1 SSP0 SSP1 SSP0 0.5tSCK+15ns 0.5tSCK+30ns 0.5tSCK+15ns 0.5tSCK+30ns tSCK+15ns tSCK+30ns Unit
tr(SCK)
tf(SCK) tw(SCKH) tw(SCKL) tNSSLQV
tSCKNSSH
last edge high SSP0 CPHA SSP1 trigger edge data output MOSI valid time trigger edge data output MOSI invalid time Data input (MISO) setup time w.r.t sampling edge Data input (MISO) hold time w.r.t sampling edge SSP0 SSP1 SSP0 SSP1 SSP0 SSP1 SSP0 SSP1
tSCKQV
tSCKQX
Data based characterisation results, tested production. frequency SSPs fPCLK/2; fPCLK MHz. This takes into account frequency limitation speed capability. SSP0 uses type while SSP1 uses type I/Os.
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure configuration master mode, single transfer
OUTPUT tc(SCK)
Electrical parameters
tSCKNSSH (CPHA=0) CPHA=0 CPOL=0
OUTPUT
sample edge
trigger edge
sample edge
trigger edge
CPHA=0 CPOL=1 CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tsu(MISO) th(MISO) tr(SCK) tf(SCK) trigger edge sample edge trigger edge tSCKNSSH (CPHA=1) sample edge
MISO INPUT
DONT CARE
tNSSLQV tSCKQV
DONT CARE
tSCKQX
tSCKQX
MOSI OUTPUT
Figure configuration master mode, continuous transfer, CPHA=0
tc(SCK) OUTPUT
sample trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample
1.5*tc(SCK)
OUTPUT
CPOL=0 CPOL=1 tNSSLQV DONT CARE DONT CARE tNSSLQV
MOSI OUTPUT MISO INPUT
FRAME
FRAME
Figure configuration master mode, continuous transfer, CPHA=1
tc(SCK) OUTPUT
trigger sample trigger sample trigger sample trigger samlpe trigger sample trigger sample trigger sample trigger sample trigger
OUTPUT
CPOL=0 CPOL=1
MOSI OUTPUT
FRAME
FRAME
MISO INPUT DONT CARE
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure configuration master mode, single transfer
OUTPUT
tc(SCK) trigger edge sample edge trigger edge sample edge trigger edge sample edge
OUTPUT
tw(SCKH)
tw(SCKL) tr(SCK) th(MISO) DONT CARE
tf(SCK) tsu(MISO) MISO
INPUT
DONT CARE tSCKQV
tSCKQX
MOSI
OUTPUT
Figure configuration master mode, continuous transfer
tc(SCK) OUTPUT
trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample
tc(SCK)
OUTPUT MOSI OUTPUT FRAME DONT CARE
MISO INPUT DONT CARE
FRAME
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Electrical parameters
synchronous serial peripheral slave mode (SPI mode)
Subject general operating conditions with Table
Symbol fSCK
slave mode characteristics(1)
Parameter clock frequency SSP1 input setup time w.r.t first edge input hold time w.r.t last edge Data Output MISO valid time Data Output MISO invalid time trigger edge data output MISO valid time trigger edge data output MISO invalid time MOSI setup time w.r.t sampling edge MOSI hold time w.r.t sampling edge SSP0 SSP1 SSP0 SSP1 SSP0 SSP1 SSP0 SSP1 SSP0 SSP1 SSP0 SSP1 SSP0 SSP1 SSP0 SSP1 2tPCLK 2tPCLK 3tPCLK+15 3tPCLK+15 tPCLK+15ns tPCLK+15ns 2tPCLK 2tPCLK 2tPCLK 2tPCLK 3tPCLK+30 3tPCLK+30 3tPCLK+15 3tPCLK+15 Conditions SSP0 2.66 (fPLCK/12) Unit
tsu(NSS)
th(NSS)
tNSSLQV
tNSSLQZ
tSCKQV
tSCKQX
tsu(MOSI)
th(MOSI)
Data based characterisation results, tested production.
Figure configuration, slave mode with CPHA=0, single transfer
INPUT tsu(NSS) INPUT CPHA=0 CPOL=0 CPHA=0 CPOL=1 tw(SCKH) tw(SCKL) tSCKQV(MISO)
th(NSS)
trigger edge sample edge trigger edge
sample edge
tc(SCK) tr(SCK) tf(SCK) tSCKQX(MISO)
tNSSHQZ
tNSSLQV MISO OUTPUT tsu(SI) MOSI INPUT
DONT CARE
th(SI)
BIT1 DONT CARE
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure configuration slave mode with CPHA=0, continuous transfer
1.5*tc(SCK) INPUT
sample trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample
tc(SCK)
1.5*tc(SCK)
INPUT
CPOL=0 CPOL=1
tNSHQZ tNSSLQV
tNSSLQV
MISO OUTPUT DONT CARE
MOSI INPUT
FRAME
DONT CARE
FRAME
Figure configuration, slave mode with CPHA=1, single transfer
INPUT tsu(NSS) INPUT CPHA=1 CPOL=0 CPHA=1 CPOL=1 tw(SCKH) tw(SCKL) tNSSLQV tSCKQV(MISO) tSCKQX(MISO)
th(NSS)
sample edge trigger edge sample edge
trigger edge
tc(SCK) tr(SCK) tf(SCK) tNSSHQX tNSSHQZ
MISO OUTPUT
tsu(SI) MOSI INPUT
DONT CARE
th(SI)
BIT1 DONT CARE
Figure configuration slave mode with CPHA=1, continuous transfer
tc(SCK) OUTPUT
trigger sample trigger sample trigger sample trigger samlpe trigger sample trigger sample trigger sample trigger sample trigger
OUTPUT
CPOL=0 CPOL=1
MOSI OUTPUT
FRAME
FRAME
MISO INPUT DONT CARE
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure configuration slave mode, single transfer
INPUT
Electrical parameters
tsu(NSS) tc(SCK)/2 trigger edge tc(SCK) sample edge trigger edge sample edge trigger edge sample edge tc(SCK)/2
INPUT
tw(SCKH)
tw(SCKL) tr(SCK) th(MOSI) DONT CARE
tf(SCK) tsu(MOSI) MOSI
INPUT
DONT CARE tSCKQV
tSCKQZ
tSCKQX
MISO
OUTPUT
Figure configuration slave mode, continuous transfer
tsu(NSS) OUTPUT
trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample trigger sample
tc(SCK)
th(NSS)
tc(SCK)
OUTPUT
MOSI INPUT DONT CARE MISO OUTPUT
FRAME
FRAME
DONT CARE
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
serial memory interface
Subject general operating conditions with Table
Symbol fSMI_CK tr(SMI_CK) tf(SMI_CK) clock frequency clock rise time clock fall time
characteristics(1)
Parameter 32(2)(3) 48(4) Unit
tv(SMI_DOUT) Data output valid time th(SMI_DOUT) Data output hold time tv(SMI_CSSx) output valid time th(SMI_CSSx) output hold time tsu(SMI_DIN) th(SMI_DIN) Data input setup time Data input hold time
Data based characterisation results, tested production. Max. frequency fPCLK/2 64/2 MHz. Valid temperature ranges: with load capacitance. Valid with load capacitance.
Figure timing diagram
tc(SMI_CK) SMI_CK OUTPUT tw(SMI_CKH) tw(SMI_CKL) tsu(SMI_DIN) SMI_DIN INPUT tv(SMI_DOUT) th(SMI_DIN) tr(SMI_CK) tf(SMI_CK)
BIT6
th(SMI_DOUT)
SMI_DOUT OUTPUT tv(SMI_CSS) SMI_CSSX OUTPUT
BIT6
th(SMI_CSS)
Inter control interface
Subject general operating conditions VDD_IO, fPCLK, unless otherwise specified. interface meets requirements Standard communication protocol described following table with restriction mentioned below: Restriction: pins which mapped "True" OpenDrain: when configured open-drain, PMOS connected between VDD_IO disabled, still present. Also, there protection diode between VDD_IO. Consequently, when using this multi-master network,
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Electrical parameters
possible power STR7x while some another master node remains powered otherwise, STR7x will powered protection diode. Refer port characteristics more details input/output alternate function characteristics (SDA SCL). Table
Symbol
characteristics
Parameter Standard mode Min(2)
Fast mode I2C(1) Unit
tw(SCLL) tw(SCLH) tsu(SDA) th(SDA) tr(SDA) tr(SCL) tf(SDA) tf(SCL) th(STA) tsu(STA) tsu(STO)
clock time clock high time setup time data hold time rise time fall time START condition hold time Repeated START condition setup time STOP condition setup time
0(3) 1000
speed (400 kHz).
0(4) 20+0.1Cb 20+0.1Cb 900(3)
tw(STO:STA) STOP START condition time (bus free) Capacitive load each line
fPCLK, must least achieve fast maximum hold time th(SDA) applicable
Data based standard protocol requirement, tested production. device must internally provide hold time least signal order bridge undefined region falling edge SCL.
Figure Typical application with timing diagram
4.7k 4.7k
STRT75X
REPEATED START START
tsu(STA)
tw(STO:STA)
START
tf(SDA)
tr(SDA)
tsu(SDA)
th(SDA)
STOP
th(STA)
tw(SCKH)
tw(SCKL)
tr(SCK)
tf(SCK)
tsu(STO)
Measurement points done CMOS levels: 0.3xVDD 0.7xVDD.
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
6.3.11
characteristics
interface USB-IF certified (Full Speed). Table
Symbol tSTARTUP
startup time
Parameter transceiver startup time Conditions Unit
Table
characteristics
Electrical Characteristics
Symbol
Parameter
Conditions Input Levels
Min.(1)(2) Max.(1)(2) Unit
Differential Input Sensitivity Differential Common Mode Range Single Ended Receiver Threshold
I(DP, Includes range
Output Levels Static Output Level Static Output Level High 3.6V(3) VSS(3)
voltages measured from local ground potential. important aware that DP/DM pins tolerant. consequence, case shortcut with Vbus (typ: 5.0V), protection diodes DP/DM pins will direct biased This will damage device more than sunk longer than hours reliability affected. load connected drivers
Figure USB: data signal rise fall time
Differential Data Lines
VCRS
Crossover points
Table Symbol
USB: Full speed electrical characteristics Parameter Conditions Driver characteristics: Unit
Rise time(1) Fall Time1)
CL=50 CL=50
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Table Symbol trfm VCRS USB: Full speed electrical characteristics Parameter Rise/ Fall Time matching Output signal Crossover Voltage Conditions tr/tf
Electrical parameters
Unit
Measured from data signal. more detailed informations, please refer Specification Chapter (version 2.0).
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
6.3.12
10-bit characteristics
Subject general operating conditions VDDA_ADC, fPCLK, unless otherwise specified. Table
Symbol fADC VAIN RAIN CAIN
10-bit characteristics
Parameter clock frequency Conversion voltage range(2) External input impedance(3)(4) External capacitor analog input(3)(4) +400 injected -400 injected except specific adjacent pins Table -400µA injected specific adjacent pins Table Conditions VSSA_ADC Typ(1) VDDA_ADC Unit
Ilkg
Induced input leakage current
CADC tCAL
Internal sample hold capacitor Calibration Time fCK_ADC=8
725.25 5802
1/fADC 1/fADC
tCONV
Total Conversion time (including sampling time)
fCK_ADC=8
3.75 sampling Successive Approximation)
IADC
Sunk VDDA_ADC
Unless otherwise specified, typical data based TA=25°C. They given only design guidelines tested. Calibration needed once after each power-up. CPARASITIC represents capacitance (dependent soldering layout quality) plus capacitance pF). high CPARASITIC value will downgrade conversion accuracy. remedy this, fADC should reduced. Depending input signal variation (fAIN), CAIN increased stabilization time reduced allow larger serial resistor (RAIN). valid fADC frequencies MHz.
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Electrical parameters
accuracy negative injection current
Injecting negative current specific pins listed Table (generally adjacent analog input being converted) should avoided this significantly reduces accuracy conversion being performed. recommended Schottky diode (pin ground) pins which potentially inject negative current. Table List adjacent pins
Related adjacent pins None None P0.11 P0.18 P0.16 P0.24 None P2.04 P1.11 P0.26 P0.30 P0.28 None P1.05 P1.04 P1.13 P2.17 P0.27 None P1.14 P1.01 None
Analog input AIN1/P0.03 AIN2/P0.12 AIN3/P0.17 AIN4/P0.19 AIN5/P0.22 AIN6/P0.23 AIN7/P0.27 AIN8/P0.29 AIN9/P1.04 AIN10/P1.06 AIN11/P1.08 AIN12/P1.11 AIN13/P1.12 AIN14/P1.13 AIN15/P1.14
Figure Typical application with
0.6V RAIN VAIN CAIN 0.6V AINx
STR75XX
2k(max)
10-Bit Conversion CADC 3.2pF
Analog power supply reference pins
VDDA_ADC VSSA_ADC pins analog power supply converter cell. Separation digital analog power pins allow board designers improve performance. Conversion accuracy impacted voltage drops noise event heavily loaded badly decoupled power supply lines (see General design guidelines page 74).
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Electrical parameters
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
General design guidelines
obtain best results, some general design layout rules should followed when designing application shield noise-sensitive, analog physical interface from noise-generating CMOS logic signals.
separate digital analog planes. analog ground plane should connected digital ground plane single point PCB. Filter power analog power planes. recommended connect capacitors, with good high frequency characteristics, between power ground lines, placing optionally, needed capacitors close possible STR7 power supply pins capacitor close power source (see Figure 43). analog digital power supplies should connected star network. resistor, VDDA_ADC used reference voltage converter resistance would cause voltage drop loss accuracy. Properly place components route signal traces shield analog inputs. Analog signals paths should over analog ground plane short possible. Isolate analog signals from digital signals that switch while analog inputs being sampled converter. toggle digital outputs near input being converted.
Software filtering spurious conversion results
performance reasons, recommended filter conversion outliers using software filtering techniques. Figure Power supply filtering
STR75XX
STR7 DIGITAL NOISE FILTERING
0.1F
VDD_IO
POWER SUPPLY SOURCE (3.3V 5.0V) EXTERNAL NOISE FILTERING
0.1F
VDDA_ADC
VSSA_ADC
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Table accuracy
Electrical parameters
accuracy with fCK_SYS MHz, fADC=8 MHz, RAIN This assumes that calibrated(1) Symbol |ET| Parameter Total unadjusted error Conditions VDDA_ADC=3.3 VDDA_ADC=5.0 Offset error(2) VDDA_ADC=3.3 VDDA_ADC=5.0 Gain Error VDDA_ADC=3.3 VDDA_ADC=5.0 Differential linearity error(2) VDDA_ADC=3.3 VDDA_ADC=5.0 Integral linearity error VDDA_ADC=3.3 VDDA_ADC=5.0 0.15 0.15 -0.8 -0.8 -0.2 -0.2 Unit
|EO|
|ED|
|EL|
Calibration needed once after each power-up. Refer accuracy negative injection current page Accuracy (Main Clock Output): accuracy significantly degraded when activating P0.01 while converting analog channel (especially those which close pin). avoid this, when conversion launched, strongly recommended disable MCO.
Figure accuracy characteristics
Digital Result ADCDR
1023 1022 1021 1LSB IDEAL Example actual transfer curve ideal transfer curve point correlation line
1024
VSSA LSBIDEAL
ET=Total Unadjusted Error: maximum deviation between actual ideal transfer curves. EO=Offset Error: deviation between first actual transition first ideal one. EG=Gain Error: deviation between last ideal transition last actual one. ED=Differential Linearity Error: maximum deviation between actual steps ideal one. EL=Integral Linearity Error: maximum deviation between actual transition point correlation line.
1021 1022 1023 1024 VDDA
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Package characteristics
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Package characteristics
order meet environmental requirements, offers these devices different grades ECOPACK® packages, depending their level environmental compliance. ECOPACK® specifications, grade definitions product status available www.st.com. ECOPACK® trademark.
Package mechanical data
0.10mm .004 seating plane
Figure 64-pin profile quad flat package (10x10)
Dim. E3E1 IDENTIFICATION 0.45 0.05 1.35 0.17 0.09 12.00 10.00 12.00 10.00 0.50 3.5° 0.60 1.00 Values inches converted from rounded decimal digits. 1.40 0.22 1.60 0.15 0.0020 inches(1) 0.0630 0.0059
1.45 0.0531 0.0551 0.0571 0.27 0.0067 0.0087 0.0106 0.20 0.0035 0.4724 0.3937 0.4724 0.3937 0.0197 3.5° 0.0394 Number pins 0.75 0.0177 0.0236 0.0295 0.0079
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STR750Fxx STR751Fxx STR752Fxx STR755Fxx Figure 100-pin profile flat package (14x14)
Dim.
Package characteristics
inches(1) 0.0630 0.0059 0.0571 0.0106 0.0079
1.60 0.05 0.15 0.0020 1.35 1.40 1.45 0.0531 0.0551 0.17 0.22 0.27 0.0067 0.0087 0.09 0.20 0.0035 16.00 0.6299 14.00 0.5512 16.00 0.6299 14.00 0.5512 0.50 0.0197 3.5° 3.5° 0.45 0.60 0.75 0.0177 0.0236 1.00 0.0394 Number Pins
0.0295
Values inches converted from
rounded decimal digits.
Figure 64-ball profile fine pitch ball grid array package
Dim.
decimal digits.
inches(1) 0.0669 0.0441 0.0197 0.3150 0.2205 0.3150 0.2205 0.0315 0.0472
1.210 0.270 1.120 0.450 0.500 7.750 8.000 5.600 7.750 8.000 5.600 0.720 0.800 1.050 1.200
1.700 0.0476 0.0106 0.550 0.0177 8.150 0.3051 8.150 0.3051
0.0217 0.3209 0.3209 0.0346 0.0531 0.0047
0.880 0.0283 1.350 0.0413 0.120 Number Pins
Values inches converted from rounded
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Package characteristics
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Figure 100-ball profile fine pitch ball grid array package
Dim.
digits.
inches(1) 1.700 0.0106 0.0669 0.0427 0.0118 0.0315 0.0177 0.0197 0.0217 0.3878 0.3937 0.3996 0.2835 10.15 0.3878 0.3937 0.3996 0.2835 0.0315 0.055 0.12 0.005 0.15 0.006 0.08 0.003 Number Balls 0.80 0.55 10.15
0.270 1.085 0.30 0.45 9.85 9.85 0.50 10.00 7.20 10.00 7.20 0.80 1.40
Values inches converted from rounded decimal
Figure Recommended design rules (0.80/0.75mm pitch BGA)
0.37 0.52 typ. (depends solder mask registration tolerance Solder paste 0.37 aperture diameter solder mask defined pads recommended mils screen print
Dpad
Dpad
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Package characteristics
Thermal characteristics
maximum chip junction temperature (TJmax) must never exceed values given Table General operating conditions page maximum chip-junction temperature, TJmax, degrees Celsius, calculated using following equation: TJmax TAmax (PDmax Where: TAmax maximum Ambient Temperature Package Junction-to-Ambient Thermal Resistance, C/W, PDmax PINTmax PI/Omax (PDmax PINTmax PI/Omax), PINTmax product VDD, expressed Watts. This maximum chip internal power. PI/Omax represents maximum Power Dissipation Output Pins. Where: PI/Omax (VOL*IOL) ((VDD-VOH)*IOH), taking into account actual I/Os high level application. Thermal characteristics(1)
Parameter Thermal Resistance Junction-Ambient LQFP pitch Thermal Resistance Junction-Ambient LQFP pitch Thermal Resistance Junction-Ambient LFBGA 1.7mm Thermal Resistance Junction-Ambient LFBGA 1.7mm Value Unit °C/W °C/W °C/W °C/W
Table
Symbol
Thermal resistances based JEDEC JESD51-2 with 4-layer natural convection environment.
7.2.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions Natural Convection (Still Air). Available from www.jedec.org
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Package characteristics
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7.2.2
Selecting product temperature range
When ordering microcontroller, temperature range specified order code Table Order codes page following example shows calculate temperature range needed given application. Assuming following application conditions: Maximum ambient temperature TAmax= (measured according JESD51-2), IDDmax=8 maximum I/Os used same time output level with VOL= PINTmax PIOmax 0.4V This gives: PINTmax= PIOmax PDmax Thus: PDmax Using values obtained Table TJmax calculated follows: LQFP100, 46°C/W TJmax (46° 82°C 21°C 103° This within range suffix version parts (-40 105° this case, parts must ordered least with temperature range suffix (see Table Order codes page 81). BGA64, 58°C/W TJmax (58° 82°C 27°C 109° This within range suffix version parts (-40 125° this case, parts must ordered least with temperature range suffix (see Table Order codes page 81). Figure LQFP100 PDmax
Suffix Suffix
(mW)
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Order codes
Order codes
Table Order codes
Flash Prog. Memory Order code (Bank Kbytes STR750FV0T6 STR750FV1T6 STR750FV2T6 STR750FV0H6 STR750FV1H6 STR750FV2H6 STR751FR0T6 STR751FR1T6 STR751FR2T6 STR751FR0H6 STR751FR1H6 STR751FR2H6 STR752FR0T6 STR752FR1T6 STR752FR2T6 STR752FR0H6 STR752FR1H6 STR752FR2H6 STR752FR0T7 STR752FR1T7 STR752FR2T7 STR752FR0H7 STR752FR1H7 STR752FR2H7 STR755FR0T6 STR755FR1T6 STR755FR2T6 STR755FR0H6 STR755FR1H6 STR755FR2H6 LFBGA64 +85°C LQFP64 10x10 LFBGA64 +105°C LQFP64 10x10 LFBGA64 +85°C LQFP64 10x10 LFBGA64 +85°C LQFP64 10x10 LFBGA100 10x10 +85°C LQFP100 14x14 Package Periph Periph Nominal Temp. Range (TA)
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Order codes Table Order codes (continued)
Flash Prog. Memory Order code (Bank Kbytes STR755FV0T6 STR755FV1T6 STR755FV2T6 STR755FV0H6 STR755FV1H6 STR755FV2H6
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Package
Periph
Periph
Nominal Temp. Range (TA)
LQFP100 14x14 +85°C
LFBGA100 10x10
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Revision history
Revision history
Table
Date 25-Sep-2006 30-Oct-2006
Document revision history
Revision Initial release Added power consumption data operation Section Changed datasheet title from STR750F STR750FXX STR751Fxx STR752Fxx STR755xx. Added Table Device summary page Added note Table Added STOP mode max. values Table Updated driving current Table Updated Table Updated Table XRTC1 external clock source page Updated Table Output speed page Added characteristics synchronous serial peripheral master mode (SPI mode) page synchronous serial peripheral slave mode (SPI mode) page Added characteristics serial memory interface page Added Table startup time page Updated Section 6.2.3: Thermal characteristics page Updated Section 6.3: Operating conditions page Updated Table external clock source page Updated Table XRTC1 external clock source page Updated Section Package characteristics page (inches rounded decimal digits instead Updated Ordering information Section Order codes page Modified note below Table Current characteristics page Added clock frequency write access Flash registers Table General operating conditions page Modified note below Table characteristics page Description Changes
04-Jul-2007
23-Oct-2007
17-Feb-2009
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