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STAC9460/62
Six-Channel, 24-Bit, Audio Codec
PRELIMINARY INFORMATION 8/24/01
2-9460-D1-1-0-0801
Copyright 2001 SigmaTel, Inc. rights reserved. contents this document protected copyright reproduced without express written consent SigmaTel, Inc. registered trademark Philips Semiconductor requires license interface. SigmaTel, SigmaTel logo, combinations thereof trademarks SigmaTel, Inc. Other product names used this publication identification purposes only trademarks registered trademarks their respective companies. contents this document provided connection with SigmaTel, Inc. products. SigmaTel, Inc. made best efforts ensure that information contained herein accurate reliable. However, SigmaTel, Inc. makes warranties, express implied, accuracy completeness contents this publication providing this publication IS". SigmaTel, Inc. reserves right make changes specifications product descriptions time without notice, discontinue make changes products time without notice. SigmaTel, Inc. does assume liability arising application product circuit, specifically disclaims liability, including without limitation special, consequential, incidential damages.
STAC9460/62
Six-Channel, 24-Bit, Audio Codec TABLE CONTENTS
TABLE CONTENTS
1.1. List Figures 1.2. List Tables
PRODUCT BRIEF
2.1. FEATURES 2.2. Ordering Information 2.3. Block Diagram 2.4. Related Materials 2.5. Additional Support
CHARACTERISTICS SPECIFICATIONS
3.1. Absolute Maximum Ratings 3.2. Recommended Operating Conditions 3.3. Power Consumption 3.4. Static Digital Specifications 3.5. STAC9460 Analog Performance Characteristics
TYPICAL CONNECTION DIAGRAM SERIAL INTERFACE
5.1. Clocking 5.2. Reset
DIGITAL AUDIO INTERFACE
6.1. Serial Interface 6.2. Single Line Format 6.3. I2C-Bus Interface
PROGRAMMABILITY
7.1. List Registers 7.1.1. Reset/Status Register (00h) 7.1.2. Status Register (01h) 7.1.3. Master Volume Register (02h) 7.1.4. LF/RF, LR/RR, Center/LFE Output Channel Volume Registers(03h-08h) 7.1.5. Microphone Input Volume Registers (09h-0Ah) 7.1.6. De-Emphasis Register (0Ch) 7.1.7. General Purpose Register (0Dh) 7.1.8. Audio Port Control (0Eh) 7.1.9. Master Clocking Register (0Fh) 7.1.10. Powerdown Control Registers (10h-11h) 7.1.11. Revision Code Register (12h) 7.1.12. Address Control Register/Address Register (13h-14h)
DESCRIPTION
8.1. STAC9460 Signal Description 8.2. STAC9462 Signal Description 8.3. Digital 8.4. Analog 8.5. Filter/References 8.6. Power Ground Signals
PACKAGE DRAWING
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec 1.1. List Figures
Figure STAC9460 Block Diagram Figure Typical Connection Diagram Figure Serial interface microcontroller microprocessor Figure Format Figure Left Justified Format Figure Right Justified Format Figure Single Line Data Mode Timing Diagram Figure Timing Diagram Figure STAC9460 Designation Figure STAC9462 Designation Figure Package Outline
1.2.
List Tables
Table Digital Audio Interface Configuration Table Single Line Data Mode, Data Valid Rising Edge SCLK Table Mode Specifications Table Programming Registers Table Reset/Status Register Table Master Volume Register Table Digital Volume Registers Table Left Right Input Volume Registers Table On/Off De-emphasis Selection Each Channel Table De-emphasis Filter Selection Table Microphone/Differential Input Selection Table High Pass Filter Disable Table Microphone DifferentialMux By-Pass Control Table Audio Data Format Selection Table Sample Rate Mode Table MCLK Mode Table Powerdown Control Table Digital Signal List Table Analog Signal List Table Filtering Voltage References Table Power Signal List
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec PRODUCT BRIEF
SigmaTel's STAC9460/62 two-channel general-purpose 24-bit, full duplex, audio codecs consumer applications. STAC9460/62 incorporate SigmaTel's proprietary Sigma-Delta technology achieve SNRs excess DACs, ADCs integrated with analog I/Os, which include differential analog inputs. There three audio inputs digital output. STAC9460/62 communicates standard two-wire serial interface providing simplicity audio system design. Packaged 28pin SSOP, STAC9460 STAC9462 require minimal space implementation. STAC9460 provides variable sample rate conversion, well analog processing. Supported audio sample rates include kHz, 44.1 kHz, kHz, 88.2 kHz, kHz, 176.4 kHz. Supported audio sample rates inclued kHz, 44.1 kHz, kHz, 88.2 kHz,and kHz. digital data interface communicates standard I2C® compatible serial control interface digital audio interface. stereo sample rate ADC's provide record capability from microphone inputs differential inputs. DAC's operate 24-bit resolution with sample rate based MCLK programmable registers. ADCs operate 24-bit resolution supply full 24-bit filter data. STAC9460 supports three digital audio inputs digital audio output. These digital options provide number advanced architectural implementations, with volume controls mute capabilities built directly into codec each individual channel. output volume ranges from with steps. input, input volume ranges from 22.5 with steps. STAC9460 also supports single-line format. STAC9460 designed primarily support 6-channel audio. True AC-3 playback achieved 6-speaker applications taking advantage STAC9460 architecture combining with appropriate processing. This product ideal home theatre, DVD, karaoke, set-top-box applications.
2.1.
FEATURES
High performance technology channels with independent volume controls 24-bit full duplex stereo DACs 24-bit full duplex stereo 44.1, 88.2, 176.4 sample rates 44.1, 88.2 sample rates Standard compatible serial interfaces Digital de-emphasis capability >100 Differential Stereo Analog Input Dual inputs with independent volume controls 28-pin SSOP package Energy saving dynamic power modes Analog with 3.3V Digital capability
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec 2.2. Ordering Information
PART NUMBER CHANNELS PACKAGE TEMPERATURE RANGE SUPPLY RANGE AVdd DVdd 3.3V STAC9460S DAC; 28-pin SSOP STAC9462S DAC; 28-pin SSOP AVdd DVdd 3.3V STEECBAC9460B (Evaluation Board): please send email request apps@sigmatel.com Note: SigmaTel reserves right change specifications without notice.
2.3.
Block Diagram
SCLK SDATA RESET
I2C® Port
VOLUME VOLUME DIFF_L DIFF_GND DIFF_R VOLUME SDI1 SDI2 SDI3 D_SCLK D_LRCLK SDATA_OUT DAC_RR VOLUME DAC_RF
MIC_L MIC_R
VOLUME
DAC_LF
VOLUME
DAC_LR
Port
VOLUME
DAC_CTR
VOLUME
DAC_BASS
MCLK
DVdd
DVss
VREF
AVdd AVss
Figure STAC9460 Block Diagram
2.4.
Related Materials
Product Brief Evaluation Boards Reference Designs
2.5.
Additional Support
Additional product company information obtained going SigmaTel website www.sigmatel.com
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec CHARACTERISTICS SPECIFICATIONS 3.1. Absolute Maximum Ratings
Voltage relative Ground Operating Temperature Storage Temperature Soldering Temperature Output Current +125 SECONDS
3.2.
Recommended Operating Conditions
PARAMETER Digital Digital Analog 3.135 4.75 4.75 3.435 5.25 5.25 UNITS
Power Supplies
Ambient Temperature
3.3.
Power Consumption
PARAMETER Digital Digital Analog UNITS
Digital Supply Current Analog Supply Current
3.4.
Static Digital Specifications
(Tambient DVdd AVss=DVss=0 50pF external load)
PARAMETER SYMBOL -0.30 0.65xDVdd 0.90xDVdd DVdd 0.30 0.30xDVdd 0.2xDVdd UNITS
Input Voltage Range level input range High level input voltage High level output voltage level output voltage Input Leakage Current (Digital inputs) Output Leakage Current (Digital outputs) Output buffer drive current
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STAC9460/62
Six-Channel, 24-Bit, Audio Codec 3.5. STAC9460 Analog Performance Characteristics
(Tambient AVdd 5.0V DVdd 5.0V AVss=DVss=0V; input sine wave; Sample Frequency kHz; Vrms, K/50 load, Testbench Characterization kHz, settings gain stages)
PARAMETER Full Scale Input Voltage: Differential Inputs Inputs Full Scale Output Voltage: Line Output Analog Frequency Response (Note Digital (Note Total Harmonic Distortion: Line Output (Note Frequency Response (Note Frequency Response (Note Transition Band(Note Stop Band(Note Deviation from Linear Phase (Note Stop Band Rejection Out-of-Band Rejection (Note Group Delay Power Supply Rejection Ratio (1kHz) Crosstalk between Input channels Spurious Tone Rejection Gain Step Size Input Impedance Differential Input Impedance Input Capacitance VREFout Interchannel Gain Mismatch Interchannel Gain Mismatch Gain Drift Offset Voltage External Load Impedance Mute Attenuation (Vrms input) 19,200 28,800 -100 0.45 AVdd 20,000 20,000 20,000 28,800 UNITS Vrms Vrms Vrms degree
Note:
limits. sample rate greater than equal frequency response becomes kHz. ratio output level with full scale input output level with zeros into digital input. Measured weighted" over bandwidth. (AES17-1991 Idle Channel Noise EIAJ CP-307 Signal-to-noise Ratio). gain, Sample Frequency 0.25 limits. freq. response becomes with sampling rates kHz. ±3dB response range from 20-22,500Hz 48kHz, 20-20,000Hz 44.1kHz 20-45,000Hz 96kHz. Transition band 40-60% sample rate. Stop band begins sample rate. Digital De-Emphasis OFF. integrated Out-of-Band noise generated process, during normal audio playback, over bandwidth 28.8 kHz, with respect Vrms output.
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec TYPICAL CONNECTION DIAGRAM
Ferrite Bead Suggested
0.1uF
DVdd
0.1uF
10uF AVdd MCLK
RESET DIFF_L SCLK SDATA SDI1 SDI2 SDI3 SDATA_OUT D-SCLK D_LRCLK DAC_RF DAC_LR DIFF_GND DIFF_R MIC_L MIC_R
STAC9460
Vref
0.1uF 10uF
DAC_LF
10uF
DAC_RR DAC_CTR DAC_LFE DVss AVss
0.1uF
Terminate ground plane close power supply possible
Digital
Analog
Figure Typical Connection Diagram
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec SERIAL INTERFACE
Below figure serial interface between STAC9460/62 register settings chip control performed this serial interface, except address LSB.
Note: This functions standard 2-wire compatible interface, however, (chip select) line offers address flexibility must either hard wired ground tied other chips connected bus. Refer Table 7.1.1 page additional information.
9460
Figure Serial interface microcontroller microprocessor
5.1.
Clocking
STAC9460/62 derives clock from externally connected clock through MCLK combination with Master CLocking Register, which further explained section 7.1.9.
5.2.
Reset
There types resets detailed below: hard reset achieved driving reset line soft reset achieved writing Reset/Status register (00h)
writing Reset/Status Register (00h) reset Address Control Register will occur. Writing value this register performs register reset, which causes registers revert their default values. This soft reset will also place state machine "stop" condition, will continue auto-increment through address space. Additional information about Address Control Register found section 7.1.12.
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec DIGITAL AUDIO INTERFACE 6.1. Serial Interface
STAC9460/62 communicates digital audio information through digital serial interface. interface configured with standard format, left justified, right justified line format. Input signals SDI1, SDI2, SDI3 interface Left Right Front Channels, Left Right Rear Channels Center Channels respectively. SDATA_OUT line outputs data from ADCs.
LINE SDI1 SDI2 SDI3 Alternate SDI1 SDATA_OUT ANALOG CHANNEL Left Right Front Left Right Rear Center Channels Diff FUNCTION data interface DAC_LF DAC_RF data interface DAC_LR DAC_RR data interface DAC_CTR DAC_LFE line mode channels data interface from ADCs
Table Digital Audio Interface Configuration
D_LRCK D_SCLK SDIN 1/2/3 SDATA_OUT
Left Channel
Right Channel
Figure Format
Left Channel
D_LRCK
Right Channel
D_SCLK SDIN 1/2/3 SDATA_OUT
Figure Left Justified Format
D_LRCK D_SCLK SDIN 1/2/3 SDATA_OUT Left Channel Right Channel
Figure Right Justified Format
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec 6.2.
LRCK SCLK SDIN 1/2/3 SDATA_OUT
Single Line Format
Left Channel
Right Channel
Front
Rear
Center
Front
Rear
Bass
Figure Single Line Data Mode Timing Diagram Bits/Sample SCLK Rate Notes inputs, outputs, only
Table Single Line Data Mode, Data Valid Rising Edge SCLK
Single line data mode STAC9460 allows data channels input chip single SDATA_IN line, (Pin output analog outs (Pins 2328). data will valid during first SCLK cycles following D_LRCLK transition.
6.3.
I2C-Bus Interface
I2C-Bus STAC9460 operates compliance with I2C-Bus Interface Specification from Philips Semiconductor. I2C-Bus STAC9460 does include AutoIncrement feature identified Phillips specification. Example, typical write would have following format: START.Chip Address bits).Register Address(8 bits).Data(Register Address bits).Data (Register Address bits).Data (Register Address bits).STOP. addresses will increment through address space until "STOP" condition spec) received part. detailed information relating I2C, please reference I2C-Bus Interface Specification from Philips Semiconductor. Additional information Address Registers found section 7.1.12
Stop Start Repeated Start Stop
tbuf thdst thigh
thdst tsusp
tlow thdd tsud tsust
Figure Timing Diagram
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec
PARAMETER
SYMBOL
UNITS
Mode (SDOUT ground) (Note
Clock Frequency Buss Free Time Between Transmissions Start Condition Hold Time (prior first clock pulse) Clock Time Clock High Time Setup Time Repeated Start Hold Time from Falling (Note Setup Time Rising Rise Time Both Lines Fall Time Both Lines Setup Time Stop Condition
fscl tbuf thdst tlow thigh tsust thdd tsud tsusp
4700 4000 4700 4000 4700
1000 4700
Note:
registered trademark Philips Semiconductor requires license use. Data must held sufficient time bridge transition time Table Mode Specifications
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec PROGRAMMABILITY
NAME Reset/Status Status Master Volume Volume Volume Volume Volume Center Volume Volume Volume Volume De-Emphasis General Purpose Audio Port Control Master Clocking Powerdown Ctrl Powerdown Ctrl Revision Code Address Control Register Address Register
RESERVED
DIFF DEMRF
DEMLF
DEFAULT
MMute Mute Mute Mute Mute Mute Mute Mute ADCL Mute ADCR DEM1
RESERVED RESERVED
DEMLR
RESERVED DEM0 HPFD RSVD HPFF ADF4 MCM2 ADF3 MCM1 Bias PCTR DEMRR
RESERVED ADF2 MCM0 VREF ADF1 SRM1 ADF0 SRM0 DIFF
RESERVED RESERVED RESERVED
PLFE
Table Programming Registers registers shown reserved. bits marked "Reserved" should written zero normal operation
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec 7.1. List Registers
7.1.1. Reset/Status Register (00h)
Writing value this register performs register reset, which causes registers revert their default values. Reading this register returns corresponding status chip section represented bits. bits defined below:
D3-D7 NAME DIFF RESERVED DESCRIPTION Microphone inputs Differential inputs Reference RESERVED
Table Reset/Status Register
7.1.2.
Status Register (01h)
Reading this (read only) register returns corresponding status chip section represented bits. bits defined below:
NAME DESCRIPTION Left front channel Right front channel Left rear channel Right rear channel Center channel Frequency Effects Channel Left Right Table Status Register
7.1.3.
Master Volume Register (02h)
This register manages output signal volume channels simultaneously adds individual channel volume registers. range from with each step equivalent approximately 0.75 MSB, register mute DACs. When this set, output level Bits MV6. used control master volume.
MMUTE MV6.MV0 0000 1111 xxxx FUNCTION Attenuation Attenuation Attenuation
Table Master Volume Register
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec
7.1.4. LF/RF, LR/RR, Center/LFE Output Channel Volume Registers(03h-08h)
These registers determines output signal volumes ranging from with 0.75 steps. register mute channel. When this outputlevel that channel Please note STAC9462 only uses registers Left Right Front Channels.
D6.D0 0000 1111 XXXX FUNCTION Attenuation Attenuation Attenuation
Table Digital Volume Registers
7.1.5.
Microphone Input Volume Registers (09h-0Ah)
These registers control gain/attenuation each microphone inputs ranging from 10.5 with each step corresponding approximately 1.5dB.
ML3.ML0 0000 1111 XXXX FUNCTION 22.5 Attenuation MR3.MR0 0000 1111 XXXX FUNCTION 22.5 Attenuation
Table Left Right Input Volume Registers
7.1.6.
De-Emphasis Register (0Ch)
This register used turn de-emphasis each channel. De-emphasis control bits D5.D0 (DEMLFE DEMLF) select whether de-emphasis turned given bits D7-D6 (DEM1 DEM0) determine which response curve use.
FUNCTION De-emphasis De-emphasis De-emphasis select De-emphasis select CENTER De-emphasis select RIGHT REAR De-emphasis select LEFT REAR De-emphasis select RIGHT FRONT De-emphasis select LEFT FRONT Table On/Off De-emphasis Selection Each Channel FUNCTION Response Curve 44.1 Response Curve Response Curve Response Curve Table De-emphasis Filter Selection
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec
7.1.7. General Purpose Register (0Dh)
(MD) selects between inputs DIFF inputs being routed ADCs. (HPFD) disables pass filter capability. High Pass FIlter Freeze, maintains high pass filter output's current offset
HPFF FUNCTION High Pass Filter Not-Frozen High Pass Filter Frozen Table HPFD FUNCTION Differential Input Selected Microphone Selected
Table Microphone Differential By-Pass Control HPFD FUNCTION High Pass Filter Enabled High Pass Filter Disabled Table High Pass Filter Disable
7.1.8.
Audio Port Control (0Eh)
port controlled bits contained this register. Formatting controlled Audio Data Format bits, ADF4.ADF0 (bits register. audio formats available standard I2S, Left Justified, Right Justified (16, 24-Bit) Line.
ADF4 ADF0 D4.D0 00000 00001 00010 01010 10010 00011 AUDIO DATA FORMAT Left Justified Right Justified Right Justified Right Justified Line settings shown Reserved
Table Audio Data Format Selection
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec
7.1.9. Master Clocking Register (0Fh)
Master Clocking Register used sampling rate converters three sample rate modes. Base rate, rate high rate selected with bits D1-D0 register. master clock mode selecting bits D4,,D2. master clock mode used generate internal clock correct frequency based MCLK supplied user. example, default mode (MCM=100 SRM=00), MCLK 512x, sample rate 48kHz then MCLK must 24.576MHz, which 512x48kHz. with MCM=011 SRM=01 (Mid Rate Mode) sample rate 96kHz, then MCLK must 192x96kHz which 18.432MHz. Master CLocking Register should before unmuting channels register 0Ah. MCM2 (D4) default mode.
SRM1SRM0 D1,D0 (default) SAMPLE RATE 192kHz Reserved FUNCTION Base Rate Mode Rate Mode High Rate Mode* Reserved
Note:*ADC operates Rate Mode when High Rate Mode selected, will send each sample successive frames.
Table Sample Rate Mode MCM2 MCM0 D4,D3,D2 MCLK Mode* 128x Reserved Reserved Reserved 256x 128x 384x 192x (default) 512x 256x 128x 768x 384x 192x Reserved Reserved Reserved Reserved Reserved Reserved *Note: MCLK rate relative sample rate. (MCM MCLK). number D_SCLKs/D_LRCLK independant MCLK mode STAC9460/62, most controllers will generate D_SCLK 1/2, 1/4, 1/8, 1/16 MCLK rate. Table MCLK Mode
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec
7.1.10. Powerdown Control Registers (10h-11h)
STAC9460 capable operating reduced power when activity required. state power down controlled Powerdown register. There separate power down commands. Powerdown options listed Table bits used individually combination with each other, control power distribution ADC's DAC's. VREF option selected powers down entire chip. Please note rear, center, bass DAC's should powered down operation with STAC9462.
PCTR PLFE FUNCTION DAC_LF DAC_RF DAC_LR DAC_RR DAC_CTR DAC_LFE Left Right DIFF VREF Bias FUNCTION Differential Powers down De-emphasis Voltage Reference Powerdown Bias circuitry
Note: Powers down De-emphasis denotes reserved Table Powerdown Control
7.1.11.
Revision Code Register (12h)
device Revision register contains software readable revision-specific code used identify performance, architectural, software differences between various device revisions.
7.1.12.
Address Control Register/Address Register (13h-14h)
address chip defaulted 55/56 54/55 read write. (bit programmable with Address Register (14h) changed. change address, must first written Address Control Register (13h). soft hard reset will reset Address Register default value with representing (D1).
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec DESCRIPTION 8.1. STAC9460 Signal Description
STAC9460 MIC_L MIC_R DIFF_L DIFF_GND DIFF_R VREF AVss AVdd SCLK SDATA SDATA_OUT MCLK denotes active Figure STAC9460 Designation STAC9460 DAC_LF DAC_RF DAC_LR DAC_RR DAC_CTR DAC_LFE DVss DVdd RESET# D_LRCLK D_SCLK SDI3 SDI2 SDI1
STAC9460 28-Pin SSOP
8.2.
STAC9462 Signal Description
STAC9462 MIC_L MIC_R DIFF_L DIFF_GND DIFF_R VREF AVss AVdd SCLK SDATA SDATA_OUT MCLK denotes active Figure STAC9462 Designation STAC9462 DAC_LF DAC_RF N.C. N.C. N.C. N.C. DVss DVdd RESET# D_LRCLK D_SCLK N.C. N.C. SDI1
STAC9462 28-Pin SSOP
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec 8.3. Digital
These signals connect STAC9460/62 external µC/µP, DSP, external crystal.
SIGNAL NAME TYPE DESCRIPTION RESET Master Hareware Reset MCLK Table page details Chip select SCLK Serial data clock SDATA Serial data input/output SDI1 digital data input channels SDI2 digital data input channels (STAC9460 only) SDI3 digital data input Center LFEchannels (STAC9460 only) SDATA_OUT Serial data output outputs D_LRCLK digital data left/right clock D_SCLK digital data clock denotes active Table Digital Signal List
8.4.
Analog
These signals connect STAC9460/62 analog sources sinks, including microphones seakers.
SIGNAL NAME MIC_L MIC_R DIFF_L DIFF_GND DIFF_R DAC_LF DAC_RF DAC_LR DAC_RR DAC_CTR DAC_LFE TYPE DESCRIPTION Left microphone input Right microphone input Left differential input Differential input common ground Right differential input Left front channel (LF) Right front channel (RF) Left rear channel (LR) (STAC9460 only) Right rear channel (RR) (STAC9460 only) Center channel (CTR) (STAC9460 only) Frequency Effects output (LFE) (STAC9460 only)
Table Analog Signal List
8.5.
Filter/References
SIGNAL NAME VREF TYPE DESCRIPTION Reference Voltage reference
Table Filtering Voltage References
2-9460-D1-1-0-0801
STAC9460/62
Six-Channel, 24-Bit, Audio Codec 8.6. Power Ground Signals
SIGNAL NAME AVdd AVss DVdd DVss TYPE DESCRIPTION Analog Analog Digital Digital
Table Power Signal List
PACKAGE DRAWING
2-9460-D1-1-0-0801
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