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8-bit with single voltage Flash, data EEPROM, ADC, timers, SPI, LINSCI
Memories Kbytes program memory: single voltage extended Flash (XFlash) Program memory with read-out protection, In-Circuit Programming In-Application programming (ICP IAP), data retention: years 55°C. bytes bytes data EEPROM with read-out protection. 300K write/erase cycles guaranteed, data retention: years 55°C. Clock, Reset Supply Management Enhanced reset system Enhanced voltage supervisor (LVD) main supply auxiliary voltage detector (AVD) with interrupt capability implementing safe power-down procedures Clock sources: Internal oscillator, crystal/ceramic resonator external clock Optional internal clock Five Power Saving Modes: Halt, Active-Halt, Wait Slow, Auto Wake From Halt Ports multifunctional bidirectional lines high sink outputs Timers Configurable Watchdog Timer 8-bit Lite Timers with prescaler, realtime base input capture 12-bit Auto-reload Timers with outputs, input capture output compare functions
QFN20 SO20 DIP20 Communication Interfaces Master/slave LINSCIasynchronous serial interface synchronous serial interface Interrupt Management interrupt vectors plus TRAP RESET external interrupt lines vectors) Converter input channels 10-bit resolution Instruction 8-bit data manipulation basic instructions with illegal opcode detection main addressing modes unsigned multiply instructions Development Tools Full hardware/software development package (Debug module)
Table Device summary
Features Program memory bytes (stack) bytes Data EEPROM bytes Peripherals Operating Supply Frequency Operating Temperature Packages ST7LITE30 ST7LITE35 ST7LITE39 (128) Lite Timer, Autoreload Timer, SPI, LINSCI, 10-bit 2.7V 5.5V 8Mhz 8Mhz 16MHz 16MHz) 1MHz PLLx8/4MHz) -40°C +125°C SO20 300", DIP20, QFN20
INTRODUCTION DESCRIPTION REGISTER MEMORY FLASH PROGRAM MEMORY INTRODUCTION MAIN FEATURES PROGRAMMING MODES INTERFACE MEMORY PROTECTION RELATED DOCUMENTATION REGISTER DESCRIPTION
DATA EEPROM INTRODUCTION MAIN FEATURES MEMORY ACCESS POWER SAVING MODES ACCESS ERROR HANDLING DATA EEPROM READ-OUT PROTECTION REGISTER DESCRIPTION
CENTRAL PROCESSING UNIT INTRODUCTION MAIN FEATURES REGISTERS
SUPPLY, RESET CLOCK MANAGEMENT INTERNAL OSCILLATOR ADJUSTMENT PHASE LOCKED LOOP REGISTER DESCRIPTION MULTI-OSCILLATOR (MO) RESET SEQUENCE MANAGER (RSM) SYSTEM INTEGRITY MANAGEMENT (SI)
INTERRUPTS MASKABLE SOFTWARE INTERRUPT EXTERNAL INTERRUPTS PERIPHERAL INTERRUPTS
POWER SAVING MODES INTRODUCTION SLOW MODE WAIT MODE HALT MODE
ACTIVE-HALT MODE AUTO WAKE FROM HALT MODE
PORTS 10.1 INTRODUCTION 10.2 FUNCTIONAL DESCRIPTION 10.3 PORT IMPLEMENTATION 10.4 UNUSED PINS 10.5 POWER MODES 10.6 INTERRUPTS ON-CHIP PERIPHERALS 11.1 WATCHDOG TIMER (WDG) 11.2 DUAL 12-BIT AUTORELOAD TIMER (AT3) 11.3 LITE TIMER (LT2) 11.4 SERIAL PERIPHERAL INTERFACE (SPI) 11.5 LINSCI SERIAL COMMUNICATION INTERFACE (LIN MASTER/SLAVE) 11.6 10-BIT CONVERTER (ADC) INSTRUCTION 12.1 ADDRESSING MODES 12.2 INSTRUCTION GROUPS ELECTRICAL CHARACTERISTICS 13.1 PARAMETER CONDITIONS 13.2 ABSOLUTE MAXIMUM RATINGS 13.3 OPERATING CONDITIONS 13.4 SUPPLY CURRENT CHARACTERISTICS 13.5 CLOCK TIMING CHARACTERISTICS 13.6 MEMORY CHARACTERISTICS 13.7 CHARACTERISTICS 13.8 PORT CHARACTERISTICS 13.9 CONTROL CHARACTERISTICS 13.10 COMMUNICATION INTERFACE CHARACTERISTICS 13.11 10-BIT CHARACTERISTICS PACKAGE CHARACTERISTICS 14.1 PACKAGE MECHANICAL DATA 14.2 THERMAL CHARACTERISTICS 14.3 SOLDERING INFORMATION DEVICE CONFIGURATION 15.1 FLASH OPTION BYTES 15.2 DEVICE ORDERING INFORMATION TRANSFER CUSTOMER CODE 15.3 DEVELOPMENT TOOLS 15.4 APPLICATION NOTES KNOWN LIMITATIONS
16.1 CLEARING ACTIVE INTERRUPTS OUTSIDE INTERRUPT ROUTINE 16.2 LINSCI LIMITATION REVISION HISTORY
obtain most recent version this datasheet, please check www.st.com>products>technical literature>datasheet
Please also special attention Section "KNOWN LIMITATIONS" page 171.
ST7LITE3 member microcontroller family. devices based common industry-standard 8-bit core, featuring enhanced instruction set. ST7LITE3 features FLASH memory with byte-by-byte In-Circuit Programming (ICP) InApplication Programming (IAP) capability. Under software control, ST7LITE3 device placed WAIT, SLOW, HALT mode, reducing power consumption when application idle standby state. enhanced instruction addressing modes offer both power flexibility software developers, enabling design highly Figure General Block Diagram efficient compact application code. addition standard 8-bit data management, microcontrollers feature true manipulation, unsigned multiplication indirect addressing modes. easy reference, parametric data located section page 131. devices feature on-chip Debug Module (DM) support in-circuit debugging (ICD). description registers, refer Protocol Reference Manual.
CLKIN OSC1 OSC2
Ext. 1MHz 16MHz
12-Bit Auto-Reload TIMER 8-Bit LITE TIMER Internal CLOCK PA7:0 bits) PB6:0 bits)
RESET POWER SUPPLY CONTROL 8-BIT CORE
LINSCI PROGRAM MEMORY Bytes)
DATA EEPROM Bytes)
Figure 20-Pin Package Pinout
RESET SS/AIN0/PB0 SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 CLKIN/AIN4/PB4
(HS)/LTIC (HS)/ATIC (HS)/ATPWM0 (HS)/ATPWM1 (HS)/ATPWM2 (HS)/ATPWM3/ICCDATA
(HS) 20mA High sink capability associated external interrupt vector
Figure 20-Pin Package Pinout
RESET SS/AIN0/PB0 SCK/AIN1/PB1 MISO/AIN2/PB2 MOSI/AIN3/PB3 CLKIN/AIN4/PB4 AIN5/PB5 RDI/AIN6/PB6 OSC1/CLKIN OSC2 (HS)/LTIC (HS)/ATIC (HS)/ATPWM0 (HS)/ATPWM1 (HS)/ATPWM2 (HS)/ATPWM3/ICCDATA PA6/MCO/ICCCLK/BREAK (HS)/TDO
(HS) 20mA high sink capability associated external interrupt vector
DESCRIPTION (Cont'd) Legend Abbreviations Table Type: input, output, supply In/Output level: CMOS 0.3VDD/0.7VDD with input trigger Output level: 20mA high sink N-buffer only) Port control configuration: Input: float floating, weak pull-up, interrupt, analog Output: open drain, push-pull RESET configuration each shown bold which valid long device reset state. Table Device Description
Level SO20/DIP20 Type Input Name Output QFN20 Port Control Input float Main Output Function (after reset) Ground Main power supply priority maskable interrupt (active low) Analog Input Slave Select (active low) Caution: negative current injection allowed this pin. details, refer section 13.2.2 page Analog Input Serial Clock Caution: negative current injection allowed this pin. details, refer section 13.2.2 page Analog Input Master Slave Data Analog Input Master Slave Data Analog Input External clock input Analog Input Analog Input LINSCI Input LINSCI Output Alternate Function
PB1/AIN1/SCK PB2/AIN2/ MISO PB3/AIN3/ MOSI PB4/AIN4/ CLKIN** PB5/AIN5
Port Port Port Port Port Port
Level SO20/DIP20 Type Output QFN20 Input Name
Port Control Input float Main Output Function (after reset) Alternate Function
Main Clock Output Circuit Communication Clock External BREAK /MCO/ ICCCLK/ BREAK Caution: During normal operation this must pulled- internally externally (external pull-up mandatory noisy environment). This avoid entering mode unexpectedly during reset. application, even configured output, reset will back input pull-up. Auto-Reload Timer PWM3 Circuit Communication Data Auto-Reload Timer PWM2 Auto-Reload Timer PWM1 Auto-Reload Timer PWM0 Auto-Reload Timer Input Capture Lite Timer Input Capture
Port Port Port Port Port Port
PA4/ATPWM2 PA3/ATPWM1 PA2/ATPWM0 PA1/ATIC PA0/LTIC OSC2 OSC1/CLKIN
Resonator oscillator inverter output Resonator oscillator inverter input External clock input
Notes: mandatory connect available VDDA pins supply voltage VSSA pins ground. input with interrupt possibility "eix" defines associated external interrupt vector which assigned pins using EISR register. Each interrupt either weak pull-up floating defined through option register
shown Figure capable addressing bytes memories registers. available memory locations consist bytes register locations, bytes RAM, bytes data EEPROM Kbytes user program memory. space includes bytes stack from 180h 1FFh. highest address bytes contain user reset interrupt vectors. Figure Memory
Flash memory contains sectors (see Figure mapped upper part addressing space reset interrupt vectors located Sector (F000h-FFFFh). size Flash Sector other device options configurable Option byte. IMPORTANT: Memory locations marked "Reserved" must never accessed. Accessing reseved area have unpredictable effects device.
Short Addressing (zero page)
0000h 007Fh 0080h 01FFh 0200h
Registers (see Table (384 Bytes) Reserved
0FFFh 1000h 10FFh 1100h
Data EEPROM (256 Bytes)
RCCRH0 RCCRL0 RCCRH1
FLASH PROGRAM MEMORY
section page Note
Flash Memory (8K)
FBFFh FC00h FFFFh
Kbytes SECTOR Kbyte SECTOR
Interrupt Reset Vectors (see Table
DEE0h, DEE1h, DEE2h DEE3h addresses located reserved area special bytes containing also calibration values which read-accessible only user mode. EEPROM data Flash space (including calibration values locations) been erased (after read protection removal), then calibration values still obtained through these addresses.
Table Hardware Register
Address 0000h 0001h 0002h 0003h 0004h 0005h 0006h 0007h 0008h 0009h 000Ah 000Bh 000Ch 000Dh 000Eh 000Fh 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h 0019h 001Ah 001Bh 001Ch 001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h 0024h 0025h 0026h 002Dh 002Eh 0002Fh 00030h FLASH EEPROM WDGCR FCSR EECSR LTCSR2 LTARR LTCNTR LTCSR1 LTICR ATCSR CNTR1H CNTR1L ATR1H ATR1L PWMCR PWM0CSR PWM1CSR PWM2CSR PWM3CSR DCR0H DCR0L DCR1H DCR1L DCR2H DCR2L DCR3H DCR3L ATICRH ATICRL ATCSR2 BREAKCR ATR2H ATR2L DTGR Block Register Label PADR PADDR PAOR PBDR PBDDR PBOR Register Name Port Data Register Port Data Direction Register Port Option Register Port Data Register Port Data Direction Register Port Option Register Reserved area bytes) Lite Timer Control/Status Register Lite Timer Auto-reload Register Lite Timer Counter Register Lite Timer Control/Status Register Lite Timer Input Capture Register Timer Control/Status Register Counter Register High Counter Register Auto-Reload Register High Auto-Reload Register Output Control Register Control/Status Register Control/Status Register Control/Status Register Control/Status Register Duty Cycle Register High Duty Cycle Register Duty Cycle Register High Duty Cycle Register Duty Cycle Register High Duty Cycle Register Duty Cycle Register High Duty Cycle Register Input Capture Register High Input Capture Register Timer Control/Status Register Break Control Register Auto-Reload Register High Auto-Reload Register Dead Time Generator Register Reserved area bytes) Watchdog Control Register Flash Control/Status Register Data EEPROM Control/Status Register 0x00 00x0b 0x00 0000b Read Only Read Only Read Only Read Only Read Only Read Only Reset Status FFh1) Remarks R/W2)
Address 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Fh 0040h 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh 0050h 0051h 007Fh
Register Label SPIDR SPICR SPICSR ADCCSR ADCDRH ADCDRL EICR MCCSR RCCR SICSR
Register Name Data Register Control Register Control Status Register Control Status Register Data Register High control Data Register External Interrupt Control Register Main Clock Control/Status Register oscillator Control Register System Integrity Control/Status Register Reserved area byte)
Reset Status 0110 0xx0b
Remarks Read Only
External Interrupt Selection Register Reserved area bytes)
LINSCI (LIN Master/Slave)
SCISR SCIDR SCIBRR SCICR1 SCICR2 SCICR3 SCIERPR SCIETPR
Status Register Data Register Baud Rate Register Control Register Control Register Control Register Extended Receive Prescaler Register Extended Transmit Prescaler Register Reserved area byte)
AWUPR AWUCSR DMCR DMSR DMBK1H DMBK1L DMBK2H DMBK2L
Prescaler Register Control/Status Register Control Register Status Register Breakpoint Register High Breakpoint Register Breakpoint Register High Breakpoint Register Reserved area bytes)
Legend: x=undefined, R/W=read/write Notes: contents port registers readable only output configuration. input configuration, values pins returned instead register contents. bits associated with unavailable pins must always keep their reset value. description registers, Reference Manual.
FLASH PROGRAM MEMORY
Introduction single voltage extended Flash (XFlash) non-volatile memory that electrically erased programmed either byte-by-byte basis bytes parallel. XFlash devices programmed off-board (plugged programming tool) on-board using In-Circuit Programming In-Application Programming. array matrix organisation allows each sector erased reprogrammed without affecting other sectors. Main
(In-Circuit Programming) (In-Application Programming) (In-Circuit Testing) downloading executing user application test patterns Sector size configurable option byte Read-out write protection
PROGRAMMING MODES programmed three different ways: Insertion programming tool. this mode, FLASH sectors option byte data EEPROM present) programmed erased. In-Circuit Programming. this mode, FLASH sectors option byte data EEPROM present) programmed erased without removing device from application board. In-Application Programming. this mode, sector data EEPROM present) programmed erased without removing
device from application board while application running. 4.3.1 In-Circuit Programming (ICP) uses protocol called (In-Circuit Communication) which allows plugged printed circuit board (PCB) communicate with external programming device connected cable. performed three steps: Switch mode (In-Circuit Communications). This done driving specific signal sequence ICCCLK/DATA pins while RESET pulled low. When enters mode, fetches specific RESET vector which points System Memory containing protocol routine. This routine enables receive bytes from interface. Download Driver code from ICCDATA Execute Driver code program FLASH memory Depending Driver code downloaded RAM, FLASH memory programming fully customized (number bytes program, program locations, selection serial communication interface downloading). 4.3.2 Application Programming (IAP) This mode uses Driver program previously programmed Sector user mode). This mode fully controlled user software. This allows adapted user application, (user-defined strategy entering programming mode, choice communications protocol used fetch data stored etc.) mode used program memory areas except Sector which write/erase protected allow recovery case errors occur during programming operation.
FLASH PROGRAM MEMORY (Cont'd) INTERFACE needs minimum pins connected programming tool. These pins are: RESET: device reset VSS: device power supply ground Figure Typical Interface
PROGRAMMING TOOL CONNECTOR Cable CONNECTOR HE10 CONNECTOR TYPE (See Note OPTIONAL (See Note APPLICATION RESET SOURCE Note APPLICATION BOARD
ICCCLK: output serial clock ICCDATA: input serial data CLKIN/PB4: main clock input external source VDD: application board power supply (optional, Note
APPLICATION POWER SUPPLY (See Note CLKIN/PB4
Note caution APPLICATION Note RESET ICCCLK ICCDATA
Notes: ICCCLK ICCDATA pins only used outputs application, signal isolation necessary. soon Programming Tool plugged board, even session progress, ICCCLK ICCDATA pins available application. they used inputs application, isolation such serial resistor implemented another device forces signal. Refer Programming Tool documentation recommended resistor values. During session, programming tool must control RESET pin. This lead conflicts between programming tool application reset circuit drives more than high level (push pull output pull-up resistor<1K). schottky diode used isolate application RESET circuit this case. When using classical network with R>1K reset management with open drain output pull-up resistor>1K, additional components needed. cases user must ensure that external reset generated application during session. connector depends Programming Tool architecture. This
must connected when using most Programming Tools used monitor application power supply). Please refer Programming Tool manual. must connected when clock available application selected clock option programmed option byte. devices with multi-oscillator capability must have OSC2 grounded this case. With programming tool, while option disabled, external clock must provided PB4. 38-pulse mode, internal oscillator forced clock source, regardless selection option byte. ST7LITE30 devices which support internal oscillator, "option byte disabled" mode must used (35pulse mode entry, clock provided tool). Caution: During normal operation ICCCLK must pulled- internally externally (external pull-up mandatory noisy environment). This avoids entering mode unexpectedly during reset. application, even configured output, reset puts back input pull-up.
FLASH PROGRAM MEMORY (Cont'd) Memory Protection There different types memory protection: Read Protection Write/Erase Protection which applied individually. 4.5.1 Read Protection Readout protection, when selected provides protection against program memory content extraction against write access Flash memory. Even protection considered totally unbreakable, feature provides very high level protection general purpose microcontroller. Both program data memory protected. flash devices, this protection removed reprogramming option. this case, both program data memory automatically erased device reprogrammed. Read-out protection selection enabled removed through FMP_R option byte. 4.5.2 Flash Write/Erase Protection Write/erase protection, when set, makes impossible both overwrite erase program memory. does apply data. purpose provide advanced security applications prevent change being made memory content. Warning: Once set, Write/erase protection never removed. write-protected flash device longer reprogrammable. Write/erase protection enabled through FMP_W option byte. Related Documentation details Flash programming protocol, refer Flash Programming Reference Manual Protocol Reference Manual. Register Description FLASH CONTROL/STATUS REGISTER (FCSR) Read/Write Reset Value: 0000 (00h) RASS Key: 0101 0110 (56h) RASS Key: 1010 1110 (AEh)
Note: This register reserved programming using ICP, other programming methods. controls XFlash programming erasing operations. When another programming tool used socket mode), RASS keys sent automatically.
INTRODUCTION Electrically Erasable Programmable Read Only Memory used volatile backup storing data. Using EEPROM requires basic access protocol described this chapter. MAIN FEATURES
Bytes programmed same cycle EEPROM mono-voltage (charge pump) Chained erase programming cycles Internal control global programming cycle duration WAIT mode management Readout protection
Figure EEPROM Block Diagram
HIGH VOLTAGE PUMP
EEPROM MEMORY MATRIX BITS)
BITS DATA LATCHES
DATA EEPROM (Cont'd) MEMORY ACCESS Data EEPROM memory read/write access modes controlled E2LAT EEPROM Control/Status register (EECSR). flowchart Figure describes these different memory access modes. Read Operation (E2LAT=0) EEPROM read normal location when E2LAT EECSR register cleared. this device, Data EEPROM also used execute machine code. Take care write Data EEPROM while executing from This would result unexpected code being executed. Write Operation (E2LAT=1) access write mode, E2LAT software (the E2PGM remains cleared). When write access EEPROM area occurs, Figure Data EEPROM Programming Flowchart value latched inside data latches according address. When software, previous bytes written data latches programmed EEPROM cells. effective high address (row) determined last EEPROM write sequence. avoid wrong programming, user must take care that bytes written between programming sequences have same high address: only five Least Significant Bits address change. programming cycle, bits cleared simultaneously. Note: Care should taken during programming cycle. Writing same memory location will over-program memory (logical between write access data result) because data latches only cleared programming cycle falling edge E2LAT bit. possible read latched data. This note ilustrated Figure
READ MODE E2LAT=0 E2PGM=0
WRITE MODE E2LAT=1 E2PGM=0
READ BYTES EEPROM AREA
WRITE BYTES EEPROM AREA (with same address)
START PROGRAMMING CYCLE E2LAT=1 E2PGM=1 (set software)
DATA EEPROM (Cont'd) Figure Data E2PROM Write Operation
Byte DEFINITION Read operation impossible Physical Address
00h.1Fh 20h.3Fh Nx20h.Nx20h+1Fh
Read operation possible
Programming cycle PHASE
Writing data latches E2LAT
Waiting E2PGM E2LAT fall
Note: programming cycle interrupted reset action), integrity data memory guaranteed.
DATA EEPROM (Cont'd) POWER SAVING MODES Wait mode DATA EEPROM enter WAIT mode execution instruction microcontroller when microcontroller enters Active-HALT mode.The DATA EEPROM will immediately enter this mode there programming progress, otherwise DATA EEPROM will finish cycle then enter WAIT mode. Active-Halt mode Refer Wait mode. Halt mode DATA EEPROM immediately enters HALT mode microcontroller executes HALT instruction. Therefore EEPROM will stop function progress, data corrupted. ACCESS ERROR HANDLING read access occurs while E2LAT=1, then data will driven. write access occurs while E2LAT=0, then data will latched. programming cycle interrupted RESET action), integrity data memory guaranteed. Data EEPROM Read-out Protection read-out protection enabled through option (see section 15.1 page 162). When this option selected, programs data stored EEPROM memory protected against read-out (including re-write protection). Flash devices, when this protection removed reprogramming Option Byte, entire Program memory EEPROM first automatically erased. Note: Both Program Memory data EEPROM protected using same option bit.
Figure Data EEPROM Programming Cycle
READ OPERATION POSSIBLE INTERNAL PROGRAMMING VOLTAGE ERASE CYCLE WRITE DATA LATCHES WRITE CYCLE READ OPERATION POSSIBLE
DATA EEPROM (Cont'd) REGISTER DESCRIPTION EEPROM CONTROL/STATUS REGISTER (EECSR) Read/Write Reset Value: 0000 0000 (00h)
Bits Reserved, forced hardware E2LAT Latch Access Transfer This software. cleared hardware programming cycle. only cleared software E2PGM cleared. Read mode Write mode E2PGM Programming control status This software begin programming cycle. programming cycle, this cleared hardware. Programming finished started Programming cycle progress Note: E2PGM cleared during programming cycle, memory data guaranteed Table DATA EEPROM Register Reset Values
Address (Hex.) 0030h Register Label EECSR Reset Value E2LAT E2PGM
CENTRAL PROCESSING UNIT
INTRODUCTION This full 8-bit architecture contains internal registers allowing efficient 8-bit data manipulation. MAIN FEATURES
basic instructions Fast 8-bit 8-bit multiply main addressing modes 8-bit index registers 16-bit stack pointer power modes Maskable hardware interrupts Non-maskable software interrupt
REGISTERS registers shown Figure present memory mapping accessed specific instructions. Figure Registers
RESET VALUE RESET VALUE RESET VALUE
Accumulator Accumulator 8-bit general purpose register used hold operands results arithmetic logic calculations manipulate data. Index Registers indexed addressing modes, these 8-bit registers used create either effective addresses temporary storage areas data manipulation. (The Cross-Assembler generates precede instruction (PRE) indicate that following instruction refers register.) register affected interrupt automatic procedures (not pushed popped from stack). Program Counter (PC) program counter 16-bit register containing address next instruction executed CPU. made 8-bit registers (Program Counter which LSB) (Program Counter High which MSB).
PROGRAM COUNTER RESET VALUE RESET VECTOR FFFEh-FFFFh CONDITION CODE REGISTER
RESET VALUE STACK POINTER RESET VALUE STACK HIGHER ADDRESS Undefined Value
REGISTERS (cont'd) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx
logical data manipulation. copy result. result last operation positive null. result last operation negative (that most significant logic This accessed JRMI JRPL instructions. Zero This cleared hardware. This indicates that result last arithmetic, logical data manipulation zero. result last operation different from zero. result last operation zero. This accessed JREQ JRNE test instructions. Carry/borrow This cleared hardware software. indicates overflow underflow occurred during last arithmetic operation. overflow underflow occurred. overflow underflow occurred. This driven instructions tested JRNC instructions. also affected "bit test branch", shift rotate instructions. REGISTERS (Cont'd) STACK POINTER (SP) Read/Write Reset Value: 01FFh
8-bit Condition Code register contains interrupt mask four flags representative result instruction just executed. This register also handled PUSH instructions. These bits individually tested and/or controlled specific instructions. Half carry This hardware when carry occurs between bits during instruction. reset hardware during same instructions. half carry occurred. half carry occurred. This tested using JRNH instruction. useful arithmetic subroutines. Interrupt mask This hardware when entering interrupt software disable interrupts except TRAP software interrupt. This cleared software. Interrupts enabled. Interrupts disabled. This controlled RIM, IRET instructions tested JRNM instructions. Note: Interrupts requested while latched processed when cleared. default interrupt routine interruptible because hardware start routine reset IRET instruction routine. cleared software interrupt routine, pending interrupts serviced regardless priority level current interrupt routine. Negative This cleared hardware. representative result sign last arithmetic,
Stack Pointer 16-bit register which always pointing next free location stack. then decremented after data been pushed onto stack incremented before data popped from stack (see Figure 11). Since stack bytes deep, most significant bits forced hardware. Following
Reset, after Reset Stack Pointer instruction (RSP), Stack Pointer contains reset value (the bits set) which stack higher address. least significant byte Stack Pointer (called directly accessed instruction. Note: When lower limit exceeded, Stack Pointer wraps around stack upper limit, without indicating stack overflow. previously stored information then overwritten therefore lost. stack also wraps case underflow. stack used save return address during subroutine call context during interrupt. user also directly manipulate stack means PUSH instrucFigure Stack Manipulation Example
CALL Subroutine 0180h Interrupt Event PUSH
tions. case interrupt, stored first location pointed Then other registers stored next locations shown Figure When interrupt received, decremented context pushed stack. return from interrupt, incremented context popped from stack. subroutine call occupies locations interrupt five locations stack area.
Stack Higher Address 01FFh Stack Lower Address 0180h
SUPPLY, RESET CLOCK MANAGEMENT
device includes range utility features securing application critical situations (for example case power brown-out), reducing number external components. Main features
tion code. This area cannot erased programmed operation. compatibility reasons with SICSR register, CR[1:0] bits stored position DEE1 DEE3 addresses. Note: 38-pulse mode, internal oscillator forced clock source, regardless selection option byte. ST7LITE30 devices which support internal oscillator, "option byte disabled" mode must used (35-pulse mode entry, clock provided tool). "ELECTRICAL CHARACTERISTICS" page 131. more information frequency accuracy oscillator. improve clock stability frequency accuracy, recommended place decoupling capacitor, typically 100nF, between pins close possible device These bytes systematically programmed including FASTROM devices. Consequently, customers intending FASTROM service must these bytes. RCCR0 RCCR1 calibration values will erased read-out protection reset after been "Read Protection" page Caution: voltage temperature conditions change application, frequency need recalibrated. Refer application note AN1324 information calibrate frequency using external reference signal. PHASE LOCKED LOOP used multiply 1MHz frequency from oscillator external clock obtain fOSC MHz. enabled multiplication factor selected option bits. intended operation with 2.7V 3.3V range intended operation with 3.3V 5.5V range Refer Section 15.1 option byte description. disabled oscillator enabled, then fOSC 1MHz.
Clock Management internal oscillator (enabled option byte, available ST7LITE35 ST7LITE39 devices only) 32kHz External crystal/ceramic resonator (selected option byte) External Clock Input (enabled option byte) multiplying frequency (enabled option byte) Reset Sequence Manager (RSM) System Integrity Management (SI) Main supply voltage detection (LVD) with reset generation (enabled option byte) Auxiliary Voltage detector (AVD) with interrupt capability monitoring main supply (enabled option byte)
INTERNAL OSCILLATOR ADJUSTMENT device contains internal oscillator with accuracy given device, temperature voltage range (4.5V-5.5V). must calibrated obtain frequency required application. This done software writing 8-bit calibration value RCCR Control Register) bits [6:5] SICSR Control Status Register). Whenever microcontroller reset, RCCR returns default value (FFh), i.e. each time device reset, calibration value must loaded RCCR. Predefined calibration values stored EEPROM supply voltages 25°C, shown following table.
RCCR RCCRH0 RCCRL0 RCCRH1 RCCRL1 Conditions VDD=5V TA=25°C fRC=1MHz VDD=3.3V TA=25°C fRC=1MHz ST7LITE3 Addresses DEE0h (CR[9:2] bits) DEE1h (CR[1:0] bits) DEE2h (CR[9:2] bits) DEE3h (CR[1:0] bits)
DEE0h, DEE1h, DEE2h DEE3h addresses located reserved area non-volatile memory. They read-only bytes applica-
both oscillator disabled, fOSC driven external clock. Figure Output Frequency Timing Diagram LOCKED input freq. tSTAB
REGISTER DESCRIPTION MAIN CLOCK CONTROL/STATUS REGISTER (MCCSR) Read Write Reset Value: 0000 0000 (00h)
Bits Reserved, must kept cleared. Output freq. tLOCK tSTARTUP Main Clock enable This read/write software cleared hardware after reset. This allows enable output clock. clock disabled, port free general purpose I/O. clock enabled. Slow Mode select This read/write software cleared hardware after reset. This selects input clock fOSC fOSC/32. Normal mode (fCPU fOSC Slow mode (fCPU fOSC/32) CONTROL REGISTER (RCCR) Read Write Reset Value: 1111 1111 (FFh)
When started, after reset wakeup from Halt mode AWUFH mode, outputs clock after delay tSTARTUP. When output signal reaches operating frequency, LOCKED SICSCR register set. Full accuracy (ACCPLL) reached after stabilization time tSTAB (see Figure 13.3.4Internal Oscillator PLL) Refer section 7.6.4 page description LOCKED SICSR register.
Bits CR[9:2] Oscillator Frequency Adjustment Bits These bits must written immediately after reset adjust oscillator frequency obtain accuracy application store correct value each voltage range EEPROM write this register start-up. maximum available frequency lowest available frequency These bits used with CR[1:0] bits SICSR register. Refer section 7.6.4 page Note: tune oscillator, write series different values register until correct frequency reached. fastest method dichotomy starting with 80h.
Figure Clock Management Block Diagram
SICSR CLKIN/2 (Ext Clock) 8MHz 1MHz 8MHz 4MHz 1MHz 4MHz Option Clock
Tunable Oscillator 1MHz OSCRANGE[2:0] Option bits CLKIN CLKIN fCLKIN CLKIN DIVIDER
OSC,PLLOFF, OSCRANGE[2:0] Option bits
CLKIN/ OSC1 OSC2
8-BIT LITE TIMER COUNTER fOSC DIVIDER fOSC/32
fLTIMER (1ms timebase fOSC)
MULTI-OSCILLATOR (MO) main clock generated four different source types coming from multioscillator block 16MHz 32kHz): external source crystal ceramic resonator oscillators internal high frequency oscillator Each oscillator optimized given frequency range terms consumption selectable through option byte. associated hardware configurations shown Table Refer electrical characteristics section more details. External Clock Source this external clock mode, clock signal (square, sinus triangle) with ~50% duty cycle drive OSC1 while OSC2 tied ground. Note: when Multi-Oscillator used, selected default external clock. Crystal/Ceramic Oscillators This family oscillators advantage producing very accurate rate main clock ST7. selection within list oscillators with different frequency ranges done option byte order reduce consumption (refer section 15.1 page more details frequency ranges). this mode multi-oscillator, resonator load capacitors have placed close possible oscillator pins order minimize output distortion start-up stabilization time. loading capacitance values must adjusted according selected oscillator. These oscillators stopped during RESET phase avoid losing time oscillator start-up phase. Internal Oscillator this mode, tunable 1%RC oscillator used main clock source. oscillator pins have tied ground. calibration done through RCCR[7:0] SICSR[6:5] registers. Table Clock Sources
RESET SEQUENCE MANAGER (RSM) 7.5.1 Introduction reset sequence manager includes three RESET sources shown Figure External RESET source pulse Internal RESET (Low Voltage Detection) Internal WATCHDOG RESET Note: reset also triggered following detection illegal opcode prebyte code. Refer section 12.2.1 page further details. These sources RESET always kept during delay phase. RESET service routine vector fixed addresses FFFEh-FFFFh memory map. basic RESET sequence consists phases shown Figure Active Phase depending RESET source 4096 clock cycle delay (see table below) RESET vector fetch Caution: When unprogrammed fully erased, Flash blank RESET vector programmed. this reason, recommended keep RESET state until programming mode entered, order avoid unwanted behavior. 4096 clock cycle delay allows oscillator stabilise ensures that recovery taken place from Reset state. shorter longer clock cycle delay automatically selected depending clock source chosen option byte: RESET vector fetch phase duration clock cycles.
Clock Source Internal Oscillator External clock (connected CLKIN pin) External Crystal/Ceramic Oscillator (connected OSC1/OSC2 pins) clock cycle delay 4096
enabled option byte, outputs clock after additional delay tSTARTUP (see Figure 12). Figure RESET Sequence Phases
Active Phase INTERNAL RESET 4096 CLOCK CYCLES FETCH VECTOR
7.5.2 Asynchronous External RESET RESET both input open-drain output with integrated weak pull-up resistor. This pull-up fixed value varies accordance with input voltage. pulled external circuitry reset device. Electrical Characteristic section more details. RESET signal originating from external source must have duration least th(RSTL)in order recognized (see Figure 16). This detection asynchronous therefore enter reset state even HALT mode.
Figure Reset Block Diagram
Filter INTERNAL RESET
WATCHDOG RESET ILLEGAL OPCODE RESET1) RESET
Note "Illegal Opcode Reset" page 128. more details illegal opcode reset conditions.
RESET SEQUENCE MANAGER (Cont'd) RESET asynchronous signal which plays major role performance. noisy environment, recommended follow guidelines mentioned electrical characteristics section. 7.5.3 External Power-On RESET disabled option byte, start microcontroller correctly, user must ensure means external reset circuit that reset signal held until over minimum level specified selected fOSC frequency. proper reset signal slow rising supply generally provided external network connected RESET pin. 7.5.4 Internal Voltage Detector (LVD) RESET different RESET sequences caused internal circuitry distinguished: Power-On RESET Voltage Drop RESET device RESET acts output that pulled when VDD<VIT+ (rising edge) VDD<VIT- (falling edge) shown Figure filters spikes larger than tg(VDD) avoid parasitic resets. 7.5.5 Internal Watchdog RESET RESET sequence generated internal Watchdog counter overflow shown Figure Starting from Watchdog counter underflow, device RESET acts output that pulled during least tw(RSTL)out.
Figure RESET Sequences
EXTERNAL RESET SOURCE
WATCHDOG RESET WATCHDOG UNDERFLOW INTERNAL RESET (256 4096 TCPU) VECTOR FETCH
SYSTEM INTEGRITY MANAGEMENT (SI) System Integrity Management block contains voltage Detector (LVD) Auxiliary Voltage Detector (AVD) functions. managed SICSR register. Note: reset also triggered following detection illegal opcode prebyte code. Refer section 12.2.1 page further details. 7.6.1 Voltage Detector (LVD) Voltage Detector function (LVD) generates static reset when supply voltage below VIT-(LVD) reference value. This means that secures power-up well power-down keeping reset. VIT-(LVD) reference value voltage drop lower than VIT+(LVD) reference value poweron order avoid parasitic reset when starts running sinks current supply (hysteresis). Reset circuitry generates reset when below: VIT+(LVD)when rising VIT-(LVD) when falling function illustrated Figure voltage threshold configured option byte low, medium high. Provided minimum value (guaranteed oscillator frequency) above VIT-(LVD), only modes: under full software control static safe reset these conditions, secure operation always ensured application without need external reset hardware. During Voltage Detector Reset, RESET held low, thus permitting reset other devices. Notes: allows device used without external RESET circuitry. with capacitive power supply: with this type power supply, power cuts occur application, recommended pull down ensure optimum restart conditions. Refer circuit example Figure page note optional function which selected option byte. recommended make sure that supply voltage rises monotonously when device exiting from Reset, ensure application functions properly.
Figure Voltage Detector Reset
Vhys VIT+(LVD) VIT-(LVD)
Figure Reset Supply Management Block Diagram
WATCHDOG TIMER (WDG)
SYSTEM INTEGRITY MANAGEMENT RESET SEQUENCE RESET MANAGER (RSM) SICSR
WDGRF LOCKED LVDRF AVDF AVDIE
VOLTAGE DETECTOR (LVD)
AUXILIARY VOLTAGE DETECTOR (AVD)
SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.6.2 Auxiliary Voltage Detector (AVD) Voltage Detector function (AVD) based analog comparison between VIT-(AVD) VIT+(AVD) reference value main supply voltage (VAVD). VIT-(AVD) reference value falling voltage lower than VIT+(AVD) reference value rising voltage order avoid parasitic detection (hysteresis). output comparator directly readable application software through real time status (AVDF) SICSR register. This read only. Caution: functions only enFigure Using Monitor Early Warning Interrupt (Power dropped, reset)
abled through option byte. 220.127.116.11 Monitoring Main Supply voltage threshold value relative selected threshold configured option byte (see section 15.1 page 162). interrupt enabled, interrupt generated when voltage crosses VIT+(LVD) VIT-(AVD) threshold (AVDF set). case drop voltage, interrupt acts early warning, allowing software shut down safely before resets microcontroller. Figure
VIT+(AVD) VIT-(AVD) VIT+(LVD) VIT-(LVD)
AVDF INTERRUPT REQUEST AVDIE
INTERRUPT Cleared reset
INTERRUPT Cleared hardware
SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.6.3 Power Modes
Mode WAIT Description effect interrupts cause device exit from Wait mode. SICSR register frozen. becomes inactive interrupt cannot used exit from Halt mode. Interrupt Event event Enable Event Control Flag AVDF AVDIE Exit from Wait Exit from Halt
interrupt mask register reset (RIM instruction).
18.104.22.168 Interrupts interrupt event generates interrupt corresponding Enable Control (AVDIE)
SYSTEM INTEGRITY MANAGEMENT (Cont'd) 7.6.4 Register Description SYSTEM INTEGRITY (SI) CONTROL/STATUS REGISTER (SICSR) Read/Write AVDF Voltage Detector flag This read-only cleared hardware. Reset Value: 0110 0xx0 (6xh) AVDIE set, interrupt request generated when AVDF set. Refer Figure Section 22.214.171.124 additional details. over threshold LOCKED LVDRF AVDF AVDIE under threshold Reserved, must kept cleared. Bits CR[1:0] Oscillator Frequency Adjustment bits These bits, well CR[9:2] bits RCCR register must written immediately after reset adjust oscillator frequency obtain accuracy Refer section page WDGRF Watchdog reset flag This indicates that last Reset generated Watchdog peripheral. hardware (watchdog reset) cleared software reading SICSR register) Reset ensure stable cleared state WDGRF flag when starts). Combined with LVDRF flag information, flag description given following table.
RESET Sources External RESET Watchdog LVDRF WDGRF
AVDIE Voltage Detector interrupt enable This cleared software. enables interrupt generated when AVDF flag set. pending interrupt information automatically cleared when software enters interrupt routine. interrupt disabled interrupt enabled Application notes LVDRF flag cleared when another RESET type occurs (external watchdog), LVDRF flag remains keep trace original failure. this case, watchdog reset detected software while external reset not.
LOCKED Locked Flag This cleared hardware. automatically when reaches operating frequency. locked locked LVDRF reset flag This indicates that last Reset generated block. hardware (LVD reset) cleared software reading). When disabled OPTION BYTE, LVDRF value undefined.
core interrupted different methods: Maskable hardware interrupts listed "interrupt mapping" table nonmaskable software interrupt (TRAP). Interrupt processing flowchart shown Figure maskable interrupts must enabled clearing order serviced. However, disabled interrupts latched processed when they enabled (see external interrupts subsection). Note: After reset, interrupts disabled. When interrupt serviced: Normal processing suspended current instruction execution. registers saved onto stack. register prevent additional interrupts. then loaded with interrupt vector interrupt service first instruction interrupt service routine fetched (refer Interrupt Mapping table vector addresses). interrupt service routine should finish with IRET instruction which causes contents saved registers recovered from stack. Note: consequence IRET instruction, cleared main program resumes. Priority Management default, servicing interrupt cannot interrupted because hardware entering interrupt routine. case when several interrupts simultaneously pending, hardware priority defines which will serviced first (see Interrupt Mapping table). Interrupts Power Mode interrupts allow processor leave WAIT power mode. Only external specifically mentioned interrupts allow processor leave HALT power mode (refer "Exit from HALT" column Interrupt Mapping table). MASKABLE SOFTWARE INTERRUPT This interrupt entered when TRAP instruction executed regardless state bit. serviced according flowchart Figure EXTERNAL INTERRUPTS External interrupt vectors loaded into register corresponding external interrupt occurred cleared. These interrupts allow processor leave HALT power mode. external interrupt polarity selected through miscellaneous register interrupt register available). external interrupt triggered edge will latched interrupt request automatically cleared upon entering interrupt service routine. Caution: type sensitivity defined Miscellaneous Interrupt register available) applies source. case NANDed source described ports section), level pin, configured input with interrupt, masks interrupt request even case risingedge sensitivity. PERIPHERAL INTERRUPTS Different peripheral interrupt flags status register able cause interrupt when they active both: register cleared. corresponding enable control register. these conditions false, interrupt latched thus remains pending. Clearing interrupt request done Writing corresponding status register Access status register while flag followed read write associated register. Note: clearing sequence resets internal latch. pending interrupt (that waiting being enabled) will therefore lost clear sequence executed.
INTERRUPTS (cont'd) Figure Interrupt Processing Flowchart
FROM RESET SET?
FETCH NEXT INSTRUCTION
STACK LOAD FROM INTERRUPT VECTOR
RESTORE FROM STACK THIS CLEARS DEFAULT
Table Interrupt Mapping
Source Block RESET TRAP LITE TIMER TIMER Reset Software Interrupt Interrupt External Interrupt External Interrupt External Interrupt External Interrupt LTCSR2 SCICR1/ SCICR2 SICSR PWMxCSR ATCSR ATCSR LTCSR LTCSR SPICSR ATCSR2 Lowest Priority yes2) yes2) Description Register Label AWUCSR Priority Order Exit from HALT Highest Priority yes1) Address Vector FFFEh-FFFFh FFFCh-FFFDh FFFAh-FFFBh FFF8h-FFF9h FFF6h-FFF7h FFF4h-FFF5h FFF2h-FFF3h FFF0h-FFF1h FFEEh-FFEFh FFECh-FFEDh FFEAh-FFEBh FFE8h-FFE9h FFE6h-FFE7h FFE4h-FFE5h FFE2h-FFE3h FFE0h-FFE1h
LITE TIMER LITE TIMER RTC2 interrupt LINSCI TIMER LINSCI Interrupt interrupt TIMER Output Compare Interrupt Input Capture Interrupt TIMER Overflow Interrupt LITE TIMER Input Capture Interrupt LITE TIMER RTC1 Interrupt Peripheral Interrupts TIMER Overflow Interrupt
Note This interrupt exits from "Auto Wake-up from Halt" mode only. Note These interrupts exit from "ACTIVE-HALT" mode only.
INTERRUPTS (Cont'd) EXTERNAL INTERRUPT CONTROL REGISTER (EICR) Read/Write Reset Value: 0000 0000 (00h)
IS31 IS30 IS21 IS20 IS11 IS10 IS01 IS00
EXTERNAL INTERRUPT SELECTION REGISTER (EISR) Read/Write Reset Value: 0000 0000 (00h)
ei31 ei30 ei21 ei20 ei11 ei10 ei01 ei00
IS3[1:0] sensitivity These bits define interrupt sensitivity (Port according Table IS2[1:0] sensitivity These bits define interrupt sensitivity (Port according Table IS1[1:0] sensitivity These bits define interrupt sensitivity (Port according Table IS0[1:0] sensitivity These bits define interrupt sensitivity (Port according Table Note: These bits written only when register set. Table Interrupt Sensitivity Bits
ei3[1:0] selection These bits written software. They select Port used external interrupt according table below. External Interrupt selection
ei31 ei30 interrupt
Reset State ei2[1:0] selection These bits written software. They select Port used external interrupt according table below. External Interrupt selection
ei21 ei20 interrupt
External Interrupt Sensitivity Falling edge level Rising edge only Falling edge only Rising falling edge
INTERRUPTS (Cont'd) ei1[1:0] selection These bits written software. They select Port used external interrupt according table below. External Interrupt selection
ei11 ei10 interrupt*
Port used external interrupt according table below. External Interrupt selection
ei01 ei00 Interrupt*
Reset State Bits Reserved.
Reset State ei0[1:0] selection These bits written software. They select
POWER SAVING MODES
INTRODUCTION give large measure flexibility application terms power consumption, five main power saving modes implemented (see Figure 21): Slow Wait (and Slow-Wait) Active Halt Auto Wake From Halt (AWUFH) Halt After RESET normal operating mode selected default (RUN mode). This mode drives device (CPU embedded peripherals) means master clock which based main oscillator frequency divided multiplied (fOSC2). From mode, different power saving modes selected setting relevant register bits calling specific software instruction whose action depends oscillator status. Figure Power Saving Mode Transitions
High SLOW WAIT SLOW WAIT ACTIVE HALT AUTO WAKE FROM HALT HALT POWER CONSUMPTION
SLOW MODE This mode targets: reduce power consumption decreasing internal clock device, adapt internal clock frequency (fCPU) available supply voltage. SLOW mode controlled MCCSR register which enables disables Slow mode. this mode, oscillator frequency divided peripherals clocked thislower frequency. Note: SLOW-WAIT mode activated when entering WAIT mode while device already SLOW mode. Figure SLOW Mode Clock Transition
fOSC/32 fCPU fOSC
NORMAL MODE REQUEST
POWER SAVING MODES (Cont'd) WAIT MODE WAIT mode places power consumption mode stopping CPU. This power saving mode selected calling `WFI' instruction. peripherals remain active. During WAIT mode, register cleared, enable interrupts. other registers memory remain unchanged. remains WAIT mode until interrupt RESET occurs, whereupon Program Counter branches starting address interrupt Reset service routine. will remain WAIT mode until Reset Interrupt occurs, causing wake Refer Figure Figure WAIT Mode Flow-chart
RESET INTERRUPT OSCILLATOR PERIPHERALS
4096 CLOCK CYCLE DELAY
FETCH RESET VECTOR SERVICE INTERRUPT
Note: Before servicing interrupt, register pushed stack. register during interrupt routine cleared when register popped.
POWER SAVING MODES (Cont'd) HALT MODE HALT mode lowest power consumption mode MCU. entered executing `HALT' instruction when ACTIVE-HALT disabled (see section page more details) when AWUEN AWUCSR register cleared. exit HALT mode reception either specific interrupt (see Table "Interrupt Mapping," page RESET. When exiting HALT mode means RESET interrupt, oscillator immediately turned cycle delay used stabilize oscillator. After start delay, resumes operation servicing interrupt fetching reset vector which woke (see Figure 25). When entering HALT mode, register forced enable interrupts. Therefore, interrupt pending, wakes immediately. HALT mode, main oscillator turned causing internal processing stopped, including operation on-chip peripherals. peripherals clocked except ones which their clock supply from another clock generator (such external auxiliary oscillator). compatibility Watchdog operation with HALT mode configured "WDGHALT" option option byte. HALT instruction when executed while Watchdog system enabled, generate Watchdog RESET (see section 15.1 page more details). Figure HALT Timing Overview
HALT 4096 CYCLE DELAY RESET INTERRUPT FETCH VECTOR
Figure HALT Mode Flow-chart
HALT INSTRUCTION (Active Halt disabled) (AWUCSR.AWUEN=0) ENABLE WDGHALT WATCHDOG RESET OSCILLATOR PERIPHERALS WATCHDOG DISABLE
RESET INTERRUPT OSCILLATOR PERIPHERALS
4096 CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS
FETCH RESET VECTOR SERVICE INTERRUPT
HALT INSTRUCTION [Active Halt disabled]
Notes: WDGHALT option bit. option byte section more details. Peripheral clocked with external clock source still active. Only some specific interrupts exit from HALT mode (such external interrupt). Refer Table "Interrupt Mapping," page more details. Before servicing interrupt, register pushed stack. register during interrupt routine cleared when register popped.
POWER SAVING MODES (Cont'd) 126.96.36.199 Halt Mode Recommendations Make sure that external event available wake microcontroller from Halt mode. When using external interrupt wake microcontroller, reinitialize corresponding "Input Pull-up with Interrupt" "floating interrupt" before executing HALT instruction. main reason this that wrongly configured external interference unforeseen logical condition. same reason, reinitialize level sensitiveness each external interrupt precautionary measure. opcode HALT instruction 0x8E. avoid unexpected HALT instruction program counter failure, advised clear occurrences data value 0x8E from memory. example, avoid defining constant program memory with value 0x8E. HALT instruction clears interrupt mask register allow interrupts, user choose clear pending interrupt bits before executing HALT instruction. This avoids entering other peripheral interrupt routines after executing external interrupt routine corresponding wake-up event (reset external interrupt). ACTIVE-HALT MODE ACTIVE-HALT mode lowest power consumption mode with real time clock (RTC) available. entered executing `HALT' instruction. decision enter either ACTIVE-HALT HALT mode given LTCSR/ATCSR register status shown following table:.
ATCSR LTCSR1 ATCSR ATCSR OVFIE1 TB1IE Meaning ACTIVE-HALT mode disabled ACTIVE-HALT mode enabled
exit ACTIVE-HALT mode reception specific interrupt (see Table "Interrupt Mapping," page RESET. When exiting ACTIVE-HALT mode means RESET, cycle delay occurs. After start delay, resumes operation fetching reset vector which woke (see Figure 27). When exiting ACTIVE-HALT mode means interrupt, immediately resumes operation servicing interrupt vector which woke (see Figure 27). When entering ACTIVE-HALT mode, register cleared enable interrupts. Therefore, interrupt pending, wakes immediately (see Note ACTIVE-HALT mode, only main oscillator selected timer counter (LT/AT) running keep wake-up time base. other peripherals clocked except those which their clock supply from another clock generator (such external auxiliary oscillator). Note: soon ACTIVE-HALT enabled, executing HALT instruction while Watchdog active does generate RESET. This means that device cannot spend more than defined delay this power saving mode.
POWER SAVING MODES (Cont'd) Figure ACTIVE-HALT Timing Overview
ACTIVE 4096 HALT CYCLE DELAY RESET INTERRUPT
AUTO WAKE FROM HALT MODE Auto Wake From Halt (AWUFH) mode similar Halt mode with additional internal oscillator wake-up. Compared ACTIVEHALT mode, AWUFH lower power consumption (the main clock kept running), there accurate realtime clock available. entered executing HALT instruction when AWUEN AWUCSR register been set. Figure AWUFH Mode Block Diagram
HALT INSTRUCTION [Active Halt Enabled]
Figure ACTIVE-HALT Mode Flow-chart
HALT INSTRUCTION (Active Halt enabled) (AWUCSR.AWUEN=0) OSCILLATOR PERIPHERALS
Oscillator 32-KHz Oscillator fAWU_RC
Auto-Reload Timer Input Capture
OSCILLATOR PERIPHERALS 4096 CLOCK CYCLE DELAY OSCILLATOR PERIPHERALS
AWUFH interrupt (ei0 source)
FETCH RESET VECTOR SERVICE INTERRUPT
Notes: This delay occurs only exits ACTIVEHALT mode means RESET. Peripherals clocked with external clock source still active. Only RTC1 interrupt some specific interrupts exit from ACTIVE-HALT mode. Refer Table "Interrupt Mapping," page more details. Before servicing interrupt, register pushed stack. register during interrupt routine cleared when register popped.
soon HALT mode entered, AWUEN been AWUCSR register, oscillator provides clock signal (fAWU_RC). frequency divided fixed divider programmable prescaler controlled AWUPR register. output this prescaler provides delay time. When delay elapsed AWUF flag hardware interrupt wakes-up from Halt mode. same time main oscillator immediately turned cycle delay used stabilize After this start-up delay, resumes operation servicing AWUFH interrupt. flag associated interrupt cleared software reading AWUCSR register. compensate frequency dispersion oscillator, calibrated measuring clock frequency fAWU_RC then calculating right prescaler value. Measurement mode enabled setting AWUM AWUCSR register mode. This connects fAWU_RC input capture 12-bit Auto-Relad timer, allowing fAWU_RC measured using main oscillator clock reference timebase.
POWER SAVING MODES (Cont'd) Similarities with Halt mode following AWUFH mode behaviour same normal Halt mode: exit AWUFH mode means interrupt with exit from Halt capability reset (see Section HALT MODE). When entering AWUFH mode, register forced enable interrupts. Therefore, interrupt pending, wakes immediately. AWUFH mode, main oscillator turned causing internal processing stopped, including operation on-chip peripherals. None peripherals clocked except those which their clock supply from another clock generator (such external auxiliary oscillator like oscillator). compatibility Watchdog operation with AWUFH mode configured WDGHALT option option byte. Depending this setting, HALT instruction when executed while Watchdog system enabled, generate Watchdog RESET.
Figure AWUF Halt Timing Diagram tAWU MODE
POWER SAVING MODES (Cont'd) Figure AWUFH Mode Flow-chart
HALT INSTRUCTION (Active-Halt disabled) (AWUCSR.AWUEN=1) ENABLE WDGHALT WATCHDOG RESET MAIN PERIPHERALS I[1:0] BITS WATCHDOG DISABLE
Notes: WDGHALT option bit. option byte section more details. Peripheral clocked with external clock source still active. Only AWUFH interrupt some specific interrupts exit from HALT mode (such external interrupt). Refer Table "Interrupt Mapping," page more details. Before servicing interrupt, register pushed stack. I[1:0] bits register current software priority level interrupt routine recovered when register popped.
RESET INTERRUPT MAIN PERIPHERALS I[1:0] BITS CLOCK CYCLE DELAY MAIN PERIPHERALS I[1:0] BITS FETCH RESET VECTOR SERVICE INTERRUPT
POWER SAVING MODES (Cont'd) 188.8.131.52 Register Description AWUFH CONTROL/STATUS REGISTER (AWUCSR) Read/Write Reset Value: 0000 0000 (00h)
AWUF AWUM AWUEN
AWUFH PRESCALER REGISTER (AWUPR) Read/Write Reset Value: 1111 1111 (FFh)
Bits Reserved. AWUF Auto Wake Flag This hardware when module generates interrupt cleared software reading AWUCSR. Writing this does change value. interrupt occurred interrupt occurred AWUM Auto Wake Measurement This enables oscillator connects output input capture 12-bit auto-reload timer. This allows timer used measure oscillator dispersion then compensate this dispersion providing right value AWUPR register. Measurement disabled Measurement enabled AWUEN Auto Wake From Halt Enabled This enables Auto Wake From Halt feature: once HALT mode entered, AWUFH wakes microcontroller after time delay dependent prescaler value. cleared software. AWUFH (Auto Wake From Halt) mode disabled AWUFH (Auto Wake From Halt) mode enabled Table Register Reset Values
Address (Hex.) 0049h 004Ah Register Label
Bits 7:0= AWUPR[7:0] Auto Wake Prescaler These bits define AWUPR Dividing factor explained below
AWUPR[7:0] Dividing factor Forbidden
mode, period that stays Halt Mode (tAWU Figure page defined
AWUPR RCSTRT AWURC
This prescaler register programmed modify time that stays Halt mode before waking automatically. Note: written AWUPR, depending product, interrupt generated immediately after HALT instruction, AWUPR remains unchanged.
AWUPR AWUPR7 AWUPR6 AWUPR5 AWUPR4 AWUPR3 AWUPR2 AWUPR1 AWUPR0 Reset Value AWUCSR AWUF AWUM AWUEN Reset Value
10.1 INTRODUCTION ports allow data transfer. port contain pins. Each programmed independently either digital input digital output. addition, specific pins have several other functions. These functions include external interrupt, alternate signal input/output onchip peripherals analog input. 10.2 FUNCTIONAL DESCRIPTION Data Register (DR) Data Direction Register (DDR) always associated with each port. Option Register (OR), which allows input/output options, implemented. following description takes into account register. Refer Port Configuration table device specific information. programmed using corresponding bits DDR, registers: corresponding port. Figure shows generic block diagram. 10.2.1 Input Modes Clearing DDRx selects input mode. this mode, reading returns digital value from that pin. available, different input modes configured software: floating pull-up. Refer Port Implementation section configuration. Notes: Writing modifies latch value does change state input pin. read/modify/write instructions (BSET/BRES) modify register. External Interrupt Function Depending device, setting while input mode configure input with interrupt. this configuration, signal edge level input generates interrupt request corresponding interrupt vector (eix). Falling rising edge sensitivity programmed independently each interrupt vector. External Interrupt Control Register (EICR) Miscellaneous Register controls this sensitivity, depending device. device have external interrupts. Several pins tied external interrupt vector. Refer Description which ports have external interrupts. several interrupt pins same interrupt vector selected simultaneously, they logically combined. this reason interrupt pins tied low, mask others. External interrupts hardware interrupts. Fetching corresponding interrupt vector automatically clears request latch. Modifying sensitivity bits will clear pending interrupts. 10.2.2 Output Modes Setting DDRx selects output mode. Writing bits applies digital value through latch. Reading bits returns previously stored value. available, different output modes selected software: push-pull opendrain. Refer Port Implementation section configuration. Value Output Status
Push-Pull Open-Drain Floating
10.2.3 Alternate Functions Many ST7s I/Os have more alternate functions. These include output signals from, input signals on-chip peripherals. Device Description table describes which peripheral signals input/output which ports. signal coming from on-chip peripheral output I/O. this, enable on-chip peripheral output (enable peripheral's control register). peripheral configures output takes priority over standard programming. I/O's state readable addressing corresponding data register. Configuring floating enables alternate function input. recommended configure pull-up this will increase current consumption. Before using alternate input, configure without interrupt. Otherwise spurious interrupts occur. Configure input floating on-chip peripheral signal which input output. Caution: I/Os which configured both analog digital alternate function need special attention. user must control peripherals that signals arrive same time same pin. external clock used, only clock alternate function should employed that other alternate function.
PORTS (Cont'd) Figure Port General Block Diagram
REGISTER ACCESS ALTERNATE OUTPUT
From on-chip peripheral
P-BUFFER (see table below) PULL-UP (see table below)
N-BUFFER CMOS SCHMITT TRIGGER
DIODES (see table below) ANALOG INPUT
Combinational Logic on-chip peripheral
EXTERNAL INTERRUPT REQUEST (eix)
FROM OTHER BITS Note: Refer Port Configuration
table device specific information.
Table Port Mode Options
Configuration Mode Input Floating with/without Interrupt Pull-up with/without Interrupt Push-pull Open Drain (logic level) True Open Drain Pull-Up P-Buffer Diodes
Legend: implemented implemented activated implemented activated Note diode implemented true open drain pads. local protection between
implemented protect device against positive stress. Note further details port configuration, please refer Table Table page
PORTS (Cont'd) Table Configurations
NOTE PULL-UP CONDITION REGISTER ACCESS
FROM OTHER PINS INTERRUPT COMBINATIONAL POLARITY LOGIC SELECTION CONDITION
ALTERNATE INPUT on-chip peripheral EXTERNAL INTERRUPT SOURCE (eix)
NOTE REGISTER ACCESS
ALTERNATE OUTPUT From on-chip peripheral
Notes: When port input configuration associated alternate function enabled output, reading register will read alternate function output status. When port output configuration associated alternate function enabled input, alternate function reads status given register content. true open drain, these elements implemented.
PORTS (Cont'd) Analog alternate function Configure floating input input. analog multiplexer (controlled registers) switches analog voltage present selected common analog rail, connected input. Analog Recommendations change voltage level loading while conversion progress. have clocking pins located close selected analog pin. WARNING: analog input voltage level must within limits stated absolute maximum ratings. 10.3 PORT IMPLEMENTATION hardware implementation each port depends settings registers specific port features such input open drain. Switching these ports from state another should done sequence that prevents unwanted side effects. Recommended safe transitions illustrated Figure Other transitions potentially risky should avoided, since they present unwanted side-effects such spurious interrupt generation. Figure Interrupt Port State Transitions
INPUT floating/pull-up interrupt
10.4 UNUSED PINS Unused pins must connected fixed voltage levels. Refer Section 13.8. 10.5 POWER MODES
Mode WAIT HALT Description effect ports. External interrupts cause device exit from WAIT mode. effect ports. External interrupts cause device exit from HALT mode.
10.6 INTERRUPTS external interrupt event generates interrupt corresponding configuration selected with registers register cleared (RIM instruction).
Interrupt Event External interrupt selected external event Enable Event Control Flag DDRx Exit from Wait Exit from Halt
INPUT floating (reset state)
Related Documentation 970: Communication between EEPROM AN1045: implementation master AN1048: Software driver
PORTS (Cont'd) port register configurations summarised follows. Standard Ports PA7:0, PB6:0
MODE floating input pull-up input open drain output push-pull output
Interrupt Ports Ports where external interrupt capability selected using EISR register
MODE floating input pull-up interrupt input
Table Port Configuration (Standard ports)
floating floating pull-up pull-up
open drain open drain push-pull push-pull
Note: ports where external interrupt capability selected using EISR register, configuration will follows: Table Port Configuration (external interrupts)
Input with interrupt (DDR=0 EISR00)
floating floating pull-up pull-up
Table Port Register Reset Values
Address (Hex.) 0000h 0001h 0002h 0003h 0004h 0005h Register Label PADR Reset Value PADDR Reset Value PAOR Reset Value PBDR Reset Value PBDDR Reset Value PBOR Reset Value
11.1 WATCHDOG TIMER (WDG) 11.1.1 Introduction Watchdog timer used detect occurrence software fault, usually generated external interference unforeseen logical conditions, which causes application program abandon normal sequence. Watchdog circuit generates reset expiry programmed time period, unless program refreshes counter's contents before becomes cleared. 11.1.2 Main Features Programmable free-running downcounter increments 16000 cycles) Programmable reset Reset watchdog activated) when reaches zero Figure Watchdog Block Diagram
Optional reset HALT instruction (configurable option byte) Hardware Watchdog selectable option byte
11.1.3 Functional Description counter value stored register (bits T[6:0]), decremented every 16000 machine cycles, length timeout period programmed user increments. watchdog activated (the WDGA set) when 7-bit timer (bits T[6:0]) rolls over from becomes cleared), initiates reset cycle pulling reset typically 30µs.
WATCHDOG CONTROL REGISTER (CR) WDGA
CLOCK DIVIDER ÷16000
WATCHDOG TIMER (Cont'd) application program must write register regular intervals during normal operation prevent reset. This downcounter freerunning: counts down even watchdog disabled. value stored register must between (see Table .Watchdog Timing): WDGA (watchdog enabled) prevent generating immediate reset T[5:0] bits contain number increments which represents time delay before watchdog produces reset. Following reset, watchdog disabled. Once activated cannot disabled, except reset. used generate software reset (the WDGA cleared). watchdog activated, HALT instruction will generate Reset. Table 14.Watchdog Timing Notes: timing variation shown Table unknown status prescaler when writing register.
fCPU 8MHz Counter Code [ms] [ms]
11.1.4 Hardware Watchdog Option Hardware Watchdog selected option byte, watchdog always active WDGA used. Refer Option Byte description section 15.1 page 162. 184.108.40.206 Using Halt Mode with (WDGHALT option) Halt mode with Watchdog enabled option byte watchdog reset HALT instruction), recommended before executing HALT instruction refresh counter, avoid unexpected reset immediately after waking microcontroller.
WATCHDOG TIMER (Cont'd) 11.1.5 Interrupts None. 11.1.6 Register Description CONTROL REGISTER (CR) Read/Write Reset Value: 0111 1111 (7Fh)
T[6:0] 7-bit timer (MSB LSB). These bits contain decremented value. reset produced when rolls over from becomes cleared).
WDGA Activation bit. This software only cleared hardware after reset. When WDGA watchdog generate reset. Watchdog disabled Watchdog enabled Note: This used hardware watchdog option enabled option byte.
WATCHDOG TIMER (Cont'd) Table Watchdog Timer Register Reset Values
Address (Hex.) 002Eh Register Label WDGCR Reset Value WDGA
11.2 DUAL 12-BIT AUTORELOAD TIMER (AT3) 11.2.1 Introduction 12-bit Autoreload Timer used general-purpose timing functions. based free-running 12-bit upcounters with input capture register four output channels. There external pins: Four outputs ATIC/LTIC Input Capture function BREAK forcing break condition outputs 11.2.2 Main Features Single Timer Dual Timer mode with 12-bit upcounters (CNTR1/CNTR2) 12-bit autoreload registers (ATR1/ATR2) Maskable overflow interrupts Figure Single Timer Mode (ENCNTR2=0)
mode Generation four independent PWMx signals Dead time generation Half bridge driving mode with programmable dead time Frequency 2KHz-4MHz fCPU) Programmable duty-cycles Polarity control Programmable output modes Output Compare Mode Input Capture Mode 12-bit input capture register (ATICR) Triggered rising falling edges Maskable interrupt Long range input capture Break control Flexible Clock control
Edge Detection Circuit
12-bit Input Capture Output Compare Interrupt Dead Time Generator PWM2 Duty Cycle Generator PWM3 BPEN OVF1 Interrupt Break Function PWM0 PWM1
PWM0 Duty Cycle Generator 12-Bit Autoreload Register PWM1 Duty Cycle Generator Clock Control 12-Bit Upcounter
from Lite Timer
PWM3 Duty Cycle Generator fCPU
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) Figure Dual Timer Mode (ENCNTR2=1)
ATIC 12-bit Input Capture Output Compare Interrupt Dead Time Generator Break Function
Edge Detection Circuit
12-Bit Autoreload Register
PWM0 Duty Cycle Generator PWM1 Duty Cycle Generator OVF1 interrupt OVF2 interrupt
12-Bit Upcounter Clock Control 12-Bit Upcounter fCPU
PWM2 Duty Cycle Generator PWM3 Duty Cycle Generator
12-Bit Autoreload Register BPEN
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) 11.2.3 Functional Description 220.127.116.11 Mode This mode allows four Pulse Width Modulated signals generated PWMx output pins. Frequency four signals have same frequency (fPWM) have different frequencies. This selected ENCNTR2 which enables single timer dual timer mode (see Figure Figure 35). frequency controlled counter period register value. dual timer mode, PWM2 PWM3 generated with different frequency controlled CNTR2 ATR2. fPWM fCOUNTER (4096 ATR) Following above formula, fCOUNTER Mhz, maximum value fPWM (ATR register value 4094),the minimum value (ATR register value Duty Cycle duty cycle selected programming DCRx registers. These preload registers. DCRx values transferred Active duty cycle registers after overflow event corresponding transfer (TRANx bit) set. TRAN1 controls PWMx outputs driven counter TRAN2 controls PWMx outputs driven counter generation output compare done comparing these active DCRx values with counter. maximum available resolution PWMx duty cycle Resolution (4096 ATR) where equal With this maximum resolution, 100% duty cycle obtained changing polarity. reset, counter starts counting from When upcounter overflow occurs (OVF event), preloaded Duty cycle values transferred
active Duty Cycle registers PWMx signals high level. When upcounter matches active DCRx value PWMx signals level. obtain signal PWMx pin, contents corresponding active DCRx register must greater than contents register. maximum value 4094 because must lower than value which must 4095 this case. Polarity Inversion polarity bits used invert four output signals. inversion synchronized with counter overflow corresponding transfer ATCSR2 register (reset value). Figure Figure Polarity Inversion
inverter PWMx PWMx
TRANx ATCSR2 Register counter overflow
Data Flip Flop (DFF) applies polarity inversion when triggered counter overflow input. Output Control PWMx output signals enabled disabled using bits PWMCR register.
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) Figure Function
4095 DUTY CYCLE REGISTER (DCRx)
AUTO-RELOAD REGISTER (ATR)
WITH OE=1 OPx=0 WITH OE=1 OPx=1
Figure Signal from 100% Duty Cycle
fCOUNTER ATR= FFDh COUNTER PWMx OUTPUT WITH MOD00=1 OPx=0 FFDh FFEh FFFh FFDh FFEh FFFh FFDh FFEh
DCRx=000h DCRx=FFDh DCRx=FFEh
PWMx OUTPUT WITH MOD00=1 OPx=1
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) Dead Time Generation dead time inserted between PWM0 PWM1 using DTGR register. This required half-bridge driving where signals must overlapped. non-overlapping PWM0/ PWM1 signals generated through programmable dead time setting bit. Dead time value DT[6:0] Tcounter1 DTGR[7:0] buffered inside avoid deforming current cycle. DTGR effect will take place only after overflow. Figure Dead Time Generation Tcounter1
Notes: Dead time generated only when DTE=1 DT[6:0] DT[6:0]=0, output signals will their reset state. Half Bridge driving possible only polarities PWM0 PWM1 inverted, i.e. set. polarity inverted, overlapping PWM0/PWM1 signals will generated.
DT[6:0] Tcounter1 above example, when set: goes DCR0 match goes high ATR1+Tdt PWM1 goes high DCR0+Tdt goes match. With this programmable delay (Tdt), PWM0 PWM1 signals which generated overlapped.
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) Break Function break function used perform emergency shutdown application being driven signals. break function activated external BREAK (active low). order BREAK must previously enabled software setting BPEN BREAKCR register. When level detected BREAK pin, break function activated. this case, signals stopped. Software activate break function without using BREAK pin. When break function activated =1):
break pattern (PWM[3:0] bits BREAKCR) forced directly PWMx output pins (after inverter). 12-bit counter CNTR1 reset value, i.e. 00h. 12-bit counter CNTR2 reset value,i.e. 00h. ATR1, ATR2, Preload Active DCRx their reset values. PWMCR register reset. Counters stop counting. When break function deactivated after applying break goes from software): control outputs transferred port registers.
Figure Block Diagram Break Function
BREAK (Active Low)
BREAKCR Register BPEN PWM3 PWM2 PWM1 PWM0
PWM0 PWM1 PWM2
PWM0 PWM1 PWM2 PWM3 (Inverters) Note: BREAK value latched bit. When set: counter Reset value ATRx DCRx Reset value Mode Reset value
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) 18.104.22.168 Output Compare Mode this function, load 12-bit value Preload DCRxH DCRxL registers. When 12-bit upcounter (CNTR1) reaches value stored Active DCRxH DCRxL registers, CMPFx PWMxCSR register interrupt request generated CMPIE set. output compare function always performed CNTR1 both Single Timer mode Dual Timer mode, never CNTR2. difference that Single Timer mode counter compared with four registers,
Dual Timer mode, counter compared with DCR0 DCR1. Notes: output compare function only available DCRx values other than (reset value). Duty cycle registers buffered internally. writes Preload Duty Cycle Registers these values transferred Active Duty Cycle Registers after overflow event corresponding transfer (TRAN1 bit) set. Output compare done comparing these active DCRx values with counter.
Figure Block Diagram Output Compare Mode (single timer)
DCRx PRELOAD DUTY CYCLE REGx
(ATCSR2) TRAN1 (ATCSR)
ACTIVE DUTY CYCLE REGx CNTR1 COUNTER OUTPUT COMPARE CIRCUIT
CMPFx (PWMxCSR) CMPIE (ATCSR)
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) 22.214.171.124 Input Capture Mode 12-bit ATICR register used latch value 12-bit free running upcounter CNTR1 after rising falling edge detected ATIC pin. When input capture occurs, ATICR register contains value free running upcounter. interrupt generated ICIE set. reset Figure Block Diagram Input Capture Mode reading ATICRH/ATICRL register when set. ATICR read only register always contains free running upcounter value which corresponds most recent input capture. further input capture inhibited while set.
ATIC ATICR ATCSR
12-BIT INPUT CAPTURE REGISTER
fLTIMER timebase 8MHz) fCPU CNTR1 ATR1
12-BIT UPCOUNTER1 12-BIT AUTORELOAD REGISTER
Figure Input Capture timing diagram
ATIC INTERRUPT FLAG ATICR READ INTERRUPT
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) Long input capture Pulses that last between measured with accuracy fOSC 8MHz following conditions: 12-bit Timer clocked Lite Timer (RTC pulse: CK[1:0] ATCSR register) ATCSR2 register that LTIC used trigger Timer capture.
signal captured connected LTIC Input Capture registers LTICR, ATICRH ATICRL read This configuration allows cascade Lite Timer 12-bit Timer 20-bit input capture value. Refer Figure
Figure Long Range Input Capture Block Diagram
8-bit Input Capture Register
8-bit Timebase Counter1 LITE TIMER 12-Bit ARTIMER
12-bit AutoReload Register
12-bit Input Capture Register
Notes: Since input capture flags (ICF) both timers (AT3 Timer Timer) when signal transition occurs, software must mask interrupt clearing corresponding ICIE before setting bit. changes (from from spurious transition might occur input capture signal because different values LTIC ATIC. avoid this situation, recommended follows: First, reset both ICIE bits. Then bit. Reset both bits.
then ICIE desired interrupt. compute pulse length with long input capture feature. both timers used, computing pulse length straight-forward. procedure follows: first input capture rising edge pulse, assume that values registers follows: LTICR ATICRH ATH1 ATICRL ATL1 Hence ATICR1 [11:0] ATH1 ATL1 Refer Figure page
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) second input capture falling edge pulse, assume that values registers follows: LTICR ATICRH ATH2
ATICRL ATL2 Hence ATICR2 [11:0] ATH2 ATL2 pulse width between first capture second capture will decimal 0.004ms decimal (ATICR2 ATICR1
Figure Long Range Input Capture Timing Diagram
ATICR ATICRH[3:0] ATICRL[7:0]
11.2.4 Power Modes Mode SLOW WAIT ACTIVEHALT HALT Description input frequency divided effect timer timer halted except CK0=1, CK1=0 OVFIE=1 timer halted.
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) 11.2.5 Interrupts
Interrupt Event Enable Exit Event Control from Flag WAIT Exit Exit from from ACTIVE HALT -HALT Yes2)
Overflow OVF1 OVIE1 Event ICIE Event Event CMPFx CMPIE
Note events connected same interrupt vector. event mapped separate vector (see Interrupts chapter). They generate interrupt enable
ATCSR register interrupt mask register reset (RIM instruction). Note Only CK0=1 CK1=0 (fCOUNTER
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) 11.2.6 Register Description TIMER CONTROL STATUS REGISTER (ATCSR) Read Write Reset Value: 0x00 0000 (x0h)
ICIE OVF1 OVFIE1 CMPIE
Overflow interrupt disabled. Overflow interrupt enabled.
CMPIE Compare Interrupt Enable. This read/write software cleared hardware after reset. used mask interrupt generated when CMPFx set. Output compare interrupt disabled. Output Compare interrupt enabled.
Reserved. COUNTER REGISTER HIGH (CNTR1H) Read only Reset Value: 0000 0000 (000h)
CNTR1_ CNTR1_ CNTR1_ CNTR1_
Input Capture Flag. This hardware cleared software reading ATICR register read access ATICRH ATICRL will clear this flag). Writing this does change value. input capture input capture occurred
ICIE Interrupt Enable. This cleared software. Input capture interrupt disabled Input capture interrupt enabled
COUNTER REGISTER (CNTR1L) Read only Reset Value: 0000 0000 (000h)
Bits CK[1:0] Counter Clock Selection. These bits cleared software cleared hardware after reset. They select clock frequency counter.
Counter Clock Selection fLTIMER timebase MHz) fCPU
CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_ CNTR1_
Bits 15:12 Reserved. Bits 11:0 CNTR1[11:0] Counter Value. This 12-bit register read software cleared hardware after reset. counter CNTR1 incremented continuously soon counter clock selected. obtain 12-bit value, software should read counter value consecutive read operations. CNTR1H register incremented between reads, order accurate when fTIMER=fCPU, software should take this into account when CNTR1L CNTR1H read. CNTR1L close highest value, CNTR1H could incremented before read. When counter overflow occurs, counter restarts from value specified ATR1 register.
OVF1 Overflow Flag. This hardware cleared software reading TCSR register. indicates transition counter1 CNTR1 from ATR1 value. counter overflow occurred Counter overflow occurred
OVFIE1 Overflow Interrupt Enable. This read/write software cleared hardware after reset.
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) AUTORELOAD REGISTER (ATR1H) Read Write Reset Value: 0000 0000 (00h)
ATR11 ATR10 ATR9 ATR8 CMPFx
PWMx CONTROL STATUS REGISTER (PWMxCSR) Read Write Reset Value: 0000 0000 (00h)
AUTORELOAD REGISTER (ATR1L) Read Write Reset Value: 0000 0000 (00h)
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
Bits 7:2= Reserved, must kept cleared. PWMx Output Polarity. This read/write software cleared hardware after reset. This selects polarity signal. signal inverted. signal inverted. CMPFx PWMx Compare Flag. This hardware cleared software reading PWMxCSR register. indicates that upcounter value matches Active DCRx register value. Upcounter value does match DCRx value. Upcounter value matches DCRx value.
Bits 11:0 ATR1[11:0] Autoreload Register This 12-bit register which written software. ATR1 register value automatically loaded into upcounter CNTR1 when overflow occurs. register value used frequency.
OUTPUT CONTROL REGISTER (PWMCR) Read/Write Reset Value: 0000 0000 (00h)
BREAK CONTROL REGISTER (BREAKCR) Read/Write Reset Value: 0000 0000 (00h)
BPEN PWM3 PWM2 PWM1
Bits OE[3:0] PWMx output enable. These bits cleared software cleared hardware after reset. mode disabled. PWMx Output Alternate Function disabled (I/O free general purpose I/O) mode enabled
Bits Reserved. Forced hardware Break Active. This read/write software, cleared hardware after reset hardware when BREAK low. activates/deactivates Break function. Break active Break active
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) BPEN Break Enable. This read/write software cleared hardware after Reset. Break disabled Break enabled PWM[3:0] Break Pattern. These bits read/write software cleared hardware after reset. They used force four PWMx output signals into stable state when Break function active.
INPUT CAPTURE REGISTER HIGH (ATICRH) Read only Reset Value: 0000 0000 (00h)
ICR11 ICR10 ICR9 ICR8
INPUT CAPTURE REGISTER (ATICRL) Read only Reset Value: 0000 0000 (00h)
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
PWMx DUTY CYCLE REGISTER HIGH (DCRxH) Read Write Reset Value: 0000 0000 (00h)
Bits 15:12 Reserved.
DCR11 DCR10 DCR9 DCR8
PWMx DUTY CYCLE REGISTER (DCRxL) Read Write Reset Value: 0000 0000 (00h)
DCR7 DCR6 DCR5 DCR4 DCR3 DCR2 DCR1 DCR0
Bits 11:0 ICR[11:0] Input Capture Data. This 12-bit register which readable software cleared hardware after reset. ATICR register contains captured value 12-bit CNTR1 register when rising falling edge occurs ATIC LTIC (depending ICS). Capture will only performed when flag cleared. TIMER CONTROL REGISTER2 (ATCSR2) Read/Write Reset Value: 0000 0011 (03h)
Bits 15:12 Reserved. Bits 11:0 DCRx[11:0] PWMx Duty Cycle Value This 12-bit value written software. defines duty cycle corresponding output signal (see Figure 37). mode (OEx=1 PWMCR register) DCR[11:0] bits define duty cycle PWMx output signal (see Figure 37). Output Compare mode, they define value compared with 12-bit upcounter value.
ENCNT TRAN2 TRAN1
Bits Reserved. Forced hardware Input Capture Shorted This read/write software. allows ATtimer CNTR1 LTIC long input capture. ATIC CNTR1 input capture LTIC CNTR1 input capture
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) OVFIE2 Overflow interrupt enable This read/write software controls overflow interrupt counter2. Overflow interrupt disabled. Overflow interrupt enabled. OVF2 Overflow Flag. This hardware cleared software reading ATCSR2 register. indicates transition counter2 from FFFh ATR2 value. counter overflow occurred Counter overflow occurred ENCNTR2 Enable counter2 This read/write software switches second counter CNTR2. this set, PWM2 PWM3 will generated using CNTR2. CNTR2 stopped. CNTR2 starts running. TRAN2 Transfer enable2 This read/write software, cleared hardware after each completed transfer hardware after reset. controls transfers CNTR2. allows value Preload DCRx registers transferred Active DCRx registers after next overflow event. bits transferred shadow bits same way. (Only DCR2/DCR3 controlled with this bit) TRAN1 Transfer enable This read/write software, cleared hardware after each completed transfer hardware after reset. controls transfers CNTR1. allows value Preload DCRx registers transferred Active DCRx registers after next overflow event. bits transferred shadow bits same way.
AUTORELOAD REGISTER2 (ATR2H) Read Write Reset Value: 0000 0000 (00h)
ATR11 ATR10 ATR9 ATR8
AUTORELOAD REGISTER (ATR2L) Read Write Reset Value: 0000 0000 (00h)
ATR7 ATR6 ATR5 ATR4 ATR3 ATR2 ATR1 ATR0
Bits 11:0 ATR2[11:0] Autoreload Register This 12-bit register which written software. ATR2 register value automatically loaded into upcounter CNTR2 when overflow CNTR2 occurs. register value used PWM2/PWM3 frequency when ENCNTR2 set. DEAD TIME GENERATOR REGISTER (DTGR) Read/Write Reset Value: 0000 0000 (00h)
Bits Dead Time Enable This read/write software. enables dead time generation PWM0/PWM1. Dead time insertion. Dead time insertion enabled. DT[6:0] Dead Time Value These bits read/write software. They define dead time inserted between PWM0/PWM1. Dead time calculated follows: Dead Time DT[6:0] Tcounter1
DUAL 12-BIT AUTORELOAD TIMER (Cont'd) Table Register Reset Values
Address (Hex.) Register Label ATCSR Reset Value CNTR1H Reset Value ICIE OVF1 OVFIE1 CMPIE
CNTR1_11 CNTR1_10 CNTR1_9 CNTR1_8 CNTR1_2 CNTR1_1 CNTR1_0 ATR10 ATR2 DCR10 DCR2 DCR10 DCR2 DCR10 DCR2 DCR10 DCR2 ICR10 ICR2 ATR9 ATR1 DCR9 DCR1 DCR9 DCR1 DCR9 DCR1 DCR9 DCR1 ICR9 ICR1 ATR8 ATR0 CMPF0 CMPF1 CMPF2 CMPF3 DCR8 DCR0 DCR8 DCR0 DCR8 DCR0 DCR8 DCR0 ICR8 ICR0
CNTR1L CNTR1_7 CNTR1_6 CNTR1_5 CNTR1_4 CNTR1_3 Reset Value ATR1H Reset Value ATR1L Reset Value PWMCR Reset Value PWM0CSR Reset Value PWM1CSR Reset Value PWM2CSR Reset Value PWM3CSR Reset Value DCR0H Reset Value DCR0L Reset Value DCR1H Reset Value DCR1L Reset Value DCR2H Reset Value DCR2L Reset Value DCR3H Reset Value DCR3L Reset Value ATICRH Reset Value ATICRL Reset Value ATR7 DCR7 DCR7 DCR7 DCR7 ICR7 ATR6 DCR6 DCR6 DCR6 DCR6 ICR6 ATR5 DCR5 DCR5 DCR5 DCR5 ICR5 ATR4 DCR4 DCR4 DCR4 DCR4 ICR4 ATR11 ATR3 DCR11 DCR3 DCR11 DCR3 DCR11 DCR3 DCR11 DCR3 ICR11 ICR3
Register Label ATCSR2 Reset Value BREAKCR Reset Value ATR2H Reset Value ATR2L Reset Value DTGR Reset Value
OVFIE2 BPEN ATR4
OVF2 PWM3 ATR11 ATR3
ENCNTR2 PWM2 ATR10 ATR2
TRAN2 PWM1 ATR9 ATR1
TRAN1 PWM0 ATR8 ATR0
11.3 LITE TIMER (LT2) 11.3.1 Introduction Lite Timer used general-purpose timing functions. based free-running 8bit upcounters 8-bit input capture register. 11.3.2 Main Features Realtime Clock (RTC) 8-bit upcounter timebase period fOSC) Figure Lite Timer Block Diagram
fOSC/32 LTCNTR 8-bit TIMEBASE COUNTER LTCSR2
8-bit upcounter with autoreload programmable timebase period from 1.024ms increments fOSC) Maskable timebase interrupts Input Capture 8-bit input capture register (LTICR) Maskable interrupt with wakeup from Halt Mode capability
LTTB2 Interrupt request
LTARR 8-bit AUTORELOAD REGISTER fLTIMER 12-bit TImer
8-bit TIMEBASE COUNTER fLTIMER
Timebase 8MHz fOSC)
LTICR LTIC 8-bit INPUT CAPTURE REGISTER LTCSR1
LTTB1 INTERRUPT REQUEST LTIC INTERRUPT REQUEST
LITE TIMER (Cont'd) 11.3.3 Functional Description 126.96.36.199 Timebase Counter 8-bit value Counter cannot read written software. After reset, starts incrementing from frequency fOSC/32. overflow event occurs when counter rolls over from 00h. fOSC MHz, then time period between counter overflow events This period doubled setting LTCSR1 register. When Counter overflows, TB1F hardware interrupt request generated TB1IE set. TB1F cleared software reading LTCSR1 register. 188.8.131.52 Timebase Counter Counter 8-bit autoreload upcounter. read accessing LTCNTR register. After reset, increments frequency fOSC/32 starting from value stored LTARR register. counter overflow event occurs when counter rolls over from Figure Input Capture Timing Diagram.
LTARR reload value. Software write value anytime LTARR register, this value will automatically loaded counter when next overflow occurs. When Counter overflows, TB2F LTCSR2 register hardware interrupt request generated TB2IE set. TB2F cleared software reading LTCSR2 register. 184.108.40.206 Input Capture 8-bit input capture register used latch free-running upcounter (Counter after rising falling edge detected LTIC pin. When input capture occurs, LTICR register contains value Counter interrupt generated ICIE set. cleared reading LTICR register. LTICR read-only register always contains data from last input capture. Input capture inhibited set.
CLEARED READING LTIC REGISTER
LTIC FLAG LTICR REGISTER
LITE TIMER (Cont'd) 11.3.4 Power Modes Description effect Lite timer SLOW (this peripheral driven directly fOSC/32) WAIT effect Lite timer ACTIVE-HALT effect Lite timer HALT Lite timer stops counting 11.3.5 Interrupts
Interrupt Event Enable Event Control Flag TB1IE TB2IE ICIE Exit from Wait Exit from Active Halt Exit from Halt
11.3.6 Register Description LITE TIMER CONTROL/STATUS REGISTER (LTCSR2) Read Write Reset Value: 0x00 0000 (x0h)
Bits Reserved, must kept cleared. TB2IE Timebase Interrupt enable. This cleared software. Timebase (TB2) interrupt disabled Timebase (TB2) interrupt enabled TB2F Timebase Interrupt Flag. This hardware cleared software reading LTCSR2 register. Writing this effect. Counter overflow Counter overflow occurred LITE TIMER AUTORELOAD (LTARR) Read Write Reset Value: 0000 0000 (00h)
Timebase TB1F Event Timebase TB2F Event Event
Note: TBxF interrupt events connected separate interrupt vectors (see Interrupts chapter). They generate interrupt enable LTCSR1 LTCSR2 register interrupt mask register reset (RIM instruction).
Bits AR[7:0] Counter Reload Value. These bits register read/write software. LTARR value automatically loaded into Counter (LTCNTR) when overflow occurs.
LITE TIMER (Cont'd) LITE TIMER COUNTER (LTCNTR) Read only Reset Value: 0000 0000 (00h)
CNT7 CNT7 CNT7 CNT7 CNT3 CNT2 CNT1 CNT0
Timebase period selection. This cleared software. Timebase period tOSC 8000 (1ms MHz) Timebase period tOSC 16000 (2ms MHz) TB1IE Timebase Interrupt enable. This cleared software. Timebase (TB1) interrupt disabled Timebase (TB1) interrupt enabled TB1F Timebase Interrupt Flag. This hardware cleared software reading LTCSR register. Writing this effect. counter overflow counter overflow occurred Bits Reserved
Bits CNT[7:0] Counter Reload Value. This register read software. LTARR value automatically loaded into Counter (LTCNTR) when overflow occurs. LITE TIMER CONTROL/STATUS REGISTER (LTCSR1) Read Write Reset Value: 0x00 00x0 (xxh)
ICIE TB1IE TB1F
ICIE Interrupt Enable. This cleared software. Input Capture (IC) interrupt disabled Input Capture (IC) interrupt enabled Input Capture Flag. This hardware cleared software reading LTICR register. Writing this does change value. input capture input capture occurred Note: After reset, software must initialise reading LTICR register
LITE TIMER INPUT CAPTURE REGISTER (LTICR) Read only Reset Value: 0000 0000 (00h)
ICR7 ICR6 ICR5 ICR4 ICR3 ICR2 ICR1 ICR0
Bits ICR[7:0] Input Capture Value These bits read software cleared hardware after reset. LTCSR cleared, value 8-bit up-counter will captured when rising falling edge occurs LTIC pin.
LITE TIMER (Cont'd) Table Lite Timer Register Reset Values
Address (Hex.) Register Label LTCSR2 Reset Value LTARR Reset Value LTCNTR Reset Value LTCSR1 Reset Value LTICR Reset Value TB2IE CNT1 ICR1 TB2F CNT0 ICR0
CNT7 ICIE ICR7
CNT4 TB1IE ICR4
CNT3 TB1F ICR3
ON-CHIP PERIPHERALS (cont'd) 11.4 SERIAL PERIPHERAL INTERFACE (SPI) 11.4.1 Introduction Serial Peripheral Interface (SPI) allows fullduplex, synchronous, serial communication with external devices. system consist master more slaves system which devices either masters slaves. 11.4.2 Main Features Full duplex synchronous transfers three lines) Simplex synchronous transfers lines) Master slave operation master mode frequencies (fCPU/4 max.) fCPU/2 max. slave mode frequency (see note) Management software hardware Programmable clock polarity phase transfer interrupt flag Write collision, Master Mode Fault Overrun flags Note: slave mode, continuous transmission possible maximum frequency software overhead clearing status flags initiate next transmission sequence. 11.4.3 General Description Figure page shows serial peripheral interface (SPI) block diagram. There three registers: Control Register (SPICR) Control/Status Register (SPICSR) Data Register (SPIDR) connected external devices through four pins: MISO: Master Slave data MOSI: Master Slave data SCK: Serial Clock masters input slaves Slave select: This input signal acts `chip select' master communicate with slaves individually avoid contention data lines. Slave inputs driven standard ports master Device.
SERIAL PERIPHERAL INTERFACE (SPI) (cont'd) Figure Serial Peripheral Interface Block Diagram
Data/Address SPIDR Read Read Buffer Interrupt request
8-bit Shift Register
SPIF WCOL MODF
SPR2 MSTR CPOL CPHA SPR1 SPR0
MASTER CONTROL SERIAL CLOCK GENERATOR
SERIAL PERIPHERAL INTERFACE (cont'd) 220.127.116.11 Functional Description basic example interconnections between single master single slave illustrated Figure MOSI pins connected together MISO pins connected together. this data transferred serially between master slave (most significant first). communication always initiated master. When master device transmits data slave device MOSI pin, slave device responds sending data master device Figure Single Master/ Single Slave Application
MASTER MSBit LSBit MISO
MISO pin. This implies full duplex communication with both data data synchronized with same clock signal (which provided master device pin). single data line, MISO MOSI pins must connected each node this case only simplex communication possible). Four possible data/clock timing relationships chosen (see Figure page master slave must programmed with same timing mode.
SLAVE MSBit MISO LSBit
8-bit SHIFT REGISTER
8-bit SHIFT REGISTER
used managed software
SERIAL PERIPHERAL INTERFACE (cont'd) 18.104.22.168 Slave Select Management alternative using control Slave Select signal, application choose manage Slave Select signal software. This configured SPICSR register (see Figure 51). software management, external free other application uses internal signal level driven writing SPICSR register. Master mode: internal must held high continuously
Slave Mode: There cases depending data/clock timing relationship (see Figure 50): CPHA (data latched second clock edge): internal must held during entire transmission. This implies that single slave applications either tied VSS, made free standard managing function software (SSM SPICSR register) CPHA (data latched first clock edge): internal must held during byte transmission pulled high between each byte allow slave write shift register. pulled high, Write Collision error will occur when slave writes shift register (see Section 22.214.171.124).
Figure Generic Timing Diagram
MOSI/MISO Master Slave CPHA Slave CPHA
Figure Hardware/Software Slave Select Management
SERIAL PERIPHERAL INTERFACE (cont'd) 126.96.36.199 Master Mode Operation master mode, serial clock output pin. clock frequency, polarity phase configured software (refer description SPICSR register). Note: idle state must correspond polarity selected SPICSR register pulling CPOL pulling down CPOL operate master mode operate master mode, perform following steps order: Write SPICR register: Select clock frequency configuring SPR[2:0] bits. Select clock polarity clock phase configuring CPOL CPHA bits. Figure shows four possible configurations. Note: slave must have same CPOL CPHA settings master. Write SPICSR register: Either clear high complete byte transmit sequence. Write SPICR register: MSTR bits Note: MSTR bits remain only high). Important note: SPICSR register written first, SPICR register setting (MSTR bit) taken into account. transmit sequence begins when software writes byte SPIDR register. 188.8.131.52 Master Mode Transmit Sequence When software writes SPIDR register, data byte loaded into 8-bit shift register then shifted serially MOSI most significant first. When data transfer complete: SPIF hardware. interrupt request generated SPIE interrupt mask register cleared. Clearing SPIF performed following software sequence: access SPICSR register while SPIF read SPIDR register
Note: While SPIF set, writes SPIDR register inhibited until SPICSR register read. 184.108.40.206 Slave Mode Operation slave mode, serial clock received from master device. operate slave mode: Write SPICSR register perform following actions: Select clock polarity clock phase configuring CPOL CPHA bits (see Figure 52). Note: slave must have same CPOL CPHA settings master. Manage described Section 220.127.116.11 Figure CPHA must held continuously. CPHA must held during byte transmission pulled between each byte slave write shift register. Write SPICR register clear MSTR enable functions. 18.104.22.168 Slave Mode Transmit Sequence When software writes SPIDR register, data byte loaded into 8-bit shift register then shifted serially MISO most significant first. transmit sequence begins when slave device receives clock signal most significant data MOSI pin. When data transfer complete: SPIF hardware. interrupt request generated SPIE interrupt mask register cleared. Clearing SPIF performed following software sequence: access SPICSR register while SPIF write read SPIDR register Notes: While SPIF set, writes SPIDR register inhibited until SPICSR register read. SPIF cleared during second transmission; however, must cleared before second SPIF order prevent Overrun condition (see Section 22.214.171.124).
SERIAL PERIPHERAL INTERFACE (cont'd) 11.4.4 Clock Phase Clock Polarity Four possible timing relationships chosen software, using CPOL CPHA bits (See Figure 52). Note: idle state must correspond polarity selected SPICSR register pulling CPOL pulling down CPOL combination CPOL clock polarity CPHA (clock phase) bits selects data capture clock edge. Figure Data Clock Timing Diagram
Figure shows transfer with four combinations CPHA CPOL bits. diagram interpreted master slave timing diagram where pin, MISO MOSI directly connected between master slave device. Note: CPOL changed communication byte boundaries, must disabled resetting bit.
MISO (from master) MOSI (from slave) slave)
MISO (from master) MOSI (from slave) slave)
Note: This figure should used replacement parametric information. Refer Electrical Characteristics chapter.
SERIAL PERIPHERAL INTERFACE (cont'd) 11.4.5 Error Flags 126.96.36.199 Master Mode Fault (MODF) Master mode fault occurs when master device's pulled low. When Master mode fault occurs: MODF interrupt request generated SPIE set. reset. This blocks output from device disables peripheral. MSTR reset, thus forcing device into slave mode. Clearing MODF done through software sequence: read access SPICSR register while MODF set. write SPICR register. Notes: avoid conflicts application with multiple slaves, must pulled high during MODF clearing sequence. MSTR bits restored their original state during after this clearing sequence. Hardware does allow user MSTR bits while MODF except MODF clearing sequence. slave device, MODF set, multimaster configuration device slave mode with MODF set. MODF indicates that there might have been multimaster conflict allows software handle this using interrupt routine either perform reset return application default state.
188.8.131.52 Overrun Condition (OVR) overrun condition occurs when master device sent data byte slave device cleared SPIF issued from previously transmitted byte. When Overrun occurs: interrupt request generated SPIE set. this case, receiver buffer contains byte sent after SPIF last cleared. read SPIDR register returns this byte. other bytes lost. cleared reading SPICSR register. 184.108.40.206 Write Collision Error (WCOL) write collision occurs when software tries write SPIDR register while data transfer taking place with external device. When this happens, transfer continues uninterrupted software write will unsuccessful. Write collisions occur both master slave mode. also Section 220.127.116.11 Slave Select Management. Note: "read collision" will never occur since received data byte placed buffer which access always synchronous with operation. WCOL SPICSR register write collision occurs. interrupt generated when WCOL (the WCOL status flag only). Clearing WCOL done through software sequence (see Figure 53).
Figure Clearing WCOL (Write Collision Flag) Software Sequence
Clearing sequence after SPIF (end data byte transfer) Step Read SPICSR
RESULT SPIF WCOL
Clearing sequence before SPIF (during data byte transfer) Step Read SPICSR RESULT Step Read SPIDR WCOL Note: Writing SPIDR register instead reading does reset WCOL bit.
SERIAL PERIPHERAL INTERFACE (cont'd) 18.104.22.168 Single Master Multimaster Configurations There types systems: Single Master System Multimaster System Single Master System typical single master system configured using device master four devices slaves (see Figure 54). master device selects individual slave devices using four pins parallel port control four pins slave devices. pins pulled high during reset since master device ports will forced inputs that time, thus disabling slave devices. Note: prevent conflict MISO line, master allows only active slave device during transmission.
more security, slave device respond master with received data byte. Then master will receive previous byte back from slave device MISO MOSI pins connected slave written SPIDR register. Other transmission security methods ports handshake lines data bytes with command fields. Multimaster System multimaster system also configured user. Transfer master control could implemented using handshake method through ports exchange code messages through serial peripheral interface system. multimaster system principally handled MSTR SPICR register MODF SPICSR register.
Figure Single Master Multiple Slave Configuration
Slave Device MOSI MISO Slave Device MOSI
Slave Device MOSI
Slave Device MOSI
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