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High-Speed DMOS Analog Switches Switch Arrays Introduction
This Application Note describes detail principle operation SD210/5000 series high-speed analog switches switch arrays. contains explanation most important switch characteristics, application examples, test data, other application hints. surface-mount applications SST211 series offered TO-253 (SOT-143) package. SD5400 series comes narrow body gull-wing SO-14 package.
Fast switching speeds, on-state resistance, high channel-to-channel isolation, capacitance, charge injection make these DMOS devices especially well suited variety applications. many possible application areas DMOS analog switches follows: Video switching (high speed, high offisolation, crosstalk): -Multiple video distribution networks -Sampling scanners systems Audio routing (glitch- noise-free): -High-speed switching -Audio switching systems using digitized remote control Data acquisition (highspeed, charge injection, leakage): -High-speed sample-and-holds -Audio communication converters Other: -Digital switching -PCM distribution networks -UHF Amplifiers -VHF Modulators Double-Balanced Mixers -High-speed inverters/drivers -Switched capacitor filters -Choppers
Description
Linear Systems SD210 SD5000 series discretes quad monolithic arrays, respectively, single-pole single-throw analog switches. These switches n-channel enhancement-mode silicon field effect transistors built using double-diffusion (DMOS) silicon gate technology. Surfacemount versions (SST211, SD5400 Series) also available. This family devices designed handle wide variety video, fast ATE, telecom analog switching applications. They capable ultrafast switching speeds tOFF excellent transient response. Thanks reduced parasitic capacitances, DMOS handle wideband signals with high off-isolation minimum crosstalk. SD210 series single-channel FETs produced without Zener protection reduce leakage Zener protected versions reduce electrostatic discharge hazards. SD5000 series available 16-lead dual inline surface mount sidebraze ceramic packages. Analog signal voltage ranges frequencies controlled.
Linear Integrated Systems, Inc. 4042 Clipper Fremont, 94538 Tel: 490-9160 Fax: 353-0261
Principle Operation
Figure depicts n-channel enhancementmode device with insulated gate asymmetrical structure. gate protection Zener shown with broken lines indicate that, although present chip, main constituent fundamental switch structure.
Gate Protection Zener Asymmetrical Structure Insulated Gate Drain Enhancement Mode n-Channel Body
Figure DMOS Electrical System
double-diffusion process creates thin selfaligning region p-type material, isolating source from drain region. very short channel length that results between junction depths produces extremely sourceto-drain gate-to-drain capacitances same time that provides good breakdown voltages. When gate potential equal negative with respect source, switch off. this state, p-type material channel forms back-to-back diodes prevents channel conduction (Figure 3a). voltage applied between regions, only small junction leakage current will flow.
Source
rDS(on)
DMOS field-effect transistor (FET) normally when gate-to-source voltage (VGS) lateral DMOS transistor, shown cross-section Figure three terminals (source, gate, drain) surface (the body substrate) bottom. Zener diode with breakdown voltage approximately added protect gate against overvoltage electrostatic discharges.
Source Oxide Gate Drain
State State Figure Equivalent Circuits
silicon oxide insulation present between gate source forms small capacitor that accumulates charge. gate-to-source potential (VGS) made positive, capacitive effect attracts electrons channel area immediately adjacent gate oxide. increases, electron density channel will exceed hole density, channel will become n-type region. channel conductivity enhanced, n-n-n structure becomes simple silicon resistor through which current easily flow either direction. Figure shows typical biasing analog signal processing. Note that drain
Channel
Body
Figure Cross Sectional View Idealized DMOS Structure
Linear Integrated Systems, Inc. 4042 Clipper Fremont, 94538 Tel: 490-9160 Fax: 353-0261
recommended output. Since this causes less charge injection noise load. seen from Figures body-source body-drain junctions should kept reverse biased times-otherwise, signal clipping even device damage occur unlimited currents allowed flow. Body biasing conveniently set, most cases, connecting substrate
circuit shown Figure exhibits rDS(on) analog signal voltage relationship shown Figure When analog signal excursion large (for example channel on-resistance changes function signal level. achieve minimum distortion, this channel onresistance modulation should kept mind, amount resistance series with switch should properly sized. instance, switch resistance varies between over signal range switch series with load, result will total Whereas, load will only 0.01
rDS(on)
RGEN Switch Input
Control Input Switch Output
Figure Normal Switch Configuration Analog Switch
Main Switch Characteristics
rDS(on)
Channel on-resistance controlled electric field present across along channel. Channel resistance mainly determined gate-to-source voltage difference. When exceeds threshold voltage (VGS(th)), starts turn Numerous applications call switching point ground. these cases source substrate connected ground gate voltage sufficient ensure switching action. With excess resistance path exists between source drain.
VBODY VGATE VBODY VGATE VBODY VGATE
Figure Resistance Characteristics
Threshold Voltage
threshold voltage (VGS(th)) parameter used describe much voltage needed initiate channel conduction. Figure shows applicable test configuration. this circuit, worth noting, instance, that device VGS(th) when channel resistance will RCHANNEL 0.5V 500k
Linear Integrated Systems, Inc. 4042 Clipper Fremont, 94538 Tel: 490-9160 Fax: 353-0261
VGS(th)
VGS(th)
VGS(th)
Figure Threshold Voltage Test Configuration
Body Effect
MOSFET with uniformly doped substrate, threshold voltage proportional square root applied source-to-body voltage. SD5000 family non-uniform substrate, VGS(th) behaves somewhat differently. Figure shows typical VGS(th) variation function source-to-body voltage VSB. body voltage increases negative direction, threshold goes Consequently, small, on-resistance channel very high. Figure shows effects rDS(on). Therefore, maintain on-resistance preferable bias body voltage close negative peaks gate voltage high possible.
Figure Threshold Source Body Voltage
rDS(on)
Charge Injection
Charge injection describes that phenomenon which voltage excursion gate produces injection electric charges gate-todrain gate-to-source capacitances into analog signal path. Another popular name this phenomenon "switching spikes."
Figure Resistance Source Body Gate Source Voltages
Linear Integrated Systems, Inc. 4042 Clipper Fremont, 94538 Tel: 490-9160 Fax: 353-0261
Since these DMOS devices asymmetrical1, charge injected into terminals different. Typical parasitic capacitances order CSG. Another factor that influences amount charge injected amplitude gatevoltage excursion. This directly proportional relationship: larger excursion, larger injected charge. This seen comparing curves Figure other variable consider rate gate-voltage change. Large amounts charge injected when faster rise fall times present gate. This shown curves Figure
impedance tends produce rapid decay extra charge introduced channel. turnoff, however, injected charge might become stored sampling capacitor create offsets errors. These errors will have magnitude that inversely proportional magnitude holding capacitance. Figure illustrates several typical charge injection characteristics. Figure shows some corresponding waveforms. DMOS FETs, because their inherent parasitic capacitances, produce very charge injection when compared other analog switches (PMOS, CMOS, JFET, BIFET etc.). Still, when offsets created unacceptable, charge injection compensation techniques exist that eliminate minimize them. solution basically consists injecting another charge equal amplitude opposite polarity time when switch turns off.
(pC)
Off-Isolation Crosstalk
on-state resistance typically off-state resistance typically 1010 which results off-state on-state resistance ratio excess 108. However, video switching applications, upper usable frequency limit determined much incoming signal coupled through parasitic capacitances appears switch outputwhen ideally signal should appear there state. Off-Isolation defined formula:
V/µs 0.03 V/µs V/µs
Figure SD5000 Charge Injection
Switching spikes occur switch turn-on well turn-off time. When switch turns charge injection effect minimized usually signal-source impedance. This
chip geometry such that non-identical behavior occurs when source drain terminals reversed circuit.
Isolation (dB) 20log
VOUT
When several analog switches simultaneously being used control high frequency signals, crosstalk becomes very important characteristic. video applications, stray signal coupled parasitic
Linear Integrated Systems, Inc. 4042 Clipper Fremont, 94538 Tel: 490-9160 Fax: 353-0261
VGATE
TOP: V/div BOT: mV/div HOR: µs/div POINT TOP: V/div BOT: mV/div HOR: µs/div POINT
Figure Waveforms Points Figure
capacitances signal adjacent channel form ghosts signal interference. help obtain high degrees isolation, becomes necessary exercise careful circuit layout, reducing parasitic capacitive inductive couplings, proper shielding bypassing techniques. Figure shows excellent off-isolation crosstalk performance typical this family DMOS analog switches.
Insertion Loss
frequencies, attenuation caused switch function on-resistance load impedance. They form simple series voltage divider network. example, load impedance insertion loss voice signals Vrms kHz) less than Thus, SD5000 series make good audio crosspoint switches.
Vrms
Crosstalk
Crosstalk
(dB)
Isolation
Vrms
Isolation
Frequency (Hz)
Figure SD5000 Crosstalk Isolation Frequency
Linear Integrated Systems, Inc. 4042 Clipper Fremont, 94538 Tel: 490-9160 Fax: 353-0261
Scope
+VDD
VOUT
Scope
td(on) td(off)
RGEN
Figure Switching Test Circuit
Speed
Because on-resistance input capacitance low, DMOS switches capable subnanosecond switching speeds. these speeds external circuit rather than itself often responsible rise fall times that obtained. Let's consider switching test circuit Figure turn-on, fall time observed drain function input pulse amplitude rise time. sooner reaches VGS(th), sooner turnon will occur, lower rDS(on) reached, faster will discharged. turn-off time rise time much limited velocity which discharged gate control pulse, time takes charge load resistor Table shows typical performances obtained. important realize that stray capacitance parasitic inductances, well scope probe capacitance, seriously affect rise fall times (switching speed).
td(on) (ns)
(ns)
tOFF (ns)
tOFF dependant does depend device characteristics. Table Typical Switching Times
Drivers
switch driver's function translate logic control levels (either TTL, CMOS, ECL) into appropriate voltages needed gate that switch turned off. SD5000 operated inverter capable driving This high-voltage rating, together with high speed, make excellent driver other members family. Figure shows several driver circuits. Since switching times depend charge/discharge times, important note that driver's current source/sink capability plays very important role process.
Linear Integrated Systems, Inc. 4042 Clipper Fremont, 94538 Tel: 490-9160 Fax: 353-0261
SD5000 CMOS SD5000
SD210 SD5000
CMOS SD210
SD5000
SD211
Figure Various DMOS Drivers
High-Speed Multiplexer
typical application, circuit Figure used multiplex sample-and-hold analog signals 5-MHz rate. switches SD5000 used level shifter/drivers provide gate drive single-pole-double-throw arrangement formed switches Capacitors provide charge injection compensation. Signal 6-V, 156-kHz square wave. Signal 2-Vpp, 78-kHz alternating waveform with offset -3.4 (Figure 15).
Figure illustrates resulting composite waveform present holding capacitor along with gate control signal. seen, switching times about acquisition time holding time about total sample-and-hold cycle takes Even though maximized, this speed faster than what other presently available analog switch products achieve.
Linear Integrated Systems, Inc. 4042 Clipper Fremont, 94538 Tel: 490-9160 Fax: 353-0261
timing amplitude gate gate control-signals examined Figure Figure shows single-pole single-throw configuration used select modulated 10-MHz signals. Figure illustrates waveforms available output. Table contains typical values crosstalk off-isolation attainable with this configuration.
FREQ (Hz)
LOSS ISOL XTALK (dBm) (dB) (dB) (dB)
Table SPDT Switching Performance
Signal
Signal
Signal VOUT
Signal
Figure Analog Signals Sampled
VOUT
VOUT
Figure 5-MHz Multiplexer Sample Hold Circuit
Figure Composite Sample Hold Output Gate Control Signal
Linear Integrated Systems, Inc. 4042 Clipper Fremont, 94538 Tel: 490-9160 Fax: 353-0261
High-Speed Circuit
Figure shows fast unity gain input buffer (Si581) driving SD5000 switch. half SD5000 configured dummy switches charge injection compensation. JFET output buffer minimizes droop. Transistors through level shift control input signals into voltage (referenced analog signal voltage) used drive DMOS FETs.
Figure Gate Control Signals SPDT Switch Configuration
Deglitcher
very small charge injection makes DMOS FETs excellent deglitcher switches. Figure illustrates typical circuit configuration.
SD210 Input Shield 0.047 0.047
Control
DG413 Output
Channel
SD210
0.047 Input Shield
0.047
Channel Figure High Frequency SPDT Switch Figure 10-MHZ Modulated Outputs SPDT Switch Figure
Linear Integrated Systems, Inc. 4042 Clipper Fremont, 94538 Tel: 490-9160 Fax: 353-0261
LS3250 LS3550
-5.2
SD5000 Output
Analog Signal
Figure Fast Circuit Achieves Minimum Step Errors
SD5000 IOUT
OP-27
VOUT
Figure Deglitcher Using DMOS Switches Zener Protection
None None
Part Number
Package
Type
Single Single Single Single Single Quad Quad Quad Quad Quad Single Single
rDS(on)
45/50 45/50 45/50
V(BR)DS
SD210DE TO-72 SD214DE TO-72 SD/SST211 TO-72/SOT-143 SD/SST213 TO-72/SOT-143 SD/SST215 TO-72/SOT-143 SD5000N PDIP SD5001N PDIP SD5000I CDIP SD5400CY SOIC SD5401CY SOIC SD/SST823 TO-72/SOT-143 SD/SST824 TO-72/SOT-143 Future devices available 2003
Table DMOS Device Part Numbers Packages
Linear Integrated Systems, Inc. 4042 Clipper Fremont, 94538 Tel: 490-9160 Fax: 353-0261
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