SN74LV163A SN54LV163A

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SN74LV163A - SN74LV163A
SN54LV163A - SN54LV163A

SN54LV163A, SN74LV163A SYNCHRONOUS BINARY COUNTERS
5.5-V Operation Typical VOLP (Output Ground Bounce)
<0.8 25°C Typical VOHV (Output Undershoot) >2.3 25°C Support Mixed-Mode Voltage Operation Ports Internal Look Ahead Fast Counting Carry Output n-Bit Cascading
Synchronous Counting Synchronously Programmable Ioff Supports Partial-Power-Down Mode
Operation Latch-Up Performance Exceeds JESD Class Protection Exceeds JESD 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101)
SN54LV163A PACKAGE (TOP VIEW)
LOAD
internal connection
description/ordering information
ORDERING INFORMATION
PACKAGE SOIC -40°C 85°C SSOP Reel 1000 Tube Reel 2500 Reel 2000 Reel 2000 Tube TSSOP TVSOP CDIP 125°C -55°C Reel 2000 Reel Reel 2000 Tube Tube ORDERABLE PART NUMBER SN74LV163ARGYR SN74LV163AD SN74LV163ADR SN74LV163ANSR SN74LV163ADBR SN74LV163APW SN74LV163APWR SN74LV163APWT SN74LV163ADGVR SNJ54LV163AJ SNJ54LV163AW LV163A SNJ54LV163AJ SNJ54LV163AW LV163A LV163A 74LV163A LV163A TOP-SIDE MARKING LV163A
LCCC Tube SNJ54LV163AFK SNJ54LV163AFK Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package. Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. POST OFFICE 655303
Copyright 2005, Texas Instruments Incorporated
DALLAS, TEXAS 75265
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SN54LV163A PACKAGE SN74LV163A DGV, PACKAGE (TOP VIEW)
SN74LV163A PACKAGE (TOP VIEW)
SN54LV163A, SN74LV163A SYNCHRONOUS BINARY COUNTERS
description/ordering information (continued)
'LV163A devices 4-bit synchronous binary counters designed 5.5-V operation. These synchronous, presettable counters feature internal carry look ahead application high-speed counting designs. 'LV163A devices 4-bit binary counters. Synchronous operation provided having flip-flops clocked simultaneously that outputs change coincident with each other when instructed count-enable (ENP, ENT) inputs internal gating. This mode operation eliminates output counting spikes normally associated with synchronous (ripple-clock) counters. buffered clock (CLK) input triggers four flip-flops rising (positive-going) edge clock waveform. These counters fully programmable; that they preset number between presetting synchronous, setting level load input disables counter causes outputs agree with setup data after next clock pulse, regardless levels enable inputs. clear function 'LV163A devices synchronous. level clear (CLR) input sets four flip-flop outputs after next low-to-high transition CLK, regardless levels enable inputs. This synchronous clear allows count length modified easily decoding outputs maximum count desired. active-low output gate used decoding connected synchronously clear counter 0000 (LLLL). carry look-ahead circuitry provides cascading counters n-bit synchronous applications without additional gating. ENP, ENT, ripple-carry output (RCO) instrumental accomplishing this function. Both must high count, forward enable RCO. Enabling produces high-level pulse while count maximum with high). This high-level overflow ripple-carry pulse used enable successive cascaded stages. Transitions allowed, regardless level CLK. These counters feature fully independent clock circuit. Changes control inputs (ENP, ENT, LOAD) that modify operating mode have effect contents counter until clocking occurs. function counter (whether enabled, disabled, loading, counting) dictated solely conditions meeting stable setup hold times. These devices fully specified partial-power-down applications using Ioff. Ioff circuitry disables outputs, preventing damaging current backflow through devices when they powered down.
FUNCTION TABLE INPUTS LOAD OUTPUTS FUNCTION Reset Preset data count count Count count
change change Count change
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SN54LV163A, SN74LV163A SYNCHRONOUS BINARY COUNTERS
logic diagram (positive logic)
LOAD
2T/1C3 2T/1C3
2T/1C3
2T/1C3
simplicity, routing complementary signals shown this overall logic diagram. uses these signals shown logic diagram flip-flops. numbers shown DGV, RGY, packages.
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SN54LV163A, SN74LV163A SYNCHRONOUS BINARY COUNTERS
logic diagram, each flip-flop (positive logic)
origins shown overall logic diagram device.
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SN54LV163A, SN74LV163A SYNCHRONOUS BINARY COUNTERS
typical clear, preset, count, inhibit sequence
following sequence illustrated below: Clear outputs zero (synchronous) Preset binary Count Inhibit
LOAD Inhibit Count Sync Preset Clear Async Clear
Data Inputs
Data Outputs
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SN54LV163A, SN74LV163A SYNCHRONOUS BINARY COUNTERS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (see Note -0.5 Output voltage range applied high state, (see Notes -0.5 Voltage range applied output power-off state, (see Note -0.5 Input clamp current, Output clamp current, Continuous output current, VCC) Continuous current through Package thermal impedance, (see Note package 73°C/W (see Note package 82°C/W (see Note package 120°C/W (see Note package 64°C/W (see Note package 108°C/W (see Note package 39°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output current ratings observed. This value limited maximum. package thermal impedance calculated accordance with JESD 51-7. package thermal impedance calculated accordance with JESD 51-5.
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SN54LV163A, SN74LV163A SYNCHRONOUS BINARY COUNTERS
recommended operating conditions (see Note
SN54LV163A Supply voltage SN74LV163A ns/V UNIT
High-level input voltage
Low-level input voltage
Input voltage Output voltage
High-level output current
Low-level output current
Input transition rise fall rate
Operating free-air temperature NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
SN54LV163A PARAMETER TEST CONDITIONS GND, VCC-0.1 2.48 0.44 0.55 SN74LV163A VCC-0.1 2.48 0.44 0.55 UNIT
Ioff
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
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SN54LV163A, SN74LV163A SYNCHRONOUS BINARY COUNTERS
timing requirements over recommended operating (unless otherwise noted) (see Figure
free-air
temperature
SN74LV163A 11.5
range,
UNIT
25°C Pulse duration, high Data Setup time before ENP, LOAD Hold time, synchronous inputs after
SN54LV163A 11.5
timing requirements over recommended operating (unless otherwise noted) (see Figure
free-air
temperature
SN74LV163A
range,
UNIT
25°C Pulse duration, high Data Setup time before ENP, LOAD Hold time, synchronous inputs after
SN54LV163A
timing requirements over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
25°C Pulse duration, high Data Setup time before ENP, LOAD Hold time, synchronous inputs after SN54LV163A SN74LV163A UNIT
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
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SN54LV163A, SN74LV163A SYNCHRONOUS BINARY COUNTERS
switching characteristics over recommended operating (unless otherwise noted) (see Figure
PARAMETER fmax (count mode) (preset mode) (count mode) (preset mode) 12.1* 8.7* 11.9 14.6 11.7 FROM (INPUT) (OUTPUT) LOAD CAPACITANCE
free-air
temperature
SN74LV163A 19.5* 20.5* 24.5* 22.5 23.5 27.5 19.5 20.5
range,
UNIT
25°C 115* 8.5* 9.1* 16.2* 20.6* 15.7* 19.2 23.6 18.7
SN54LV163A
24.5 22.5 23.5 27.5
products compliant MIL-PRF-38535, this parameter production tested.
switching characteristics over recommended operating (unless otherwise noted) (see Figure
PARAMETER fmax (count mode) (preset mode) (count mode) (preset mode) 8.8* 6.5* 10.7 FROM (INPUT) (OUTPUT) LOAD CAPACITANCE
free-air
temperature
SN74LV163A 14.5* 18.5 19.5 23.5
range,
UNIT
25°C 160* 6.2* 6.8* 12.8* 13.6* 17.2* 12.3* 16.3 17.1 20.7 15.8
SN54LV163A
14.5 18.5 19.5 23.5
products compliant MIL-PRF-38535, this parameter production tested.
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
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SN54LV163A, SN74LV163A SYNCHRONOUS BINARY COUNTERS
switching characteristics over recommended operating (unless otherwise noted) (see Figure
PARAMETER fmax (count mode) (preset mode) (count mode) (preset mode) 6.4* 4.9* FROM (INPUT) (OUTPUT) LOAD CAPACITANCE 135*
free-air
temperature
SN74LV163A 9.5* 9.5* 9.5* 11.5 11.5 11.5
range,
UNIT
25°C 210* 4.7* 5.2* 8.1* 8.1* 10.3* 8.1* 10.1 10.1 12.3 10.1
SN54LV163A 115*
11.5 11.5 11.5
products compliant MIL-PRF-38535, this parameter production tested.
noise characteristics, 25°C (see Note
SN74LV163A PARAMETER VOL(P) VOL(V) VOH(V) VIH(D) Quiet output, maximum dynamic Quiet output, minimum dynamic Quiet output, minimum dynamic High-level dynamic input voltage 2.31 0.99 -0.2 -0.8 UNIT
VIL(D) Low-level dynamic input voltage NOTE Characteristics surface-mount packages only.
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS 23.8 UNIT
PRODUCT PREVIEW information concerns products formative design phase development. Characteristic data other specifications design goals. Texas Instruments reserves right change discontinue these products without notice.
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SN54LV163A, SN74LV163A SYNCHRONOUS BINARY COUNTERS
PARAMETER MEASUREMENT INFORMATION
Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open
From Output Under Test (see Note
Test Point
From Output Under Test (see Note
LOAD CIRCUIT TOTEM-POLE OUTPUTS
LOAD CIRCUIT 3-STATE OPEN-DRAIN OUTPUTS
Timing Input Input VOLTAGE WAVEFORMS PULSE DURATION Input tPLH In-Phase Output tPHL Out-of-Phase Output tPHL tPLH Output Waveform (see Note Output Waveform (see Note tPZH VOLTAGE WAVEFORMS SETUP HOLD TIMES tPZL tPLZ tPHZ Data Input
Output Control
VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING
NOTES: includes probe capacitance. Waveform output with internal conditions such that output low, except when disabled output control. Waveform output with internal conditions such that output high, except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time, with input transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPHL tPLH same tpd. parameters waveforms applicable devices.
Figure Load Circuit Voltage Waveforms
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device SN74LV163AD SN74LV163ADBR SN74LV163ADBRE4 SN74LV163ADE4 SN74LV163ADGVR SN74LV163ADGVRE4 SN74LV163ADR SN74LV163ADRE4 SN74LV163ANSR SN74LV163ANSRE4 SN74LV163APW SN74LV163APWE4 SN74LV163APWR SN74LV163APWRE4 SN74LV163APWT SN74LV163APWTE4 SN74LV163ARGYR SN74LV163ARGYRG4
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type SOIC SSOP SSOP SOIC TVSOP TVSOP SOIC SOIC TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP
Package Drawing
Pins Package Plan Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Call
Peak Temp Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-2-260C-1YEAR Call
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
1000 Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS
Addendum-Page
PACKAGE OPTION ADDENDUM
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6-Feb-2006
compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
MECHANICAL DATA
MPDS006C FEBRUARY 1996 REVISED AUGUST 2000
(R-PDSO-G**)
PINS SHOWN 0,23 0,13
PLASTIC SMALL-OUTLINE
0,40
0,07
0,16 4,50 4,30 6,60 6,20
Gage Plane
0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,08
PINS
3,70 3,50
3,70 3,50
5,10 4,90
5,10 4,90
7,90 7,70
9,80 9,60
11,40 11,20
4073251/E 08/00 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion, exceed 0,15 side. Falls within JEDEC: 24/48 Pins MO-153 14/16/20/56 Pins MO-194
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MECHANICAL DATA
MSSO002E JANUARY 1995 REVISED DECEMBER 2001
(R-PDSO-G**)
PINS SHOWN 0,65 0,38 0,22 0,15
PLASTIC SMALL-OUTLINE
0,25 0,09 5,60 5,00 8,20 7,40
Gage Plane 0,25 0,95 0,55
Seating Plane 2,00 0,05 0,10
PINS
6,50
6,50
7,50
8,50
10,50
10,50
12,90
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 12/01
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-150
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MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
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SN74LV163A SN54LV163A

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