SN74ALS819 SN74ALS29818
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SN74ALS819 - SN74ALS819
SN74ALS29818 - SN74ALS29818
SN74ALS819, SN74ALS29818 DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
High-Speed 8-Bit Parallel Pipeline Register Serial Shadow Register With Right-Shift Only 'ALS29818 Performs Parallel-to-Serial Serial-to-Parallel Conversion Designed Specifically Applications Such Write Control Store ('ALS29818) Serial Shadow-Register Diagnostics 'ALS819 Provides Even-Parity Output Power Dissipation Typical 'ALS29818 Functionally Equivalent AM29818 Package Options include Plastic Small Outline Packages, Standard Plastic DIPs, Plastic Chip Carriers
SN74ALS819 PACKAGE (TOP VIEW)
SRCLK MODE ORCLK
SN74ALS819 PACKAGE (TOP VIEW)
SRCLK MODE ORCLK
description
SN74ALS819 SN74ALS29818 8-bit pipeline registers each with on-chip shadow register. They applications such write control store shadow register diagnostics. output registers 'ALS819 'ALS29818 loaded parallel from either port (DQ0-DQ7) shadow register. shadow register 'ALS2981A loaded serially from either port (Y0-Y7) pipeline register. 'ALS819 shadow register loaded serially from port (DQ0-DQ7). addition, 'ALS819 provides Parity-Even (PE) output, which monitors parity output register. Operation these devices controlled Mode inputs shown function table. SN74ALS819 SN74ALS29818 characterized operation from 70°C.
SN74ALS29818 PACKAGE (TOP VIEW)
SRCLK MODE ORCLK
SN74ALS29818 PACKAGE (TOP VIEW)
SRCLK MODE 1718 ORCLK
internal connection
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1986, Texas Instruments Incorporated
POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 1443 HOUSTON, TEXAS 77001
SN74ALS819, SN74ALS29818 DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
logic symbols
SN74ALS819 [PIPELINE REGISTER] ORCLK SRG8 M1/4EN5 Z3/G4 ORCLK SRCLK MODE SN74ALS29818 [PIPELINE REGISTER] SRG8 M1/5,3D,EN6 M2/Z4/G5 1,3D [SHADOW REGISTER] 30,1,2,3D 31,1,2,3D
SRCLK MODE
1,2D [SHADOW REGISTER] 1,2D/Z10 1,2D/Z11
1,2D/Z17 10,6D
37,1,2,3D 10,1 20,1
17,6D [EVEN PARITY OUTPUTS]
17,1 27,1 These symbols accordance with ANSI/IEEE 91-1984 Publication 617-12. numbers shown packages.
POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 1443 HOUSTON, TEXAS 77001
SN74ALS819, SN74ALS29818 DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
logic diagrams (positive logic)
SN74ALS819 ORCLK
Shadow Register MODE SRCLK SRG8 1,2D 1,2D 1,2D
3-State Buffers
Pipeline Register Y7-Y0
DQ7-DQ0
SN74ALS29818 ORCLK SRCLK Shadow Register MODE SRG8 1,3D 1,2,3D 1,2,3D DQ7-DQ0
3-State Buffer
Pipeline Register
3-State Buffer Y7-Y0
numbers shown packages.
POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 1443 HOUSTON, TEXAS 77001
SN74ALS819 DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
SN74ALS819 gate-level logic diagram (positive logic)
ORCLK SRCLK MODE
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Identical Sections Shown
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numbers shown packages.
POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 1443 HOUSTON, TEXAS 77001
SN74ALS819 DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
SN74ALS819 gate-level logic diagram (positive logic) (continued)
From Previous Sheet
numbers shown packages.
POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 1443 HOUSTON, TEXAS 77001
SN74ALS29818 DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
SN74ALS29818 gate-level logic diagram (positive logic)
ORCLK SRCLK MODE
Identical Sections Shown
numbers shown packages.
POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 1443 HOUSTON, TEXAS 77001
SN74ALS819, SN74ALS29818 DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
Function Tables
SN74ALS819 INPUTS MODE SRCLK ORCLK OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT OUTPUT -DQ7 HI-Z INPUT INPUT INPUT INPUT OUTPUT OUTPUT HOLD HI-Z OPERATION FUNCTION Serial input, shift right Parallel load shadow register from -DQ7 Parallel load shadow register pipeline register from -DQ7 Load pipeline register from -DQ7 Load pipeline register from -DQ7 while shifting shadow register Load pipeline register from shadow register Serial data serial data Hold shadow register, enable -DQ7, transitions SRCLK ignored Disable -DQ7 outputs
SN74ALS29818 INPUTS MODE SRCLK ORCLK OUTPUT INPUT OUTPUT OUTPUT -DQ7 HI-Z HI-Z HI-Z INPUT INPUT HI-Z OUTPUT OPERATION FUNCTION Serial input, shift right, disable -DQ7 Parallel load shadow register from -Y7, disable -DQ7 Parallel load shadow register from pipeline register, disable -DQ7 Load pipeline register from -DQ7 Load pipeline register from -DQ7 while shifting shadow register Load pipeline register from shadow register Serial data serial data Exchange data between registers, -DQ7 disabled Hold shadow register, transitions SRCLK effect shadow register Enable -DQ7 parallel shadow register output
-DQ7 outputs must disabled before applying data -DQ7.
POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 1443 HOUSTON, TEXAS 77001
SN74ALS819, SN74ALS29818 DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
absolute maximum ratings over operating free-air temperature range
Supply voltage, Input voltage, input port Operating free-air temperature range 70°C Storage temperature range -65°C 150°C
recommended operating conditions
Supply voltage High-level input voltage Low-level input voltage -Y7, High-level output current Low-level output current Pulse duration others -Y7, others SRCLK high ORCLK high ('ALS29818) MODE Setup time before SRCLK ORCLK ('ALS29818) -DQ7 MODE ('ALS29818) SRCLK ('ALS29818) Hold time after RCLK MODE -DQ7 Hold time after ORCLK MODE ('ALS29818) ('ALS819) Operating free-air temperature This setup time ensures that shadow register will stable data from output register. This setup time ensures that output register will stable data from shadow register. 4.75 5.25 UNIT
Setup time before ORCLK
POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 1443 HOUSTON, TEXAS 77001
SN74ALS819, SN74ALS29818 DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
electrical characteristics over recommended operating temperature range (unless otherwise noted)
PARAMETER -Y7, 'ALS819 'ALS29818 5.25 Note typical values 25°C. ports, parameters include off-state current. more than output should shorted time duration short circuit should exceed second. NOTE measured with 3-state outputs high-impedance state. MODE, others 5.25 5.25 others -Y7, others 4.75 4.75 4.75 4.75 4.75 5.25 5.25 TEST CONDITIONS -3mA 0.35 0.35 -250 -1.2 UNIT
POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 1443 HOUSTON, TEXAS 77001
SN74ALS819, SN74ALS29818 DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
SN74ALS819 switching characteristics (see Figure
PARAMETER FROM (INPUT) (OUTPUT) TEST CONDITIONS 25°C MODE ORCLK ORCLK SRCLK MODE MODE -DQ7 -DQ7 4.75 5.25 70°C UNIT
tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ
SN74ALS29818 switching characteristics (see Figure
PARAMETER FROM (INPUT) (OUTPUT) TEST CONDITIONS 25°C MODE ORCLK SRCLK SRCLK SRCLK -DQ7 -DQ7 4.75 5.25 70°C UNIT
tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPHZ tPLZ tPZH tPZL
POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 1443 HOUSTON, TEXAS 77001
SN74ALS819, SN74ALS29818 DIAGNOSTICS/PIPELINE REGISTERS
SDAS105A JANUARY 1986 REVISED OCTOBER 1986
PARAMETER MEASUREMENT INFORMATION
From Output Under Test (see Note From Output Under Test (see Note Test Point SWITCH POSITION TABLE TEST Diodes 1N916 1N3064 tPLH tPHL tPZH tPZL tPHZ tPLZ Closed Closed Open Closed Closed Closed Closed Closed Closed Open Closed Closed
LOAD CIRCUIT BI-STATE TOTEM-POLE OUTPUTS Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES Input tPLH In-Phase Output tPHL Out-of-Phase Output tPHL tPLH VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES
LOAD CIRCUIT 3-STATE OUTPUTS Low-Level Input VOLTAGE WAVEFORMS PULSE DURATIONS Output Control tPZL tPLZ Waveform (see Note Waveform (see Note
High-Level Input
tPZH
tPHZ
VOLTAGE WAVEFORMS ENABLE DISABLE TIMES, 3-STATE OUTPUTS NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz,
Figure
POST OFFICE 655303 DALLAS, TEXAS 75265 POST OFFICE 1443 HOUSTON, TEXAS 77001
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device SN74ALS29818DW SN74ALS29818DWR SN74ALS29818DWR SN74ALS29818NT SN74ALS29818NT
Status OBSOLETE OBSOLETE OBSOLETE OBSOLETE OBSOLETE
Package Type SOIC SOIC SOIC PDIP PDIP
Package Drawing
Pins Package Plan
Lead/Ball Finish Call Call Call Call Call
Peak Temp Call Call Call Call Call
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device SN74ALS29818DW SN74ALS29818DWR SN74ALS29818DWR SN74ALS29818NT SN74ALS29818NT
Status OBSOLETE OBSOLETE OBSOLETE OBSOLETE OBSOLETE
Package Type SOIC SOIC SOIC PDIP PDIP
Package Drawing
Pins Package Plan
Lead/Ball Finish Call Call Call Call Call
Peak Temp Call Call Call Call Call
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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