SN74ABTH32543 SN54ABTH32543

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SN74ABTH32543 - SN74ABTH32543
SN54ABTH32543 - SN54ABTH32543

SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
Members Texas Instruments Widebus+Family State-of-the-Art EPIC-B BiCMOS Design Significantly Reduces Power Dissipation Latch-Up Performance Exceeds JEDEC Standard JESD-17 Typical VOLP (Output Ground Bounce) 25°C High-Impedance State During Power Power Down Released DSCC 5962-9557801NXD
Distributed Configuration Minimizes High-Speed Switching Noise High-Drive Outputs (-32-mA IOH, 64-mA IOL) Hold Data Inputs Eliminates Need External Pullup/Pulldown Resistors Package Options Include 100-Pin Plastic Thin Quad Flat (PZ) Package With 14-mm Body Using 0.5-mm Lead Pitch Space-Saving 100-Pin Ceramic Quad Flat (HS) Package
'ABTH32543 PACKAGE (TOP VIEW)
1A10 1A11 1A12 1A13 1A14 1A15 1A16 1A17 1A18 2A10
1CEBA 1OEBA 1LEBA 1LEAB 1OEAB 1CEAB
1B10 1B11 1B12 1B13 1B14 1B15 1B16 1B17 1B18 2B10
package production released.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. Widebus+ EPIC-B trademarks Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
2A11 2A12 2A13 2A14 2A15 2A16 2A17 2A18 2CEBA 2OEBA 2LEBA 2LEAB 2OEAB 2CEAB 2B18 2B17 2B16 2B15 2B14 2B13 2B12 2B11
Copyright 1997, Texas Instruments Incorporated
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SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
SN54ABTH32543 PACKAGE (TOP VIEW)
1CEBA 1OEBA 1LEBA 1LEAB 1OEAB 1CEAB
1A10 1A11 1A12 1A13 1A14 1A15 1A16 1A17 1A18 2A10 2A11 2A12
1B10 1B11 1B12 1B13 1B14 1B15 1B16 1B17 1B18 2B10 2B11 2B12 2B13
package availability, please contact factory your local Field Sales Office.
description
'ABTH32543 36-bit registered transceivers that contain sets D-type latches temporary storage data flowing either direction. These devices used 18-bit transceivers 36-bit transceiver. Separate latch-enable (LEAB LEBA) output-enable (OEAB OEBA) inputs provided each register permit independent control either direction data flow. A-to-B enable (CEAB) input must enter data from output data from CEAB LEAB low, A-to-B latches transparent; subsequent low-to-high transition LEAB puts latches storage mode. With CEAB OEAB both low, 3-state outputs active reflect data present output latches. Data flow from similar requires using CEBA, LEBA, OEBA inputs.
2A13 2A14 2A15 2A16 2A17 2A18 2CEBA 2OEBA 2LEBA 2LEAB 2OEAB 2CEAB 2B18 2B17 2B16 2B15 2B14
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
description (continued)
When between device high-impedance state during power power down. However, ensure high-impedance state above should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. Active bus-hold circuitry provided hold unused floating data inputs valid logic level. SN54ABTH32543 characterized operation over full military temperature range -55°C 125°C. SN74ABTH32543 characterized operation from -40°C 85°C.
FUNCTION TABLE (each 18-bit section) INPUTS CEAB LEAB OEAB OUTPUT
A-to-B data flow shown; B-to-A flow control same except that uses CEBA, LEBA, OEBA. Output level before indicated steady-state input conditions were established
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
logic diagram (positive logic)
1OEBA 1CEBA 1LEBA 1OEAB 1CEAB 1LEAB
Other Channels 2OEBA 2CEBA 2LEBA 2OEAB 2CEAB 2LEAB
Other Channels numbers shown package.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input voltage range, (except ports) (see Note -0.5 Voltage range applied output high power-off state, -0.5 Current into output state, SN54ABTH32543 SN74ABTH32543 Input clamp current, Output clamp current, Package thermal impedance, (see Note package 50°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output negative-voltage ratings exceeded input output clamp-current ratings observed. package thermal impedance calculated accordance with EIA/JEDEC JESD51.
recommended operating conditions (see Note
SN54ABTH32543 t/VCC Supply voltage High-level input voltage Low-level input voltage Input voltage High-level output current Low-level output current Input transition rise fall rate Power-up ramp rate Operating free-air temperature Outputs enabled SN74ABTH32543 UNIT ns/V µs/V
NOTE Unused control pins must held high prevent them from floating.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER Vhys Control inputs ports Control inputs ports II(hold) IOZPU IOZPD Ioff ICEX ports -100 -180 -100 -100 ±100 -180 TEST CONDITIONS SN54ABTH32543 -1.2 0.55 0.55 0.55 SN74ABTH32543 -1.2 UNIT
Outputs high Outputs high Outputs Outputs disabled
Control inputs ports
input Other inputs
typical values 25°C. This parameter specified characterization. more than output should tested time, duration test should exceed second. This increase supply current each input that specified voltage level rather than GND.
timing requirements over recommended ranges supply voltage operating free-air temperature (unless otherwise noted) (see Figure
25°C# Pulse duration, LEAB LEBA Setup time Hold time Data before LEAB LEBA Data before CEAB CEBA Data after LEAB LEBA Data after CEAB CEBA SN54ABTH32543 SN74ABTH32543 UNIT
These limits apply only SN74ABTH32543.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
switching characteristics over recommended ranges supply voltage operating free-air temperature, (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ FROM (INPUT) (OUTPUT) 25°C SN54ABTH32543 SN74ABTH32543 UNIT
These limits apply only SN74ABTH32543.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54ABTH32543, SN74ABTH32543 36-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
Open TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Open
From Output Under Test (see Note
LOAD CIRCUIT Input VOLTAGE WAVEFORMS PULSE DURATION
Timing Input Data Input VOLTAGE WAVEFORMS SETUP HOLD TIMES Output Control tPZL Output Waveform (see Note Output Waveform Open (see Note tPZH VOLTAGE WAVEFORMS ENABLE DISABLE TIMES LOW- HIGH-LEVEL ENABLING tPLZ tPHZ
Input tPLH Output tPHL tPHL tPLH Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING NONINVERTING OUTPUTS
NOTES: includes probe capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. input pulses supplied generators having following characteristics: MHz, outputs measured time with transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated

SN74ABTH32543 SN54ABTH32543

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