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SM5964A - SM5964A
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
Product List
SM5964AL25, 25MHz 64KB internal flash
Feature
Working Voltage:3.0V through 3.6V 80C51 Central Processor Unit (CPU) chip flash memory with InSystem-Programming(ISP) capability programmed 3.3V 1024 RAM, expandable externally 64KB standard 16-bits timers/counters additional 16-bits timer/counter coupled capture compare register. 8-bits 5-bits resolution Pulse-Width-Modulation (PWM) outputs Four 8-bits ports.(For PDIP package) Four 8-bits ports plus 4-bits port. (For PLCC package) TWSI-bus serial port with master slave functions Full-duplex UART interrupt sources with priority levels Temperature range +70) Software enable/disable output pulse Wake-up from POWER-DOWN mode external interrupt RESET. service program space configurable N*512 byte (N=0 size
General Description
SM5964A single-chip 8-bits microcontroller manufactured advanced CMOS process with chip flash memory. supports InSystem Programming (ISP) function derivative 8052 microcontroller family. SM5964A same instructions 80C51. SM5964A contains 64KB 3.3V chip program flash, volatile 1024 data RAM, four 8-bits ports, 4-bits port, 16-bits timer/event counters, additional 16-bits timer coupled capture compare latches, two-priority-level, nested interrupt structure, pulse-width- modulation (PWM) outputs, serial interfaces (UART TWSI bus). system that requires extra capability SM5964A expanded using standard LVTTL compatible memory logic. addition, SM5964A software selectable modes power saving IDLE mode POWER-DOWN mode. IDLE mode freezes while allowing RAM, timer, serial ports, interrupt system continue functioning. POWER-DOWN mode saves contents freezes oscillator, causing other chip functions inoperative. SM5964A designed 3.3V applications. chip flash memory store data while program running. also upgrade user program down-load code form other devices. chip considered small integrated system.
Ordering Information
SM5964AihhkL
yymmv process identifier {L=3.0V~3.6V} working clock {25} package type postfix below table} year month version identifier
free identifier text Non-PB free, free}
Specifications subject change without notice contact your sales representatives most recent information. Taiwan No.10-2 Hsin Road Science-based Industrial Park, Hsinchu, Taiwan 30078 TEL: 886-3-567-1820 886-3-567-1880 FAX: 886-3-567-1891 886-3-567-1894
SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
Package Spec.
Package
Configuration
PLCC PDIP
Figure Figure Figure
Figure
PLCC Package
Figure Package
Figure
PDIP Package
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
Block Diagram
PWM0 PWM1 T2EX
Xtal1 Xtal2 PSEN
UART
Int-RAM
256x8
FLASH 64Kx8
Ext-RAM
768x8
Timer2
CORE
iBUS
Timer0 Timer1
PDWU
Port0
Parallel ports Ext.
Port1 Port2 Port3 Port4
TWSI
Notes: (1): Alternate function (3): Alternate function
Specifications subject change without notice contact your sales representatives most recent information.
INT0
INT0 INT1
INT1
SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
Description
MNEMONIC
PDIP
PQFP
PLCC
Names Functions
Power supply: +3.3V power supply during normal operations power saving modes. Port Port open-drain, bidirectional port. Port pins that have written them become floating used highimpedance inputs. Port also multiplexed low-order address data during accesses external program data memory. this application, uses strong internal pull-ups when emitting Port 8-bits bidirectional port with internal pull-ups pins. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally pulled will source current because internal pull-ups. (See Electrical Characteristics: IIL). Alternate function SM5964A include Port Alternative function P1.0 TIMER2 clock output P1.1 T2EXTIMER2 reload/capture DIR. P1.2 PWM0PWM channel output P1.3 PWM1PWM channel output P1.6 SCLTWSI clock P1.7 SDATWSI data Reset: high this machine cycles while oscillator running resets device. internal resistor permits power-on reset using only external capacitor VCC. Port Port 8-bits bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally being pulled will source current because internal pull-ups. (See Electrical Characteristics: IIL). Port emits high-order address byte during fetches from external program memory during accesses external data memory that uses 16-bits addresses (MOVX @DPTR). this application, uses strong internal pull-ups when emitting During accesses external data memory that uses 8-bits addresses (MOV @Ri), port emits contents special function register. Port Port 8-bits bidirectional port with internal pull-ups. Port pins that have written them pulled high internal pull-ups used inputs. inputs, port pins that externally being pulled will source current because pull-ups. (See Electrical Characteristics: IIL). Port also serves special features. Port Alternative function P3.0 UART input P3.1 UART output P3.2 #EX0 external interrupt P3.3 #EX1 external interrupt P3.4 Timer external input P3.5 Timer external input P3.6 External data memory write strobe P3.7 External data memory read strobe
P0.0 P0.7
39,38,37,36 35,34,33,32
37,36,35,34 33,32,31,30
43,42,41,40 39,38,37,36
P1.0 P1.7
1,2,3,4, 5,6,7,8
40,41,42,43, 44,1,2,3
2,3,4,5, 6,7,8,9
P2.0 P2.7
21,22,23,24, 25,26,27,28
18,19,20,21 22,23,24,25
24,25,26,27, 28,29,30,31
P3.0 P3.7
10,11,12,13 14,15,16,17
5,7,8,9, 10,11,12,13
13,14,15, 16,17,18,19
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SM5964A 10/2006
SM5964A
MNEMONIC
PDIP
PQFP
8-Bit Micro-controller With 64KB Flash TWSI embedded PLCC Names Functions
Address Latch Enable: Output pulse latching byte address during access external memory. normal operation, emitted twice every machine cycle, used external timing clocking. Note that pulse skipped during each access external data memory. Setting SCONF.0 disable ALE. With this set, will active only during MOVX instruction. Program Store Enable: read strobe external program memory. When executing code from external program memory, #PSEN activated twice each machine cycle, except that #PSEN activations skipped during each access external data memory. #PSEN activated during fetches from internal program memory. External Access Enable: must externally held enable device fetch code from external program memory locations. held high, device executes from internal program memory. Crystal Input inverting oscillator amplifier input internal clock generator circuits. Crystal Output from inverting oscillator amplifier.
#PSEN
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
Mapping
special function register SM5964A fall into following categories CORE register: ACC, DPL, DPH, PSW, ports: P0,P1, P1CON Timer/Counter register: T2CON, T2MOD, TCON, TMOD, TH0, TH1, TH2, TL0, TL1, TL2, RCAP2L, RCAP2H UART register: SBUF, SCON TWSI register: TWSIS, TWSIA, TWSIC1, TWSIC2, TWSITXD, TWSIRXD Power system control register: PCON, SCONF Interrupt system register: IP1, IE1, Flash programming register :ISPFAH, ISPFAL, ISPFD, ISPC output register: PWMC0, PWMC1, PWMD0, PWMD1
Table 0000 0000 xxxx 1111 0000 0000 T2CON 0000 0000 TWSIS 0000 0000 0000 0000 1111 1111 0000 0000 1111 1111 SCON 0000 0000 1111 1111 TCON 0000 0000 1111 1111 0000 0000 ISPFAH 0000 0000 ISPFAL 0000 0000 ISPFD 0000 0000 ISPC 0000 0000 PWMC0 0000 0000 RCAP2H 0000 0000 TWSIC2 0000 0000 PWMC1 0000 0000 0000 0000 TWSITXD 1111 1111 0000 0000 TWSIRXD 0000 0000 SCONF 0000 0000 PWMD0 0000 0000 0000 0000 0000 0000 PWMD1 0000 0000 SBUF xxxx xxxx P1CON 0000 0000 TMOD 0000 0000 0000 0111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RCON 0000 0000 PCON 0000 0000
T2MOD xxxx xx00 TWSIA 1010 0000 0000 0000
RCAP2L 0000 0000 TWSIC1 0000 0001
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded Table list (8051, I/O, Timer, UART, TWSI, System, Interrupt)
Symbol P1CON TCON TMOD T2CON T2MOD RCAP2H RCAP2L SCON SBUF TWSIS TWSIA TWSIC1 TWSIC2
TWSITXD TWSIRXD
Description Accumulator register Stack Pointer Process Status Data Pointer High Data Pointer Port Port Port Port Port Control Timer Control register Timer Mode Timer High Timer Timer High Timer Timer Control Timer Mode RCAP2 High RCAP2 Timer High Time UART Control UART Buffer TWSI status TWSI address TWSI control TWSI Control TWSI Transmit Data TWSI Received Data Power Control register System Control Interrupt Enable Interrupt Enable Interrupt Flag Interrupt Priority Interrupt Priority Internal Control Address high Address Data Control Control Control Data Data
Direct
8051 Core
RESET
P0.7 P1.7 P2.7 P3.7 SDAE GATE
P0.6 P1.6 P2.6 P3.6
PORT P0.5 P1.5 P2.5 P3.5
P0.4 P1.4 P2.4 P3.4
SCLE TIMER Counter
P0.3 P1.3 P2.3 P3.3 P4.3 PWM1E GATE
P0.2 P1.2 P2.2 P3.2 P4.2 PWM0E
P0.1 P1.1 P2.1 P3.1 P4.1
P0.0 P1.0 P2.0 P3.0 P4.0
EXF2
RCLK
TCLK
EXEN2
T2OE
CPRL2 DCEN
UART TWSI
RXIF TWSIE
TXIF
TFIF
NAKIF Busy
RXAK TWSIFS2
MASTER TWSIFS1
TXAK TWSIFS0
Match
RESTART
Power System PCON SCONF RCON ISPFAH ISPFAL ISPFD ISPC PWMC0 PWMC1 PWMD0 PWMD1 SMOD PDWUE Interrupt system ISPE ETWSI TWSIIF PTWSI RAMS1 FLASH memory IDLE ALEI
Data Memory
RAMS0
START output
PWMD.7 PWMD.7 PWMD.6 PWMD.6 PWMD.5 PWMD.5 PWMD.4 PWMD.4 PWMD.3 PWMD.3 PWMD.2 PWMD.2
ISPF1 PFS1 PFS1
PWMD.1 PWMD.1
ISPF0 PFS0 PFS0
PWMD.0 PWMD.0
Operating Conditions
Symbol Description Operating temperature Min. Typ. Max. Unit. Remarks Ambient temperature under bias
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
VCC33 Fosc Supply voltage Oscillator Frequency 3.3V application
Characteristic
3.3V (±10%), VSS=0V
SYMBOL VIL1 VIL2 VIH1 VIH2 IIL1 IIL2 ISK1 ISK2 ISR1 ISR2 VOL1 VOL2 VOH1 VOH1 RRST Supply Voltage Supply current operating Supply current IDLE mode Supply current Power-Down mode Input voltage, Port 0,1,2,3,4,/EA Input voltage, RES, XTAL1 Input HIGH voltage, Port 0,1,2,3,4,EA Input HIGH voltage, RES, XTAL1 Input current level Port 1,2,3,4 except P1.6,P1.7 Input current level Port 0,P1.6,P1.7 Transition current High Port 1,2,3,4 Input leakage current Sink Current Port Sink Current Port 0,ALE, /PSEN Source Current Port Source Current Port 0,ALE, /PSEN Output voltage, Port 0,ALE, /PSEN Output voltage, Port Output High voltage Port0 ALE, /PSEN Output High voltage Port 1,2,3,4 Internal RESET pull-down resistor capacitance 0.45V 0.45V 0.45V 3.3V, 3.3V, 3.3V, 3.3V, OUTPUT 3.2mAVCC=3.3V 1.6mAVCC=3.3V -300uAVCC=3.3V -20AVCC=3.3V VCC=3.6V Test freq=1MHz, TA=25 notes fCLK 12MHz 3.6V note fCLK 12MHz 3.6V note VCCmax INPUT -0.5 PARAMETER TEST CONDITIONS LIMITS Vcc+0.2 Vcc+0.2 -650 -650 UNIT
NOTES ELECTRICAL CHARACTERISTICS operating supply current measured with output disconnected; XTAL1 driven with 5ns; VSS+0.5V; VIH=VCC-0.5V; XTAL2 connect;/EA=RST=Port0=VDD; IDLE MODE supply current measured with output pins disconnected; XTAL1 driven with 5ns; VSS+0.5V; VIH=VCC-0.5V; XTAL2 connect;/EA= Port0=VDD; POWER-DOWN MODE supply current measured with output pins disconnected; VSS+0.5V; VIH=VCC-0.5V; XTAL2 connect; /EA= Port0=VDD; Port sources transition current when they being externally driven from HIGH LOW. transition current reaches maximum value when approximately Capacities loading port cause spurious noise superimposed port noise external capacitance discharging into port port pins when these pins make 1-to-0 transitions during operations. worst cases (capacities loading 100pF), noise pulse exceed 0.8V. such cases, desirable qualify with Schmitt Trigger, address latch with Schmitt trigger STROBE input. Under steady state (non-transient) conditions, must externally Limited follows: Maximum (use sign only) 10mA Maximum 8-bit port port 26mA port 1,2,3 15mA Maximum total output pins 71mA exceeds condition, exceed related specification. Pins guaranteed sink current greater than listed test conditions. Specifications subject change without notice contact your sales representatives most recent information.
SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
Characteristic
VCC=3.3V±10%, VSS=0V, tclk fmax(maximum operating frequency) TA=0 CL=100pF Port0, /PSEN; CL=80pF other outputs unless otherwise specified.
Symbol tCLK tCLKH tCLKL tCLKR tCLKF tCYC
NOTES Operating 25MHz.
FIGURE
PARAMETER External Clock drive into XTAL1 Xtal1 Period Xtal1 HIGH time Xtal1 time XTAL1 rise time XTAL1 fall time Controller cycle time tCLK 40(1) 3.33
UNIT
Symbol 1/tCLK tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ tAVLL tLLAX tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tQVWH tWHQX tRLAZ tWHLH tXLXL tQVXH tXHQX tXHDX tXHDV
FIGURE
PARAMETER Program Memory System clock frequency pulse width Address valid Address hold after valid instruction /PSEN /PSEN pulse width /PSEN valid instruction Input instruction hold after /PSEN Input instruction float after /PSEN Address valid instruction /PSEN address float Data Memory Address valid Address hold after pulse width pulse width valid data Data hold after Data float after valid data Address valid data Address valid Data valid transition Data before Data hold after address float HIGH HIGH UART Serial port clock time Output data setup clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge input data valid
2tCLK-40 tCLK-40 tCLK-30 tCLK-30 3tCLK-45
UNIT
4tCLK-100
3tCLK-105 tCLK 5tCLK-105 tCLK-40 tCLK-35 6tCLK-100 6tCLK-100 5tCLK-165 2tCLK-70 8tCLK-150 9tCLK-165 3tCLK+50
3tCLK-50 4tCLK-130 tCLK-50 7tCLK-150 tCLK-50 tCLK-40 12tCLK 10tCLK-133 2tCLK-117
tCLK+40
10tCLK-133
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
tCLKH VIH1 0.8V
tCLKR
tCLKF
tCLKL tCLK Figure External Clock Drive waveform
2.0V 0.8V
2.0V Test Points 0.8V
Notes: inputs during testing driven 2.4V logic "HIGH" 0.45V logic "LOW". Timing measurements 2.0V logic "HIGH" 0.8V logic "LOW" Figure Testing Input/Output
Floating 2.0V 0.8V 2.0V 0.8V
Notes: float state define point which PORT pins sinks 3.2mA source 400A voltage test level. Figure Testing, Floating Waveform
LHLL LLPL AVLL /PSEN PLAZ LLAX LLIV PORT0 A0-A7 AVIV PORT2 A8-A15 A8-A15 A8-A15 INSTR PXIZ PXIX A0-A7 PLIV PLPH
Figure External Program Memory Read Cycle
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
WHLH /PSEN LLDV LLWL AVLL LLAX PORT0
DPL)
RLRH RLDV RLAZ DATA RHDZ RHDX (PCL) INSTR
AVDV AVWL PORT2 PORT2 (PCH)
Figure external memory read cycle
tWHLH /PSEN LLWL tQVWH tAVLL PORT0 LLAX tAVWL PORT2 PORT2 (PCH) QVWX DATA tWHQX (PCL) INSTR WLWH
DPL)
Figure external memory write cycle
nstruction
tXLXL CLOCK tQVXH tXHDV VALID tXHQX tXHDX VALID VALID VALID VALID VALID VALID Set_R VALID
Figure UART waveform Shift Register MODE
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
repeat START condition tSU;STA
START repeat START condition
STOP condition
tHD;DAT
0.7VCC 0.3VCC
tBUF tSU;STO START
tSU;DAT3 tHD;STA tLOW tHIGH tSU;DAT1 tSU;DAT tSU;DAT2
Figure Timing waveform TWSI interface
Standard-MODE TWSI fSCL tBUF tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tRD,tRC tSU;STO tSU;STA NOTES: fast-mode TWSI device used standard-mode TWSI system, requirement tSU;DAT 250ns must met. This will automatically case device does stretch period signal. such device does stretch period signal, must output next data line tRMAX tSU;DAT 1000 1250 (according standard-mode TWSI specification) before line released. Total capacitance line clock frequency free time between stop stop condition Hold time (repeated) START condition. After this period, first clock pulse generated Period clock High period clock Set-up time repeated START condition Data hold time Data Setup-Time Rise time both Fall time both Set-up time STOP START condition Capacitive load each line Pulse width spikes which must suppressed input filter 1000
Symbol
FIGURE
PARAMETER
Fast-MODE
UNIT
20+0.1Cb 20+0.1Cb
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
Function Description
SM5964A stand-alone high-performance microcontroller designed using 3.3V applications, such monitor, instrumentation, high-end consumer applications. addition 80C51 standard functions, device provides number dedicated hardware functions these applications. SM5964A control-oriented with on-chip program data memory. extended with external data memory bytes. system requiring extra capability, SM5964A enhanced using external memory peripherals. SM5964A software selectable modes saving power consumptionIDLE POWER- DOWN. IDLE mode freezes while allowing RAM, timer, serial ports interrupt system continue functioning. POWER-DOWN mode save contents freezes oscillator causing other chip functions inoperative. POWER-DOWN mode terminated reset, external interrupt.
SM5964A compatible standard 80C51. structure this shown FIGURE contains Instruction Register (IR), Instruction Decoder, Program Counter (PC), Accumulator (ACC), Register, control logic. This provides 8-bits bi-direction communicate with other blocks chip. address data transferred through same 8-bits bus.
PROG. ADDR.
Timing Reset
CONTROL LOGIC
TMP2 TMP1
PROGRAM ADDR.REGISTER
BUFFER CTRL.
INSTRUCTION DECODER Register
PROGRAM INCREMENT PROGRAM COUNTER DPTR
INSTRUCTION REGISTER DATA IN/OUT PCON
POWER CTRL Signal
Figure structure
Timing
machine cycle consists sequence states, numbered through Each state time lasts oscillator periods. Thus machine cycle takes oscillator periods. Each state divided into PHASE1 half PHASE2 half. FIGURE shows relationships between oscillator, phase, S1-S6.
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
PHASE (Xtal2) SEQUENCE
Figure Sequences Phases
FIGURE shows fetch execute sequences states phases various kinds instructions. Normally program fetches generated during each machine cycle, even instruction being executed doesn't require instruction being executed doesn't need more code bytes, simply ignores extra fetch, PROGRAM COUNTER incremented accordingly. Execution one-cycle instruction (FIGURE begins during machine cycle, when OPCODE latched into INSTRUCTION REGISTER. second fetch occurs during same machine cycle. Execution completed this machine cycle. MOVX instructions take machine cycles execute. program fetch generated during second cycle MOVX instruction. This only time program fetches skipped. fetch/execute sequence MOVX instructions shown FIGURE fetch execute sequences same whether PROGRAM MEMORY internal external chip. Execution times depend whether PROGRAM MEMORY internal external. FIGURE shows signals timing involved program fetches when program memory external. PROGRAM MEMORY external, PROGRAM MEMORY READ STOBE (/PSEN) normally activated twice machine cycle, shown FIGURE 15(A). access external DATA MEMORY occurs, shown FIGURE 15(B), (/PSEN) SKIPPED, because address data being used DATA MEMORY access. Note that DATA MEMORY cycle takes twice much time PROGRAM MEMORY cycle. FIGURE shows relative time address begin emitted PORT0 PORT2, /PSEN. used latch address byte form PORT0 into address latch. When executing from internal PROGRAM MEMORY, /PSEN activated, program address emitted. However, continues activated twice machine cycle available clock output signal. Note, however, that skipped during execution MOVX instruction.
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
byte, Cycle Instruction
Read OPCODE
Read next OPCODE Discard
Read next OPCODE again
machine cycle byte, Cycle Instruction
Read OPCODE
Read 2'nd Byte
Read next OPCODE
machine cycle byte, Cycle Instruction
Read OPCODE 1'st cycle
Read next OPCODE (Discard) 2'nd cycle
ACCESS external memory DATA
Read next OPCODE again
MOVX: byte, Cycle Instruction
ADDR
Fetch
Fetch
Read OPCODE
Read next OPCODE (Discard)
Read next OPCODE Again
1'st cycle
2'nd cycle
Figure Timing various instructions
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
Without MOVX cycle /PSEN
cycle
INST.
INST.
INST.
INST.
With MOVX 1'st cycle /PSEN 2'nd cycle
INST.
Addr.
Data.
INST.
Figure15: cycle external program memory mode
Instruction
SM5964A uses powerful instruction 80C51. consists single-byte, two-byte, three- byte instructions. Among them instructions executed machine-cycle, instructions machine-cycles, multiply, instructions machine-cycles. summary instruction given Table
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
Addressing Mode
Notes instruction address modes: direct #data #data16 addr11 Register R7-R0 currently selected register bank. 8-bits internal data location's address. This could internal DATA location (0-127) [i.e., port, control register, status register, etc. (128-255)] 8-bits location addressed indirectly through register actual register bank 8-bits constant included instruction 16-bits constant included instruction 11-bits destination address. Used ACALL AJMP. branch anywhere within same bytes page program memory first byte following instruction. Signed (2's complement) 8-bits offset byte. Used SJMP conditional jumps. Range -128 +127 bytes relative first byte following instruction. Direct addressed internal data Table Summary instruction OPERATION direct <@Ri> #data direct #data direct <@Ri> A#data A=A+1 direct direct <@Ri> <@Ri> direct direct <@Ri> <@Ri> DPTR DPTR (A/B) (A/B) Decimal adjust .AND. .AND. direct .AND. <@Ri> .AND. #data direct .AND. direct .AND. #data .OR. .OR. direct .OR. <@Ri> .OR. #data direct .OR. direct .OR. #data .XOR. .XOR. direct .XOR. <@Ri> .XOR. #data direct .XOR. direct .XOR. #data
Mnemonic Arithmetic Instructions A,Rn A,direct A,@Ri A,#data ADDC A,Rn ADDC A,direct ADDC ADDC SUBB SUBB SUBB SUBB A,@Ri A,#data A,Rn A,direct A,@Ri A,#data direct direct DPTR
BYTE
CYCLE
Logical Instructions A,Rn A,direct A,@Ri A,#data direct,A direct,#data A,Rn A,direct A,@Ri A,#data direct,A direct,#data A,Rn A,direct A,@Ri A,#data direct,A direct,#data
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
SWAP Data Transfers Instructions A,Rn A,direct A,@Ri A,#data Rn,A Rn,direct Rn,#data direct,A direct,Rn direct,direct direct,@Ri direct,#data @Ri,A @Ri,direct @Ri,#data DPTR,#data16 MOVC A,@A+DPTR MOVC A,@A+PC MOVX A,@Ri MOVX A,@DPTR MOVX @Ri,A MOVX @DPTR,A PUSH direct direct A,Rn A,direct A,@Ri XCHD A,@Ri Boolean Instructions SETB SETB C,bit C,/bit C,bit C,/bit C,bit bit,C bit,rel bit,rel bit,rel Jump Instructions ACALL addr11 LCALL addr16 RETI AJMP addr11 LJMP addr16 SJMP @A+DPTR CJNE direct,rel Rotate Left Rotate Left through Carry Rotate Right Rotate Right through Carry Swap Nibbles direct <@Ri> #data direct #data direct direct direct direct direct <@Ri> direct #data <@Ri> <@Ri> direct <@Ri> #data DPTR #data16 code memory[A+DPTR] code memory[A+PC] external memory[Ri] (8-bits address) external memory[DPTR] (16-bits address) external memory[Ri] (8-bits address) external memory[DPTR] (16-bits address) "@'SP', direct direct "@SP": exchange data direct exchange data exchange data exchange nibbles /bit .AND. .AND. /bit .OR. .OR. /bit Jump Jump Jump Jump Jump Call Subroutine only bytes Address Call Subroutine bytes Address Return from subroutine Return from interrupt Jump only bytes Address Jump bytes Address Jump bytes Jump DPTR Jump Jump Jump direct
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
CJNZ CJNZ CJNZ DJNZ DJNZ #data,rel #data,rel @Ri, #data,rel Rn,rel direct,rel Jump #data Jump #data Jump #data Decrement jump zero Decrement jump direct zero Operation
Memory organization
central processing unit (CPU) manipulates operands three memory spaces; there 1024 bytes internal data memory (consisting bytes standard bytes AUX-RAM) bytes internal/external program memory (see FIGURE
Overlapped space
Internal FLASH memory /EA=1 External FLASH memory /EA=0 0080 DIRECT INDIRECT 0000 0000 0000 INDIRECT ONLY DIRECT (SFR) XRAM (OME=1) 02FF XRAM (OME=0)
Program memory
Internal DATA memory
Figure Memory organization SM5964A
External DATA memory
Program memory
program memory SM5964A consists bytes FLASH memory chip. during RESET, held HIGH, SM5964A does execute internal program memory. held during RESET SM5964A fetch instructions from external program memory. FLASH memory SM5964A programmed during program running using ISP. Normally, Writer used programming. feature FLASH memory shown following: READ: byte-wise WRITE: byte-wise within 30us (previously erased chip erase).
ERASE:
Full Erase (64K bytes) within sec. Erased bytes contain Endurance erase write cycles each byte TA=25 Retention years
Program Code Security
MOVC instruction executed from external program memory space will able fetch internal codes from chip program memory after chip protected Writer.
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SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
Internal Data memory
Data memory SM5964A consists 1024 bytes internal data memory (256 bytes standard bytes AUX-RAM). AUX-RAM enable SCONF.1 ($BF.1), read/write MOVX
Internal Control Register (RCON, $85)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 RAMS1 Bit0 RAMS0
SM5964A byte on-chip which accessed external memory addressing method only. instruction MOVX). address space instruction MOVX determined (RAMS1, RAMS0) RCON. default setting RAMS1, RAMS0 bits (page0).
Pulse Width Modulation (PWM)
output pins P1.2 P1.3. clock {FOSC/ (2xDivider)}, output frequency {(PWM clock)/32} bits resolution {(PWM clock)/256} bits resolution. shown below:
PWMC [0:1] ($D3H $D4H)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 PFS1 Bit0 PFS0
PBS: when set, bits resolution. [1:0]: clock divider select.
PFS1 PFS0 clock divider select
PWMD [0:1] ($B3H $B4H)
Bit7 PWMD.7 Bit6 PWMD.6 Bit5 PWMD.5 Bit4 PWMD.4 Bit3 PWMD.3 Bit2 PWMD.2 Bit1 PWMD.1 Bit0 PWMD.0
Two-Wire Series Interface (TWSI)
TWSI module uses (clock) (data) line communicate with external TWSI interface between other TWSI parts. speed 400K (max.) software setting TWSIFS [2:0]. TWSI module used shown below TWSI Status Register:
TWSIS ($C0H)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 RXIF TXIF TFIF NAKIF RXAK MASTER TXAK RXIF: data Receive Interrupt Flag (RXIF) after TWSIRxD (TWSI Receive Data Buffer) loaded with newly receive data. TXIF: data Transmit Interrupt Flag (TXIF) when data TWSITxD (TWSI Transmit Data Buffer) downloaded shift register TWSIA downloaded shift register Master Transmit mode. TFIF: Transmit Fail Interrupt Flag when data transmit fail.
Specifications subject change without notice contact your sales representatives most recent information.
SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
NAKIF: Non-acknowledge Interrupt Flag only master mode when there acknowledge detected after byte data calling address transferred. RXAK: Acknowledge Status indicate bit. When clear, means acknowledge signal been received after complete bits data transmit bus. MASTER: This define this module working master mode. TXAK: Acknowledge status transmit bit. When received complete bits data, this will (NoAck) clear (Ack) transmit master indicate receive status.
TWSIA ($C1H)
Bit7 Bit6 Bit5 Bit4 Bit3 TWSIA.7 TWSIA.6 TWSIA.5 TWSIA.4 TWSIA.3 TWSIA [7:1]: TWSI Address registers bits. EXTADDR: only compare bits when this bit. Bit2 TWSIA.2 Bit1 TWSIA.1 Bit0 EXTADDR
TWSIC1 ($C2H)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWSIE BusBusy TWSIFS2 TWSIFS1 TWSIFS0 TWSIE: enable TWSI module. BusBusy: When start condition detected, this will set. When stop condition detected, this will clear. TWSIFS [2:0]: TWSI speed divider select.
TWSIFS [2:0] Speed Xtal/32 Xtal/64(default) Xtal/128 Xtal/256 Xtal/512 Xtal/1024 Xtal/2048 Xtal/4096
TWSIC2 ($C3H)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MATCH RESTART MATCH: When first received data (following START signal) TWSIRxD register matches with address that address register (TWSIA) set, this will set. SRW: slave mode read (received) wrote (transmit) TWSI bus. When this clear, slave module received data TWSI (SDA). RESTART: This only master mode. master will send start signal then send TWSIA after signal when this setting. TFIF (the NonACK signal received), master mode will release, this will clear. MRW: This determined data transmit direction. this will transmit bit0 Address (Address collection TWSIA [7:1] bits data). When clear this master transmits mode clear receive mode.
TWSITXD ($C4)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWSITxD.7 TWSITxD.6 TWSITxD.5 TWSITxD.4 TWSITxD.3 TWSITxD.2 TWSITxD.1 TWSITxD.0 data written into this register will automatically downloaded shift register when module detects calling address matched received data (Slave transmit mode) when data shift register been transmitted with received acknowledge (RXAK) transmit
Specifications subject change without notice contact your sales representatives most recent information.
SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
mode.
TWSIRXD $C5)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 TWSIRxD.7 TWSIRxD.6 TWSIRxD.5 TWSIRxD.4 TWSIRxD.3 TWSIRxD.2 TWSIRxD.1 TWSIRxD.0 TWSI Receive Data Buffer (TWSIRxD) contains last received data when MATCH flag calling address from master when MATCH flag zero. TWSIRxD register will updated after data byte received previous received data been read out, otherwise TWSI module will pull down line inhabit next data transfer. read-only register. read operation this register will clear RXIF flag. After RXIF flag cleared, register load received data again RXIF flag generate interrupt request reading newly received data.
In-System Programming (ISP)
SM5964A generator flash control signal internal hardware circuit. That only need service code into code area Kbytes divided zones) area lock-bit (N), lock-bit number code area relation ship shown below:
Lock-bit number code area bytes (from $FE00h $FFFF) bytes (from $FC00H $FFFF) bytes (from $FA00H $FFFF) bytes (from $F800H $FFFF) bytes (from $F600H $FFFF) bytes (from $F400H $FFFF) bytes (from $F200H $FFFF) bytes (from $F000H $FFFF)
There three ways into code area: Blank reset: Hardware reset with first flash address blank ($0000H #FFH). Execute "LJMP" instruction. hardware setting:
P2.6 P2.7 10ms P4.3 10ms 10ms 10ms
register:
Specifications subject change without notice contact your sales representatives most recent information.
SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
ISPFAH ($F4H)
Bit7 Bit6 Bit5 Bit4 FA15 FA14 FA13 FA12 FA15 FA8: flash address-high function Bit3 FA11 Bit2 FA10 Bit1 Bit0
ISPFAL ($F5H)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 FA0: flash address-low function ISPFAH ISPFAL provide 16-bits flash memory address function. flash memory address should include service program space address. flash memory address indicated ISPFAH ISPFAL registers overlay with service program space address, flash program/page erase function executed thereafter will have effect.
ISPFD ($F6H)
Bit7 Bit6 Bit5 Bit4 FD0: flash data function ISPFD provide 8-bits data function. Bit3 Bit2 Bit1 Bit0
ISPC ($F7H)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 START ISPF[1: function select START: function start start function which indicated (ISPF1, ISPF0) operation Bit1 ISPF1 Bit0 ISPF0
START read-only default, software must write three specific values 55H, sequentially ISPFD register enable START write attribute. That
ExOpen function: ISPFD, #55H ISPFD, #0AAH ISPFD, #55H
attempt START will allowed without procedure above. After START then SM5964A hardware circuit will latch address data hold program counter until START reset when function finished. User does need check START status software method
ISPF [1:0] function Byte Program Chip Protect Page erase (512 Bytes) Chip Erase
ISPF[1:0]: function select bits page flash memory bytes. perform byte program page erase function, user need specify flash address first. When performing page erase function, SM5964A will erase entire page which flash address indicated ISPFAH registers located within page. perform chip erase function, SM5964A will erase flash program memory data flash memory except
Specifications subject change without notice contact your sales representatives most recent information.
SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
service program space lock been configured. Also, SM5964A will un-protect flash memory automatically. perform chip protect function, flash memory will read zero. e.g. service program byte program program data #22H address $1005H
ISPFD, #55H ISPFD, #0AAH ISPFD, #55H SCONF, #04H ISPFAH, #10H ISPFAL, #05H ISPFD, #22H ISPFC, #80H open function enable SM5964A function flash address-high, flash address-low, flash data programmed, data start program data flash address $1005H after byte program finished, START ISPC will reset automatically program counter then point next instruction
Power Down Wake (PDWU) function
device into Power Down mode writing PCON.1. instruction that does this will last instruction executed before device goes into Power Down mode. Power Down mode, clocks stopped device comes halt. activity completely stopped power consumption reduced lowest possible value. this state PSEN pins pulled low. port pins output values held their respective SFRs.
PCON ($87H)
Bit7 Bit6 Bit5 Bit4 Bit3 SMOD SMOD: This make UART baud-rate double. GF1: General-purpose flag bit. GF0: General-purpose flag bit. When will into Power Down mode IDLE: When will into IDLE mode Bit2 Bit1 Bit0 IDLE
SCONF ($BFH)
Bit4 PDWUE PDWUE: When `1', enable PDWU function. ISPE: When `1', enable function. Bit7 Bit6 Bit5 Bit3 Bit2 ISPE Bit1 Bit0 ALEI
($A8H)
Bit7 Bit6 Bit5 Bit4 When `1', enable interrupt global. ET2: When `1', enable Timer2 interrupt. ES0: When `1', enable UART interrupt. ET1: When `1', enable Timer1 interrupt. EX1: When `1', enable external interrupt ET0: When `1', enable Timer0 interrupt. EX0: When `1', enable external interrupt Bit3 Bit2 Bit1 Bit0
($A9H)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 ETWSI Bit0
Specifications subject change without notice contact your sales representatives most recent information.
SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
ETWSI: When `1', enable TWSI interrupt.
($AAH)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 TWSIIF Bit0
TWSIIF: When `1', enable TWSI interrupt flag.
TCON ($88H)
Bit7 Bit6 Bit5 TF1: Timer overflow flag. TR1: Timer control bit. TF0: Timer overflow flag. TR0: Timer control bit. IE1: External Interrupt edge flag. IT1: Interrupt type control bit. IE0: External Interrupt edge flag. IT0: Interrupt type control bit. Bit4 Bit3 Bit2 Bit1 Bit0
TMOD ($89H)
Bit7 Bit6 Bit5 Bit4 GATE Note: High bits Timer1, bits Timer0. Bit3 GATE Bit2 Bit1 Bit0
GATE: Gating control when set. Timer/Counter enabled only while "INTx" high "TRx" control set. when cleared Timer enabled whenever "TRx" control set. C/T: Timer Counter Selector cleared Timer operation (input from in=ternal system clock.) Counter operation (input from "Tx" input pin). Mode OPERATING 13-bit Timer Mode. 8-bit Timer/Counter with 5-bit prescaler. 16-bit Timer Mode. 16-bit Timer/Counters cascaded; there prescaler. 8-bit Auto Reload. 8-bit auto-reload Timer/Counter holds value which reloaded into each time overflows. Split Timer Mode (Timer 8-bit Timer/Counter controlled standard Timer control bits. 8-bit timer only controlled Timer control bits. (Timer Timer/Counter stopped.
($B8H)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
PT2: Timer2 interrupt priority. PS0: UART interrupts priority. PT1: Timer1 interrupt priority. PX1: external interrupt priority. PT0: Timer0 interrupt priority.
Specifications subject change without notice contact your sales representatives most recent information.
SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
PX0: external interrupt priority.
IP1($B9H)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 PTWSI Bit0
PTWSI: When `1', enable TWSI interrupt priority.
Priority structure vector locations interrupts:
Source External interrupt Timer overflow External interrupt Timer overflow UART interrupt Timer overflow TWSI Flag RI+TI TF2+EXF2 RXIF+ TXIF+ TFIF+ NAKIF Priority level 1(highest) Vector Address
T2MOD ($C9H)
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 T2OE Bit0 DCEN
T2OE: Timer2 clock Output Enable bit. Timer2 clock will output P1.0. DCEN: Down Count Enable. When this then allows Timer2 configured up/down counter.
Application Reference
X'tal X'tal Note: 3MHz open 16MHz open Valid SM5964A 6MHz 9MHz open open 25MHz open
12MHz open
X'tal
SM5964A
Oscillation circuit differs with different crystal ceramic resonator higher oscillation frequency which each crystal ceramic resonator characteristics. User should check with crystal ceramic resonator manufacturer appropriate value external components.
Specifications subject change without notice contact your sales representatives most recent information.
SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
PDIP (600mil) Package Information
Symbol
Dimension
0.254 3.683 0.356 0.356 1.016 1.016 0.203 0.203 52.07 14.99 13.69 15.75 2.921 1.727 1.651
Dimension
2050
3.810 0.500 0.457 1.270 1.321 0.254 0.254 52.2 15.24 13.87 2.540 16.26 3.302 1.981 1.778
3.937 0.660 0.508 1.524 1.626 0.432 0.356 52.32 15.49 13.94 16.76 3.683 2.235 1.905
2055
2060
Note: Refer JEDEC STD.MS-011(AC). Dimension include mold protrusion. Allowable protrusion 0.25 side. maximum plastic body size dimension include mold mismatch. Dimension does include dambar protrusion. Allowable dambar protrusion shall cause lead width exceed maximum dimension more than 0.2mm.
Specifications subject change without notice contact your sales representatives most recent information.
SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
PLCC Package Information
UNIT SYMBOL
INCH(REF)
0.180(MAX) 0.024 ±0.005 0.105 ±0.005 0.018 0.004 0.002 0.028 0.004 0.002 0.010(TYP) 0.690 ±0.010 0.653 ±0.003 0.610 ±0.020 0.690 ±0.010 0.653 ±0.003 0.610 ±0.010 0.050(TYP) 0.003(MAX) 0~5°
MM(BASE)
4.572(MAX) 0.52 ±0.14 2.667 ±0.127 0.457 0.102 0.051 0.711 0.102 0.051 0.254(TYP) 17.526 ±0.254 16.586 ±0.076 15.494 ±0.508 17.526 ±0.254 16.586 ±0.076 15.494 ±0.254 1.270(TYP) 0.076(MAX) 0~5°
Specifications subject change without notice contact your sales representatives most recent information.
SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded
44L(10x10x2.0mm) Package Information
Symbol
Note: Refer JEDC STD.MS-022(AB). Dimension include mold protrusion. Allowable protrusion 0.25mm side.E1 maximum plastic body size dimension include mold mismatch Dimension does include dambar protrusion .Allowable dambar protrusion shall cause lead width exceed maximum dimension more than
Dimension
0.05 1.90 0.29 0.29 0.11 0.11 13.00 9.90 0.73 1.50
Dimension
74.8 11.4 11.4 28.7 59.1
0.15 2.00 0.32 0.30 0.17 0.15 13.20 10.00 0.800 0.88 1.60
2.45 0.25 2.10 0.45 0.41 0.23 0.19 13.40 10.10 1.03 1.70 0.076
78.7 12.6 11.8 31.5 34.6 63.0
82.7 17.7 16.1 40.6 66.9
Specifications subject change without notice contact your sales representatives most recent information.
SM5964A 10/2006
SM5964A
8-Bit Micro-controller With 64KB Flash TWSI embedded writer list
Company Advantech No.98, Ming-Chung Rd., Shin-Tien City, Taipei, Taiwan, site: http://www.aec.com.tw Hi-Lo Guang Rd., Taipei, Taiwan, ROC. site: http://www.hilosystems.com.tw Leap F1-4, Lane 609, Chunghsin Rd., Sec. Sanchung, Taipei Hsien, Taiwan, site: http://www.leap.com.tw Xeltek Electronic Co., Hongwu Road, Nanjing, China 210002 site: http://www.xeltek-cn.com Contact info Tel:02-22182325 Fax:02-22182435 E-mail: aecwebmaster@advantech.com.tw Programmer Model Number Tool 48XP Tool (1*8)
Tel:02-87923301 Fax:02-87923285 E-mail: support@hilosystems.com.tw
(1*1) Gang (1*8)
Tel:02-29991860 Fax:02-29990015 E-mail: service@leap.com.tw
Leap-48 (1*1) 2000 (1*8)
Tel:+86-25-84408399, 84543153-206 E-mail: xelclw@jlonline.com, xelgbw@jlonline.com
Superpro/2000 (1*1) Superpro/280U (1*1) Superpro/L+(1*1)
Specifications subject change without notice contact your sales representatives most recent information.
SM5964A 10/2006
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