SLLS318A
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SN75LVDS84/5 - SN75LVDS84/5
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SN75LVDS86A FLATLINKRECEIVER
3:21 Data Channel Expansion Million Bytes Second Throughput Suited SVGA, XGA, SXGA Display Data Transmission From Controller Display With Very Data Channels Clock Low-Voltage Differential Channels Data Clock Low-Voltage Channels Operates From Single 3.3-V Supply Tolerates 4-kV Packaged Thin Shrink Small-Outline Package (TSSOP) With 20-Mil Terminal Pitch Consumes Less Than When Disabled Wide Phase-Lock Input Frequency Range External Components Required Inputs Meet Exceed Standard Requirements ANSI EIA/TIA-644 Standard Improved Replacement DS90C364 SN75LVDS86 Improved Jitter Tolerance
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description
LVDSGND LVDSVCC LVDSGND CLKINM CLKINP LVDSGND PLLGND PLLVCC PLLGND SHTDN CLKOUT
SN75LVDS86A FlatLink receiver contains connected three serial-in 7-bit parallel-out shift registers four low-voltage differential signaling (LVDS) line receivers single integrated circuit. These functions allow receipt synchronous data from compatible transmitter, such SN75LVDS81, '83, '84, '85, over four balanced-pair conductors expansion bits single-ended low-voltage LVTTL synchronous data lower transfer rate. When receiving, high-speed LVDS data received loaded into registers seven times LVDS input clock (CLKIN) rate. data then unloaded 21-bit wide LVTTL parallel CLKIN rate. SN75LVDS86A presents valid data falling edge output clock (CLKOUT). SN75LVDS86A requires only four line-termination resistors differential inputs little control. data appears same input transmitter output receiver with data transmission transparent user(s). only user intervention possible shutdown/clear (SHTDN) active-low input inhibit clock shut LVDS receivers lower power consumption. level this signal clears internal registers level. SN75LVDS86A characterized operation over ambient free-air temperatures 70_C.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. FlatLink trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1999, Texas Instruments Incorporated
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functional block diagram
Serial-In/ParallelOut Shift Register Serial
Serial-In/ParallelOut Shift Register Serial
Serial-In/ParallelOut Shift Register Serial
Control Logic SHTDN
Clock Generator CLKINP CLKINM Clock
Clock
CLKOUT
Input
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SN75LVDS86A FLATLINKRECEIVER
CLKIN
Previous Cycle
D0-1
Current Cycle
Next Cycle
D6+1
D7-1
D13+1
D14-1
D20+1
CLKOUT
Figure SN75LVDS86A Load Shift Timing Sequences
equivalent input output schematic diagrams
INPUT SHTDN
INPUT
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OUTPUT
Output
SN75LVDS86A FLATLINKRECEIVER
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, (see Note Voltage range terminal Electrostatic discharge (see Note pins (Class pins (Class Continuous total power dissipation Dissipation Rating Table Storage temperature range, Tstg 65_C 150_C Lead temperature (1/16 inch) from case seconds 260_C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: voltage values with respect terminals unless otherwise noted. This rating measured using MIL-STD-883C Method, 3015.7. DISSIPATION RATING TABLE PACKAGE 25°C POWER RATING DERATING FACTOR ABOVE 25°C 70°C POWER RATING
1316 13.1 mW/°C This inverse junction-to-ambient thermal resistance when board mounted with flow.
recommended operating conditions (see Figure
Supply voltage, High-level input voltage, (SHTDN) Low-level input voltage, (SHTDN) Magnitude differential input voltage, |VID| Common-mode input voltage, Operating free-air temperature, UNIT
timing requirements
Cycle time, input clock, Parameter defined mean duration minimum clock cycles. 14.7 32.4 UNIT
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electrical characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER VIT+ VIT- Positive-going differential input threshold voltage Negative-going differential input threshold voltage High-level output voltage Low-level output voltage Disabled, Enabled, Quiescent current (average) inputs 15.38 -100 TEST CONDITIONS UNIT
Enabled, Grayscale pattern (see Figure 15.38 Enabled, Worst-case pattern (see Figure 15.38
High-level input current (SHTDN) Low-level input current (SHTDN) Input current inputs
High-impedance output current typical values 25°C. algebraic convention, which less-positive (more-negative) limit designated minimum, used this data sheet negative-going input voltage threshold only.
switching characteristics over recommended operating conditions (unless otherwise noted)
PARAMETER Setup time, CLKOUT Data hold time, CLKOUT TEST CONDITIONS pFSee Figure pF,See 15.38 0.2%), |Input clock jitter| 15.38 0.2%), 25°C Figure Figure UNIT
t(RSKM) Receiver input skew (see Figure tdis Delay time, CLKIN CLKOUT (see Figure Enable time, SHTDN phase lock Disable time, SHTDN state Transition time, output (10% (data only)
Transition time, output (10% (clock only) Pulse duration, output clock 0.50 typical values 25°C. parameter t(RSKM) timing margin available allocate transmitter interconnection skews clock jitter. value this parameter clock periods other than 15.38 calculated from tRSKM tc/14 |Input clock jitter| magnitude change input clock period.
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PARAMETER MEASUREMENT INFORMATION
VIAM
VIAP (VIAP VIAM)/2
Figure Voltage Definitions
CLKIN/CLKOUT D18, OTHERS NOTE 16-grayscale test-pattern test device power consumption typical display pattern.
Figure 16-Grayscale Test-Pattern Waveforms
CLKIN/CLKOUT Even NOTE worst-case test pattern produces nearly maximum switching frequency LVTTL outputs.
Figure Worst-Case Test-Pattern Waveforms
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SN75LVDS86A FLATLINKRECEIVER
PARAMETER MEASUREMENT INFORMATION
CLKOUT
Figure Setup Hold Time Waveforms
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PARAMETER MEASUREMENT INFORMATION
Tektronix HFS9003/HFS9DG1 Stimulus System (repeating patterns 1110111 0001000)
CLKIN
Device Under Test (DUT)
CLKOUT
Tektronix Microwave Logic Multi-BERT-100RX Word Error Detector
Internal Strobing Position (RSKM) (see Note tsu1 (RSKM) (see Note
CLKIN
CLKOUT
CLKIN
-300
CLKOUT NOTE CLKIN advanced delayed with respect data until errors observed receiver outputs. advance delay then reduced until there data errors observed. magnitude advance delay t(RSKM).
Figure Receiver Input Skew Margin, Setup/Hold Time, Delay Time Definitions
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SN75LVDS86A FLATLINKRECEIVER
PARAMETER MEASUREMENT INFORMATION
CLKIN
SHTDN
CLKIN tdis SHTDN
CLKOUT
Invalid
Valid
Figure Enable Time Waveforms
Figure Disable Time Waveforms
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TYPICAL CHARACTERISTICS
SUPPLY CURRENT CLOCK FREQUENCY
Supply Current
Grayscale Data Pattern 25°C
fclk Clock Frequency
Figure Grayscale Clock Frequency
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APPLICATION INFORMATION
Host SN75LVDS84/5 Cable Flat Panel Display SN75LVDS86A CLKOUT Graphics Controller 12-BIT RED0 RED1 RED2 RED3 GREEN0 GREEN1 GREEN2 GREEN3 BLUE0 BLUE1 BLUE2 BLUE3 H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK
CLKOU
CLKINM
CLKOUTP
CLKINP
NOTES: four 100- terminating resistors recommended 0603 types. applicable, these unused inputs should left open.
Figure 18-Bit Color Host Flat Panel Display Application
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SN75LVDS86A FLATLINKRECEIVER
APPLICATION INFORMATION
Host SN75LVDS81/83 Cable Flat Panel Display SN75LVDS86A CLKOUT Graphics Controller 12-BIT RED0 RED1 RED2 RED3 GREEN0 GREEN1 GREEN2 GREEN3 BLUE0 BLUE1 BLUE2 BLUE3 H_SYNC V_SYNC ENABLE CLOCK 18-BIT RED0 RED1 RED2 RED3 RED4 RED5 GREEN0 GREEN1 GREEN2 GREEN3 GREEN4 GREEN5 BLUE0 BLUE1 BLUE2 BLUE3 BLUE4 BLUE5 H_SYNC V_SYNC ENABLE CLOCK
CLKOU100 CLKOUTP
CLKINM
CLKINP
NOTES: four 100- terminating resistors recommended 0603 types. applicable, these unused inputs should left open.
Figure 24-Bit Color Host 18-Bit Color Panel Display Application FLatLink Designer's Guide (SLLA012) more application information.
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MECHANICAL INFORMATION
(R-PDSO-G**)
SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,50
0,27 0,17
0,08
6,20 6,00
8,30 7,90
0,15
Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
12,60
14,10
17,10
12,40
13,90
16,90 4040078 12/97
NOTES:
linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold protrusion exceed 0,15. Falls within JEDEC MO-153
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IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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