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Stratix Device Handbook, Volume
Innovation Drive Jose, 95134 (408) 544-7000 www.altera.com
SGX5V3-1.2
Copyright 2006 Altera Corporation. rights reserved. Altera, Programmable Solutions Company, stylized Altera logo, specific device designations, other words logos that identified trademarks and/or service marks are, unless noted otherwise, trademarks service marks Altera Corporation U.S. other countries. other product service names property their respective holders. Altera products protected under numerous U.S. foreign patents pending applications, maskwork rights, copyrights. Altera warrants performance semiconductor products current specifications accordance with Altera's standard warranty, reserves right make changes products services time without notice. Altera assumes responsibility liability arising application information, product, service described herein except expressly agreed writing Altera Corporation. Altera customers advised obtain latest version device specifications before relying published information before placing orders products services.
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Contents
Chapter Revision Dates About This Handbook
Contact Altera Typographic Conventions
Section Configuration Remote System Upgrades
Revision History Section
Chapter Configuring Stratix Stratix Devices
Introduction Device Configuration Overview MSEL[2.0] Pins VCCSEL Pins PORSEL Pins nIO_PULLUP Pins nCEO Pins Configuration File Size Altera Configuration Devices Configuration Schemes Configuration Configuration 1-21 Configuration 1-30 JTAG Programming Configuration 1-36 JTAG Programming Configuration Multiple Devices 1-39 Configuration with JRunner Software Driver 1-41 STAPL Programming Test Language 1-42 Configuring Using MicroBlaster Driver 1-51 Device Configuration Pins 1-51
Chapter Remote System Configuration with Stratix Stratix Devices
Introduction Remote Configuration Operation Remote System Configuration Modes Remote System Configuration Components Quartus Software Support 2-12 altremote_update Megafunction 2-14 Remote Update WYSIWYG ATOM 2-17
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Contents
Using Enhanced Configuration Devices Local Update Programming File Generation Remote Update Programming File Generation Combining Devices Flash Memory Using External Processor Conclusion
2-19 2-21 2-32 2-42 2-43 2-44
Section Design Guidelines
Revision History Section II-1
Chapter Transitioning APEX Designs Stratix Stratix Devices
Introduction General Architecture Logic Elements MultiTrack Interconnect DirectDrive Technology Architectural Element Names TriMatrix Memory Same-Port Read-During-Write Mode 3-10 Mixed-Port Read-During-Write Mode 3-11 Memory Megafunctions 3-12 FIFO Conditions 3-13 Design Migration Mode Quartus Software 3-13 Block 3-16 Block Megafunctions 3-16 PLLs Clock Networks 3-18 Clock Networks 3-18 PLLs 3-19 Structure 3-25 External Interfacing 3-25 Standard Support 3-26 High-Speed Differential Standards 3-26 altlvds Megafunction 3-29 Configuration 3-30 Configuration Speed Schemes 3-30 Remote Update Configuration 3-31 JTAG Instruction Support 3-31 Conclusion 3-32
Chapter Stratix Board Design Guidelines
Introduction Board Design Overview Support Circuitry Design Clock Circuitry Isolated Power Ground Plane Design
Stratix Device Handbook, Volume
Altera Corporation
Contents
Power Circuitry Decoupling Circuitry Design 4-13 Plane Capacitance 4-21 Plane Island Design 4-24 Transmission Lines 4-33 Transmission Line Topologies 4-33 Transmission Line Termination 4-52 Transmission Line Routing 4-58 Other Transmission Line Issues 4-64 Miscellaneous 4-76 Component Selection High-Speed Design 4-76 S-Parameters 4-79 Smith Chart 4-81 Versus Coupling 4-82 Unused Connections 4-84 Power Trace Thickness 4-84
Chapter Quartus Software Fitter Warnings
Suppressing Fitter Warnings Design Suggestions
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Stratix Device Handbook, Volume
Contents
Stratix Device Handbook, Volume
Altera Corporation
Chapter Revision Dates
chapters this book, Stratix Device Handbook, Volume were revised following dates. Where chapters groups chapters available separately, part numbers listed.
Chapter Configuring Stratix Stratix Devices Revised: July 2005 Part number: S52013-3.2 Chapter Remote System Configuration with Stratix Stratix Devices Revised: September 2004 Part number: S52015-3.1 Chapter Transitioning APEX Designs Stratix Stratix Devices Revised: July 2005 Part number: S52012-3.0 Chapter Stratix Board Design Guidelines Revised: February 2005 Part number: SGX53001-1.0 Chapter Quartus Software Fitter Warnings Revised: March 2005 Part number: SGX53002-1.0
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Chapter Revision Dates
Stratix Device Handbook, Volume
viii
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About This Handbook
This handbook provides comprehensive information about Altera® Stratix® family devices.
Contact Altera
Information Type
Technical support
most up-to-date information about Altera products, Altera world-wide site www.altera.com. technical support this product, www.altera.com/mysupport. additional information about Altera products, consult sources shown below. Canada
www.altera.com/mysupport/ (800) 800-EPLD (3753) (7:00 a.m. 5:00 p.m. Pacific Time)
Other Locations
www.altera.com/mysupport/ 408-544-8767 7:00 a.m. 5:00 p.m. (GMT -8:00) Pacific Time www.altera.com literature@altera.com 408-544-7000 7:00 a.m. 5:00 p.m. (GMT -8:00) Pacific Time ftp.altera.com
Product literature Altera literature services Non-technical customer service site
www.altera.com literature@altera.com (800) 767-3753
ftp.altera.com
Typographic Conventions
Visual
Bold Type with Initial Capital Letters bold type
This document uses typographic conventions shown below.
Meaning
Command names, dialog titles, checkbox options, dialog options shown bold, initial capital letters. Example: Save dialog box. External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, software utility names shown bold type. Examples: fMAX, \qdesigns directory, drive, chiptrip.gdf file. Document titles shown italic type with initial capital letters. Example: High-Speed Board Design.
Italic Type with Initial Capital Letters
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Preliminary
Typographic Conventions
Stratix Device Handbook, Volume
Visual
Italic type
Meaning
Internal timing parameters variables shown italic type. Examples: tPIA, Variable names enclosed angle brackets shown italic type. Example: <file name>, <project name>.pof file.
Initial Capital Letters "Subheading Title"
Keyboard keys menu names shown with initial capital letters. Examples: Delete key, Options menu. References sections within document titles on-line help topics shown quotation marks. Example: "Typographic Conventions." Signal port names shown lowercase Courier type. Examples: data1, tdi, input. Active-low signals denoted suffix e.g., resetn. Anything that must typed exactly appears shown Courier type. example: Also, sections actual file, such Report File, references parts files (e.g., AHDL keyword SUBDESIGN), well logic function names (e.g., TRI) shown Courier.
Courier type
etc.
Numbered steps used list items when sequence items important, such steps listed procedure. Bullets used list items when sequence items important. checkmark indicates procedure that consists step only. hand points information that requires special attention. caution indicates required information that needs special consideration understanding should read prior starting continuing with procedure process. warning indicates information that should read prior starting continuing procedure processes angled arrow indicates should press Enter key. feet direct more information particular topic.
Preliminary
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Section Configuration Remote System Upgrades
This section provides information Stratix® Stratix device configuration remote system upgrades. also provides configuration information supported configuration schemes Stratix Stratix devices. This section includes following chapters:
Chapter Configuring Stratix Stratix Devices Chapter Remote System Configuration with Stratix Stratix Devices
Revision History
table below shows revision history Chapters Chapter(s)
Date Version
July 2005, v3.2 September 2004 v3.1
Changes Made
Updated part Stratix Device Handbook update. Added chapter Stratix Device Handbook.
September 2004 v3.1
Added chapter Stratix Device Handbook.
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Section Preliminary
Configuration Remote System Upgrades
Stratix Device Handbook, Volume
Section Preliminary
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Configuring Stratix Stratix Devices
S52013-3.2
Introduction
configure Stratix® Stratix devices using several configuration schemes. configuration schemes either microprocessor, configuration device, download cable. Table 1-1.
Table 1-1. Stratix Stratix Device Configuration Schemes Configuration Scheme
Fast passive parallel (FPP) Passive serial (PS)
Typical
Configuration with parallel synchronous configuration device microprocessor interface where eight bits configuration data loaded every clock cycle. Configuration with serial synchronous microprocessor interface MasterBlastercommunications cable, Blaster, ByteBlasterII, ByteBlasterMV parallel port download cable. Configuration with parallel asynchronous microprocessor interface. this scheme, microprocessor treats target device memory. Configuration using Nios(16-bit ISA) Nios® (32-bit ISA) other embedded processor. Allows update Stratix Stratix device configuration remotely using scheme load data. Passive serial synchronous configuration using Nios other embedded processor. Allows update Stratix Stratix device configuration remotely using scheme load data. Passive parallel asynchronous configuration using Nios other embedded processor. this scheme, Nios microprocessor treats target device memory. Allows update Stratix Stratix device configuration remotely using scheme load data. Configuration through IEEE Std. 1149.1 JTAG pins. perform JTAG configuration with either download cable embedded device. Ability SignalTap® Embedded Logic Analyzer.
Passive parallel asynchronous (PPA) Remote/local update
Remote/local update
Remote/local update
Joint Test Action Group (JTAG)
This chapter discusses configure more Stratix Stratix devices. should used together with following documents:
MasterBlaster Serial/USB Communications Cable Data Sheet Blaster Port Download Cable Development Tools Data Sheet ByteBlaster Parallel Port Download Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheets Configuration Devices SRAM-Based Devices Data Sheet Enhanced Configuration Devices (EPC4, EPC8, EPC16) Data Sheet
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Device Configuration Overview
Remote System Configuration with Stratix Stratix Devices chapter
more information setting device configuration options generating configuration files, Software Setting chapter Volume Configuration Handbook. During device operation, FPGA stores configuration data SRAM cells. Because SRAM memory volatile, must load SRAM cells with configuration data each time device powers After configuration, device must initialize registers pins. After initialization, device enters user mode. Figure shows state device during configuration, initialization, user mode.
Device Configuration Overview
Figure 1-1. Stratix Stratix Configuration Cycle
nCONFIG nSTATUS CONF_DONE DCLK DATA High-Z User Pins INIT_DONE MODE Configuration Configuration Initialization User High-Z High-Z User
Notes Figure 1-1:
During initial power configuration, CONF_DONE low. After configuration, CONF_DONE goes high. device reconfigured, CONF_DONE goes after nCONFIG driven low. User pins tri-stated during configuration. Stratix Stratix devices also have weak pull-up resistor pins during configuration that enabled nIO_PULLUP. After initialization, user pins perform function assigned user's design. INIT_DONE used, will high because external resistor pull-up when nCONFIG during beginning configuration. Once option enable INIT_DONE programmed into device (during first frame configuration data), INIT_DONE will low. DCLK should left floating. should driven high low. DATA0 should left floating. should driven high low.
load configuration data Stratix Stratix device using passive configuration scheme. When using passive configuration scheme, Stratix Stratix device incorporated into system with intelligent host, such microprocessor, that controls configuration process. host supplies configuration data from storage device (e.g., hard disk, RAM, other system memory). When using passive configuration, change target device's
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Altera Corporation July 2005
Configuring Stratix Stratix Devices
functionality while system operation reconfiguring device. also perform in-field upgrades distributing programming file system users. following sections describe MSEL[2.0], VCCSEL, PORSEL, nIO_PULLUP pins used Stratix Stratix device configuration.
MSEL[2.0] Pins
select Stratix Stratix device configuration scheme driving MSEL2, MSEL1, MSEL0 pins either high low, shown Table 1-2.
Table 1-2. Stratix Stratix Device Configuration Schemes Description
configuration configuration configuration Remote/local update Remote/local update Remote/local update JTAG-based configuration Notes Table 1-2:
These schemes require that drive secondary RUnLU specify whether perform remote update local update. leave MSEL pins floating. Connect them GND. These pins support non-JTAG configuration scheme used production. only JTAG configuration used should connect MSEL pins ground. JTAG-based configuration takes precedence over other configuration schemes, which means MSEL pins ignored.
MSEL2
MSEL1
MSEL0
MSEL[] pins tied VCCIO bank they reside ground.
VCCSEL Pins
configure Stratix Stratix devices using 3.3-, 2.5-, 1.8-, 1.5-V LVTTL standard configuration JTAG input pins. VCCSEL dedicated input Stratix Stratix devices that selects between 3.3-V/2.5-V input buffers 1.8-V/1.5-V input buffers dedicated configuration input pins. logic supports 3.3-V/2.5-V signaling, logic high supports 1.8-V/1.5-V signaling. logic high also support 3.3-V/2.5-V signaling. VCCSEL affects configuration
Altera Corporation July 2005 Stratix Device Handbook, Volume
Device Configuration Overview
related banks where following pins reside: TDI, TMS, TCK, TRST, MSEL0, MSEL1, MSEL2, nCONFIG, nCE, DCLK, PLL_ENA, CONF_DONE, nSTATUS. VCCSEL pulled 1.5, 1.8, 2.5, 3.3-V logic high level. There internal 2.5-k pull-down resistor VCCSEL. Therefore, using pull-up resister pull this signal, need resistor. VCCSEL also sets power-on-reset (POR) trip point configuration related banks ensuring that these banks have powered appropriate voltage levels before configuration begins. Upon power-up, FPGA does release nSTATUS until VCCINT VCCIOs configuration banks above their trip points. VCCSEL ground (logic low), this sets trip point configuration banks voltage consistent with 3.3-V/2.5-V signaling. When VCCSEL trip point these banks high VCCIO configuration banks voltage supplied this bank(s) never reach trip point, which will allow FPGA begin configuration. VCCIO banks configuration signals used require 3.3-V 2.5-V signaling should VCCSEL (logic high) order lower trip point enable successful configuration.
Table shows should VCCSEL depending VCCIO setting configuration banks your configuration input signaling voltages.
Table 1-3. VCCSEL Setting VCCIO (banks 3,4,7,8)
3.3-V/2.5-V 1.8-V/1.5-V 3.3-V/2.5-V
Configuration Input Signaling Voltage
3.3-V/2.5-V 3.3-V/2.5-V/1.8-V/1.5-V 1.8-V/1.5-V
VCCSEL
Supported
VCCSEL signal does control dual-purpose pins, including dual-purpose configuration pins, such DATA[7.0] pins (nWS, nRS, nCS, RDYnBSY). During configuration, these dual-purpose pins drive voltage levels corresponding VCCIO supply voltage that powers bank containing pin. After configuration, dual-purpose pins inherit standards specified design.
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Configuring Stratix Stratix Devices
PORSEL Pins
PORSEL dedicated input used select delay times during power-up. When PORSEL connected ground, time when PORSEL connected VCC, time There internal 2.5-k pull-down resistor PORSEL. Therefore using pull-up resistor pull this signal, need resistor. When using enhanced configuration devices configure Stratix devices, make sure that PORSEL setting Stratix device same faster than PORSEL setting enhanced configuration device. FPGA powered after enhanced configuration device exits POR, CONF_DONE signal will high since pull-up resistor pulling this signal high. When enhanced configuration device exits POR, enhanced configuration device released pulled high pull-up resistor. Since enhanced configuration device sees nCS/CONF_DONE signal also high, enters test mode. Therefore, must ensure FPGA powers before enhanced configuration device exits POR. more margin, 100-ms setting selected when using enhanced configuration device allow Stratix FPGA power-up before configuration attempted (see Table 1-4).
Table 1-4. PORSEL Settings PORSEL Settings
Time (ms)
nIO_PULLUP Pins
nIO_PULLUP enables built-in weak pull-up resistor pull user pins VCCIO before during device configuration. nIO_PULLUP connected during configuration, weak pullups user pins dual-purpose pins disabled. connected ground, pull-ups enabled during configuration. nIO_PULLUP pulled 1.5, 1.8, 2.5, 3.3-V logic level high. There internal 2.5-k pull-down resistor nIO_PULLUP. Therefore, using pull-up resistor pull this signal, need resistor.
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Stratix Device Handbook, Volume
Configuration File Size
nCEO Pins
nCEO pins drive same voltage levels VCCIO that powers bank where resides. must select VCCIO supply bank containing accordingly. example, when using ByteBlasterMV cable, VCCIO bank containing must powered 3.3-V. current strength
Configuration File Size
Tables summarize approximate configuration file size required each Stratix Stratix device. calculate amount storage space required multi-device configurations, file size each device together.
Table 1-5. Stratix Configuration File Sizes Device
EP1S10 EP1S20 EP1S25 EP1S30 EP1S40 EP1S60 EP1S80
Binary File (.rbf) Size (Bits)
3,534,640 5,904,832 7,894,144 10,379,368 12,389,632 17,543,968 23,834,032
Table 1-6. Stratix Configuration File Sizes Device
EP1SGX10C EP1SGX10D EP1SGX25C EP1SGX25D EP1SGX25F EP1SGX40D EP1SGX40G
Binary File Size (Bits)
3,579,928 3,579,928 7,951,248 7,951,248 7,951,248 12,531,440 12,531,440
should only numbers Tables estimate file size before design compilation. exact file size vary because different Altera® Quartus® software versions slightly
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Configuring Stratix Stratix Devices
different number padding bits during programming. However, specific version Quartus software, design targeted same device same configuration file size.
Altera Configuration Devices
Altera enhanced configuration devices (EPC16, EPC8, EPC4 devices) support single-device configuration solution high-density FPGAs used configuration schemes. They ISP-capable through JTAG interface. enhanced configuration devices divided into major blocks, controller flash memory. information enhanced configuration devices, Enhanced Configuration Devices (EPC4, EPC8 EPC16) Data Sheet Using Altera Enhanced Configuration Devices chapter Configuration Handbook. EPC2 EPC1 configuration devices provide configuration support configuration scheme. EPC2 device ISP-capable through JTAG interface. EPC2 EPC1 cascaded hold large configuration files.
more information EPC2, EPC1, EPC1441 configuration devices, Configuration Devices SRAM-Based Devices Data Sheet. This section describes configure Stratix Stratix devices with following configuration schemes:
Configuration Schemes
Configuration with Configuration Devices Configuration with Download Cable Configuration with Microprocessor Configuration Configuration JTAG Programming Configuration JTAG Programming Configuration Multiple Devices
Configuration
configuration Stratix Stratix devices performed using intelligent host, such MAX® device, microprocessor with flash memory, Altera configuration device, download cable. scheme, external host (MAX device, embedded processor, configuration device, host controls configuration. Configuration data clocked into target Stratix devices DATA0 each rising edge DCLK.
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Stratix Device Handbook, Volume
Configuration Schemes
Configuration with Configuration Devices
configuration device scheme uses Altera configuration device supply data Stratix Stratix device serial bitstream (see Figure 1-3). configuration device scheme, nCONFIG usually tied (when using EPC16, EPC8, EPC4, EPC2 devices, nCONFIG connected nINIT_CONF). Upon device power-up, target Stratix Stratix device senses low-to-high transition nCONFIG initiates configuration. target device then drives open-drain CONF_DONE low, which in-turn drives configuration device's low. When exiting power-on reset (POR), both target configuration device release open-drain nSTATUS pin. Before configuration begins, configuration device goes through delay allow power supply stabilize (power Stratix Stratix device before during time configuration device). This delay maximum EPC2 devices. enhanced configuration devices, select between connecting PORSEL GND, accordingly. During this time, configuration device drives low. This signal delays configuration because connected target device's nSTATUS pin. When target configuration devices complete POR, they release nSTATUS, which then pulled high pull-up resistor. When configuring multiple devices, configuration does begin until devices release their nSTATUS pins. When devices ready, configuration device clocks data serially target devices using internal oscillator. After successful configuration, Stratix FPGA starts initialization using 10-MHz internal oscillator reference clock. After initialization, this internal oscillator turned off. CONF_DONE released target device then pulled high pull-up resistor. When initialization complete, FPGA enters user mode. CONF_DONE must have external 10-k pull-up resistor order device initialize. error occurs during configuration, target device drives nSTATUS low, resetting itself internally resetting configuration device. Auto-Restart Configuration Frame Error option-available Quartus Global Device Options dialog (Assign menu)-is turned device reconfigures automatically error occurs. find this option, choose Compiler Settings (Processing menu), then click Chips Devices tab.
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Configuring Stratix Stratix Devices
this option turned off, external system must monitor nSTATUS errors then pulse nCONFIG restart configuration. external system pulse nCONFIG under system control rather than tied VCC. When configuration complete, target device releases CONF_DONE, which disables configuration device driving high. configuration device drives DCLK before after configuration. addition, configuration device sends data then detects that CONF_DONE gone high, recognizes that target device configured successfully. this case, configuration device pulses microseconds, driving target device's nSTATUS low. Auto-Restart Configuration Frame Error option software, target device resets then pulses nSTATUS low. When nSTATUS returns high, configuration device reconfigures target device. When configuration complete, configuration device drives DCLK low. pull CONF_DONE delay initialization. Instead, Quartus software's Enable User-Supplied Start-Up Clock (CLKUSR) option synchronize initialization multiple devices that same configuration chain. Devices same configuration chain initialize together. When CONF_DONE driven after device configuration, configuration device recognizes that target device configured successfully. Figure shows configure Stratix Stratix device with configuration device.
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Stratix Device Handbook, Volume
Configuration Schemes
Figure 1-2. Single Device Configuration Circuit
Stratix Stratix Device
DCLK DATA0 nSTATUS CONF_DONE nCONFIG MSEL2 MSEL1 MSEL0 nCEO N.C.
Configuration Device
DCLK DATA nINIT_CONF
Notes Figure 1-2:
pull-up resistor should connected same supply voltage configuration device. enhanced configuration devices EPC2 devices have internal programmable pull-ups nCS. should only internal pull-ups configuration device nSTATUS CONF_DONE signals pulled (not external pull-ups used, they should nINIT_CONF available EPC16, EPC8, EPC4, EPC2 devices. nINIT_CONF used, nCONFIG must pulled through resistor. nINIT_CONF internal pull-up resistor that always active EPC16, EPC8, EPC4, EPC2 devices. These devices need external pull-up resistor nINIT_CONF pin.
Figure shows configure multiple Stratix Stratix devices with multiple EPC2 EPC1 configuration devices.
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Configuring Stratix Stratix Devices
Figure 1-3. Multi-Device Configuration Circuit Note
Stratix Stratix Device MSEL2 MSEL1 MSEL0 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Stratix Stratix Device MSEL2 MSEL1 MSEL0 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
EPC1/EPC2 DCLK DATA nCASC nINIT_CONF
EPC1/EPC2 DCLK DATA nINIT_CONF
N.C. nCEO
nCEO
Notes Figure 1-3:
When performing multi-device active serial configuration, must generate configuration device programmer object file (.pof) from each project's SOF. combine multiple SOFs using Quartus software through Device Option dialog box. more information create configuration programming files, Software Settings section Configuration Handbook, Volume pull-up resistor should connected same supply voltage configuration device. enhanced configuration devices EPC2 devices have internal programmable pull-ups nCS. should only internal pull-ups configuration device nSTATUS CONF_DONE signals pulled (not external pull-ups used, they should nINIT_CONF available EPC16, EPC8, EPC4, EPC2 devices. nINIT_CONF used, nCONFIG must pulled through resistor. nINIT_CONF internal pull-up resistor that always active EPC16, EPC8, EPC4, EPC2 devices. These devices need external pull-up resistor nINIT_CONF pin.
After first Stratix Stratix device completes configuration during multi-device configuration, nCEO activates second device's pin, prompting second device begin configuration. Because device CONF_DONE pins tied together, devices initialize enter user mode same time. addition, nSTATUS pins tied together; thus, device (including configuration devices) detects error, configuration stops entire chain. Also, first configuration device does detect CONF_DONE going high configuration, resets chain pulsing microseconds. This pulse drives second configuration device drives nSTATUS Stratix Stratix devices, causing them enter error state. Auto-Restart Configuration Frame Error option turned software, Stratix Stratix device releases nSTATUS pins after reset time-out period. When nSTATUS pins released pulled high, configuration devices reconfigure chain. Auto-
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Configuration Schemes
Restart Configuration Frame Error option turned Stratix Stratix devices drive nSTATUS until they reset with pulse nCONFIG. also cascade several EPC2/EPC1 configuration devices configure multiple Stratix Stratix devices. When data from first configuration device sent, drives nCASC low, which turn drives subsequent configuration device. Because configuration device requires less than clock cycle activate subsequent configuration device, data stream uninterrupted. cannot cascade enhanced (EPC16, EPC8, EPC4) configuration devices.
single configuration chain configure multiple Stratix Stratix devices. this scheme, nCEO first device connected second device chain. there additional devices, connect next device nCEO previous device. configure properly, device CONF_DONE nSTATUS pins must tied together. Figure shows example configuring multiple Stratix Stratix devices using configuration device.
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Configuring Stratix Stratix Devices
Figure 1-4. Configuring Multiple Stratix Stratix Devices with Single Configuration Device Note
Stratix Stratix Device MSEL2 MSEL1 MSEL0 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Stratix Stratix Device MSEL2 MSEL1 MSEL0 DCLK DATA0 nSTATUS CONF_DONE nCONFIG
Configuration Device DCLK DATA nCASC nINIT_CONF
N.C. nCEO
nCEO
Notes Figure 1-4:
When performing multi-device active serial configuration, must generate configuration device programmer object file (.pof) from each project's SOF. combine multiple SOFs using Quartus software through Device Option dialog box. more information create configuration programming files, Software Settings section Configuration Handbook, Volume pull-up resistor should connected same supply voltage configuration device. enhanced configuration devices EPC2 devices have internal programmable pull-ups nCS. should only internal pull-ups configuration device nSTATUS CONF_DONE signals pulled (not external pull-ups used, they should EPC16, EPC8, EPC4 configuration devices cannot cascaded. nINIT_CONF available EPC16, EPC8, EPC4, EPC2 devices. nINIT_CONF used, nCONFIG must pulled through resistor. nINIT_CONF internal pull-up resistor that always active EPC16, EPC8, EPC4, EPC2 devices. These devices need external pull-up resistor nINIT_CONF pin.
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Configuration Schemes
Table shows status device DATA pins during after configuration.
Table 1-7. DATA Status Before After Configuration Stratix Stratix Device Pins During
DATA0 DATA[7.1]
Pins Notes Table 1-7:
status shown configuration with configuration device. function these pins depends upon settings specified Quartus software using Device Option dialog (see Software Settings section Configuration Handbook, Volume Quartus Help software more information).
After
User defined
Used configuration
Used some configuration modes User defined Tri-state User defined
Configuration with Download Cable
configuration with download cable, intelligent host transfers data from storage device Stratix Stratix device through MasterBlaster, USB-Blaster, ByteBlaster ByteBlasterMV cable. initiate configuration this scheme, download cable generates low-to-high transition nCONFIG pin. programming hardware then places configuration data time device's DATA0 pin. data clocked into target device until CONF_DONE goes high. CONF_DONE must have external 10-k pull-up resistor order device initialize. When using programming hardware Stratix Stratix device, turning Auto-Restart Configuration Frame Error option does affect configuration cycle because Quartus software must restart configuration when error occurs. Additionally, Enable User-Supplied Start-Up Clock (CLKUSR) option affect device initialization since this option disabled when programming FPGA using Quartus software programmer download cable. Therefore, turn CLKUSR option, need provide clock CLKUSR when configuring FPGA with Quartus programmer download cable. Figure shows configuration Stratix Stratix device using MasterBlaster, USB-Blaster, ByteBLaster ByteBlasterMV cable.
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Configuring Stratix Stratix Devices
Figure 1-5. Configuration Circuit with Download Cable
Stratix Stratix Device
MSEL2 MSEL1 MSEL0 nCEO CONF_DONE nSTATUS
N.C.
Download Cable 10-Pin Male Header Mode)
DCLK DATA0 nCONFIG
Shield
Notes Figure 1-5:
should connect pull-up resistor same supply voltage MasterBlaster (VIO pin) ByteBlasterMV cable. pull-up resistors DATA0 DCLK pins only needed download cable only configuration scheme used board. This ensure that DATA0 DCLK pins left floating after configuration. example, design also uses configuration device, pull-up resistors DATA0 DCLK pins necessary. header reference voltage MasterBlaster output driver. should match device's VCCIO. This no-connect ByteBlasterMV header.
programming hardware configure multiple Stratix Stratix devices connecting each device's nCEO subsequent device's pin. other configuration pins connected each device chain. Because CONF_DONE pins tied together, devices chain initialize enter user mode same time. addition, because nSTATUS pins tied together, entire chain halts configuration device detects error. this situation, Quartus software must restart configuration; Auto-Restart Configuration Frame Error option does affect configuration cycle. Figure shows configure multiple Stratix Stratix devices with MasterBlaster ByteBlasterMV cable.
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Configuration Schemes
Figure 1-6. Multi-Device Configuration with Download Cable
MSEL0
Stratix Stratix Device
CONF_DONE nSTATUS DCLK
Download Cable 10-Pin Male Header Mode)
MSEL1 MSEL2
DATA0 nCONFIG
nCEO
Stratix Stratix Device
MSEL0 MSEL1 MSEL2 CONF_DONE nSTATUS DCLK
DATA0 nCONFIG
nCEO
N.C.
Notes Figure 1-6:
should connect pull-up resistor same supply voltage MasterBlaster (VIO pin) ByteBlasterMV cable. pull-up resistors DATA0 DCLK pins only needed download cable only configuration scheme used board. This ensure that DATA0 DCLK pins left floating after configuration. example, design also uses configuration device, pull-up resistors DATA0 DCLK pins necessary. reference voltage MasterBlaster output driver. should match device's VCCIO. MasterBlaster Serial/USB Communications Cable Data Sheet this value.
using download cable configure device(s) board that also configuration devices, should electrically isolate configuration devices from target device(s) cable. isolate configuration devices logic, such multiplexer, that select between configuration devices cable. multiplexer device should allow bidirectional transfers nSTATUS CONF_DONE signals. Another option switches five common signals (CONF_DONE, nSTATUS, DCLK, nCONFIG, DATA0) between cable configuration devices. last option remove configuration devices from board when configuring with cable. Figure shows combination configuration device download cable configure Stratix Stratix device.
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Configuring Stratix Stratix Devices
Figure 1-7. Configuring with Combined Configuration Device Scheme
Stratix Stratix Device MSEL0 MSEL1 MSEL2
CONF_DONE nSTATUS DCLK
Download Cable 10-Pin Male Header Mode)
nCEO N.C.
DATA0 nCONFIG
Configuration Device
DCLK DATA nINIT_CONF
Notes Figure 1-7:
should connect pull-up resistor same supply voltage configuration device. pull-up resistors DATA0 DCLK pins only needed download cable only configuration scheme used board. This ensure that DATA0 DCLK pins left floating after configuration. example, design also uses configuration device, pull-up resistors DATA0 DCLK pins necessary. header reference voltage MasterBlaster output driver. should match target device's VCCIO. This no-connect ByteBlasterMV header. should attempt configuration with download cable while configuration device connected Stratix Stratix device. Instead, should either remove configuration device from socket when using download cable place switch five common signals between download cable configuration device. Remove download cable when configuring with configuration device. nINIT_CONF used, nCONFIG must pulled either directly through resistor. external pull-ups used CONF_DONE nSTATUS pins, they should always resistors. internal pull-ups configuration device only CONF_DONE nSTATUS signals pulled-up (not
more information MasterBlaster ByteBlasterMV cables, following documents:
USB-Blaster Port Download Cable Data Sheet MasterBlaster Serial/USB Communications Cable Data Sheet ByteBlasterMV Parallel Port Download Cable Data Sheet ByteBlaster Parallel Port Download Cable Data Sheet
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Configuration Schemes
Configuration with Microprocessor
configuration with microprocessor, microprocessor transfers data from storage device target Stratix Stratix device. initiate configuration this scheme, microprocessor must generate low-to-high transition nCONFIG target device must release nSTATUS. microprocessor programming hardware then places configuration data time DATA0 Stratix Stratix device. least significant (LSB) each data byte must presented first. Data clocked continuously into target device until CONF_DONE goes high. After configuration data sent Stratix Stratix device, CONF_DONE goes high show successful configuration start initialization. CONF_DONE must have external 10-k pullup resistor order device initialize. Initialization, default, uses internal oscillator, which runs MHz. After initialization, this internal oscillator turned off. using clkusr option, after data transferred clkusr must clocked additional times Stratix Stratix device initialize properly. Driving DCLK device after configuration complete does affect device operation. Handshaking signals used configuration modes. Therefore, configuration clock speed must below specified frequency ensure correct configuration. maximum DCLK period exists. pause configuration halting DCLK indefinite amount time. target device detects error during configuration, drives nSTATUS alert microprocessor. microprocessor then pulse nCONFIG restart configuration process. Alternatively, Auto-Restart Configuration Frame Error option turned Quartus software, target device releases nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure target device without needing pulse nCONFIG low. microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration. microprocessor sends data initialization clock starts CONF_DONE INIT_DONE have gone high, must reconfigure target device. default INIT_DONE output disabled. enable INIT_DONE output turning Enable INIT_DONE output option Quartus software. turn Enable INIT_DONE output option Quartus software, advised wait maximum value tCD2UM (see Table 1-8) after CONF_DONE signal goes high ensure device been initialized properly that entered user mode.
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Configuring Stratix Stratix Devices
During configuration initialization, before device enters user mode, microprocessor must drive CONF_DONE signal low. optional CLKUSR used nCONFIG pulled restart configuration during device initialization, need ensure CLKUSR continues toggling during time nSTATUS (maximum µs).
Figure shows circuit configuration with microprocessor. Figure 1-8. Configuration Circuit with Microprocessor
Memory
ADDR DATA0
Stratix Device
MSEL2 CONF_DONE nSTATUS MSEL1 MSEL0 nCEO DATA0 nCONFIG DCLK N.C.
Microprocessor
Configuration Timing
Figure shows configuration timing waveform Stratix Stratix devices. Table shows timing parameters Stratix Stratix devices.
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Configuration Schemes
Table 1-8. Timing Parameters Stratix Stratix Devices Symbol
tCF2CD tCF2ST0 tCF2ST1 tCFG tSTATUS tCF2CK tST2CK tDSU tCLK fMAX tCD2UM
Parameter
nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nCONFIG pulse width nSTATUS pulse width nCONFIG high first rising edge DCLK nSTATUS high first rising edge DCLK
Data setup time before rising edge DCLK Data hold time after rising edge DCLK
Units
DCLK high time DCLK time DCLK period DCLK maximum frequency CONF_DONE high user mode
Notes Table 1-8:
minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR, multiply clock period obtain this value. This value obtainable users delay configuration extending nSTATUS pulse width.
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Configuring Stratix Stratix Devices
Figure 1-9. Timing Waveform Stratix Stratix Devices Note
tCF2ST1 tCFG nCONFIG tCF2CK
nSTATUS
tSTATUS tCF2ST0 tCF2CD tST2CK
CONF_DONE
DCLK DATA tDSU User INIT_DONE High-Z
User Mode
tCD2UM
Notes Figure 1-9:
beginning this waveform shows device user-mode. user-mode, nCONFIG, nSTATUS, CONF_DONE logic high levels. When nCONFIG pulled low, reconfiguration cycle begins. Upon power-up, Stratix device holds nSTATUS time delay. Upon power-up, before during configuration, CONF_DONE low. DCLK should left floating after configuration. should driven high low, whichever convenient. DATA[] available user I/Os after configuration state these pins depends dual-purpose settings.
Configuration
Parallel configuration Stratix Stratix devices meets continuously increasing demand faster configuration times. Stratix Stratix devices receive byte-wide configuration data clock cycle, guarantee configuration time less than with 100MHz configuration clock. Stratix Stratix devices support programming data bandwidth megabits second (Mbps) this mode. parallel configuration with EPC16, EPC8, EPC4 device, microprocessor. This section discusses following schemes configuration Stratix Stratix devices:
Configuration Using Enhanced Configuration Device Configuration Using Microprocessor
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Configuration Schemes
Configuration Using Enhanced Configuration Device
When using with enhanced configuration device, supplies data byte-wide fashion Stratix Stratix device every DCLK cycle. Figure 1-10. Figure 1-10. Configuration Using Enhanced Configuration Devices
Stratix Stratix Device
DCLK DATA[7.0] nSTATUS CONF_DONE nCONFIG MSEL2 MSEL1 MSEL0 nCEO N.C.
Enhanced Configuration Device
DCLK DATA[7.0] nINIT_CONF
Notes Figure 1-10:
pull-up resistors should connected same supply voltage configuration device. enhanced configuration devices EPC2 devices have internal programmable pull-ups nCS. should only internal pull-ups configuration device nSTATUS CONF_DONE signals pulled (not external pull-ups used, they should nINIT_CONF available EPC16, EPC8, EPC4, EPC2 devices. nINIT_CONF used, nCONFIG must pulled through resistor. nINIT_CONF internal pull-up resistor that always active EPC16, EPC8, EPC4, EPC2 devices. These devices need external pull-up resistor nINIT_CONF pin.
enhanced configuration device scheme, nCONFIG tied nINIT_CONF. power target Stratix Stratix device senses low-to-high transition nCONFIG initiates configuration. target Stratix Stratix device then drives open-drain CONF_DONE low, which in-turn drives enhanced configuration device's low. Before configuration starts, there 2-ms delay PORSEL connected enhanced configuration device. PORSEL connected ground, delay When each device determines that power stable, releases nSTATUS pin. Because enhanced configuration device's connected target Stratix Stratix device's nSTATUS pin, configuration delayed until both nSTATUS pins released each device. nSTATUS pins pulled resistor their respective
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Configuring Stratix Stratix Devices
devices once they released. When configuring multiple devices, connect nSTATUS pins together ensure configuration only happens when devices release their nSTATUS pins. enhanced configuration device then clocks data parallel Stratix Stratix device using 66-MHz internal oscillator, drives Stratix Stratix device through EXTCLK pin. there error during configuration, Stratix Stratix device drives nSTATUS low, resetting itself internally resetting enhanced configuration device. Quartus software provides Auto-restart configuration after error option that automatically initiates reconfiguration whenever error occurs. Software Settings chapter Volume Configuration Handbook information turn this option off. this option turned off, must monitor nSTATUS check errors. initiate reconfiguration, pulse nCONFIG low. external system pulse nCONFIG under system control rather than tied VCC. Therefore, nCONFIG must connected nINIT_CONF want reprogram Stratix Stratix device fly. When configuration complete, Stratix Stratix device releases CONF_DONE pin, which then pulled resistor. This action disables EPC16, EPC8, EPC4 enhanced configuration device driven high. Initialization, default, uses internal oscillator, which runs MHz. After initialization, this internal oscillator turned off. When initialization complete, Stratix Stratix device enters user mode. enhanced configuration device drives DCLK before after configuration. CONF_DONE goes high byte early parallel synchronous (FPP) asynchronous (PPA) modes using microprocessor with .rbf, .hex, .ttf file formats. This does apply mode enhanced configuration devices using .pof file format. This also does apply serial modes.
after sending data, enhanced configuration device does detect CONF_DONE going high, recognizes that Stratix Stratix device configured successfully. enhanced configuration device pulses microseconds, driving nSTATUS Stratix Stratix device low. Auto-restart configuration after error option Stratix Stratix device resets then pulses nSTATUS low. When nSTATUS returns high, reconfiguration restarted (see Figure 1-11 page 1-25).
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Configuration Schemes
drive CONF_DONE after device configuration delay initialization. Instead, Enable User-Supplied Start-Up Clock (CLKUSR) option Device Options dialog box. this option synchronize initialization multiple devices that same configuration chain. Devices same configuration chain initialize together. After first Stratix Stratix device completes configuration during multi-device configuration, nCEO activates second Stratix Stratix device's pin, prompting second device begin configuration. Because CONF_DONE pins tied together, devices initialize enter user mode same time. Because nSTATUS pins tied together, configuration stops whole chain device (including enhanced configuration devices) detects error. Also, enhanced configuration device does detect high CONF_DONE configuration, pulses microseconds reset chain. pulse drives nSTATUS Stratix Stratix devices, causing them enter error state. This state similar Stratix Stratix device detecting error. Auto-restart configuration after error option Stratix Stratix devices release their nSTATUS pins after reset time-out period. When nSTATUS pins released pulled high, configuration device reconfigures chain. Auto-restart configuration after error option off, nSTATUS stays until Stratix Stratix devices reset with pulse nCONFIG. Figure 1-11 shows configuration with configuration device timing waveform Stratix Stratix devices.
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Configuring Stratix Stratix Devices
Figure 1-11. Configuration with Configuration Device Timing Waveform Note
nINIT_CONF VCC/nCONFIG OE/nSTATUS nCS/CONF_DONE
tPOR
tDSU
DCLK DATA[7.0] User INIT_DONE
tOEZX
Byte0 Byte1
Byte2 Byte3
Byten
User Mode
Tri-State
Tri-State
Notes Figure 1-11:
timing information, Enhanced Configuration Devices (EPC4, EPC8 EPC16) Data Sheet. configuration device drives DATA high after configuration. Stratix Stratix devices enter user mode clock cycles after CONF_DONE goes high.
Configuration Using Microprocessor
When using microprocessor parallel configuration, microprocessor transfers data from storage device Stratix Stratix device through configuration hardware. initiate configuration, microprocessor needs generate low-to-high transition nCONFIG Stratix Stratix device must release nSTATUS. microprocessor then places configuration data DATA[7.0] pins Stratix Stratix device. Data clocked continuously into Stratix Stratix device until CONF_DONE goes high. configuration clock (DCLK) speed must below specified frequency ensure correct configuration. maximum DCLK period exists. pause configuration halting DCLK indefinite amount time. After configuration data sent Stratix Stratix device, CONF_DONE goes high show successful configuration start initialization. CONF_DONE must have external 10-k pullup resistor order device initialize. Initialization, default, uses internal oscillator, which runs MHz. After initialization, this internal oscillator turned off. using clkusr option, after data transferred clkusr must clocked additional times Stratix Stratix device initialize properly. Driving DCLK device after configuration complete does affect device operation.
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Configuration Schemes
default, INIT_DONE output disabled. enable INIT_DONE output turning Enable INIT_DONE output option Quartus software. turn Enable INIT_DONE output option Quartus software, advised wait maximum value tCD2UM (see Table 1-9) after CONF_DONE signal goes high ensure device been initialized properly that entered user mode. During configuration initialization before device enters user mode, microprocessor must drive CONF_DONE signal low. optional CLKUSR used nCONFIG pulled restart configuration during device initialization, need ensure CLKUSR continues toggling during time nSTATUS (maximum µs).
Stratix Stratix device detects error during configuration, drives nSTATUS alert microprocessor. microprocessor connected nSTATUS must input. microprocessor then pulse nCONFIG restart configuration error. With Auto-restart configuration after error option Stratix Stratix device releases nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure Stratix Stratix device without pulsing nCONFIG low. microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration. microprocessor sends data initialization clock starts CONF_DONE INIT_DONE have gone high, must reconfigure Stratix Stratix device. After waiting specified DCLK cycles, microprocessor should restart configuration pulsing nCONFIG low. Figure 1-12 shows circuit Stratix Stratix parallel configuration using microprocessor.
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Configuring Stratix Stratix Devices
Figure 1-12. Parallel Configuration Using Microprocessor
Memory
ADDR DATA[7.0]
Stratix Device
MSEL2 CONF_DONE nSTATUS MSEL1 MSEL0 nCEO DATA[7.0] nCONFIG DCLK N.C.
Microprocessor
Note Figure 1-12:
pull-up resistors should connected that meets Stratix highlevel input voltage (VIH) specification.
multi-device parallel configuration with microprocessor, nCEO first Stratix Stratix device cascaded second device's pin. second device chain begins configuration within clock cycle; therefore, transfer data destinations transparent microprocessor. Because CONF_DONE pins devices connected together, devices initialize enter user mode same time. Because nSTATUS pins also tied together, devices detects error, entire chain halts configuration drives nSTATUS low. microprocessor then pulse nCONFIG restart configuration. Auto-restart configuration after error option Stratix Stratix devices release nSTATUS after reset time-out period. microprocessor then reconfigure devices once nSTATUS released. Figure 1-13 shows multi-device configuration using microprocessor. Figure 1-14 shows multi-device configuration when both Stratix Stratix devices receiving same data. this case, microprocessor sends data both devices simultaneously, devices configure simultaneously.
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Configuration Schemes
Figure 1-13. Parallel Data Transfer Serial Configuration with Microprocessor
Memory
ADDR DATA[7.0]
Stratix Device
MSEL2 CONF_DONE nSTATUS MSEL1 MSEL0 nCEO DATA[7.0] nCONFIG DCLK
Stratix Device
MSEL2 CONF_DONE nSTATUS nCEO DATA[7.0] nCONFIG DCLK MSEL1 MSEL0 N.C.
Microprocessor
Note Figure 1-13:
should connect pull-up resistors that meets Stratix high-level input voltage (VIH) specification.
Figure 1-14. Multiple Device Parallel Configuration with Same Data Using Microprocessor
Memory
ADDR DATA[7.0]
Stratix Device
MSEL2 CONF_DONE nSTATUS MSEL1 MSEL0 nCEO DATA[7.0] nCONFIG DCLK N.C.
Stratix Device
MSEL2 CONF_DONE nSTATUS nCEO DATA[7.0] nCONFIG DCLK MSEL1 MSEL0 N.C.
Microprocessor
Notes Figure 1-14:
should connect pull-up resistors that meets Stratix high-level input voltage (VIH) specification. nCEO pins left unconnected when configuring same data into multiple Stratix Stratix devices.
more information configuring multiple Altera devices same configuration chain, Configuring Mixed Altera FPGA Chains chapter Configuration Handbook, Volume
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Configuring Stratix Stratix Devices
Configuration Timing
Figure 1-15 shows timing waveforms configuring Stratix Stratix device mode. Table shows timing parameters Stratix Stratix devices. Figure 1-15. Timing Waveform Configuring Devices Mode Note
tCF2ST1 tCFG nCONFIG tCF2CK
nSTATUS
tSTATUS tCF2ST0 tCF2CD tST2CK
CONF_DONE
User Mode
DCLK DATA[7.0} tDSU User INIT_DONE High-Z
User Mode
tCD2UM
Notes Figure 1-15:
beginning this waveform shows device user-mode. user-mode, nCONFIG, nSTATUS, CONF_DONE logic high levels. When nCONFIG pulled low, reconfiguration cycle begins. Upon power-up, Stratix device holds nSTATUS time delay. Upon power-up, before during configuration, CONF_DONE low. DCLK should left floating after configuration. should driven high low, whichever convenient. DATA[] available user I/Os after configuration state these pins depends dual-purpose settings.
Table 1-9. Timing Parameters Stratix Stratix Devices (Part Symbol
tCF2CK tDSU tCFG tCLK
Parameter
nCONFIG high first rising edge DCLK
Data setup time before rising edge DCLK Data hold time after rising edge DCLK
Units
nCONFIG pulse width DCLK high time DCLK time DCLK period
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Configuration Schemes
Table 1-9. Timing Parameters Stratix Stratix Devices (Part Symbol
fMAX tCD2UM tCF2CD tCF2ST0 tCF2ST1 tSTATUS tST2CK
Parameter
DCLK frequency CONF_DONE high user mode nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high nSTATUS pulse width nSTATUS high firstrising edge DCLK
Units
Notes Table 1-9:
minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR, multiply clock period obtain this value. This value obtainable users delay configuration extending nSTATUS pulse width.
Configuration
schemes, microprocessor drives data Stratix Stratix device through download cable. When using scheme, pull-up resistor pull DCLK high prevent unused configuration pins from floating. begin configuration, microprocessor drives nCONFIG high then asserts target device's high. Next, microprocessor places 8-bit configuration word target device's data inputs pulses low. rising edge nWS, target device latches byte configuration data then drives RDYnBSY signal low, indicating that processing byte configuration data. microprocessor then performs other system functions while Stratix Stratix device processing byte configuration data. Next, microprocessor checks nSTATUS CONF_DONE. nSTATUS high CONF_DONE low, microprocessor sends next data byte. nSTATUS low, device signaling error microprocessor should restart configuration. However, nSTATUS high configuration data received, device ready initialization. beginning initialization, CONF_DONE goes high indicate that configuration complete. CONF_DONE must have external 10-k pull-up resistor order device initialize. Initialization, default, uses internal oscillator, which runs MHz. After initialization, this internal oscillator turned off. When initialization complete, Stratix Stratix device enters user mode.
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Configuring Stratix Stratix Devices
Figure 1-16 shows configuration circuit. optional address decoder controls device's pins. This decoder allows microprocessor select Stratix Stratix device accessing particular address, simplifying configuration process. Figure 1-16. Configuration Circuit
Address Decoder ADDR Memory ADDR DATA[7.0] CONF_DONE nSTATUS Microprocessor DATA[7.0] nCONFIG RDYnBSY DCLK nCEO Stratix Device MSEL2 MSEL1 MSEL0 N.C.
Note Figure 1-16:
pull-up resistor should connected same supply voltage Stratix Stratix device.
device's pins toggled during configuration design meets specifications tCSSU, tWSP, tCSH given Table 1-10 page 1-36. microprocessor also directly control signals. signals active state (i.e., tied low) toggle other signal control configuration. Stratix Stratix devices serialize data internally without microprocessor. When Stratix Stratix device ready next byte configuration data, drives RDYnBSY high. microprocessor senses high signal when polls RDYnBSY, microprocessor strobes next byte configuration data into device. Alternatively, signal strobed, causing RDYnBSY signal appear DATA7. Because RDYnBSY does need
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Configuration Schemes
monitored, reading state configuration data strobing saves system port. drive data onto data while because causes contention DATA7. used monitor configuration, should high. simplify configuration, microprocessor wait total time tBUSY (max) tRDY2WS tW2SB before sending next data bit. After configuration, nCS, nRS, nWS, RDYnBSY pins user pins. However, scheme chosen Quartus software, these pins tri-stated default user mode should driven microprocessor. change default settings Quartus software, select Device Option (Compiler Setting menu). Stratix Stratix device detects error during configuration, drives nSTATUS alert microprocessor. microprocessor then pulse nCONFIG restart configuration process. Alternatively, Auto-Restart Configuration Frame Error option turned Stratix Stratix device releases nSTATUS after reset time-out period. After nSTATUS released, microprocessor reconfigure Stratix Stratix device. this point, microprocessor does need pulse nCONFIG low. microprocessor also monitor CONF_DONE INIT_DONE pins ensure successful configuration. microprocessor must monitor nSTATUS detect errors CONF_DONE determine when programming completes (CONF_DONE goes high byte early parallel mode). microprocessor sends configuration data starts initialization CONF_DONE asserted, microprocessor must reconfigure Stratix Stratix device. default, INIT_DONE disabled. enable INIT_DONE output turning Enable INIT_DONE output option Quartus software. turn Enable INIT_DONE output option Quartus software, advised wait maximum value tCD2UM (see Table 1-10) after CONF_DONE signal goes high ensure device been initialized properly that entered user mode. During configuration initialization, before device enters user mode, microprocessor must drive CONF_DONE signal low. optional CLKUSR used nCONFIG pulled restart configuration during device initialization, need ensure that CLKUSR continues toggling during time nSTATUS (maximum
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Configuring Stratix Stratix Devices
also mode configure multiple Stratix Stratix devices. Multi-device configuration similar single-device configuration, except that Stratix Stratix devices cascaded. After configure first Stratix Stratix device, nCEO asserted, which asserts second device, initiating configuration. Because second Stratix Stratix device begins configuration within write cycle first device, transfer data destinations transparent microprocessor. Stratix Stratix device CONF_DONE pins tied together; therefore, devices initialize enter user mode same time. Figure 1-17. Figure 1-17. Multi-Device Configuration Circuit
Address Decoder ADDR Memory
ADDR DATA[7.0]
Stratix Device DATA[7.0] CONF_DONE nSTATUS Microprocessor nCONFIG RDYnBSY
DCLK
Stratix Device DATA[7.0] DCLK CONF_DONE nSTATUS nCEO MSEL2 nCONFIG MSEL1 RDYnBSY MSEL0
nCEO
N.C.
MSEL2 MSEL1 MSEL0
Notes Figure 1-17:
used, connect directly. used, connected directly. Connect pull-up resistor same supply voltage Stratix Stratix device.
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Configuration Schemes
Configuration Timing
Figure 1-18 shows Stratix Stratix device timing waveforms configuration. Figure 1-18. Timing Waveforms Stratix Stratix Devices
tCFG tCF2ST1
nCONFIG nSTATUS CONF_DONE DATA[7.0]
tRDY2WS
Byte
tDSU tCSSU tCF2WS
Byte
Byte
Byte
tCSSU
tWSP tCSH
tSTATUS tCF2ST0 tCF2CD tWS2B tBUSY tCD2UM
RDYnBSY
User I/Os INIT_DONE
High-Z
Notes Figure 1-18:
Upon power-up, nSTATUS held time delay. Upon power-up, before during configuration, CONF_DONE low. After configuration, state nCS, nWS, RDYnBSY depends design programmed into Stratix Stratix device. Device pins user mode.
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Configuring Stratix Stratix Devices
Figure 1-19 shows Stratix Stratix timing waveforms when using strobed signals. Figure 1-19. Timing Waveforms Using Strobed Signals
tCF2ST1 tCFG
nCONFIG nSTATUS
tCF2SCD tCF2ST0 tSTATUS tCSSU
CONF_DONE
tCSH
DATA[7.0]
tWSP tRS2WS
Byte
tDSU
Byte
Byte
INIT_DONE User DATA7/RDYnBSY
tWS2RS tCF2WS tRSD7 tRDY2WS
tWS2RS
tWS2B
tCD2UM tBUSY
Notes Figure 1-19:
user toggle during configuration design meets specification tCSSU, tWSP, tCSH. Device pins user mode. DATA[7.0] pins available user I/Os after configuration state theses pins depends dual-purpose settings. leave DATA[7.0] floating. these pins used user-mode, should drive them high low, whichever more convenient. DATA7 bidirectional pin. represents input data input, represents output show status RDYnBSY.
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Configuration Schemes
Table 1-10 defines Stratix Stratix timing parameters configuration
Table 1-10. Timing Parameters Stratix Stratix Devices Symbol
tCF2WS tDSU tCSSU tCSH tWSP tCFG tWS2B tBUSY tRDY2WS tWS2RS tRS2WS tRSD7 tCD2UM tSTATUS tCF2CD tCF2ST0 tCF2ST1
Parameter
nCONFIG high first rising edge
Data setup time before rising edge Data hold time after rising edge Chip select setup time before rising edge Chip select hold time after rising edge
Units
pulse width nCONFIG pulse width rising edge RDYnBSY RDYnBSY pulse width RDYnBSY rising edge rising edge rising edge falling edge rising edge rising edge falling edge DATA7 valid with RDYnBSY signal CONF_DONE high user mode nSTATUS pulse width nCONFIG CONF_DONE nCONFIG nSTATUS nCONFIG high nSTATUS high
Notes Table 1-10:
minimum maximum numbers apply only internal oscillator chosen clock source starting device. clock source CLKUSR, multiply clock period obtain this value. This value obtained delay configuration extending nstatus pulse width.
information create configuration programming files this configuration scheme, Software Settings section Configuration Handbook, Volume
JTAG Programming Configuration
JTAG developed specification boundary-scan testing. This boundary-scan test (BST) architecture offers capability efficiently test components printed circuit boards (PCBs) with tight lead spacing. architecture test connections without using physical test
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Configuring Stratix Stratix Devices
probes capture functional data while device operating normally. also JTAG circuitry shift configuration data into device.
more information JTAG boundary-scan testing, IEEE 1149.1 (JTAG) Boundary-Scan Testing Altera Devices. SignalTap® embedded logic analyzer, need connect JTAG pins your Stratix device download cable header your PCB.
more information SignalTap Design Debugging Using SignalTap Embedded Logic Analyzer chapter Quartus Handbook, Volume device operating JTAG mode uses four required pins, TDI, TDO, TMS, TCK, optional pin, TRST. four JTAG input pins (TDI, TMS, TRST) have weak, internal pull-up resistors, whose values range from other pins tri-stated during JTAG configuration. begin JTAG configuration until other configuration complete. Table 1-11 shows each JTAG pin's function.
Table 1-11. JTAG Descriptions
Description
Test data input
Function
Serial input instructions well test programming data. Data shifted rising edge TCK. VCCSEL controls input buffer selection. Serial data output instructions well test programming data. Data shifted falling edge TCK. tri-stated data being shifted device. high level output voltage determined VCCIO. Input that provides control signal determine transitions Test Access Port (TAP) controller state machine. Transitions within state machine occur rising edge TCK. Therefore, must before rising edge TCK. evaluated rising edge TCK. VCCSEL controls input buffer selection. clock input circuitry. Some operations occur rising edge, while others occur falling edge. VCCSEL controls input buffer selection. Active-low input asynchronously reset boundary-scan circuit. TRST optional according IEEE Std. 1149.1. VCCSEL controls input buffer selection.
Test data output
Test mode select
Test clock input
TRST Test reset input
(optional)
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Configuration Schemes
During JTAG configuration, data downloaded device through MasterBlaster ByteBlasterMV header. Configuring devices through cable similar programming devices in-system. difference connect TRST ensure that controller reset. Figure 1-20. Figure 1-20. JTAG Configuration Single Device
TRST nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1 MSEL2 DATA0 DCLK
Stratix Stratix Device
MasterBlaster ByteBlasterMV 10-Pin Male Header (Top View)
Notes Figure 1-20:
should connect pull-up resistor same supply voltage download cable. should connect nCONFIG, MSEL0, MSEL1 pins support non-JTAG configuration scheme. only JTAG configuration, connect nCONFIG VCC, MSEL0, MSEL1, MSEL2 ground. Pull DATA0 DCLK high low. reference voltage MasterBlaster output driver. should match device's VCCIO. MasterBlaster Serial/USB Communications Cable Data Sheet this value.
configure single device JTAG chain, programming software places other devices BYPASS mode. BYPASS mode, devices pass programming data from through single bypass register without being affected internally. This scheme enables programming software program verify target device. Configuration data driven into device appears clock cycle later.
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Configuring Stratix Stratix Devices
Stratix Stratix devices have dedicated JTAG pins. perform JTAG testing Stratix Stratix devices before after, during configuration. chip-wide reset output enable pins Stratix Stratix devices affect JTAG boundary-scan programming operations. Toggling these pins does affect JTAG operations (other than usual boundary-scan operation). When designing board JTAG configuration Stratix Stratix devices, should consider regular configuration pins. Table 1-12 shows should connect these pins during JTAG configuration.
Table 1-12. Dedicated Configuration Connections During JTAG Configuration Signal
Description
Stratix Stratix devices chain, should driven connecting ground, pulling resistor, driving some control circuitry. devices that also multi-device configuration chains, pins should connected during JTAG configuration JTAG configured same order configuration chain. Stratix Stratix devices chain, nCEO left floating connected next device. description above. These pins must left floating. These pins support whichever non-JTAG configuration used production. only JTAG configuration used, should both pins ground.
nCEO MSEL nCONFIG nSTATUS
nCONFIG must driven high through JTAG programming process. Driven high connecting pulling high resistor, driven some control circuitry.
Pull 10-k resistor. When configuring multiple devices same JTAG chain, each nSTATUS should pulled individually. nSTATUS pulling middle JTAG configuration indicates that error occurred. Pull 10-k resistor. When configuring multiple devices same JTAG chain, each CONF_DONE should pulled individually. CONF_DONE going high JTAG configuration indicates successful configuration. Should left floating. Drive high, whichever more convenient your board. Should left floating. Drive high, whichever more convenient your board.
CONF_DO DCLK DATA0
JTAG Programming Configuration Multiple Devices
When programming JTAG device chain, JTAG-compatible header, such ByteBlasterMV header, connected several devices. number devices JTAG chain limited only drive capacity download cable. However, when more than five devices connected JTAG chain, Altera recommends buffering TCK, TDI, pins with on-board buffer.
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Configuration Schemes
JTAG-chain device programming ideal when contains multiple devices, when testing using JTAG circuitry. Figure 1-21 shows multi-device JTAG configuration. Figure 1-21. Multi-Device JTAG Configuration Notes (1),
MasterBlaster ByteBlasterMV 10-Pin Male Header
Stratix Device
Stratix Device nSTATUS DATA0 DCLK nCONFIG MSEL2 CONF_DONE MSEL1 MSEL0
Stratix Device nSTATUS DATA0 DCLK nCONFIG MSEL2 CONF_DONE MSEL1 MSEL0
nSTATUS DATA0 DCLK nCONFIG MSEL2 CONF_DONE MSEL1 MSEL0
Notes Figure 1-21:
Stratix, Stratix APEXII, APEX 20K, MercuryTM, ACEX® FLEX® devices placed within same JTAG chain device programming configuration. more information configuration pins connected this mode, Table 1-11 page 1-37. Connect nCONFIG, MSEL0, MSEL1, MSEL2 pins support non-JTAG configuration scheme. only JTAG configuration used, connect nCONFIG VCC, MSEL0, MSEL1, MSEL2 ground. Pull DATA0 DCLK either high low. reference voltage MasterBlaster output driver. should match device's VCCIO. MasterBlaster Serial/USB Communications Cable Data Sheet this value. must connected driven successful JTAG configuration.
must connected driven during JTAG configuration. multi-device configuration chains, first device's connected while nCEO connected next device chain. last device's input comes from previous device, while nCEO left floating. After first device completes configuration multi-device configuration chain, nCEO drives activate second device's pin, which prompts second device begin configuration. Therefore, these devices also JTAG chain, should make sure pins connected during JTAG configuration that devices JTAG configured same order configuration chain. long devices JTAG configured same order multi-device configuration chain, nCEO previous device drives next device when successfully been JTAG configured.
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Quartus software verifies successful JTAG configuration upon completion. software checks state CONF_DONE through JTAG port. CONF_DONE correct state, Quartus software indicates that configuration failed. CONF_DONE correct state, software indicates that configuration successful. VCCIO tied both pins JTAG port drive 3.3-V levels.
attempt JTAG non-JTAG configuration simultaneously. When configuring through JTAG, allow non-JTAG configuration complete first. Figure 1-22 shows JTAG configuration Stratix Stratix device with microprocessor. Figure 1-22. JTAG Configuration Stratix Stratix Devices with Microprocessor
Memory
ADDR DATA
Stratix Stratix Device
MSEL2 MSEL1 nCONFIG MSEL0 DATA0 DCLK nSTATUS CONF_DONE
Microprocessor
Notes Figure 1-22:
Connect nCONFIG, MSEL2, MSEL1, MSEL0 pins support non-JTAG configuration scheme. your design only uses JTAG configuration, connect nCONFIG MSEL2, MSEL1, MSEL0 pins ground. Pull DATA0 DCLK either high low.
Configuration with JRunner Software Driver
JRunner software driver that allows configure Altera FPGAs through ByteBlasterMV download cable JTAG mode. programming input file supported Binary File (.rbf) format. JRunner also requires Chain Description File (.cdf) generated Quartus software. JRunner targeted embedded JTAG configuration. source code been developed Windows operating system. customize code make other platforms.
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more information JRunner software driver, JRunner Software Driver: Embedded Solution JTAG Configuration White Paper file.
STAPL Programming Test Language
JamStandard Test Programming Language (STAPL), JEDEC standard JESD-71, standard file format in-system programmability (ISP) purposes. STAPL supports programming configuration programmable devices testing electronic systems, using IEEE 1149.1 JTAG interface. STAPL freely licensed open standard.
Connecting JTAG Chain Embedded Processor
There ways connect JTAG chain embedded processor. most straightforward method connect embedded processor directly JTAG chain. this method, four processor pins dedicated JTAG interface, saving board space reducing number available embedded processor pins. Figure 1-23 illustrates second method, which connect JTAG chain existing through interface PLD. this method, JTAG chain becomes address existing bus. processor then reads from writes address representing JTAG chain.
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Figure 1-23. Embedded System Block Diagram
Embedded System
to/from ByteBlasterMV
Interface Logic (Optional)
Control adr[19.0] Control d[3.0]
d[7.0]
JTAG Device MAX® 9000, 9000A, 7000S, 7000A, 7000AE, 3000 Device
TRST nSTATUS CONF_DONE nCONFIG MSEL0 MSEL1
Embedded Processor
Control
d[7.0] adr[19.0]
EPROM System Memory
adr[19.0]
MSEL1 MSEL0
Cyclone, FLEX 10K, FLEX 10KA, FLEX10KE, APEX 20K, APEX 20KE Device
DATA0 DCLK nCONFIG
Cyclone FPGA
Notes Figure 1-23:
Connect nCONFIG, MSEL2, MSEL1, MSEL0 pins support non-JTAG configuration scheme. your design only uses JTAG configuration, connect nCONFIG MSEL2, MSEL1, MSEL0 pins ground. Pull DATA0 DCLK either high low.
Both JTAG connection methods should include space MasterBlaster ByteBlasterMV header connection. header useful during prototyping because allows verify modify Stratix Stratix device's contents. During production, remove header save cost.
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Program Flow
Player provides interface manipulating IEEE Std. 1149.1 JTAG state machine. controller 16-state state machine that clocked rising edge TCK, uses control JTAG operation device. Figure 1-24 shows flow IEEE Std. 1149.1 controller state machine.
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Figure 1-24. JTAG Controller State Machine
TEST_LOGIC/ RESET
RUN_TEST/ IDLE
SELECT_DR_SCAN
SELECT_IR_SCAN
CAPTURE_DR
CAPTURE_IR
SHIFT_DR
SHIFT_IR
EXIT1_DR
EXIT1_IR
PAUSE_DR
PAUSE_IR
EXIT2_DR
EXIT2_IR
UPDATE_DR
UPDATE_IR
While Player provides driver that manipulates controller, Byte-Code File (.jbc) provides high-level intelligence needed program given device. instructions that
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send JTAG data device involve moving controller through either data register instruction register state machine. example, loading JTAG instruction involves moving controller SHIFT_IR state shifting instruction into instruction register through pin. Next, controller moved RUN_TEST/IDLE state where delay implemented allow instruction time latched. This process identical data register scans, except that data register state machine traversed. high-level instructions DRSCAN instruction scanning JTAG data register, IRSCAN instruction scanning instruction register, WAIT command that causes state machine idle specified period time. Each controller scanned repeatedly, according instructions file, until target devices programmed. Figure 1-25 illustrates functional behavior Player when parses file. When Player encounters DRSCAN, IRSCAN, WAIT instruction, generates proper data TCK, TMS, complete instruction. flow diagram shows branches DRSCAN, IRSCAN, WAIT instructions. Although Player supports other instructions, they omitted from flow diagram simplicity.
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Figure 1-25. Player Flow Diagram (Part
Start
Pulse Five Times Test-Logic-Reset Pulse Run-Test/Idle Switch WAIT Read Instruction from File Case[] DRSCAN
IRSCAN Pulse Run-Test/Idle Delay Parse Argument Parse Argument
EOF?
Pulse Twice Select-IR-Scan
Pulse Select-DR-Scan Pulse Twice Shift-DR Pulse Write Shift-DR
Pulse Three Times Test-Logic-Reset
Switch
Pulse Twice Shift-IR Pulse Write Shift-IR
Pulse Exit1-IR Pulse Pause-IR Pulse Twice Update-IR Pulse Run-Test/Idle Switch
Shift-IR Pulse Write
Continued Part Flow Diagram
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Figure 1-26. Player Flow Diagram (Part
Continued from Part Flow Diagram
Compare
Case[]
Default Capture
Pulse Store Exit1-DR Loop< Length Pulse Store Exit1-DR Pulse Pulse Update-IR Shift-DR Pulse TCK, Write TDI, Store
Loop< Length Pulse TCK, Write TDI, Store
Correct Value Pulse
Report Error
Pulse Store Exit1-DR
Loop< Length
Run-Test/Idle Switch Pulse Update-IR Pulse Write
Update-IR Pulse Run-Test/Idle Pulse Run-Test/Idle Switch
Switch
Execution program starts beginning program. program flow controlled using GOTO, CALL/RETURN, FOR/NEXT structures. GOTO CALL statements labels that symbolic names program statements located elsewhere program. language itself enforces almost constraints organizational structure control flow program. language does support linking multiple programs together including contents another file into program.
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Instructions
Each statement begins with instruction names listed Table 1-13. instruction names, including names optional instructions, reserved keywords that cannot variable label identifiers program.
Table 1-13. Instruction Names
BOOLEAN CALL DRSCAN DRSTOP EXIT EXPORT GOTO
Note Table 1-13:
This instruction name optional language extension.
INTEGER IRSCAN IRSTOP NEXT NOTE POSTDR POSTIR PREDR
PREIR PRINT PUSH RETURN STATE WAIT VECTOR VMAP
Table 1-14 shows state names that reserved keywords language. These keywords correspond state names specified IEEE Std. 1149.1 JTAG specification.
Table 1-14. Reserved Keywords (Part IEEE Std. 1149.1 JTAG State Names
Test-Logic-Reset Run-Test-Idle Select-DR-Scan Capture-DR Shift-DR Exit1-DR Pause-DR Exit2-DR Update-DR Select-IR-Scan
Reserved State Names
RESET IDLE DRSELECT DRCAPTURE DRSHIFT DREXIT1 DRPAUSE DREXIT2 DRUPDATE IRSELECT
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Table 1-14. Reserved Keywords (Part IEEE Std. 1149.1 JTAG State Names
Capture-IR Shift-IR Exit1-IR Pause-IR Exit2-IR Update-IR
Reserved State Names
IRCAPTURE IRSHIFT IREXIT1 IRPAUSE IREXIT2 IRUPDATE
Example File that Reads IDCODE
Figure 1-27 illustrates flexibility utility STAPL. example reads IDCODE single device JTAG chain. array variable, I_IDCODE, initialized with IDCODE instruction bits ordered first left) most significant (MSB) right). This order important because array field IRSCAN instruction always interpreted, sent, LSB.
Figure 1-27. Example File Reading IDCODE BOOLEAN read_data[32]; BOOLEAN I_IDCODE[10] 1001101000; `assumed BOOLEAN ONES_DATA[32] FFFFFFFF; INTEGER `Set stop state IRSCAN IRSTOP IRPAUSE; `Initialize device STATE RESET; IRSCAN I_IDCODE[0.9]; `LOAD IDCODE INSTRUCTION STATE IDLE; WAIT USEC, CYCLES; DRSCAN ONES_DATA[0.31], CAPTURE read_data[0.31]; `CAPTURE IDCODE PRINT "IDCODE:"; PRINT read_data[i]; NEXT EXIT
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Configuring Using MicroBlaster Driver Device Configuration Pins
MicroBlastersoftware driver allows configure Altera devices embedded environment using mode. MicroBlaster software driver supports Binary File (.rbf) programming input file. source code developed Windows operating system, although customize other operating systems. more information MicroBlaster software driver, Altera site (www.altera.com). following tables describe connections functionality configuration related pins Stratix Stratix device. Table 1-15 describes dedicated configuration pins, which required connected properly your board successful configuration. Some these pins required your configuration schemes.
Table 1-15. Dedicated Configuration Pins Stratix Stratix Device Name
VCCSEL
(Part Description
User Mode
Configuration Scheme
Type
Input
Dedicated input that selects which input buffer used configuration input pins; nCONFIG, DCLK, RUnLU, nCE, nWS, nRS, CLKUSR. VCCSEL input buffer powered internal pull-down resistor that always active. logic high (1.5-V, 1.8-V, 2.5-V, 3.3-V) selects 1.8-V/1.5-V input buffer, logic selects 3.3-V/2.5-V input buffer. "VCCSEL Pins" section more details.
PORSEL
Input
Dedicated input which selects between time logic high (1.5-V, 1.8V, 2.5-V, 3.3-V) selects time about logic selects time about PORSEL input buffer powered internal pull-down resistor that always active.
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Table 1-15. Dedicated Configuration Pins Stratix Stratix Device Name nIO_PULLUP User Mode
(Part Description
Configuration Scheme
Type
Input
Dedicated input that chooses whether internal pull-ups user I/Os dualpurpose I/Os (DATA[7.0], nWS, nRS, RDYnBSY, nCS, RUnLU, PGM[], CLKUSR, INIT_DONE, DEV_OE, DEV_CLR) before during configuration. logic high (1.5-V, 1.8-V, 2.5-V, 3.3-V) turns weak internal pull-ups, while logic turns them nIO_PULLUP input buffer powered internal pull-down resistor that always active.
MSEL[2.0]
Input
3-bit configuration input that sets Stratix Stratix device configuration scheme. Table appropriate connections. These pins connected bank they reside ground. This uses Schmitt trigger input buffers.
nCONFIG
Input
Configuration control input. Pulling this during user-mode causes FPGA lose configuration data, enter reset state, tri-state pins. Returning this logic high level initiates reconfiguration. your configuration scheme uses enhanced configuration device EPC2 device, nCONFIG tied directly configuration device's nINIT_CONF pin. This uses Schmitt trigger input buffers.
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Table 1-15. Dedicated Configuration Pins Stratix Stratix Device Name
nSTATUS
(Part Description
User Mode
Configuration Scheme
Type
Bidirectional device drives nSTATUS immediately open-drain after power-up releases after time. Status output. error occurs during configuration, nSTATUS pulled target device. Status input. external source drives nSTATUS during configuration initialization, target device enters error state. Driving nSTATUS after configuration initialization does affect configured device. configuration device used, driving nSTATUS causes configuration device attempt configure FPGA, since FPGA ignores transitions nSTATUS usermode, FPGA does reconfigure. initiate reconfiguration, nCONFIG must pulled low. enhanced configuration devices' EPC2 devices' pins have optional internal programmable pull-up resistors. internal pull-up resistors enhanced configuration device used, external 10-k pull-up resistors should used these pins. When using EPC2 devices, only external 10-k pull-up resistors should used. This uses Schmitt trigger input buffers.
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Table 1-15. Dedicated Configuration Pins Stratix Stratix Device Name
CONF_DONE
(Part Description
User Mode
Configuration Scheme
Type
Bidirectional Status output. target FPGA drives open-drain CONF_DONE before during configuration. Once configuration data received without error initialization cycle starts, target device releases CONF_DONE. Status input. After data received CONF_DONE goes high, target device initializes enters user mode. CONF_DONE must have external 10-k pull-up resistor order device initialize. Driving CONF_DONE after configuration initialization does affect configured device. enhanced configuration devices' EPC2 devices' pins have optional internal programmable pull-up resistors. internal pull-up resistors enhanced configuration device used, external 10-k pull-up resistors should used these pins. When using EPC2 devices, only external 10-k pull-up resistors should used. This uses Schmitt trigger input buffers.
Input
Active-low chip enable. activates device with signal allow configuration. must held during configuration, initialization, user mode. single device configuration, should tied low. multi-device configuration, first device tied while nCEO connected next device chain. must also held successful JTAG programming FPGA. This uses Schmitt trigger input buffers.
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Table 1-15. Dedicated Configuration Pins Stratix Stratix Device Name
nCEO
(Part Description
User Mode
Configuration Scheme
MultiDevice Schemes
Type
Output
Output that drives when device configuration complete. single device configuration, this left floating. multidevice configuration, this feeds next device's pin. nCEO last device chain left floating. voltage levels driven this dependent bank resides
DCLK
Synchronous configuration schemes (PS, FPP)
Input (PS, FPP)
configuration, DCLK clock input used clock data from external source into target device. Data latched into FPGA rising edge DCLK. mode, DCLK should tied high prevent this from floating. After configuration, this tri-stated. schemes that configuration device, DCLK driven after configuration done. schemes that control host, DCLK should driven either high low, whichever more convenient. Toggling this after configuration does affect configured device. This uses Schmitt trigger input buffers.
DATA0
FPP, Input
Data input. serial configuration modes, bitwide configuration data presented target device DATA0 pin. levels this dependent bank that resides After configuration, DATA0 available user state this depends Dual-Purpose settings. After configuration, EPC1 EPC1441 devices tri-state this pin, while enhanced configuration EPC2 devices drive this high.
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Table 1-15. Dedicated Configuration Pins Stratix Stratix Device Name
DATA[7.1]
(Part Description
User Mode
Configuration Scheme
Parallel configuration schemes (FPP PPA)
Type
Inputs
Data inputs. Byte-wide configuration data presented target device DATA[7.0]. levels these pins dependent banks that they reside serial configuration schemes, they function user I/Os during configuration, which means they tri-stated. After configuration, DATA[7.1] available user I/Os state these depends Dual-Purpose settings.
DATA7
Bidirectional configuration scheme, DATA7 presents RDYnBSY signal after signal been strobed low. levels this dependent bank that resides serial configuration schemes, functions user during configuration, which means tri-stated. After configuration, DATA7 available user state this depends Dual-Purpose settings.
Input
Write strobe input. low-to-high transition causes device latch byte data DATA[7.0] pins. non-PPA schemes, functions user during configuration, which means tristated. After configuration, available user state this depends Dual-Purpose settings.
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Table 1-15. Dedicated Configuration Pins Stratix Stratix Device Name
(Part Description
User Mode
Configuration Scheme
Type
Input
Read strobe input. input directs device drive RDYnBSY signal DATA7 pin. used mode, should tied high. non-PPA schemes, functions user during configuration, which means tri-stated. After configuration, available user state this depends Dual-Purpose settings.
RDYnBSY
Output
Ready output. high output indicates that target device ready accept another data byte. output indicates that target device busy ready receive another data byte. configuration schemes, this drives high after power-up, before configuration after configuration before entering usermode. non-PPA schemes, functions user during configuration, which means tri-stated. After configuration, RDYnBSY available user state this depends Dual-Purpose settings.
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Table 1-15. Dedicated Configuration Pins Stratix Stratix Device Name
nCS/CS
(Part Description
User Mode
Configuration Scheme
Type
Input
Chip-select inputs. high select target device configuration. pins must held active during configuration initialization. During configuration mode, only required either pin. Therefore, only chip-select input used, other must tied active state. example, tied while toggled control configuration.In non-PPA schemes, functions user during configuration, which means tri-stated. After configuration, available user I/Os state these pins depends Dual-Purpose settings.
RUnLU
using Remote Configuration;
Remote Configuration FPP,
Input
Input that selects between remote update local update. logic high (1.5-V, 1.8-V, 2.5-V, 3.3-V) selects remote update logic selects local update. When using remote update local update configuration modes, this pins available general-purpose user pin.
PGM[2.0]
using Remote Configuration; using
Remote Configuration FPP,
Input
These output pins select eight pages memory (either flash enhanced configuration device) when using remote configuration mode. When using remote update local update configuration modes, these pins available general-purpose user pins.
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Table 1-16 describes optional configuration pins. these optional configuration pins enabled Quartus software, they available general-purpose user pins. Therefore during configuration, these pins function user pins tri-stated with weak pull-ups.
Table 1-16. Optional Configuration Pins Name
CLKUSR
User Mode
option option off. option option off.
Type
Input
Description
Optional user-supplied clock input. Synchronizes initialization more devices. This enabled turning Enable user-supplied start-up clock (CLKUSR) option Quartus software. Status pin. used indicate when device initialized user mode. When nCONFIG during beginning configuration, INIT_DONE tri-stated pulled high external 10-k pull-up. Once option enable INIT_DONE programmed into device (during first frame configuration data), INIT_DONE goes low. When initialization complete, INIT_DONE released pulled high FPGA enters user mode. Thus, monitoring circuitry must able detect low-to-high transition. This enabled turning Enable INIT_DONE output option Quartus software. Optional that allows user override tri-states device. When this driven low, I/Os tri-stated. When this driven high, I/Os behave programmed. This enabled turning Enable device-wide output enable (DEV_OE) option Quartus software. Optional that allows override clears device registers. When this driven low, registers cleared. When this driven high, registers behave programmed. This enabled turning Enable device-wide reset (DEV_CLRn) option Quartus software.
INIT_DONE
Output opendrain
DEV_OE
option option off.
Input
DEV_CLRn
option option off.
Input
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Table 1-17 describes dedicated JTAG pins. JTAG pins must kept stable before during configuration prevent accidental loading JTAG instructions. plan SignalTap Embedded Logic Analyzer, will need connect JTAG pins your device JTAG header your board.
Table 1-17. Dedicated JTAG pins Name
User Mode
Type
Input
Description
Serial input instructions well test programming data. Data shifted rising edge TCK. JTAG interface required board, JTAG circuitry disabled connecting this This uses Schmitt trigger input buffers. Serial data output instructions well test programming data. Data shifted falling edge TCK. tri-stated data being shifted device. JTAG interface required board, JTAG circuitry disabled leaving this unconnected. Input that provides control signal determine transitions controller state machine. Transitions within state machine occur rising edge TCK. Therefore, must before rising edge TCK. evaluated rising edge TCK. JTAG interface required board, JTAG circuitry disabled connecting this This uses Schmitt trigger input buffers. clock input circuitry. Some operations occur rising edge, while others occur falling edge. JTAG interface required board, JTAG circuitry disabled connecting this GND. This uses Schmitt trigger input buffers. Active-low input asynchronously reset boundaryscan circuit. TRST optional according IEEE Std. 1149.1. JTAG interface required board, JTAG circuitry disabled connecting this GND. This uses Schmitt trigger input buffers.
Output
Input
Input
TRST
Input
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Remote System Configuration with Stratix Stratix Devices
S52015-3.1
Introduction
Altera® Stratix® Stratix devices first programmable logic devices (PLDs) featuring dedicated support remote system configuration. Using remote system configuration, Stratix Stratix device receive configuration data from remote source, update flash memory content (through enhanced configuration devices other storage device), then reconfigure itself with data. Like Altera SRAM-based devices, Stratix Stratix devices support standard configuration modes such passive serial (PS), fast passive parallel (FPP), passive parallel asynchronous (PPA). standard configuration modes with remote system configuration. This chapter discusses remote system configuration Stratix Stratix devices, interface them with enhanced configuration devices enable this capability. This document also explains some related remote system configuration topics, such watchdog timer, remote system configuration registers, factory application configurations files. Quartus® software (version later) supports remote system configuration.
Remote Configuration Operation
Remote system configuration three major parts:
Stratix Stratix device receives updated data from remote source over network through other source that transfer data). implement Nios(16-bit ISA) Nios® (32-bit ISA) embedded processor within either Stratix Stratix device external processor control read write functions configuration files from remote source memory device. updated information stored into memory device, which enhanced configuration device, industry-standard flash memory device, other storage device (see Figure 2-2). Stratix Stratix device updates itself with data from memory.
Figure shows concept remote system configuration Stratix Stratix devices.
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Remote Configuration Operation
Figure 2-1. Remote System Configuration with Stratix Stratix Devices
Network
Development Location
Data Data Data
Stratix Stratix Device Control Module
Memory
Stratix Device Configuration
Figure 2-2. Different Options Remote System Configuration
External Processor Stratix Stratix Device Enhanced Configuration Device Stratix Stratix Device Nios Processor Device Flash Memory Stratix Stratix Device Nios Processor
Processor
Enhanced Configuration Device Flash Memory
Device
Flash
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Remote System Configuration Modes
Stratix Stratix device remote system configuration modes: remote configuration mode local configuration mode. Table shows selection settings each configuration mode.
Table 2-1. Standard, Remote Local Configuration Options Note
RUnLU
Notes Table 2-1:
detailed information standard FPP, models, Configuring Stratix Stratix Devices chapter Stratix Device Handbook, Volume Stratix Stratix devices, RUnLU (remote update/local update) pin, selects between local remote configuration mode. MSEL[2] select mode selects between standard remote system configuration mode.
MSEL[2]
MSEL[1.0]
System Configuration Mode
Standard Standard Standard Remote Remote Remote Local Local Local
Configuration Mode
Remote Configuration Mode
Using remote configuration mode, manage seven different application configurations Stratix Stratix devices. sevenconfiguration-file limit number pages that PGM[] pins Stratix Stratix device enhanced configuration devices select. more than seven files sent system using remote configuration mode, previous files overwritten.
Stratix Stratix devices support remote configuration mode FPP, modes. Specify remote configuration mode setting MSEL2 RUnLU pins high. (See Table 2-1). power-up remote configuration mode, Stratix Stratix device loads user-specified factory configuration file, located default page address enhanced configuration device. After device configures, remote configuration control register points
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page address application configuration that should loaded into Stratix Stratix device. error occurs during user mode application configuration, device reloads default factory configuration page. Figure shows diagram remote configuration mode. Figure 2-3. Remote Configuration Mode
Power
Reconfigure Factory Configuration Page (000) Errors
Application Configuration [001]
Configuration Error
Errors
Reconfigure Application Configuration [111]
Local Configuration Mode
Local configuration mode-a simplified version remote configuration mode-is suitable systems that load application immediately upon power-up. this mode only application configuration, which update either remotely locally. local configuration mode, upon power-up, when nCONFIG asserted, Stratix Stratix device loads application configuration immediately. Factory configuration loads only error occurs during application configuration's user mode. enhanced configuration device, page address location application configuration data, page address location factory configuration data. configuration data page address does load correctly cyclic redundancy code (CRC) failure, times-out enhanced configuration device, external processor times-out, then factory configuration located default page (page address 000) loads into Stratix Stratix device. local configuration mode (shown Figure 2-4), user watchdog timer disabled. more information watchdog timer, "Watchdog Timer" page 2-7.
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Figure 2-4. Local Configuration Mode
Power nCONFIG Assertion Configuration Error Factory Configuration PGM[000] nCONFIG Configuration Error
nCONFIG
Application Configuration PGM[001]
local configuration mode, application configuration available device. remote local configuration mode selection, Table 2-1.
Remote System Configuration Components
following components used Stratix Stratix devices support remote local configuration modes:
Page mode feature Factory configuration Application configuration Watchdog timer Remote update sub-block Remote configuration registers
description each component follows.
Page Mode Feature
page mode feature enables Stratix Stratix devices select location read back data configuration. enhanced configuration device receive store eight different configuration files (one factory seven application files). Selection pages read from performed through PGM[2.0] pins Stratix Stratix device enhanced configuration devices. These pins Stratix Stratix device designated user pins during standard configuration mode, remote system configuration mode, they dedicated output pins. Figure shows page mode feature Stratix Stratix devices enhanced configuration devices.
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Figure 2-5. Page Mode Feature Stratix Stratix Devices Enhanced Configuration Devices
Enhanced Configuration Device tix7 Stratix Page0 Stratix Stratix Device
Page Select
Upon power-up remote configuration mode, factory configuration (see description below) selects user-specified page address through Stratix Stratix PGM[2.0] output pins. These pins drive PGM[2.0] input pins enhanced configuration device select requested page memory. intelligent host used instead enhanced configuration device, should create logic intelligent host support page mode settings similar that enhanced configuration devices.
Factory Configuration
Factory configuration default configuration data setup. enhanced configuration devices, this default page address 000. Factory configuration data written into memory device only once system manufacturer should remotely updated altered. remote configuration mode, factory configuration loads into Stratix Stratix device upon power-up. factory configuration specifications follows:
Receives configuration data writes enhanced configuration other memory devices Determines page address next application configuration that should loaded Stratix Stratix device Upon error application configuration, system reverts factory configuration Determines reason application configuration error Determines whether enable disable user watchdog timer application configurations
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Determines user watchdog timer's settings timer enabled (remote configuration mode) user watchdog timer reset after predetermined amount time, times-out system loads factory configuration data back Stratix Stratix device
system encounters error while loading application configuration data, device re-configures nCONFIG assertion, Stratix Stratix device loads factory configuration. remote system configuration register determines reason factory re-configuration. Based this information, factory configuration determines which application configuration needs loaded.
Application Configuration
application configuration configuration data received from remote source updated into different locations pages memory storage device (excluding factory default page).
Watchdog Timer
watchdog timer circuit that determines whether another mechanism functions properly. watchdog timer functions like timedelay relay that remains reset state while application runs properly. This action periodically sends reset command from working application watchdog timer. Stratix Stratix devices equipped with built-in watchdog timer remote system configuration. user watchdog timer prevents faulty application configuration from indefinitely stalling Stratix Stratix device. timer functions counter that counts down from initial value, which loaded into device from factory configuration. This 29-bit counter, only upper bits value watchdog timer. specify counter value according your design needs. timer begins counting once Stratix Stratix device goes into user mode. application configuration does reset user watchdog timer after specified time, timer times-out. this point, Stratix Stratix device re-configured loading factory configuration resetting user watchdog timer. watchdog timer disabled local configuration mode.
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Remote Update Sub-Block
remote update sub-block responsible administrating remote configuration feature. This sub-block, which controlled remote configuration state machine, generates control signals required control different remote configuration registers.
Remote Configuration Registers
Remote configuration registers series registers required keep track page addresses cause configuration errors. Table gives descriptions registers' functions. control both update shift registers; status control registers controlled internal logic, read shift register.
Table 2-2. Remote Configuration Registers Register
Control register
Description
This register contains current page address, watchdog timer setting, specifying current configuration factory application configuration. During capture application configuration, this register read into shift register. This register contains same data control register, except that updated factory configuration. factory configuration updates register with values used control register next reconfiguration. During capture factory configuration, this register read into shift register. This register accessible core logic allows update, status, control registers written sampled user logic. update register only updated factory configuration remote configuration mode. This register written into remote configuration block every reconfiguration record cause re-configuration. This information used factory configuration determine appropriate action following reconfiguration.
Update register
Shift register
Status register
Figure shows control, update, shift, status registers data path used control remote system configuration.
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Figure 2-6. Remote Configuration Registers Related Data Path
Status Register
Bit4.Bit10
Control Register
Bit16.Bit0
Logic Reconfig Logic Update Register
Bit0.Bit16
User Watchdog Timer
Shift Register
Control Logic
RU_Dout
RU_shftnhld
RU_captnupdt
RU_Din
RU_clk
RU_Timer
RU_nCONFIG
Device Core
Table describes user configuration signals that driven to/from device logic array. remote configuration logic input signal device logic array output signals from device logic array.
Table 2-3. User Configuration Signals To/From Device
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