SCLS454A

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SCLS454A - SCLS454A

CD54HC573, CD74HC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Operation Wide Operating Temperature Range -55°C 125°C 3-State Outputs Directly Drive Lines Balanced Propagation Delays Transition Times Driver Outputs Drive LS-TTL Loads Significant Power Reduction Compared LS-TTL Logic
CD54HC573 PACKAGE CD74HC573 PACKAGE (TOP VIEW)
description/ordering information
'HC573 devices octal transparent D-type latches designed operation.
When latch-enable (LE) input high, outputs follow data inputs. When low, outputs latched logic levels inputs. buffered output-enable (OE) input used place eight outputs either normal logic state (high low) high-impedance state. high-impedance state, outputs neither load drive lines significantly. high-impedance state increased drive provide capability drive lines without interface pullup components. does affect internal operations latches. data retained data entered while outputs high-impedance state. ensure high-impedance state during power power down, should tied through pullup resistor; minimum value resistor determined current-sinking capability driver. ORDERING INFORMATION
PACKAGE PDIP -55°C 125°C 55°C SOIC CDIP Tube Tube Tape reel Tube ORDERABLE PART NUMBER CD74HC573E CD74HC573M CD74HC573M96 CD54HC573F3A TOP-SIDE MARKING CD74HC573E HC573M CD54HC573F3A
Package drawings, standard packing quantities, thermal data, symbolization, design guidelines available www.ti.com/sc/package.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
Copyright 2003, Texas Instruments Incorporated
products compliant MIL-PRF-38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
POST OFFICE 655303
DALLAS, TEXAS 75265
CD54HC573, CD74HC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
FUNCTION TABLE (each latch) INPUTS OUTPUT
logic diagram (positive logic)
Seven Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, -0.5 Input clamp current, VCC) (see Note Output clamp current, VCC) (see Note Continuous output drain current output, VCC) Continuous output source sink current output, VCC) Continuous current through Package thermal impedance, (see Note package 69°C/W package 58°C/W Storage temperature range, Tstg -65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. package thermal impedance calculated accordance with JESD 51-7.
POST OFFICE 655303
DALLAS, TEXAS 75265
CD54HC573, CD74HC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
recommended operating conditions (see Note
25°C Supply voltage High-level input voltage Input voltage Output voltage Input transition (rise fall) time 3.15 1.35 1000 -55°C 125°C 3.15 1.35 1000 -40°C 85°C 3.15 1.35 1000 UNIT
Low-level input voltage
NOTE unused inputs device must held ensure proper device operation. Refer application report, Implications Slow Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS -7.8 25°C 3.98 5.48 0.26 0.26 ±0.1 ±0.5 -55°C 125°C -40°C 85°C 3.84 5.34 0.33 0.33 UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
CD54HC573, CD74HC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
timing requirements over recommended operating free-air temperature range (unless otherwise noted) (see Figure
Pulse duration, high Setup time, data before Hold time, data after 25°C -55°C 125°C -40°C 85°C UNIT
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure
PARAMETER FROM (INPUT) (OUTPUT) LOAD CAPACITANCE tdis 25°C -55°C 125°C -40°C 85°C UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
CD54HC573, CD74HC573 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
PARAMETER MEASUREMENT INFORMATION
tdis PARAMETER tPZH tPZL tPHZ tPLZ Open Closed Open Closed Open LOAD CIRCUIT Input VOLTAGE WAVEFORMS PULSE DURATION trec VOLTAGE WAVEFORMS RECOVERY TIME Input tPLH In-Phase Output tPHL Out-of-Phase Output tPLH Output Waveform (see Note tPHL tPZL Output Waveform (see Note tPZH tPLZ tPHZ Output Control Data Input Reference Input Closed Open Closed Open Open
From Output Under Test (see Note
Test Point
Input
VOLTAGE WAVEFORMS SETUP HOLD INPUT RISE FALL TIMES
VOLTAGE WAVEFORMS PROPAGATION DELAY OUTPUT TRANSITION TIMES
VOLTAGE WAVEFORMS OUTPUT ENABLE DISABLE TIMES
NOTES: includes probe test-fixture capacitance. Waveform output with internal conditions such that output except when disabled output control. Waveform output with internal conditions such that output high except when disabled output control. Phase relationships between waveforms were chosen arbitrarily. input pulses supplied generators having following characteristics: MHz, clock inputs, fmax measured with input duty cycle 50%. outputs measured time with input transition measurement. tPLZ tPHZ same tdis. tPZL tPZH same ten. tPLH tPHL same tpd.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
8-Jun-2005
PACKAGING INFORMATION
Orderable Device CD54HC573F CD54HC573F3A CD74HC573E CD74HC573M CD74HC573M96 CD74HC573M96G4 CD74HC573MG4
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type CDIP CDIP PDIP SOIC SOIC SOIC SOIC
Package Drawing
Pins Package Plan 2000 Pb-Free (RoHS) Pb-Free (RoHS) Pb-Free (RoHS)
Lead/Ball Finish Call Call NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-2-250C-1 YEAR/ Level-1-235C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
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SCLS454A

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