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TVSOP Application Brief
August 1996 (draft 1.2)
SCBA009A
Thin Very Small Outline Package (TVSOP)
Acknowledgment authors wish acknowledge following persons corporations their invaluable assistance preparation this document. co-workers Advanced System Logic (ASL) Dallas Process Automation Center (DPAC) provided expert technical editorial help guidance. Without their support, this report would have been possible. Advanced System Logic, Texas Instruments, Sherman, David Holmgreen, Launch Marketing Douglas Romm, Packaging, (Thermal Modeling) Cles Troxtell, Test Finish AVEX Electronics, Incorporated, subsidiary J.M. Huber Corporation, Huntsville, Process Automation Center, Texas Instruments, Dallas, Darvin Edwards Mike Lamson Solectron, Texas (formerly Custom Manufacturing Services, Texas Instruments), Austin, David Mendez Glen Shepherd David Spitz George Zbranek, June 1996 Maria Balian Edgar Zuniga-Ortiz Package Development
Table Contents
Thin Very Small Outline Package (TVSOP) Acknowledgment. Table Contents. List Tables. List Figures. List Equations. Introduction. TVSOP Dimensions. Advanced System Logic (ASL) Packaging Trends Line-Up Similar Packages. TVSOP Package Development Description. JEDEC Registration. Symbolization. Printed Circuit Board Manufacture with TVSOP Overview Test Site Results.10 TVSOP Results from Custom Manufacturing Services (Now Solectron, Texas) TVSOP Results from AVEX Electronics.18 Texas Instruments Reference Information Thermal Characteristics.24 Thermal Parameters.24 Thermal Measurements.25 TVSOP Power Dissipation Thermal Resistance Characteristics Power Calculations Electrical Characteristics.33 TVSOP Electrical Data.35 Reliability Qualification Data Delivery TVSOP Customers Moisture Sensitivity TVSOP Test Sockets.43
List Tables
Table TVSOP Dimensions Count Table JEDEC Registration TVSOP Packages Table Product Symbolization Table Junction Temperature Long Term Reliability Comparison Table JEDEC Thermal Test Board Table Summary TVSOP Electrical Data Table 14-pin TVSOP Package Reliability Results Table 20-pin TVSOP Package Reliability Results Table 48-pin TVSOP Package Reliability Results Table 80-pin TVSOP Package Reliability Results Table TVSOP Moisture Sensitivity Table TVSOP Moisture Sensitivity Levels Table Available TVSOP Test Sockets
List Figures
Figure TVSOP Dimensions. Figure Package Area Comparison Figure SSOP TSSOP TVSOP Package Line
Figure 56-pin TVSOP Package Dimensions. Figure 100-pin TVSOP Package Dimensions Figure Product Symbolization Format Figure Stencil Geometry Figure TVSOP Placement Printed Circuit Boards Figure TQFP Placement Printed Circuit Boards.14 Figure Defect Rate with Stencil Thickness.16 Figure Defect Rate with Stencil Thickness.17 Figure Reflow Thermal Profile Figure TVSOP Stencil Geometry Reflow Solder Process Figure AVEX TVSOP Process Flow Figure Cross Section (side view) TVSOP Lead Solder Joint Figure Cross Section (end view) TVSOP Lead Solder Joint Figure 14-pin TVSOP Derating Curves.27 Figure 16-pin TVSOP Derating Curves.27 Figure 20-pin TVSOP Derating Curves.28 Figure 24-pin TVSOP Derating Curves.28 Figure 48-pin TVSOP Derating Curves.29 Figure 56-pin TVSOP Derating Curves.29 Figure 80-pin TVSOP Derating Curves.30 Figure 100-pin TVSOP Derating Curves.30 Figure TVSOP Package Inductance (14, 56-pin) Figure TVSOP Package Inductance 100-pin) Figure TVSOP Package Capacitance (14, 56-pin) Figure TVSOP Package Capacitance 100-pin) Figure TVSOP SSOP Self Inductance Comparison Figure Carrier Cover Tape Information Reeled TVSOP Packages Figure Reel Dimensions
List Equations
Equation Equation Equation Equation Equation Equation Equation Equation Junction Temperature Relationship Power Equilibrium Equation Power Dissipation Capacitance Total Power.31 Power Calculation CMOS Input Levels Power Calculations Input Levels Static Power Calculation BiCMOS Bipolar Products Dynamic Power Calculation BiCMOS Bipolar Products
Introduction Development portable, light-weight, high-performance electronics products driving semiconductor industry toward smaller, thinner higher-density packages. Pricing pressures encouraging strong efforts toward cost reduction. Texas Instruments always been leader packaging introducing family Thin Very Small Outline Packages (TVSOP) support component miniaturization requirements industry. TVSOP package family, 100-pin types, features lead pitch mil.) device height meeting PCMCIA (Personal Computer Memory Card International Association) requirement. TVSOP packages have received JEDEC (Joint Electronics Device Engineering Council) registration under semiconductor package standard MO-194. this application article, provide overview TVSOP package family characteristics including thermal, electrical, reliability moisture sensitivity performance. Assembly mounting guidelines devices lead pitch packages also included. TVSOP Dimensions Figure Table show TVSOP package dimensions.
Figure TVSOP Dimensions
TVSOP Package 14-Pin 16-Pin 20-Pin 24-Pin 48-Pin 56-Pin 80-Pin 100-Pin Typical Dimensions 4.40 6.40 0.18 4.40 6.40 0.18 4.40 6.40 0.18 4.40 6.40 0.18 4.40 6.40 0.18 4.40 6.40 0.18 6.10 8.10 0.18 6.10 8.10 0.18 Area (mm2) 23.00 23.00 32.00 32.00 63.00 72.30 137.8 168.5 Smaller than SSOP 52.4 52.4 43.0 50.0 61.9 62.2 Smaller than TSSOP 29.3 29.3 24.0 34.0 38.0 36.0 Smaller than TQFP
3.60 3.60 5.00 5.00 9.80 11.3 17.0 20.8
0.40 0.40 0.40 0.40 0.40 0.40 0.40 0.40
30.0 35.0
Table TVSOP Dimensions Count
Advanced System Logic (ASL) Packaging Trends Figure shows TVSOP package follows trend toward smaller smaller surface mount packages.
Package Area
PDIP JEDEC SOIC EIAJ SOIC SSOP TSSOP TVSOP
Package Type 14/16
Figure Package Area Comparison
Line-Up Similar Packages Figure illustrates Texas Instruments SSOP, TSSOP TVSOP surface mount packages with pitches 0.65 0.40
EIAJ PACKAGE Type TYPE
JEDEC
SSOP
MO-153
TSSOP
MO-153
MO-194
TVSOP
MO-194
Note: drawings above representative only scale.
Figure SSOP TSSOP TVSOP Package Line
TVSOP Package Development Description Figures show basic dimensions TVSOP package.
Figure 56-pin TVSOP Package Dimensions
Figure 100-pin TVSOP Package Dimensions JEDEC Registration TVSOP packages have been registered under JEDEC MO-194 standard semiconductor packages:
Package Pins JEDEC Registration MO-194AA MO-194AB MO-194AC MO-194AD MO-194AE MO-194AF MO-194BA MO-194BB
Table JEDEC Registration TVSOP Packages
Symbolization Symbolization TVSOP follows Texas Instruments standard. small size many packages, some characters omitted characters substituted whole part types. Figure shows general symbol format Table lists character omissions substitutions. 16-pin devices small permit entire Trace Code symbolized, only year decade month characters included. Complete Trace Code information included product packaging labels.
Year; Month; LLLL Trace Code; Site
Figure Product Symbolization Format
Package Type Count 14,16,20,24 48,56 80,100 SN74ALVCH16xxx VHxxx ALVCH16xxx SN74ALVCHG16xxx VGxxx ALVCHG16xxx SN74ABTxxx ABxxx SN74ABTHxxx AKxxx SN74ABT16xxx AHxxx SN74ABTH16xxx AMxxx SN74AHCxxx HAxxx SN74AHCTxxx HBxxx SN74CBTD3xxx CCxxx SN74CBT16xxx CYxxx CBT16xxx SN74LVCxxx LCxxx SN74LVCHxxx LCHxxx SN74LVC16xxx LDxxx SN74LVCH16xxx LDHxxx Note: Please contact your nearest Sales Office Authorized Distributor specific device type availability
Table Product Symbolization
Printed Circuit Board Manufacture with TVSOP Overview Test Site Results Packaging Engineering been working cooperation with Solectron, Texas (formerly Custom Manufacturing Services, Austin) AVEX Electronics Inc. develop printed circuit board (PCB) assembly process guidelines ultra-fine pitch packages high-volume manufacturing. majority defects encountered board assembly with fine-pitch packages caused solder bridging, open circuits improper device placement. Proper lead planarity absence bent leads essential minimize assembly mount defects. Components with poor co-planarity require more solder paste obtain good solder joint. increased volume solder paste turn cause bridging. board mounted components must carefully selected based lead foot specifications provided component suppliers. Lead co-planarity data constantly monitored TVSOP packages ensure that units fall within JEDEC coplanarity specifications less than 0.08 Inaccurate device placement, last defect issues, function pick-and-place equipment capability. major potential applications TVSOP packages were addressed during assembly process development project: standard boards 16") standard PCMCIA cards. Many factors affect board performance (equipment, environment, component board quality, etc.), therefore, guidelines presented herein primarily intended give manufacturers designers useful information that resulted from lessons learned during package development work.
TVSOP Results from Custom Manufacturing Services (Now Solectron, Texas) Dave Mendez Glen Shepherd Dave Spitz George Zbranek Texas Instruments conducted evaluations establish design processing requirements along with limitation applying TVSOP series (0.4 pitch devices. intent this publication offer footprint geometry, stencil, placement processing guidelines. These guidelines needed minimize solder defect rate indiscriminate pitch devices designs. Each assembly process defect rate will unique demands pitch devices will place assembly process. Equipment accuracy, repeatability process capability play large role resultant defect rate. Therefore have tried quantify differences magnitude rates achievable through implementation recommended guidelines. Geometry Requirements TVSOP FOOTPRINT TVSOP STENCIL
Table below dimensions Count Dimension Dimension
Dimensions 11.3 17.0 20.8
Figure Stencil Geometry
recommend pitch terminal following dimensional requirements:
Terminal Length Terminal Width Terminal Pitch Gerber Position Finish 0.070" (1.8 0.011" (0.28 0.0157" (0.4 format minimum Entek
Conclusion geometry finish very important assembly defect rate widely spaced pitch devices. Stencil Geometry Requirements recommend single level, laser cut, electro-polished stainless steel 0.006" thick stencil product which both PLCC pitch devices. Boards without PLCC devices could 0.005" stencil, however, other pitch devices will trend toward insufficient solder volume.
Stencil Opening Length Stencil Opening Width Stencil Thickness Gerber position PLCC TVSOP 0.065" 0.008" 0.006" Format minimum TVSOP ONLY 0.065" 0.008" 0.005"
Conclusion stencil thickness largest influence over defect rate. experience shows that small increase solder short defect rate pitch devices much better than using thinner stencil resulting difficult detect opens solder insufficiencies. Component Placement pitch device defect rates (shorts) very sensitive their lead orientation with respect radial distance they reside from stencil alignment point (usually center board). Widely spaced TVSOP device defect rates reduced orders magnitude just placing device with leads parallel image stretch axis. Every board stencil will have image positional accuracy which usually manifests itself inches inch misregistration. Secondly, stencils have image registration accuracy tend change dimensionally with print cycles.
Placement TVSOP Devices devices with lead sides body) above dimensional considerations yield following optimum placement practices. This information applies count pitch SOP. Maximum assembly yields components placed more than inches away from center board (stencil alignment point) achieved orienting leads parallel board expansion axis with longest distance from center point. areas where distance from alignment excessive (yield degradation area) defect rate will climb rapidly without special placement guidelines.
Yield degradation area
Figure TVSOP Placement Printed Circuit Boards Devices outside inch area must have their lead positioned Figure assembly yields will degrade significantly. Correctly oriented defect expectations (see Figure
Inches from center Yield degradation
Note: Magnitude denotes times defect rate.
Devices yield degradation area Figure should avoided. unavoidable, leads should oriented degrees board expansion axis avoid excessive defects. Quad Flat Pack (QFP) Devices This information applies count pitch quad flat pack (leads sides) devices. device avoid defects orienting their leads degrees. Secondly there added complication stenciling inconsistency with leads both directions. optimum assembly yields device realized when component rotated degrees board expansion axis. Significant defects were experienced distances more than inches away from stencil alignment point with normally oriented QFP.
Yield degradation area
Figure TQFP Placement Printed Circuit Boards Correctly oriented degree defect expectations (see Figure
Inches from Center Orientation Orientation 100x 250x 500x 100x
summary, placement pitch device second largest influence over defect rate. Card Stencil Image Attributes image reproduction accuracy stencil critical obtaining sustaining satisfactory defect rate with widely spaced pitch devices. stencil only aligned point image. mis-registration approaching full space between pitch leads (0.006") will start causing shorts tens thousands PPM. Typical commercial fabrication processes have comprehended need very accurate repeatable images active side PWBs. Research indicates that specification requirements image registration well defined. hole true position registration plays very little part pitch assembly process. Some points reference were obtained. supplier suggests image registration accuracy 0.002 inches (0.00011 inch inch) over inch fabrication panel. This experiment substantiated that level registration misalignment. Image Mis-Registration
Test Board dimensions Mean inches 0.0018 inches Sigma 0.0024 Mean Sigma Inches Inch 0.00012 0.00025
0.00136
0.00138
Conclusion widely spaced pitch devices will require image registration tolerance specification testing supplier insure compliance. Anything over 0.00015 inch inch will start degrade defect rate. stencil image registration just important PWB. been experience that stencil images hard control image. Secondly, image will move with print cycles. movement somewhat predictable. Conclusion Just like every stencil image registration must specified verified when first purchased. Maximum mis-registration should 0.002 over inches (0.00015 inches inch). dimensional registration board stencil alignment extremes, would prudent rebuild stencil better match board registration trends. maximum mismatch allowable including stencil vision alignment accuracy 0.005 inches before significant defects occur. Also, compensating stencil match board lots felt counterproductive. Stencil Process Following characteristics stencil equipment process: (Equipment capability critical defect rate.)
Stencil Printer Stencil Alignment Accuracy Solder Paste Type Solder Paste Particle Size Stencil Thickness Squeegee Type Paste Actual Thickness Average Boards, Devices Leads Device Paste Volume Sigma Paste Volume 3030 0.0003 inches Alpha -500 0.006 Laser Stainless Steel Metal Mean 0.0069 inches Sigma 0.00073 Mean 3110 mils3 Sigma mils3
Component Placement Process Following characteristics placement process:
Placement Equipment Fuji Placer Placement Accuracy 0.0015 inches
parts were placed pads using local Fiducials device. Conclusion placement aligned with local Fiducials devices were placed center pads. Placement considered significant contributor defect rate.
Reflow Characteristics Following characteristics solder paste reflow process. standard reflow profile this type board used. Reflow Oven Atmosphere Chain Speed Temperature Time Over 183° Full convection TRS21 Shop nitrogen) inches minute 215° Seconds
Conclusion reflow profile least effect defect rate. profile read shown Figure Overall Special attention design assembly process critical assembly Conclusion widely spaced pitch devices. Closely spaced pitch devices offer lower defect rates. With proper design, most important placement lead rotation, widely spaced devices assembled with defect rates approaching pitch devices. paying attention basic requirements make product un-manufacturable cost manufacturer $20s dollars board touch costs. truly value added avoidable expense.
Defect Rate
10.5 13.5 Placement Radius inches) TVSOP TVSOP TQFP TQFP
Figure Defect Rate with Stencil Thickness
Defect Rate
10.5 13.5 Placement Radius inches) TVSOP TVSOP TQFP TQFP
Figure Defect Rate with Stencil Thickness
Speed (in/min)
Zone Upper Lower
200° 200°
170° 170°
170° 170°
170° 170°
220° 220°
220° 220°
220° 220°
220° 220°
Figure Reflow Thermal Profile
TVSOP Results from AVEX Electronics AVEX ELECTRONICS, INC. Huntsville, Subsidiary J.M. Huber Corporation total individual double-sided PCMCIA assemblies, located manufacturing panel, each types plating, gold EntekTM, were manufactured AVEX Electronics Inc. Experiments were each assemblies investigate effect geometry, stencil geometry assembly process flow (0.4 lead pitch components using high volume manufacturing equipment. Stencil Geometry Requirements dimensions interconnect stencil aperture have major effect quality solder joint. These dimensions must adhered board design. card stencil must produced maintain these dimensions; otherwise yields reliability will significantly reduced. following dimensions were used pitch components using PCMCIA cards:
FOOTPRINT AREA 0.14 0.18
0.18
1.57
0.23
0.23 SECTION
Dimensions
Figure TVSOP Stencil Geometry Reflow Solder Process Geometry: Terminal Length Terminal Width Terminal Pitch Finish Stencil Geometry: Stencil Opening Length 0.062" (1.57 Stencil Opening Width 0.007" (0.18 Stencil Thickness 0.005" (0.13 0.062" (1.57 0.009" (0.23 0.016" (0.4 EntekTM, Gold Plating
Assembly Process Figure shows assembly process flow conducted AVEX Electronics TVSOP packages.
Paste Inspection
First Pass
Discrete Placement Placement Reflow Soldering Inspect Touch-Up
Screen Printer
Paste Inspection
Second Pass
Discrete Placement Placement Reflow Soldering Inspect Touch-Up
Screen Printer
Figure AVEX TVSOP Process Flow equipment used fine pitch mounting evaluation listed below:
Screen Printer Stencil Alignment Accuracy Solder Paste Solder Paste Particle Size Stencil Thickness Squeegee Type Paste Actual Thickness Paste Inspection Vision Placement Vision Accuracy Reflow Oven 265GS 0.0006 inches Alpha WS609 (25-45 microns) 0.005 inches Metal 0.0055 0.007 inches Cyberoptics CM82 (for Discretes) CM92 (for IC's) 0.001 inches Heller 1700D
Process Reflow Profile Following recommended reflow used. Reflow profile below standard PCMCIA cards. Preheat Solder joint temperature must gradually increased from ambient temperature approximately 170° Celsius temperature ramp exceed degrees second Solder joint temperature should held approximately 170° Celsius period time exceed seconds. Solder joint temperature must increased from 210° Celsius temperature ramp rate exceed degrees second. Temperature dwell time above degrees Celsius range from seconds. Total heating dwell time minutes depending thermal inertia component sensitivity.
Soak Reflow
Conclusion Based experiments during TVSOP Qualification run, AVEX drawn following conclusions: There appreciable difference between gold Entekplated PCB's. Choice plating materials should based solder paste chemistry requirements. Results comparing mils aperture sizes showed that smaller aperture resulted better yield. Special consideration must given screen print process, i.e., stencil thickness, aperture size support during second pass screen print process. Dedicated tooling required machine placement PWB's less than 0.031" thickness Component inspection critical require laser inspection capability placement equipment.
Solder Joint Reliability Study following photo-micrographs cross-sections TVSOP leads attached simulated PCMCIA circuit cards.
Figure Cross Section (side view) TVSOP Lead Solder Joint
Figure Cross Section (end view) TVSOP Lead Solder Joint
Temperature Cycle Test This experiment designed determine reliability TVSOP solder joints. failures were obtained after 1200 thermal cycles between 100° Celsius. following describes AVEX thermal cycling test procedure requirements PCMCIA Environmental Stress Screening (ESS). Support testing PCB's panels) run. cycles Temperature Profile, minute dwell time, minute ramp). cycles Temperature Profile, minute dwell time, minute ramp). power source required Unit Under Test (UUT). Continuity Test requiring monitoring circuits UUT. current load required traces. Continuous monitoring Status, sample rate least sample/second. Failures removed after return degrees Celsius.
Test Implementation PCMCIA panel assemblies were loaded onto AVEX standard tray. tray modified hold panels tray metal screws with nylon standoffs. standard frame wiring used provide interface from chamber monitoring system. system monitored continuity traces through standard Digital interface card. Equipment List following equipment used perform PCMCIA test: Chamber Model ESS5-7RWC AVEX Frame each AVEX tray assemblies Dell: 486/33 system Metrabyte: PIO96 Digital card Application specific chamber controller interface card assembly Application specific test software written Borland
Chamber Profile
Temperature Range Negative Ramp Time Lower Dwell Time Positive Ramp Time Upper Dwell Time Total Cycle Length Number Cycles Total Continuous Cycles 100° Minutes Minutes Minutes Minutes Minutes Cycles 100° Minutes Minutes Minutes Minutes Minutes Cycles 1200 Cycles
Test Data profile over time period from 2/27/96 4/08/96. There were test failures observed. test data contained entries state changes Digital inputs. Definitions References Definitions: Unit Under Test. single board assembly that subjected testing. Input Output. Signal lines stimulus monitoring system board assembly. System compatible personal computer system. Used test controllers monitoring units. References: AVEX Electronics: In-Line Setup Wiring Diagram, Document 4000-14-0159 AVEX Electronics: Drawer block Diagram, Document 4978-08-2034
Texas Instruments Reference Information Thermal Characteristics Heat transferred from packages three ways; conduction, convection radiation. Conduction, simplest heat-transfer mechanism, transfer kinetic energy from more excited electron nearby electron method vibrations collisions. primary mode heat transfer within between solids. Metals good conductors they possess high number free electrons encourage collisions. This ability conduct heat quantified proportionality constant also known thermal conductivity. higher thermal conductivity, better material heat conduction. Mold compounds play role conduction contribute much copper leadframes. second method heat transfer convection. This transfer involves movement heated substance. Convection primary mode transfer between solid, liquid gas. rate convection dependent surface area package velocity physical properties air. Natural convection heat transfer caused induced differences density that result from expansion contraction subjected temperature changes. Forced convection heat transfer caused movement cooling medium across heat source. presence flow increases rate heat transfer. third mode heat transfer radiation. Radiated heat transfers occur thermal emission primarily infrared spectrum. Though radiation always exists, only mode heat transfer between objects separated vacuum. Most heat transfer will take form conduction convection. Thermal Parameters thermal impedance (k-factor) package defined increase junction temperature above ambient power dissipated device measured degrees Celsius Watt. There indices commonly used describe thermal characteristics integrated circuit package,JA (junction ambient) (junction case). Junction Temperature temperature inside package. Maintaining junction temperature within given range necessary proper device functionality long term reliability. lower junction temperature results increased component reliability reduced possibility electro-migration ball bond intermetallic failure. Table illustrates this relationship.
Junction Percent Temperature Failure Rate 100° 0.02 110° 120° 130° 140° 150° Failure rate 100,000 hours Table Junction Temperature Long Term Reliability Comparison Case Temperature temperature package surface measured center package attached K-type thermocouple. Ambient Temperature temperature surrounding air. usually used reference point calculate junction case temperature. measured some distance away from device. Thermal Measurements trying make comparisons among parameters, important understand parameters measured under what test conditions. Thermal measurement standards have been developed JEDEC which will lead more consistent correlation thermal performance between vendors. JC15 JEDEC committee formed develop standards thermal measurement modeling packages. Perhaps most important factor regarding variability thermal measurements design thermal test board. Table provides JEDEC dimensions dual-in-line packages with body length less than external lead pitch equal less than Dimension Board Thickness Board Dimension (package length Board Material Fan-out Trace Length (minimum) Fan-out Trace Position Trace Thickness Trace Width lead pitch Specification 1.57 (0.062") 76.2 114.3 (3.0" 4.5") FR-4 Epoxy Glass (0.98") centered 76.2 76.2 0.071 (0.0028")± (0.016")
Table JEDEC Thermal Test Board Thermal modeling uses internally developed software package, ThermCal. software divides package into large number small elements (meshing) then calculates temperature each element based temperatures surrounding elements.
TVSOP Power Dissipation Thermal Resistance Characteristics Device junction temperature mainly determined power consumption, surrounding temperature thermal resistance between junction atmosphere. relationship expressed following equation: where: Junction Temperature Ambient Temperature Power Thermal Resistance
Equation Junction Temperature Relationship Thermal resistivity package's resistance heat dissipation. Thermal resistivity inversely related thermal conductivity (k). When device reaches state equilibrium, electrical power delivered equal thermal heat dissipated. This thermal energy form heat given surroundings. maximum allowable power consumption given surrounding temperature computed using maximum junction temperature chip:
Equation Power Equilibrium Equation Figures through show derating curves which were obtained from above equation using thermal resistance values determined using Jedec standard boards with 1000 trace length maximum junction temperature 150° factors affecting thermal resistance mainly determined material selection, geometry packages, airflow, length width traces board. Natural convection, many cases, enough adequate heat dissipation. solution induce airflow across device. data TVSOP package shows that migrating from natural convection forced convection decrease thermal resistivity much
1.00 ft/min ft/min ft/min ft/min
0.90
0.80 Maximum Power Dissapation (Watts)
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00 Ambient Temperature (°C)
Velocity (ft/min) (°C/W)
Figure 14-pin TVSOP Derating Curves
1.00 ft/min 0.90 ft/min ft/min ft/min
0.80 Maximum Power Dissapation (Watts)
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00 Ambient Temperature (°C)
Velocity (ft/min) (°C/W)
Figure 16-pin TVSOP Derating Curves
1.40 ft/min ft/min ft/min ft/min
1.20
Maximum Power Dissapation (Watts)
1.00
0.80
0.60
0.40
0.20
0.00 Ambient Temperature (°C)
Velocity (ft/min) (°C/W)
Figure 20-pin TVSOP Derating Curves
1.40 ft/min ft/min ft/min ft/min
1.20
Maximum Power Dissipation (Watts)
1.00
0.80
0.60
0.40
0.20
0.00 Ambient Temperature
Velocity (ft/min) (°C/W)
Figure 24-pin TVSOP Derating Curves
2.50 ft/min ft/min ft/min ft/min 2.00 Maximum Power Dissipation (Watts)
1.50
1.00
0.50
0.00 Ambient Temperature (°C)
Velocity (ft/min) (°C/W)
Figure 48-pin TVSOP Derating Curves
3.00 ft/min ft/min ft/min ft/min
2.50
Maximum Power Dissipation (Watts)
2.00
1.50
1.00
0.50
0.00 Ambient Temperature (°C)
Velocity (ft/min) (°C/W)
Figure 56-pin TVSOP Derating Curves
1.60 ft/min 1.40 ft/min ft/min
Maximum Power Dissipation (Watts)
1.20
1.00
0.80
0.60
0.40
0.20
0.00 Ambient Temperature (°C)
Velocity (ft/min) (°C/W) (°C/W)
23.3
Figure 80-pin TVSOP Derating Curves
4.00 ft/min ft/min ft/min ft/min
3.50
Maximum Power Dissipation (Watts)
3.00
2.50
2.00
1.50
1.00
0.50
0.00 Ambient Temperature (°C)
Velocity (ft/min) (°C/W)
Figure 100-pin TVSOP Derating Curves
Power Calculations1 When calculating total power consumption circuit, both static dynamic currents must taken into account. Both bipolar BiCMOS devices have varying staticcurrent levels, depending state output (ICCL, ICCH, ICCZ), while CMOS device single value ICC. These values found individual data sheets. compatible CMOS BiCMOS inputs, when driven levels, also consume additional current because they driven GND; therefore, input transistors switched completely off. This value, known ICC, also provided data sheet. Dynamic power consumption results from charging discharging external load internal parasitic capacitances. parameter CMOS device parasitic capacitance which listed data sheet obtained using following equation: (dynamic input frequency (Hz) supply voltage load capacitance measured input current value
Where:
Equation Power Dissipation Capacitance Although value provided other device types, versus frequency curves display essentially same information. slope curve provides value form mA/(MHz bit), which when multiplied number outputs switching desired frequency, provides dynamic power dissipated device without load current. Equations through used calculate total power CMOS, BiCMOS bipolar devices: OTAL TATIC PD(YNAMIC Equation Total Power CMOS products with CMOS level inputs:
Equation Power Calculation CMOS Input Levels
information presented this section copied slightly modified form from Package Thermal Considerations Applications Note, SCZA002A. information also published Advanced BiCMOS Technology Data Book, SCBD002B, 1994, 13-97 13-108 other literature.
compatible CMOS products with level inputs: (dcd
Equation Power Calculations Input Levels BiCMOS Bipolar Products dcen dcen Note: bipolar devices Equation Static Power Calculation BiCMOS Bipolar Products dcen dcen MHz(bit
Equation Dynamic Power Calculation BiCMOS Bipolar Products Where:
ICCL ICCH ICCZ dcen mA/(MHz bit) Supply Voltage Power supply current (A), data sheet Power supply current outputs low, data sheet Power supply current outputs high, data sheet Power supply current outputs high impedance, data sheet Power supply current CMOS inputs level, data sheet percent duty cycle enabled percent duty cycle disabled Number outputs high state Number outputs state Number outputs switching Total number outputs Operating frequency (Hz) Operating frequency (MHz) Output voltage high state Output voltage state External load capacitance Slope frequency curve
Electrical Characteristics Mike Lamson, Process Automation Center Maria Balian, Package Development electrical characteristics packages used normally determined computer modeling programs developed in-house (PACED2) commercially available software. Electrical parameters also measured laboratories verify modeling data. measurement methods follow EIA/JEDEC Guideline EIA/JEP123 include Impedance Meters, Time Domain Reflectometers (TDR's) Network Analyzers. electrical modeling program calculates following parameters: Resistance with high frequency effects Capacitance including loading coupling capacitance Inductance including self mutual inductance
parameters available each package being modeled reported tabular form range values longest shortest leads. SPICE input file package also created modeling program. SPICE file produced formats: lumped parameter file where each lead bond wire represented element distributed parameter file where lead bond wire represented many elements. distributed version represents varying sections lead more accurately used higher frequency simulations. characteristic impedance (ZO) also calculated each section lead bond wire. This important impedance matching consideration design high speed applications. Electrical Parameters Resistance resistance package conductor significant certain package families source voltage drop. molded packages with copper (=1.7 µohm-cm)3 lead frames, most resistance bond wire because very small cross section (100 milliohms/0.1in.). alloy (=48.8 µohm-cm) lead frames used, resistance lead several hundred milli-ohms therefore much higher than wire bonds. Co-fired ceramic packages tend have higher conductor resistance since material used Tungsten/Glass mixture (=25 µohm-cm). Other families which have significant trace resistance include thin film processed interconnects some multi-chip modules thickness conductors.
PACED: Process Automation Center Electrical Design software (rho): Electrical Resistivity
Capacitance Capacitance function lead surface proximity dielectric constant insulating material. These surfaces include conductor leads, power ground planes presence floating metal such heat spreaders. electrical models molded lead frame packages assume ground plane exists board which mounted. capacitance ground usually very small these style packages most loading capacitance interlead coupling. This coupling capacitance source crosstalk noise from lead lead. relative dielectric constant vary widely among package families. Mold compound have relative dielectric constants alumina ceramic packages range from some lead-zinc-borate solder glass materials high Changing proximity conductor another affect coupling capacitance third conductor. This exploited some designs moving ground plane closer conductor leads reduce interlead coupling. Inductance Inductance function current distribution package relative permeability conductor material. Because dependence current distribution, effective inductance lead will depend ground return path system. Moving ground plane closer conductor lead will decrease magnetic field around lead reduce self mutual inductance other leads. lead width also significantly influences self inductance. Minimum inductance achieved when lead width height-of-lead-from-groundplane ratio maximized. Bond wires significant source inductance because their very narrow effective width. proximity floating, non-ferrous, metal, heat spreaders, will also decrease effective inductance eddy currents flowing these structures. eddy currents flow opposite direction from lead currents total magnetic field reduced. frequency increases, self inductance package lead will decrease. This caused reduction magnetic field internal lead skin effect (current density greater near surface conductor less center). copper lead frames, this effect very small usually ignored. magnetic lead frame materials with higher relative permeability such alloy42, frequency dependence large. modern devices, however, fast rise times dictate high frequency bandwidth package alloy42 self inductance will approach that copper. Solutions reducing effective inductance, especially ground power leads, includes increasing number lead paths that function multiple wire bonding same package pin. Doubling conductors, however, does reduce inductance half. mutual inductance between leads prevents this from happening leads tightly coupled, inductance only decrease percent maximize reduction
effective inductance, leads serving same function, such ground power, should apart possible. TVSOP Electrical Data Following electrical characteristics TVSOP packages. Figures through show minimum maximum range capacitance inductance 56-pin narrow body TVSOP packages 100-pin wide body TVSOP packages.
Minimum Maximum
Inductance (nH)
DGV14 DGV16 DGV20 DGV24 DGV48 DGV56 Narrow Body TVSOP Package Count
Figure TVSOP Package Inductance (14, 56-pin)
Minimum Maximum
Inductance (nH)
DBB80 DBB100 Wide Body TVSOP Package Count
Figure TVSOP Package Inductance 100-pin)
Minimum Maximum
Capacitance (pF)
DGV14 DGV16 DGV20 DGV24 DGV48 DGV56 Narrow Body TVSOP Count
Figure TVSOP Package Capacitance (14, 56-pin)
Minimum Maximum
Capacitance (pF)
DBB80 DBB100 Wide Body TVSOP Count
Figure TVSOP Package Capacitance 100-pin)
TVSOP Package Notes:
Resistance (ohms) 0.037 0.040 0.029 0.040 0.039 0.041 0.035 0.040 0.027 0.045 0.050 0.062 0.042 0.083 0.046 0.066
Inductance (nH) 2.31 2.85 2.32 2.86 2.43 3.21 2.17 2.94 2.26 3.71 2.57 3.84 2.50 5.57 2.58 5.51
Capacitance (pF) 0.26 0.34 0.25 0.39 0.30 0.47 0.30 0.49 0.28 0.53 0.27 0.55 0.25 0.93 0.28 0.89
Copper based leadframe gold bond wire Electrical values based maximum packages Ground plane single layer power ground planes) located board
Definitions: Self inductance Loading capacitance
Table Summary TVSOP Electrical Data
TVSOP SSOP
Self Inductance (nH)
Package Count
Figure TVSOP SSOP Self Inductance Comparison
Reliability Qualification Data 14-Pin TVSOP
Operating Life Static Test 125° 1000 Hours Biased Humidity 1000 Hours Temperature Cycle Test -65° 150° 1000 Cycles Autoclave 121° psi, Hours Solderability Solder Heat Lead Fatigue Lead Pull Destruction Lead Finish Adhesion Flammability (UL) Flammability (IEC) Salt Atmosphere X-ray View Only Manufacturability Physical Dimensions Moisture Sensitivity (Level
Required Fails 116/0 116/0 116/0 76/0 22/0 22/0 22/0 22/0 15/0 22/0 Pass/Fail 12/0
AABT126DGV Act. Fails 116/0 116/0 116/0 76/0 22/0 22/0 22/0 22/0 15/0 22/0 Pass 12/0
20-Pin TVSOP
Operating Life Static Test 125° 1000 Hours Biased Humidity 1000 Hours Temperature Cycle Test -65° 150° 1000 Cycles Autoclave 121° psi, Hours Solderability Solder Heat Lead Fatigue Lead Pull Destruction Lead Finish Adhesion Flammability (UL) Flammability (IEC) Salt Atmosphere X-ray View Only Manufacturability Physical Dimensions Moisture Sensitivity (Level
Required Fails 116/0 116/0 116/0 76/0 22/0 22/0 22/0 22/0 15/0 22/0 Pass/Fail 20/0
LVT244ADGV Act. Fails 116/0 116/0 116/0 76/0 22/0 22/0 22/0 22/0 15/0 22/0 Pass 20/0
Notes: Notes: Condition level preconditioning sequence: Condition level preconditioning sequence: C/85 relative humidity hours with bias, then C/60 relative humidity hours with bias, then Board mount (DGG, packages only), then Board mount (DGG, packages only), then 215° solder reflow simulation, minute room temp delay, another solder reflow 215° solder reflow simulation, minute room temp delay, another solder reflow simulation, then simulation, then Device clean-up with isopropyl alcohol rinse, de-ionized water rinse hour Device clean-up with isopropyl alcohol rinse, de-ionized water rinse hour drying period. drying period.
Table 14-pin TVSOP Package Reliability Results
Table 20-pin TVSOP Package Reliability Results
48-Pin TVSOP
Operating Life Static Test 125° 1000 Hours Biased Humidity 1000 Hours Storage Life Test 150° 1000 Hours Temperature Cycle Test -65° 150° 1000 Cycles Autoclave 121° psi, Hours Solderability Solder Heat Lead Fatigue Lead Pull Destruction Lead Finish Adhesion Flammability (UL) Flammability (IEC) Salt Atmosphere Resist Solvent X-Ray View Only Manufacturability Physical Dimensions Moisture Sensitivity (Level
Notes:
Required Fails 116/0 116/0 90/0 116/0 76/0 44/0 44/0 10/0 10/0 44/0 24/0 10/0 Pass/Fail 10/0 20/0
ABT16640DGV Act. Fails 116/0 116/0 90/0 116/0 76/0 44/0 44/0 10/0 10/0 44/0 24/0 10/0 Pass 10/0 20/0
80-Pin TVSOP
Operating Life Static Test 125° 1000 Hours Biased Humidity 1000 Hours Storage Life Test 150° 1000 Hours Temperature Cycle Test -65° 150° 1000 Cycles Autoclave 121° psi, Hours Lead Fatigue Lead Pull Destruction Lead Finish Adhesion Salt Atmosphere X-Ray View Only Manufacturability Physical Dimensions Moisture Sensitivity (Level
Required Fails 120/0 116/0 45/0 120/0 78/0 66/0 24/0 Pass/Fail 12/0
ALVC16901DBB Act. Fails 120/0 116/0 45/0 120/0 78/0 66/0 24/0 Pass 12/0
Notes: Condition level preconditioning sequence: C/85 relative humidity hours with bias, then Board mount (DGG, packages only), then 215° solder reflow simulation, minute room temp delay, another solder reflow simulation, then Device clean-up with isopropyl alcohol rinse, de-ionized water rinse hour drying period. Condition level preconditioning sequence: Condition level preconditioning sequence: C/60 relative humidity hours with bias, then C/60 relative humidity hours with bias, then Board mount (DGG, packages only), then Board mount (DGG, packages only), then 215° solder reflow simulation, minute room temp delay, another solder reflow 215° solder reflow simulation, minute room temp delay, another solder reflow simulation, then simulation, then Device clean-up with isopropyl alcohol rinse, de-ionized water rinse hour Device clean-up with isopropyl alcohol rinse, de-ionized water rinse hour drying period. drying period.
Table 48-pin TVSOP Package Reliability Results
Table 80-pin TVSOP Package Reliability Results
Delivery TVSOP Customers Moisture Sensitivity TVSOP Moisture sensitivity describes characteristic some plastic surface mount packages absorb sufficient moisture from their environment cause package cracking when exposed extreme temperature reflow soldering. During reflow soldering (IR, VPR, wave solder), flash vaporization absorbed moisture causes high stress resulting internal cracking delamination between chip leadframe chip pad. Packages tested moisture sensitivity accordance with JESD A112. Those packages which fail meet Level designated "moisture sensitive" packed. Table describes recommended floor life package after removed from sealed pack prior soldering. floor life extended sealing pack bags soon possible after removing components used.
Level Floor Life Conditions Duration Unlimited Year Hours Hours Hours Hours
Table TVSOP Moisture Sensitivity Pack method protecting moisture sensitive plastic surface mount devices from moisture during shipment storage. parts initially baked then placed inside moisture vapor barrier with desiccant. desiccant absorbs moisture keeps humidity inside safe level. moisture vapor barrier used pack maximum transmission rate 0.02g/100 square inches hours. desiccant used absorb grams water unit Relative Humidity (RH). actual shelf life will vary based storage conditions, quality moisture barrier provides, number desiccants used size package. humidity indicator card also added which shows internal humidity increments. this card verify that humidity level inside exceeded safe level. humidity inside pack exceeds recommended limit shown drypack label, parts must baked before soldering. Baking conditions duration described drypack labels along with outline necessary precautions seal date products. uses this pack method regardless whether parts shipped tubes tape reel.
Moisture Sensitivity Qualification Data Count Moisture Level 14-Pin Level 16-Pin Level 20-Pin Level 24-Pin Level 48-Pin Level 56-Pin Level 80-Pin Level 100-Pin Level Table TVSOP Moisture Sensitivity Levels Further reliability tests have been submitted 24-pin packages determine whether they reclassified "non-moisture sensitive" (level moisture sensitivity). Tape Reel purpose this method packaging position components such that they automatically placed. Components such limited diodes, capacitors, resistors, transistors, inductors integrated circuits packed this manner. packing materials used normally include carrier tape, cover tape reel. material used meets Industry guidelines protection. Dimensions selected based package size design configurations. dimensions established within recommendations Electronics Industry Association Standard EIA-481-1, EIA-481-2 EIA-481-3. dimensions that particular interest end-user tape width, pocket pitch quantity reel. following figures illustrate typical designs carrier tape reels TVSOP packages.
Cover Tape Width
Carrier Tape Width
Carrier Tape
Direction Feed
Cover Tape Width
Carrier Tape Width
Carrier Tape
Pocket/Component Pitch Center Center Pocket
Package
Pins 14-48
Carrier Tape Width (mm) 16.00 24.00 24.00 32.00
Cover Tape Width (mm) 13.3 21.0 21.0 25.5
Pocket Pitch (mm) 8.00 8.00 12.00 16.00
Quantity Reel 2000 2000
Figure Carrier Cover Tape Information Reeled TVSOP Packages
Reel Diameter
Reel Width Cover Tape Width
Package Type (number pins) (14-48 (56), (80) (100)
Carrier Tape Cover Tape Width Width 16.00 13.3 24.00 21.0 32.00 25.5 Dimensions
Reel Width 16.4 24.4 32.4
Reel Diameter
Figure Reel Dimensions Test Sockets following table lists available test sockets from Yamaichi Enplas (note that sockets `closed tooling'):
Vendor Yamaichi Yamaichi Yamaichi Yamaichi Yamaichi Yamaichi Yamaichi Enplas Yamaichi Count Socket with Flange IC51-0142-2074-MF IC51-0162-2073-MF IC51-0202-2072-MF IC51-0242-2071-MF IC51-0482-2069-MF IC51-0562-2067-MF IC51-0802-2077-MF IC51-1002-2076-MF Socket without Flange IC51-0142-2074 IC51-0162-2073 IC51-0202-2072 IC51-0242-2071 IC51-0482-2069 IC51-0562-2067 IC51-0802-2077 FP-80-0.4-01 IC51-1002-2076
Table Available TVSOP Test Sockets
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