SC417 SC427
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SC417 - SC417
SC427 - SC427
SC417/SC427
Integrated Regulator with Programmable
POWER MANAGEMENT Features
Input voltage Internal power MOSFETs Integrated bootstrap switch Smart power-save protection Configurable 150mA with bypass capability compensated RDS(ON) sensed current limit Pseudo-fixed frequency adaptive on-time control Designed with ceramic capacitors Programmable UVLO threshold Independent enable switcher Selectable ultra-sonic power-save (SC417) Selectable power-save (SC427) Internal soft-start soft-shutdown output Internal reference tolerance Over-voltage/under-voltage fault protection Power good output SmartDriveLead-free 5x5mm, MLPQ package Fully WEEE RoHS compliant
Description
SC417/SC427 stand-alone synchronous buck power supply. features integrated power MOSFETs, bootstrap switch, programmable spacesaving MLPQ-5x5mm 32-pin package. device highly efficient uses minimal area. uses pseudo-fixed frequency adaptive on-time operation provide fast transient response. SC417/SC427 supports using standard capacitor types such electrolytic special polymer, addition ceramic, switching frequencies 1MHz. programmable frequency, synchronous operation, selectable power-save provide high efficiency operation over wide load range. output programmable from 0.75V 5.25V using external resistors. bias voltage device supplied on-chip when 4.5V, external supply. When separate source used bias supply, programmed provide different voltage. Additional features include cycle-by-cycle current limit, soft-start, under over-voltage protection, programmable over-current protection, soft shutdown, selectable power-save. device also provides separate enable inputs controller well power good output controller. input voltage range from 28V. wide input voltage range, programmable frequency, programmable make device extremely flexible easy broad range applications. Support provided single cell multi-cell battery systems addition traditional power supply applications.
Applications
Notebook, desktop, tablet, server computers Networking telecommunication equipment Printers, DSL, applications Embedded applications Power supply modules Point load power supplies
March 2009
2009 Semtech Corporation
SC417/SC427
Typical Application Circuit
ENABLE
RILIM 7.5K
ENABLE/ PSAVE PGOOD
RTON 154K Note: tied VLDO
AGND AGND VOUT VLDO
AGND EN/PSV ILIM PGOOD
RLDO1 56.2K
SC417/SC427
RLDO2 100nF
PGND PGND PGND PGND PGND PGND
0.1F
+12V
RGND
CBST
LXBST PGND PGND
0.88H
1.05V 10A, 250kHz
COUT1 220F RFB1 COUT2 220F
VOUT
10nF
100pF
RFB2
Components Component COUT1, COUT2 Value 22F/25V 220F/15m/6.3V 0.88H/20A Manufacturer Murata Panasonic Vishay Part Number GRM32ER61E226KE15L EEFUE0J221R IHLP4040DZERR88M11 www.murata.com www.panasonic.com www.vishay.com
other small signal components (resistors capacitors) standard devices.
SC417/SC427
Configuration
PGOOD EN/PSV AGND ILIM
Ordering Information
Device
Package MLPQ-32 MLPQ-32
Evaluation Board Evaluation Board
SC417MLTRT(1)(2) SC427MLTRT(1)(2)
AGND VOUT VLDO
View
PGND PGND PGND PGND PGND PGND
SC417EVB SC427EVB
AGND
Notes: Available tape reel only. reel contains 3000 devices. Lead-free packaging only. Device WEEE RoHS compliant.
LXBST
MLPQ-32; 5x5, LEAD
Marking Information
PGND
PGND
SC417 yyww xxxxxx xxxxxx
yyww Date Code xxxxxx Semtech Number xxxxxx Semtech Number
SC427 yyww xxxxxx xxxxxx
yyww Date Code xxxxxx Semtech Number xxxxxx Semtech Number
SC417/SC427
Absolute Maximum Ratings
PGND (V). -0.3 PGND (transient 100ns max.) PGND (V). -0.3 EN/PSV, PGOOD, ILIM, -0.3 +(V5V 0.3) VOUT, VLDO, FBL, -0.3 +(V5V 0.3) PGND -0.3 PGND -0.3 +(V5V 1.5) -0.3 -0.3 +6.0 PGND -0.3 AGND PGND -0.3 +0.3 Protection Level(1) (kV)
Recommended Operating Conditions
Input Voltage PGND VOUT PGND
Thermal Information
Storage Temperature (°C) +150 Maximum Junction Temperature (°C) Operating Junction Temperature (°C) +125 Thermal resistance, junction ambient (°C/W) High-side MOSFET Low-side MOSFET controller thermal resistance Peak Reflow Temperature (°C)
Exceeding above specifications result permanent damage device device malfunction. Operation outside parameters specified Electrical Characteristics section recommended. NOTES: Tested according JEDEC standard JESD22-A114. Calculated from package still air, mounted (in), layer with thermal vias under exposed JESD51 standards.
Electrical Characteristics
Unless specified: =12V, +25°C Typ, Max, 125°C, +5V, Typical Application Circuit
Parameter
Input Supplies Input Supply Voltage Voltage
Conditions
Units
Sensed pin, rising edge 2.40 2.235 2.60 2.40 EN/PSV
2.95
UVLO Threshold(1) Sensed pin, falling edge UVLO Hysteresis EN/PSV High Measured pin, rising edge UVLO Threshold Measured pin, falling edge UVLO Hysteresis 3.75 2.565
Supply Current Standby mode; ENL=V5V, EN/PSV
SC417/SC427
Electrical Characteristics (continued)
Parameter
Input Supplies (continued) EN/PSV SC417, EN/PSV V5V, load (fSW 25kHz), 500mV(2) SC427, EN/PSV V5V, load, 500mV(2) 250kHz, EN/PSV floating load(2) Static load, On-Time Threshold Static load, Continuous mode operation Frequency Range Minimum fSW, (SC417 only), EN/PSV V5V, load Bootstrap Switch Resistance Timing On-Time Minimum On-Time Minimum Off-Time Soft-Start Soft-Start Ramp Time Analog Inputs/Outputs VOUT Input Resistance Current Sense Zero-Crossing Detector Threshold Power Good Upper limit, internal 500mV reference Power Good Threshold Lower limit, internal 500mV reference Start-Up Delay Time Fault (noise immunity) Delay Time(2) Leakage Power Good On-Resistance PGND Continuous mode operation, 15V, VOUT fSW= 300kHz, RTON 133k 1110 1220 0.495 0.505 1000 0.496 0.500 0.504
Conditions
Units
Supply Current
SC417/SC427
Electrical Characteristics (continued)
Parameter
Fault Protection Valley Current Limit ILIM Source Current ILIM Comparator Offset Output Under-Voltage Fault Smart Power-save Protection Threshold Over-Voltage Protection Threshold Over-Voltage Fault Delay(2) Over-Temperature Shutdown(2) Logic Inputs/Outputs Logic Input High Voltage Logic Input Voltage EN/PSV Input PSAVE Operation EN/PSV Input Forced Continuous Operation EN/PSV Input Disabling Switcher EN/PSV Input Bias Current Input Bias Current FBL, Input Bias Current EN/PSV= AGND FBL, AGND 10°C hysteresis With respect AGND with respect internal 500mV reference, consecutive clocks with respect internal 500mV reference with respect internal 500mV reference RILIM 5.9k
Conditions
Units
SC417/SC427
Electrical Characteristics (continued)
Parameter
Linear Regulator (LDO) Accuracy VLDO load 10mA Start-up foldback, Current Limit Operating current limit, VLDO VOUT Switch-over Threshold VLDO VOUT Non-switch-over Threshold VLDO VOUT Switch-over Resistance Drop Voltage VOUT From VVLDO, VVLDO +5V, IVLDO 100mA -140 -450 +140 +450 0.735 0.75 0.765
Conditions
Units
Notes: UVLO programmable using resistor divider from AGND. voltage compared internal reference. Guaranteed design. switch-over threshold maximum voltage differential between VLDO VOUT pins which ensures that VLDO will internally switch-over VOUT. non-switch-over threshold minimum voltage differential between VLDO VOUT pins which ensures that VLDO will switch-over VOUT. drop voltage voltage which output drops below nominal regulation point.
SC417/SC427
Typical Characteristics
Characteristics this section based using Typical Application Circuit page (SC417/SC427).
Efficiency Load Forced Continuous Mode
Internally biased VLDO 12V, VOUT 1.050V
1.100
VOUT Load Forced Continuous Mode
Internally biased VLDO 12V, VOUT 1.050V
1.075
Efficiency
VOUT
1.050 1.025
IOUT
10.0
1.000
IOUT
10.0
Efficiency Load Powersave Mode (SC417)
Externally biased 12V, VOUT 1.050V
Efficiency Load Powersave Mode (SC417)
Internally biased VLDO 12V, VOUT 1.050V
Efficiency
Efficiency
1.00 IOUT 10.00
0.10
0.10
1.00 IOUT
10.00
Efficiency Load Powersave Mode (SC427)
Externally biased 12V, VOUT 1.050V
Efficiency Load Powersave Mode (SC427)
Internally biased VLDO 12V, VOUT 1.050V
Efficiency
Efficiency
IOUT
10.0
IOUT
10.0
SC417/SC427
Typical Characteristics (continued)
Characteristics this section based using Typical Application Circuit page (SC417/SC427).
Frequency Load Forced Continuous Mode
Internally biased VLDO 12V, VOUT 1.050V
0.20
VRIPPLE Load Forced Continuous Mode
Internally biased VLDO 12V, VOUT 1.050V
+15%
VRIPPLE (VP-P)
0.15
Freq (kHz)
-15%
0.10
0.05
50mV
VOUTP-P
IOUT
10.0
0.00
IOUT
10.0
VOUT Load Powersave Mode (SC417)
1.100 Internally biased VLDO 12V, VOUT 1.050V
1.100
VOUT Load Powersave Mode (SC427)
Internally biased VLDO 12V, VOUT 1.050V
1.075
1.050
VOUT
1.050
VOUT
1.000
1.025
0.950
1.000 0.10
1.00 IOUT
10.00
0.900 IOUT 10.0
VOUT Line Forced Continuous Mode
1.100 Internally biased VLDO 12V, VOUT 1.050V
1.075
VOUT
1.050 1.025
1.000
10.0
12.0
14.0 16.0
18.0
20.0
22.0
24.0
SC417/SC427
Typical Characteristics (continued)
Characteristics this section based using Typical Application Circuit page (SC417/SC427).
Ultrasonic Powersave Mode Load (SC417)
12V, VOUT 1.05V, IOUT VLDO EN/PSV= 1.073V (50mV/div) 1.044V 29mV (50mV/div)
Powersave Mode Load (SC427)
12V, VOUT 1.05V, IOUT VLDO EN/PSV=
(10V/div)
f=26.22kHz
(10V/div)
(5V/div)
(5V/div) Time (10s/div) Time (10ms/div)
Self-Biased Start-Up Power Good True
step, VOUT 1.05V, IOUT VLDO EN/PSV=
Forced Continuous Mode Load
12V, VOUT 1.05V, IOUT VLDO EN/PSV= float 1.078V (50mV/div) 30mV
(10V/div) 1.05V (10V/div) (500mV/div) (2V/div) V/ms (10V/div) (5V/div) (5V/div) Time (400s/div)
1.048V f=227.4kHz
Time (2s/div)
Enabled Loaded Output Full Scale
12V, VOUT 1.05V, IOUT VLDO EN/PSV= 1.05V
Enabled Loaded Output Power Good True
12V, VOUT 1.05V, IOUT VLDO EN/PSV= 1.05V
(50mV/div) 1.4V/ms (500mV/div)
(10V/div)
(10V/div) ~2ms
(5V/div) Time (100s/div)
(5V/div) Time (400s/div)
SC417/SC427
Typical Characteristics (continued)
Characteristics this section based using Typical Application Circuit page (SC417/SC427).
Transient Response Load Rising (SC417)
12V, VOUT 1.05V, IOUT 10A, VLDO EN/PSV=
Transient Response Load Falling (SC417)
12V, VOUT 1.05V, IOUT VLDO EN/PSV= 1.101V
1.063V (50mV/div) 1.025V
(50mV/div) 1.055V
(10V/div)
(10V/div)
(10A/div) (10A/div) (5V/div) (5V/div)
Time (10s/div)
Time (10s/div)
Transient Response Load Rising (SC427)
12V, VOUT 1.05V, IOUT 10A, VLDO EN/PSV=
Transient Response Load Falling (SC427)
12V, VOUT 1.05V, IOUT VLDO EN/PSV=
(50mV/div)
(50mV/div)
(10V/div)
(10V/div)
(5A/div) (5A/div) (5V/div) (5V/div)
Time (10s/div)
Time (10s/div)
Output Under-voltage Response Normal Operation
12V, VOUT 1.05V, IOUT VLDO floating EN/PSV
Output Over-current Response Normal Operation
12V, VOUT 1.05V, VLDO EN/PSV= floating; IOUT ramped trip point (500mV/div) 1.05V
(10V/div) (500mV/div) V2~710mV (10A/div) IOUT 10.37A
(10V/div) (5V/div) (5V/div)
Time (100s/div)
Time (100s/div)
SC417/SC427
Typical Characteristics (continued)
Characteristics this section based using Typical Application Circuit page (SC417/SC427).
Shorted Output Response Normal Operation
12V, VOUT 1.05V, IOUT VLDO EN/PSV= (500mV/div) 1.05V
Shorted Output Response Power-UP Operation
12V, VOUT 1.05V, IOUT VLDO EN/PSV= ~1.7ms (500mV/div)
(10A/div) (10A/div)
(10V/div) (5V/div)
(10V/div)
(5V/div) Time (40s/div) Time (400s/div)
SC417/SC427
Descriptions
Name
Function
Feedback input switching regulator used program output voltage connect external resistor divider from VOUT AGND. Feedback input connect external resistor divider from VLDO AGND used program output. power input internal analog circuits gate drives connect external supply configure connect VLDO. Analog ground Switcher output voltage sense also input internal switch-over between VOUT VLDO. voltage this must less than equal voltage pin. Input supply voltage output voltage this must less than equal voltage pin. Bootstrap connect capacitor least 100nF from develop floating supply high-side gate drive. High-side gate drive connect this Boost connect capacitor. Switching (phase) node Low-side gate drive connect this Power ground Open-drain power good indicator high impedance indicates power good. external pull-up resistor required. Current limit sense used program current limit connecting resistor from ILIM sense connects RILIM. Enable/power-save input switching regulator connect AGND disable switching regulator. Float operate forced continuous mode (power-save disabled). SC417 connect operate with ultra-sonic power-save mode enabled. SC427 connect operate with power-save mode enabled with minimum frequency. On-time programming input on-time connecting through resistor AGND Enable input connect AGND disable LDO. Drive with logic logic control, program UVLO with resistor divider between VIN, ENL, AGND.
9-11, 23-25, 15-22
AGND VOUT
VLDO LXBST PGND PGOOD ILIM
EN/PSV
SC417/SC427
Block Diagram
Bootstrap Switch AGND Reference Control Status Soft Start Hi-side MOSFET Comparator Zero Cross Detector VOUT Bypass Comparator Valley Current Limit VLDO VLDO Switchover connected pins 9-11, connected pins 23-25, connected pins 15-22 connect pins ILIM Lo-side MOSFET PGND time Generator Gate Drive Control LXBST PGOOD EN/PSV
SC417/SC427
Applications Information
Synchronous Buck Converter
SC417/SC427 step down synchronous DC-DC buck converter with integrated power MOSFETs programmable LDO. device capable operation very high efficiency. space saving (mm) 32-pin package used. programmable operating frequency range 200kHz 1MHz enables optimizing configuration area efficiency. buck controller uses pseudo-fixed frequency adaptive on-time control. This control method allows fast transient response which permits smaller output capacitors. adaptive on-time determined internal oneshot timer. When one-shot triggered output ripple, device sends single on-time pulse highside MOSFET. pulse period determined VOUT VIN; period proportional output voltage inversely proportional input voltage. With this adaptive on-time arrangement, device automatically anticipates on-time needed regulate VOUT present condition selected frequency. advantages adaptive on-time control are:
Input Voltage Requirements
SC417/SC427 requires input supplies normal operation: V5V. operates over wide range from 28V. requires supply input that external source internal configured supply
Psuedo-fixed Frequency Adaptive On-time Control
control method used SC417/SC427 pseudo-fixed frequency, adaptive on-time, shown Figure ripple voltage generated output capacitor used ramp signal. This ripple used trigger on-time controller.
Predictable operating frequency compared other variable frequency methods. Reduced component count eliminating error amplifier compensation components. Reduced component count removing need sense control inductor current. Fast transient response response time controlled fast comparator instead typically slow error amplifier. Reduced output capacitance fast transient response
One-Shot Timer Operating Frequency
one-shot timer operates shown Figure Comparator output goes high when less than internal 500mV reference. This feeds into gate drive turns high-side MOSFET, also starts one-shot timer. one-shot timer uses internal comparator capacitor. comparator input connected OUT, other input connected capacitor. When on-time begins, internal capacitor charges from zero volts through current which proportional VIN. When capacitor voltage reaches VOUT, on-time completed high-side MOSFET turns off.
Threshold VOUT
COUT
Figure Control Method, VOUT Ripple
SC417/SC427
Applications Information (continued)
Comparator 500mV Gate Drives VOUT
COUT
Note that this control method regulates valley output ripple voltage, value. output voltage VOUT offset output ripple according following equation.
VOUT VRIPPLE
VOUT RTON
One-Shot Timer
On-time RTON (VOUT/VIN)
When large capacitor placed parallel with TOP) VOUT shown following equation.
VOUT VRIPPLE CTOP CTOP
Figure On-Time Generation This method automatically produces on-time that proportional VOUT inversely proportional VIN. Under steady-state conditions, switching frequency determined from on-time following equation.
VOUT
Enable Power-save Inputs
EN/PSV inputs used enable disable switching regulator LDO. When EN/PSV (grounded), switching regulator lowest power state. When off, output switching regulator soft-discharges output into internal resistor VOUT pin. When EN/PSV allowed float, voltage will float voltage V5V. switching regulator turns with power-save disabled switching forced continuous mode. When EN/PSV high (above voltage V5V) SC417, switching regulator turns with ultrasonic power-save enabled. SC417 ultra-sonic powersave operation maintains minimum switching frequency 25kHz, applications with stringent audio requirements. When EN/PSV high (above voltage V5V) SC427, switching regulator turns with powersave enabled. SC427 power-save operation designed maximize efficiency light loads with minimum frequency limits. This makes SC427 excellent choice portable battery-operated systems. input used control internal LDO. This input serves second function acting ULVO sensor switching regulator. When (grounded), off. When logic high below UVLO threshold (2.6V typical), then switcher off. When above
SC417/SC427 uses external resistor ontime which indirectly sets frequency. on-time programmed provide operating frequency from 200kHz 1MHz using resistor between ground. resistor value selected following equation.
RTON (TON 10ns) 25pF
maximum RTON value allowed shown following equation.
RTON
VOUT Voltage Selection
switcher output voltage regulated comparing VOUT seen through resistor divider internal 500mV reference voltage, Figure
VOUT
Figure Output Voltage Selection
SC417/SC427
Applications Information (continued)
UVLO threshold, enabled switcher also enabled EN/PSV grounded. low-side MOSFET remains until inductor current ramps down zero, which point low-side MOSFET turned off. Because on-times forced occur intervals greater than 40s, frequency will fall below ~25kHz. Figure shows ultra-sonic power-save operation.
minimum 25kHz Ripple Voltage (VFB) threshold (500mV) Inductor Current (0A)
Forced Continuous Mode Operation
SC417/SC427 operates switcher Forced Continuous Mode (FCM) floating EN/PSV (see Figure this mode power MOSFETs always with intentional dead time other than avoid cross-conduction. This feature results uniform frequency across full load range with trade-off being poor efficiency light loads high-frequency switching MOSFETs.
Ripple Voltage (VFB) threshold (500mV)
Inductor Current
Load Current
On-time (TON)
On-time triggered when reaches Threshold
time-out
On-time (TON)
on-time triggered when reaches Threshold.
After 40sec time-out, drives high reached threshold.
Figure Ultrasonic Power-save Operation
Power-save Mode Operation (SC427)
drives high when on-time completed. remains high until falls threshold.
Figure Forced Continuous Mode Operation
Ultra-sonic Power-save Operation (SC417)
SC417 provides ultra-sonic power-save operation light loads, with minimum operating frequency fixed 25kHz. This accomplished using internal timer that monitors time between consecutive high-side gate pulses. time exceeds 40s, drives high turn low-side MOSFET This draws current from VOUT through inductor, forcing both VOUT fall. When drops 500mV threshold, next on-time triggered. After on-time completed high-side MOSFET turned low-side MOSFET turns
SC427 provides power-save operation light loads with minimum operating frequency. With power-save enabled, internal zero crossing comparator monitors inductor current voltage across low-side MOSFET during off-time. inductor current falls zero consecutive switching cycles, controller enters power-save operation. will turn low-side MOSFET each subsequent cycle provided that current crosses zero. this time both MOSFETs remain until drops 500mV threshold. Because MOSFETs off, load supplied output capacitor. inductor current does reach zero switching cycle, controller immediately exits powersave returns forced continuous mode. Figure shows power-save operation light loads.
SC417/SC427
Applications Information (continued)
Ripple Voltage (VFB) Dead time varies according load threshold (500mV) Zero (0A)
VOUT drifts leakage current flowing into COUT Smart Power Save Threshold (550mV) threshold VOUT discharges inductor low-side MOSFET Normal VOUT ripple
Inductor Current
High-side Drive (DH) Single on-time pulse after turn-off Low-side Drive (DL) turns when Smart PSAVE threshold reached turns when threshold reached Normal pulse after on-time pulse
On-time (TON) On-time triggered when reaches Threshold.
Figure Smart Power-save
drives high when on-time completed. remains high until inductor current reaches zero.
Figure Power-save Operation
Smart Power-save Protection
Active loads leak current from higher voltage into switcher output. Under light load conditions with power-save enabled, this force VOUT slowly rise reach over-voltage threshold, resulting hard shutdown. Smart power-save prevents this condition. When voltage exceeds above nominal (exceeds 550mV), device immediately disables power-save, drives high turn low-side MOSFET. This draws current from VOUT through inductor causes VOUT fall. When drops back 500mV trip point, normal switching cycle begins. This method prevents hard shutdown also cycles energy from VOUT back VIN. also minimizes operating power avoiding forced conduction mode operation. Figure shows typical waveforms Smart Power-save feature.
Current Limit Protection
device features programmable current limiting, which accomplished using RDSON lower MOSFET current sensing. current limit RILIM resistor. RILIM resistor connects from ILIM which also drain low-side MOSFET. When low-side MOSFET internal ~10A current flows from ILIM through RILIM resistor, creating voltage drop across resistor. While low-side MOSFET inductor current flows through creates voltage across RDSON. voltage across MOSFET negative with respect ground. this MOSFET voltage drop exceeds voltage across RILIM, voltage ILIM will negative current limit will activate. current limit then keeps low-side MOSFET will allow another high-side on-time, until current low-side MOSFET reduces enough bring ILIM voltage back zero. This method regulates inductor valley current level shown ILIM Figure
SmartDrivedrivers will turn high-side MOSFET lower rate initially, allowing softer, smooth turn-off low-side diode. Once diode off, SmartDrive circuit automatically drives high-side MOSFET rapid rate. This technique reduces switching while maintaining high efficiency also avoids need snubbers series resistors gate drive.
SC417/SC427
Applications Information (continued)
Inductor Current
IPEAK ILOAD ILIM
During soft-start regulator turns low-side MOSFET cycle inductor current falls zero. This prevents negative inductor current, allowing device start into pre-biased output.
Power Good Output
Time
Figure Valley Current Limit Setting valley current limit results peak inductor current plus peak ripple current. this situation, average (load) current through inductor plus one-half peak-to-peak ripple current. internal current source temperature compensated 4100ppm order provide tracking with RDSON. RILIM value calculated following equation. RILIM ILIM When selecting value RILIM sure exceed absolute maximum voltage value ILIM pin. Note that because low-side MOSFET with RDSON used current sensing, layout, solder connections, connection node must done carefully obtain good results. RILIM should connected directly (pin 28).
power good (PGOOD) output open-drain output which requires pull-up resistor. When output voltage below nominal voltage, PGOOD pulled low. held until output voltage returns above nominal. PGOOD held during start-up will allowed transition high until soft-start completed (when reaches 500mV) typically passed. PGOOD will transition exceeds +20% nominal, which also over-voltage shutdown threshold (600mV). PGOOD also pulls EN/PSV when present.
Output Over-Voltage Protection
Over-voltage protection becomes active soon device enabled. threshold 500mV (600mV). When exceeds threshold, latches high low-side MOSFET turned remains high controller remains off, until EN/PSV input toggled cycled. There delay built into detector prevent false transitions. PGOOD also after event.
Output Under-Voltage Protection
When falls below nominal voltage (falls 375mV) eight consecutive clock cycles, switcher shut drives pulled tristate MOSFETs. controller stays until EN/PSV toggled cycled.
Soft-Start Regulator
Soft-start achieved regulator using internal voltage ramp reference Comparator. voltage ramp generated using internal charge pump which drives reference from zero 500mV ~1.2mV increments, using internal ~500kHz oscillator. When ramp voltage reaches 500mV, ramp ignored comparator switches over fixed 500mV threshold. During soft-start output voltage tracks internal ramp, which limits start-up inrush current provides controlled softstart profile wide range applications. Typical softstart ramp time 850s.
UVLO,
Under-Voltage Lock-Out (UVLO) circuitry inhibits switching tri-states DH/DL drivers until rises above 3.9V. internal Power-On Reset (POR) occurs when exceeds 3.9V, which resets fault latch soft-start counter prepare soft-start. SC417/SC427 then begins soft-start cycle. will shut falls below 3.6V.
SC417/SC427
Applications Information (continued)
Regulator
device features integrated regulator with programmable output voltage from 0.75V 5.25V using external resistors. feedback (FBL) regulated 750mV. There also enable (ENL) that provides independent control. voltage also used provide bias voltage switching regulator.
VLDO RLDO1 RLDO2
VVLDO Final VVLDO Final Voltage regulating with ~200mA current limit
Constant current startup
Figure Start-Up
Switch-Over Operation
SC417/SC427 includes switch-over function LDO. switch-over function designed increase efficiency using more efficient DC-DC converter power output, avoiding less efficient regulator when possible. switch-over function connects VLDO directly VOUT using internal switch. When switch-over complete turned off, which results power savings maximizes efficiency. output used bias SC417/SC427, then after switch-over device selfpowered from switching regulator with turned off. switch-over logic waits switching cycles before starts switch-over. There methods that determine switch-over VLDO VOUT. first method, already regulation DC-DC converter later enabled. soon PGOOD output goes high, cycles started. voltages VLDO VOUT pins then compared; voltages within ±300mV each other, VLDO connects VOUT using internal switch, turned off. second method, DC-DC converter already running enabled. this case cycles started soon reaches final value. this time, VLDO VOUT pins compared, within ±300mV switch-over occurs turned off.
Figure Start-Up output voltage following equation.
VLDO 750mV RLDO1 RLDO
minimum capacitance referenced AGND normally required output stability. providing bias power device, then minimum 0.1F capacitor referenced AGND required along with minimum 1.0F capacitor referenced PGND filter gate drive pulses. Refer layout guidelines section.
Start-up
Before start-up, checks status following signals ensure proper operation maintained. VLDO output input voltage When high above UVLO point, will begin start-up. During initial phase, when output voltage near zero, initiates current-limited start-up (typically 85mA) charge output capacitor. When VLDO reached final value sensed pin), current limit increased ~200mA output quickly driven nominal value internal regulator.
SC417/SC427
Applications Information (continued)
Switch-over Limitations VOUT VLDO
Because internal switch-over circuit always compares VOUT VLDO pins start-up, there limitations permissible combinations these pins. Consider case where VOUT programmed 3.0V VLDO programmed 3.3V. After start-up, device would connect VOUT VLDO disable LDO, since voltages within ±300mV switch-over window. avoid unwanted switch-over, minimum difference between voltages VOUT VLDO should ±500mV. recommended switch-over feature output voltage less than since this does provide sufficient voltage gate-source drive internal p-channel switch-over MOSFET.
UVLO
also acts switcher under-voltage lockout supply. UVLO voltage programmable resistor divider VIN, AGND pins. enable/disable signal LDO. order implement UVLO there also timing requirement that needs satisfied. transitions within switching cycles then will turn switcher remains goes below UVLO threshold stays above then switcher will turn remains UVLO function typical threshold 2.6V rising edge. falling edge threshold 2.4V. Note that possible operate switcher with disabled, must below logic threshold (0.4V maximum).
Switch-over MOSFET Parasitic Diodes
switch-over MOSFET contains parasitic diodes that inherent construction, shown Figure
Switchover control VLDO Switchover MOSFET VOUT
Logic Control Operation
Parasitic diode Parasitic diode
Figure Switch-over MOSFET Parasitic Diodes There some important design rules that must followed prevent forward bias these diodes. following conditions need satisfied order parasitic diodes stay off.
When input driven above 2.6V, impossible determine output going used power device not. self-powered operation where will power device, necessary during start-up hold switching until reached final value. This prevents overloading current-limited output during start-up. However, switcher previously operating (with EN/PSV high ground, supplied externally), then undesirable shut down switcher. prevent this, when input taken above 2.6V (above UVLO threshold), internal logic checks PGOOD signal. PGOOD high, then switcher already running will through start-up cycle without affecting switcher. PGOOD low, then will allow switching until output reached it's final value.
VLDO VOUT
either VLDO VOUT higher than V5V, then respective diode will turn SC417/SC427 operating current will flow through this diode. This potential damaging device.
SC417/SC427
Applications Information (continued)
Using On-chip Bias SC417/SC427
following steps must followed when using onchip bias device.
250kHz Load maximum
Connect VLDO before enabling LDO. initial current limit 40mA start-up, therefore, connect external load VLDO during start-up. When VLDO reaches final value, current limit increases 200mA. this time used supply required bias current device.
Frequency Selection Selection switching frequency requires making trade-off between size cost external filter components (inductor output capacitor) power conversion efficiency. desired switching frequency 250kHz which results from using components selected optimum size cost resistor (RTON) used program on-time (indirectly setting frequency) using following equation.
RTON (TON 10ns) 25pF VOUT
Attempting operate self-powered mode other configuration cause unpredictable results damage device.
Design Procedure
When designing switch mode supply input voltage range, load current, switching frequency, inductor ripple current must specified. maximum input voltage (VINMAX) highest specified input voltage. minimum input voltage VINMIN) determined lowest input voltage after evaluating voltage drops connectors, fuses, switches, traces. following parameters define design.
select RTON, maximum value VIN, value associated with maximum VIN.
INMAX
13.2VIN, 1.05VOUT, 250kHz Substituting RTON results following solution. RTON 154.9k, RTON 154k Inductor Selection order determine inductance, ripple current must first defined. inductor values result smaller size create higher ripple current which reduce efficiency. Higher inductor values will reduce ripple current/voltage given resistance more efficient. However, larger inductance translates directly into larger packages higher cost. Cost, size, output ripple, efficiency used selection process. ripple current will also boundary powersave operation. switching will typically enter powersave mode when load current decreases ripple current. example, ripple current then Power-save operation will typically start loads less than ripple current maximum load current, then power-save will start loads less than maximum current.
Nominal output voltage (VOUT Static output tolerance Transient response Maximum load current (IOUT
There values load current evaluate continuous load current peak load current. Continuous load current relates thermal stresses which drive selection inductor input capacitors. Peak load current determines instantaneous component stresses filtering requirements such inductor saturation, output capacitors, design current limit circuit. following values used this design.
VOUT 1.05V
SC417/SC427
Applications Information (continued)
inductor value typically selected provide ripple current that between maximum load current. This provides optimal trade-off between cost, efficiency, transient performance. During on-time, voltage across inductor (VIN VOUT equation determining inductance shown next.
VOUT IRIPPLE
design goal that output voltage regulation under static conditions. internal 500mV reference tolerance Allowing tolerance from resistor divider, this allows tolerance VOUT ripple. Since this error comes from ripple voltage, allowable ripple 42mV 1.05V output. maximum ripple current 4.4A creates ripple voltage across ESR. maximum value allowed shown following equations.
ESRMAX VRIPPLE IRIPPLEMAX 42mV
Example
this example, inductor ripple current equal maximum load current. Therefore ripple current will find minimum inductance needed, values that correspond VINMAX.
(13.2 1.05) 318ns 0.77
ESRMAX output capacitance usually chosen meet transient requirements. worst-case load release, from maximum load load exact moment when inductor current peak, determines required capacitance. load release instantaneous (load changes from maximum zero 1s), output capacitor must absorb inductor's stored energy. This will cause peak voltage capacitor according following equation.
IOUT COUTMIN IRIPPLEMAX
slightly larger value 0.88H selected. This will decrease maximum IRIPPLE 4.4A. Note that inductor must rated maximum load current plus ripple current. ripple current under minimum conditions also checked using following equations.
VINMIN
IRIPPLE
VPEAK
VOUT
25pF RTON VOUT VINMIN
VOUT
10ns
384ns
Assuming peak voltage VPEAK 1.150 (100mV rise upon load release), load release, required capacitance shown next equation.
0.88 1.05
IRIPPLE
(10.8 1.05 384ns 0.88
4.25
COUTMIN
1.15
Capacitor Selection output capacitors chosen based required capacitance. maximum requirement controlled output ripple requirement tolerance. output voltage value that equal valley output ripple plus peak-to-peak ripple. Change output ripple voltage will lead change voltage output.
COUTMIN 595F load release relatively slow, output capacitance reduced. heavy loads during normal switching, when above 500mV reference, output high low-side MOSFET During this time, voltage across inductor approximately -VOUT. This causes down-slope falling di/dt
SC417/SC427
Applications Information (continued)
inductor. load di/dt much faster than -di/dt inductor, then inductor current will tend track falling load current. This will reduce excess inductive energy that must absorbed output capacitor, therefore smaller capacitance used. following used calculate needed capacitance given dILOAD/dt. Peak inductor current shown next equation. ILPK IMAX IRIPPLEMAX ILPK 12.2A
Rate change Load Current dlLOAD
Stability Considerations
Unstable operation possible with adaptive on-time controllers, usually takes form double-pulsing loop instability. Double-pulsing occurs switching noise seen input because ripple voltage low. This causes comparator trigger prematurely after 250ns minimum off-time expired. extreme cases noise cause three more successive on-times. Double-pulsing will result higher ripple voltage output, most applications will affect operation. This form instability usually avoided providing with smooth, clean ripple signal that least 10mVp-p, which dictate need increase output capacitors. also imperative provide proper layout discussed Layout Guidelines section. Another eliminate doubling-pulsing small 10pF) capacitor across upper feedback resistor, shown Figure This capacitor should left unpopulated until confirmed that double-pulsing exists. Adding capacitor will couple more ripple into help eliminate problem. optional connection should available this capacitor.
CTOP
IMAX maximum load release
COUT
ILPK
VOUT
IMAX dlLOAD VOUT
Example
dlLOAD
This would cause output current move from giving minimum output capacitance requirement shown following equation.
VOUT
0.88 COUT 12.2
12.2 1.05 1.15 1.05
COUT Note that COUT much smaller this example, 379F compared 595F based worst-case load release. meet design criteria minimum 379F maximum ESR, select capacitors rated 220F ESR. recommended that additional small capacitor placed parallel with COUT order filter high frequency switching noise.
Figure Capacitor Coupling loop instability caused insufficient ESR. details this stability issue discussed Requirements section. best method checking stability apply zero-to-full load transient observe output voltage ripple envelope overshoot ringing. Ringing more than cycle after initial step indication that should increased.
SC417/SC427
Applications Information (continued)
simple solve this problem trace resistance high current output path. side effect adding trace resistance decrease load regulation.
Highside COUT
Requirements
minimum required reasons. reason generate enough output ripple voltage provide 10mVp-p (after resistor divider) avoid double-pulsing. second reason prevent instability insufficient ESR. on-time control regulates valley output ripple voltage. This ripple voltage voltages. ripple generated ESR, other ripple capacitive charging discharging during switching cycle. most applications minimum ripple voltage dominated output capacitors, typically POSCAP devices. stability zero output capacitor should lower than approximately one-third switching frequency. formula minimum shown following equation.
Lowside
Figure Virtual Ramp Current component values used this circuit calculated using following procedure. Select (100nF) provide 25mV ripple across (VCL).
VOUT
where
Using Ceramic Output Capacitors
applications using ceramic output capacitors, normally small meet above criteria. these applications necessary small virtual network composed capacitors resistor, shown Figure This network creates ramp voltage across analogous ramp voltage generated across standard capacitor. This ramp then capacitively coupled into capacitor
VOUT
Next choose value that
where
resistor values voltage divider circuit VOUT switcher.
SC417/SC427
Applications Information (continued)
Dropout Performance
output voltage adjust range continuous-conduction operation limited fixed 250ns (typical) minimum off-time one-shot. When working with input voltages, duty-factor limit must calculated using worst-case values times. duty-factor limitation shown next equation.
DUTY TON(MIN) TON(MIN) TOFF(MAX
tor. This trace resistance should optimized that full load output droops near lower regulation limit. Passive droop minimizes required output capacitance because voltage excursions load steps reduced seen load. feedback resistors result error. tighter accuracy required, 0.1% resistors should used. output inductor value change with current. This will change output ripple therefore will have minor effect output voltage. output also affects output ripple thus minor effect output voltage.
inductor resistance MOSFET on-state voltage drops must included when performing worst-case dropout duty-factor calculations.
System Accuracy (VOUT Controller)
Three factors affect VOUT accuracy: trip point error comparator, ripple voltage variation with line load, external resistor tolerance. error comparator offset trimmed that under static conditions trips when feedback 500mV, on-time pulse from SC417/SC427 design example calculated give pseudo-fixed frequency 250kHz. Some frequency variation with line load expected. This variation changes output ripple voltage. Because constant on-time converters regulate valley output ripple, output ripple appears regulation error. example, output ripple 50mV with volts, then measured output will 25mV above comparator trip point. ripple increases 80mV with 25V, then measured output will 40mV above comparator trip. best minimize this effect minimize output ripple. compensate valley regulation, desirable passive droop. Take feedback directly from output side inductor place small amount trace resistance between inductor output capaci-
Switching Frequency Variations
switching frequency will vary depending line load conditions. line variations result fixed propagation delays on-time one-shot, well unavoidable delays external MOSFET switching. increases, these factors make actual on-time slightly longer than ideal on-time. effect that frequency tends falls slightly with increasing input voltage. switching frequency also varies with load current result power losses MOSFETs inductor. conventional constant-frequency converter, load increases duty cycle also increases slightly compensate switching losses MOSFETs inductor. constant on-time converter must also compensate same losses increasing effective duty cycle (more time spent drawing energy from losses increase). on-time essentially constant given VOUT/VIN combination, offset losses off-time will tend reduce slightly load increases. effect that switching frequency increases slightly with increasing load.
SC417/SC427
Applications Information (continued)
Layout Guidelines
optimum layout SC417/SC427 shown Figure This layout shows integrated buck regulator with maximum current 10A. total area approximately Critical Layout Guidelines following critical layout guidelines must followed ensure proper performance device. Decoupling capacitors PGND plane AGND island VOUT, other analog control signals BST, ILIM, COUT placement Current Loops Decoupling Capacitors capacitor must located close possible directly connected pins (V5V) (AGND).
other decoupling capacitors must located close possible
PGND Plane PGND requires copper plane with other signal traces routed Copper planes, multiple vias wide traces needed connect PGND input capacitors, output capacitors, PGND pins PGND copper area between input capacitors, output capacitors PGND pins must tight compact possible reduce area that exposed noise current flow this node. Connect PGND AGND with short trace resistor. This connection should close possible.
Decoupling Capacitor AGND plane inner layer
RLDO2
RGND AGND connects PGND close SC417/SC427
RILIM RLDO1 CLDO
marking SC417/SC427 with vias AGND, plane inner bottom layer
components shown Side
CV5V
RFB1
RFB2
PGND Layer
COUT
CBST
VOUT Plane layer
PGND
PGND inner bottom layer plane inner bottom layer
Figure Layout
SC417/SC427
Applications Information (continued)
AGND Island AGND should have island copper with other signal traces routed this layer that connects AGND pins analog control components. components analog control circuitry should located that connections AGND done wide copper traces vias down AGND. Connect PGND AGND with short trace resistor. This connection should close possible.
VOUT, Other Analog Control Signals connection from power analog control circuitry must routed from output capacitors located quiet layer. traces between Vout analog control circuitry (VOUT, pins) must short routed away from noise sources, such BST, VIN, PGND between input capacitors, output capacitors, ILIM nodes must short possible ensure best accuracy current limit time. RILIM should close connected with Kelvin trace pins connected which should sufficient connection will prevent need connect resistor further into plane. feedback components switcher need close pins possible reduce possibility noise corrupting these analog signals.
BST, ILIM very noisy nodes must routed minimized area that exposed these signals. connections boost capacitor between must short directly connected LXBST (pin 13). connections current limit resistor between ILIM must short possible directly connected (LXS). node between inductor should wide enough handle inductor current short enough eliminate possibility noise corrupting other signals. Multiple vias should used provide good connection between inductor.
Capacitors Current Loops current loops between input capacitors, inductor, output capacitors must close possible each other reduce drop across copper. bypass output capacitors must connected close possible
SC417/SC427
Outline Drawing MLPQ-5x5-32
DIMENSIONS MILLIMETERS INCHES 1.00 .031 .039 0.80 0.05 .000 .002 0.00 (.008) (0.20) .007 .010 .012 0.18 0.25 0.30 .193 .197 .201 4.90 5.00 5.10 .076 .078 .080 1.92 1.97 2.02 .193 .197 .201 4.90 5.00 5.10 .135 .137 .139 3.43 3.48 3.53 .020 0.50 .012 .016 .020 0.30 0.40 0.50 0.08 .003 0.10 .004
INDICATOR (LASER MARK)
3.48 0.76 1.05 SEATING PLANE
1.49 3.61 1.66 R0.20 IDENTIFICATION NOTES: CONTROLLING DIMENSIONS MILLIMETERS (ANGLES DEGREES). COPLANARITY APPLIES EXPOSED WELL TERMINALS.
0.76
SC417/SC427
Land Pattern MLPQ-5x5-32
3.48 1.74 3.61 1.74 DIMENSIONS INCHES (.195) .165 .137 .059 .065 .078 .041 .020 .012 .030 .224 MILLIMETERS (4.95) 4.20 3.48 1.49 1.66 1.97 1.05 0.50 0.30 0.75 5.70
NOTES: CONTROLLING DIMENSIONS MILLIMETERS (ANGLES DEGREES).
THIS LAND PATTERN REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES MET. THERMAL VIAS LAND PATTERN EXPOSED SHALL CONNECTED SYSTEM GROUND PLANE. FAILURE COMPROMISE THERMAL AND/OR FUNCTIONAL PERFORMANCE DEVICE. SQUARE PACKAGE-DIMENSIONS APPLY BOTH DIRECTIONS.
Contact Information
Semtech Corporation Power Mangement Products Division Flynn Road, Camarillo, 93012 Phone: (805) 498-2111 Fax: (805) 498-3804 www.semtech.com
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