S3C6410 S3C6400 S3C6430

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Product Technical Brief S3C6410 July 2008
S3C6410 16/32-bit RISC cost-effective, power, high performance micro-processor solution mobile phones, Portable Navigation Devices other general applications. provide optimized performance 2.5G communication services, S3C6410 adopts 64/32-bit internal architecture includes many powerful hardware accelerators tasks such motion video processing, display control scaling. integrated Multi Format Codec (MFC) supports encoding decoding MPEG4/H.263, H.264 decoding VC1. This Encoder/Decoder supports real-time video conferencing NTSC mode. addition, S3C6410 Includes advanced triangles/ graphics accelerator with OpenGL 2.0, D3DM support S3C6410 optimized interface external memory capable sustaining demanding memory bandwidths required high-end communication services. memory system dual DRAM Flash/ROM external memory ports parallel access. DRAM port configured support mobile standard SDRAM. Flash/ROM Port supports NAND Flash, NOR-Flash, OneNAND type external memory. reduce total system cost enhance overall functionality, S3C6410 includes many hardware peripherals such camera interface, 24-bit true color controller, System Manager power management, CF+, I/F, 4-channel UART, 32-channel DMA, 4-channel Timers, General Ports, I2S, I2CBUS interface, controller integrated transceiver operating high speed(480Mbps), Host High Speed Multi-Media Card Interface PLLs clock generation. Furthermore, S3C6410 both software compatible with S3C6400 S3C6430, thus allowing easier migration, platformization, minimal engineering resources, ultimately faster time market. S3C6410 manufactured using Power 65nm process allowing power, cost sensitive applications. (Package Package) options with technology available small form factor applications.
This document contains specification information under development. Samsung Electronics reserves right change specification information without prior notice.
Advance Spec.
S3C6410
Features Summary
ARM1176JZF-S based Subsystem with Java acceleration Engine 16/16KB Cache, 16/16KB 533/667/800MHz operating frequency 8-bit 601/656 Camera Interface pixel scaled pixel un-scaled resolution Multi Format CODEC provides encoding decoding MPEG-4/H.263/H.264 >30fps@SD/D1 decoding video >30fps@SD/D1 triangles/sec graphics accelerator with OpenGL 2.0, D3DM support Graphics Accelerator with BitBlit Rotation 3-ch I2S: Dolby channel support combined AC97 1/2/4/8 Palletized 8/16/24bpp Non-Palletized Color-TFT support 1024x1024 2-Channel interface support Dedicated IrDA port Configurable GPIOs On-chip controller transceiver supporting high speed (480Mbps, on-chip transceiver) On-chip Host controller transceiver supporting full speed (12Mbps, on-chip transceiver) 3-Channel HS-MMC/MMC/SDHC/SDIO card support CompactFlash Spec compatible (except MDMA operation) Real time clock, PLL's, timer with watch timer channel controller Support matrix 8-ch 12-bit (Touch screen interface) Advanced power management mobile applications Power Modes Normal, Idle, Stop, Deep Stop, Sleep Intelligent Power Gating Multiple Power Domains MtCMOS Technology Power 65nm Process Memory Subsystem SRAM/ROM/NOR Interface with data Muxed OneNAND Interface with data NAND Flash Interface with data bus, with 1/4/8-bit hardware circuit page mode SDRAM Interface with data Mobile SDRAM Interface with data (133Mbps/pin rate) Mobile Interface with data (266Mbps/pin DDR) Package options Single package type: 424-pins FBGA (0.5mm Pitch), 1.4mm type: 491-pins FBGA (0.5mm Pitch), 1.7mm configuration OneNAND+1Gb mDDR configuration NAND 512Mb mDDR 512Mb OneDRAM
Advance Spec.
S3C6410
System Peripheral Timer Watch Timer DMA(32ch) Keypad
Core 1176JZF-S cache 16KB/16KB 16KB/16KB 533MHz @1.1V 667MHz @1.2V 800MHz @TBD
Multimedia Acceleration Camera controller: Multi Format CODEC (H.264 MPEG4/ VC1) NTSC, Image Enhancement) JPEG codec Graphics
Connectivity GPIO 24-bit D-5.1ch AC97
UART IrDA v1.1
Secure Boot
Crypto Engine
Graphics tri/sec (OpenGL 1.1/2.0) Standalone Rotator post processor
X64/32 Multi-layer AXI/AHB
12bit HS-SPI Modem I/F: DPRAM Host SDHC/HS-MMC Power Management
Normal, Idle, Stop, D-Stop, Sleep with MtCMOS
Memory Subsystem Controller 24/18bit 8bit Dual 1024x1024 output 5-layer 16bit a-blending SRAM/ROM/NOR/ OneNAND Mobile SDRAM SDRAM NAND Flash 8-bit ECC, page mode controller
Advance Spec.
S3C6410
Product Details
Core
ARM1176JZF-S processor incorporates architecture. supports Thumbinstruction sets, Jazelle technology direct execution Java bytecodes. range SIMD instructions that operate 16-bit 8-bit data values 32-bit registers. ARM1176JZF Features TrustZonesecurity extensions Driven Power Management High-speed Advanced Microprocessor Architecture (AMBA) Advanced Extensible Interface (AXI) level interfaces supporting prioritized multiprocessor implementations. Integer unit with integral Embedded ICERT logic Eight-stage pipeline Branch prediction with return stack interrupt latency configuration External coprocessor interface coprocessors CP14 CP15 Instruction Data Memory Management Units (MMUs), managed using MicroTLB structures backed unified Main Instruction data caches, including non-blocking data cache with Hit-UnderMiss (HUM) Virtually indexed physically addressed caches 64-bit interface both caches Vector Floating-Point (VFP) coprocessor support External coprocessor support Trace support JTAG-based debug
Memory Subsystem
SRAM/ROM/NOR Interface data Address range support: 20-bits (1MB) Support byte half-word access Muxed OneNAND Interface data Support byte half-word access SDRAM Interface X16, data 1.8V interface voltage Density support data with 133Mbps/pin data rate Mobile SDRAM feature support (Driver Strength Control) TCSR (Temperature Compensated SelfRefresh Control) PASR (Partial Array Self-Refresh Control) Mobile Interface x16, data with 266Mbps/pin double data rate (DDR) 1.8V interface voltage Density support NAND Interface Support industry standard NAND interface data 1.8V, 2.5V, 3.3V interface voltage internal buffer (stepping stone) System booted from NAND (boot loader) when system initialization begins Rest memory area used storing user data 1/4/8-bit hardware circuit page read mode support Secure boot moviNAND booting help embedded
Advance Spec.
S3C6410
Multimedia Acceleration
Camera Interface 8-bit ITU-R601/ITU-R656 format input pixel scaled pixel unscaled resolution YCrCb 4:2:2 4:2:0 down-sampling, downscaling MPEG JPEG 24-bit 16-bit output preview (720) Interlaced Input Support Image windowing zoom-in function Test pattern generation Image flip supports Y-mirror, X-mirror, 180' rotation Color Space Conversion controller direct path supported Image effect supported Multi Format CODEC (MFC) Real-time Video Encoding decoding MPEG4/H.263/H.264 decoding WMV9 MPEG4 Simple Profile: >30fps@SD/D1 H.263 Baseline Profile: >30fps@SD/D1 H.264 Baseline Profile L3.0: >30fps@SD/D1 Decoding: >30fps@SD/D1 JPEG Codec Compression/decompression 65536 65536 Encoding format: YCbCr4:2:2 YCbCr4:2:0 Decoding format: YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0 Gray Rotator Supported image format YCbCr 4:2:2(interleave), YCbCr 4:2:0 (non-interleave), RGB565 RGB888(unpacked) Supported rotate degree 270, flip vertical flip horizontal Supported image size 2048 2048 Graphic Accelerator Primitive drawing engine Line/Point drawing Block Trasfer (BitBLT) Color expansion: Text drawing Per-pixel operation (max 2048x2048 resolution) 90°/180°/270°/X-flip/Y-flip rotation Window clipping Rasterization 256-level per-pixel alpha blending TV(NTSC/PAL) Encoder with Image Enhancer Video Format NTSC-M/PAL-B,D,G,H,I Compliant Macrovision anti-taping (Version 7.1.L1) Support source format YCbCr420/422, 16/18/24 Built (Mobile Image Enhancer) Engine Black White Stretch Blue Stretch Flesh-Tone Correction Dynamic Horizontal Peaking Black White Noise Reduction
Original, Full Size, Wide Size Video-Out
Video Post Processor Video input format conversion Video/Graphic scaling up/down zooming in/out Color space conversion from YCbCr Color space conversion from YCbCr Dedicated local interface display Dedicated Scaler Encoder
Advance Spec.
S3C6410
Graphic Accelerator
Architecture Floating-point pipeline Object-order rendering 4-Way SIMD vertex shader pixel shader Shader Model 3.0: World implementation 128-bit (32-bit Vertex Shader 128-bit (32-bit Pixel Shaders 8-stage pipeline Instruction Slots (configurable) Memory Optimization Hierarchical Caching solution OpenGL 1.1/2.0 Mobile, OpenVG (TBD) Rendering performance @Max freq. (133MHz) Peak vertex geometry performance (transform only): 9.28M vertices/s Vertex geometry performance with single light condition: 7.55 vertices/s Shaded fill rate: 125.6M pixel/sec Bilinear-filtered textured fill rate with Alpha blending: 37.8M pixel/sec
Security Subsystem
On-Chip secure boot 32KB secure boot secure boot Crypto Accelerator Securely integrated AES, DES/3DES, SHA1/MD5, TrustZoneEnabling enhanced secure platform separate (secure/non-secure) execution environment security sensitive application
Display Controller
24/18 Interface Support Interface Support Dual Interface Support 601/656 Interface Support 1/2/4/8bpp Palletized 8/16/24-bpp NonPalletized Color-TFT support 320X240, 640x480 other display resolutions 1024x1024 Max. virtual screen size Support Window Layer Realtime overlay plane multiplexing Programmable window positioning 16-level alpha blending
Advance Spec.
S3C6410
Connectivity
Interface 3-ch I2S-bus audio-codec interface with DMA-based operation Serial, 8/16/20/24-bit channel data transfers Supports I2S, MSB-justified LSB-justified data format Various clock frequency codec clock frequency support clock frequency 256, 384, 512, codec clock frequency Multi channel Audio support Audio
16-bit mono audio Master mode only
Interface 2-ch Multi-Master I2C-Bus Serial, 8-bit oriented bi-directional data transfers made Kbit/s standard mode Kbit/s fast mode UART 4-channel High-Speed UART (4Mbps) with DMA-based interrupt-based operation Supports 5-bit, 6-bit, 7-bit, 8-bit serial data transmit/receive Supports external clock UART operation (UCLK) Programmable baud rate Loop back mode testing Non-integer clock divides Baud clock generation (BRM) IrDA IrDA v1.1 support (1.152Mpbs 4Mpbs) SIR(111.5kbps) mode supported UART IrDA block Internal 64-byte Tx/Rx FIFO Complies with Supports high speed 480Mbps On-chip transceiver Host Complies with Supports full speed 12Mbps On-chip transceiver
AC97 Audio
Independent channels stereo stereo Out, mono 16-bit stereo(2-channel) audio. Variable sampling rate AC97 Codec interface (48KHz below)
Modem
Asynchronous direct indirect 16-bit SRAM-style interface (support style) On-chip dual-ported SRAM buffer direct interface On-chip Write/Read FIFO (each 288-word) support indirect burst transfer
MIPI Standard Draft Compliant
High speed synchronous serial interface
CF+/ATA controller CompactFlash Spec compatible including ATA6 (except MDMA operation)
Advance Spec.
S3C6410
HS-MMC/SDIO Multimedia Card Protocol version compatible (HS-MMC) SD/SDIO Memory Card Protocol version spec version compatible SDHC High Capacity) card support based Interrupt based operation Bytes HS-MMC) Bytes (MMC) FIFO Tx/Rx: word FIFO Tx/Rx CE-ATA support 3-ch SD/SDIO/MMC 1-ch HS-MMC/SDHC SD/SDIO/MMC Interface 2-ch Serial Peripheral Interface Protocol with full-duplex: 50Mbps DMA-based interrupt-based operation Keypad Matrix support Provides internal de-bounce filter Converter Touch Screen Interface 8-ch multiplexed Max. 500K samples/sec 12bit resolution Configurable GPIO (TBD)
System Peripheral
Real Time Clock Full clock features: sec, min, hour, date, day, week, month, year 32.768 operation Alarm interrupt Time-tick interrupt Three on-chip PLLs, APLL/ MPLL EPLL APLL dedicates core MPLL generates system reference clock EPLL generates clocks audio interface Timer with Pulse Width Modulation 4-ch 32-bit Timer with 1-ch 32-bit internal timer with DMA-based interrupt-based operation Programmable duty cycle, frequency, polarity Dead-zone generation Support external clock source 16-bit Watch Timer General embedded. channel supported each then totally channel supported Memory memory, memory, memory support Burst transfer mode enhance transfer rate
Advance Spec.
S3C6410
Vectored Interrupt Controller multiple interrupt request inputs, each interrupt source, interrupt request output processor interrupt request input software mask particular interrupt requests prioritization interrupt sources interrupt nesting. Power Management Clock-off control individual components Intelligent Power Gating Multiple Power Domains switch unused blocks. Various power-down modes available such Slow, Idle, Stop, Deep-Stop Sleep mode Wake-up external interrupts alarm interrupt Step-by-Step "Noise Aware" Wake-up Design MtCMOS Technology Memory/Logic Retention
Electrical Characteristics
Operating Conditions Supply voltage core logic (tbd) 533MHz @1.1V 667MHz @1.2V 800MHz @TBD Supply voltage Alive/PLL: 1.2V (tbd) External memory port 1.8V 3.3V (tbd) External memory port 1.8V 2.5V (tbd) External interface: 1.8V 3.3V (tbd)
Package option
S3C6410X01 Package type: Single-Chip 424-pins FBGA (0.5mm Pitch) Dimension: 1.4mm S3C6410X5A Package type: (package package) 491-pins FBGA (0.5mm Pitch) configuration: OneNAND mDDR Dimension: 1.7mm S3C6410X5D Package type: (package package) 491-pins FBGA (0.5mm Pitch) configuration: NAND 512Mb mDDR 512Mb OneDRAM Dimension: 1.7mm
Electrical Characteristics
Operating Conditions Supply voltage core logic (tbd) 533MHz @1.1V 667MHz @1.2V 800MHz @1.3V Supply voltage Alive/PLL: 1.2V (tbd) External memory port 1.8V 3.3V (tbd) External memory port 1.8V 2.5V (tbd) External interface: 1.8V 3.3V (tbd)

S3C6410 S3C6400 S3C6430

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