PS014401-1001
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Z86E61/Z86E63
CMOS 16K/32K EPROM Microcontroller
PS014401-1001
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PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table Contents
FEATURES GENERAL DESCRIPTION FUNCTIONS ROMless (Input, Active Low). (Output, Active Low). (Output, Active Low). XTAL2, XTAL1 (Output, Write Low). RESET (Input, Active Low). Port (P07-P00) Port (P17-P10) UART OPERATION ADDRESS SPACE FUNCTIONAL DESCRIPTION Counter/Timers Interrupts PROGRAMMING Z86E61/E63 User Modes Z86E63 Signal Description EPROM Program/Read ABSOLUTE MAXIMUM RATINGS STANDARD TEST CONDITIONS CHARACTERISTICS CHARACTERISTICS CHARACTERISTICS CONTROL REGISTER DIAGRAMS CHARACTERISTICS Supply Current CHARACTERISTICS Standby Current INSTRUCTION NOTATION INSTRUCTION FORMATS INSTRUCTION SUMMARY OPCODE PACKAGE INFORMATION ORDERING INFORMATION CODES
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Z86E61/E63 Functional Block Diagram 40-Pin Configuration 44-Pin PLCC Configuration 40-Pin Configuration 44-Pin PLCC Configuration Port Configuration Port Configuration Port Configuration Port Configuration Serial Data Formats Program Memory Configuration Data Memory Configuration Register File Register Pointer Counter/Timers Block Diagram Interrupt Block Diagram Oscillator Configuration EPROM Read EPROM Program Verity Programming EPROM, Protect, Size Selection Programming EPROM, Protect, Size Selection Intelligent Programming Flowchart Test Load Diagram External Memory Read/Write Timing Additional Timing Input Handshake Timing Output Handshake Timing Serial Register (F0H: Read/Write) Timer Mode Register (F1H: Read/Write) Counter/Timer Register (F2H: Read/Write) Prescaler Register (F3H: Write Only) Counter/Timer Register (F4H: Read/Write) Prescaler Register (F5H: Write Only) Port Mode Register (F6H: Write Only)
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Port Mode Register (F7H: Write Only) Port Mode Register (F8H: Write Only) Interrupt Priority Register (F9H: Write Only) Interrupt Request Register (FAH: Read/Write) Interrupt Mask Register (FBH: Read/Write) Flag Register (FCH: Read/Write) Register Pointer Register (FDH: Read/Write) Stack Pointer Register (FEH: Read/Write) Stack Pointer Register (FFH: Read/Write) Typical Frequency Typical ICC1 Frequency Instruction Formats Opcode 40-Pin Package Diagram 44-Pin PLCC Package Diagram 44-Pin Package Diagram
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
List Tables
Table 40-Pin Identification. Table 44-Pin PLCC Identification Table 40-Pin Identification. Table 44-Pin PLCC Identification Table Port Assignments Table Programming Table Timing Programming Waveforms. Table Absolute Maximum Ratings Table Characteristics Table External Memory Read Write Timing Table Clock Dependent Formulas Table Additional Timing Table Handshake Timing Table Instruction Notation Table Condition Codes. Table Instruction Summary
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
viii
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
FEATURES
8-Bit CMOS Microcontroller 40-Pin DIP, 44-Pin PLCC, 44-Pin Style Packages 4.5V 5.5V Operating Range Clock Speeds: Power Consumption: (max) Fast Instruction Pointer: Standby Modes: STOP HALT Input/Output Lines Full-Duplex UART Digital Inputs Levels Auto Latches High Voltage Protection High Voltage Inputs EPROM Protect EPROM: Kbytes Z86E61 Kbytes Z86E63 Bytes Register File Bytes General-Purpose Bytes Control Status Registers Bytes Ports Programmable 8-Bit Counter/Timers. Each with 6-Bit Programmable Prescaler Vectored, Priority Interrupts from Eight Different Sources On-Chip Oscillator that accepts Crystal, Ceramic Resonator, External Clock Drive
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
GENERAL DESCRIPTION
Z86E61/E63 microcontrollers members single-chip microcontroller family with 16K/32 Kbytes EPROM bytes general-purpose RAM. Offered 40-pin DIP, 44-pin PLCC 44-Pin package styles, these devices pin-compatible EPROM versions Z86C61/ ROMless option available 44-pin versions only. With Kbytes bytes general-purpose RAM, Z86E61/E63 offers fast execution, efficient memory, sophisticated interrupts, input/output manipulation capabilities, easy hardware/software system expansion. applications demanding powerful capabilities, Z86E61/E63 offers pins dedicated input output. These lines grouped into four ports. Each port consists eight lines, configurable under software control provide timing, status signals, serial parallel with without handshake, address/data interfacing external memory. Z86E61/E63 address both external memory preprogrammed ROM, making well suited high-volume applications where code flexibility required. There three basic address spaces available support this configuration: Program Memory, Data Memory, general-purpose registers. unburden system from coping with real-time tasks such counting/timing serial data communication, Z86E61/E63 offers on-chip counter/timers with large number user selectable modes (Figure Power connections follow conventional descriptions below:
Connection Power Ground Circuit Device
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Output Input
XTAL
RESET
Port
Machine Timing Instruction Control
UART
FLAGS Prg. Memory 16K/32K Register Pointer Register File 8-Bit Program Counter
Counter/ Timers
Interrupt Control
Port
Port
Port
(Bit Programmable)
Address/Data (Byte Programmable)
Address (Nibble Programmable)
Figure Z86E61/E63 Functional Block Diagram
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
DESCRIPTION Standard Mode
XTAL2 XTAL1 RESET
Z86E61 /E63
Figure 40-Pin Configuration
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table 40-Pin Identification Standard Mode 13-20 21-28 31-38 Symbol XTAL2 XTAL1 RESET P07-P00 P17-P10 P27-P20 Function Power Supply Crystal, Oscillator Clock Crystal, Oscillator Clock Port Port Reset Read/Write Data Strobe Address Strobe Port Ground Port Port Pins 0,1,2,3,4,5,6,7 Port Pins 0,1,2,3,4,5,6,7 Port Port Port Pins 0,1,2,3,4,5,6,7 Port Port Direction Input Output Input Output Input Input Output Output Output Output Input Input Input/Output Input/Output Output Input Input/Output Input Output
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
RESET
XTAL1 XTAL2 Z86E61/E63 PLCC
R/RL
Figure 44-Pin PLCC Configuration
Table 44-Pin PLCC Identification Standard Mode Symbol XTAL2 XTAL1 RESET Function Power Supply Crystal, Osc. Clock Crystal, Osc. Clock Port Port Connected Reset Read/Write Data Strobe Address Strobe Port Ground Direction Input Output Input Output Input Input Input Output Output Output Output Input
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table 44-Pin PLCC Identification (Continued) Standard Mode Symbol Function Port Port Pins Direction Input Input/Output
14-16 P02-P00 R/RL
ROM/ROMless control Input Port Pins 3,4,5,6,7 Port Pins 0,1,2,3,4 Connected Port Pins 5,6,7 Port Port Port Pins 0,1,2,3,4 Connected Port Pins 5,6,7 Port Port Input/Output Input/Output Input Input/Output Output Input Input/Output Input Input/Output Input Output
18-22 07-P03 23-27 10-P14
29-31 P17-P15
34-38 P24-P20
40-42 P27-P25
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
XTAL2 XTAL1 RESET
Z86E61 /E63
Figure 40-Pin Configuration
Table 40-Pin Identification EPROM Mode Symbol XTAL2 XTAL1 Function Power Supply Crystal, Osc. Clock Crystal, Osc. Clock Connected Chip Enable Direction Input Output Input Input Input
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table 40-Pin Identification (Continued) EPROM Mode 7-10 Symbol RESET Function Reset Connected Ground EPROM Prog Mode Address 0,1,2,3,4,5,6,7 Data 0,1,2,3,4,5,6,7 Connected Prog Voltage Direction Input Input Input Input Input In/Output Input Input
13-20 A7-A0 21-28 D7-D0
31-37 A14-A8
Address 8,9,10,11,12,13,14 Input Prog Mode Output Enable Connected Input Input Input
RESET
Figure 44-Pin PLCC Configuration
PS014401-1001
XTAL1 XTAL2 Z86E61/E63 PLCC
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table 44-Pin PLCC Identification EPROM 8-11 Symbol XTAL2 XTAL1 RESET Function Power Supply Crystal, Osc. Clock Crystal, Osc. Clock Connected Chip Enable Connected Reset Connected Ground EPROM Prog Mode Address 0,1,2 Connected Address 3,4,5,6,7 Data 0,1,2,3,4 Connected Data 5,6,7 Connected Prog Voltage Address 8,9,10,11,12 Connected Address 13,14 Prog Mode Output Enable Connected Direction Input Input Input Input Input Input Input Input Input Input Input Input Input In/Output Input In/Output Input Input Input Input Input Input Input Input
14-16 A0-A2
18-22 A7-A3 23-27 D4-D0
29-31 D7-D5
34-38 A12-A
40-41 A13-A14
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
FUNCTIONS
ROMless (Input, Active Low).
Connecting this disables internal forces device function Z86C91 ROMless (see Z86C91 product specification more information). When pulled High VCC, device functions normal Z86E61/E63 EPROM version. Note: This only available 44-pin versions Z86E61/ E63.
(Output, Active Low).
Data Strobe activated once each external memory transfer. READ operation, data must available prior trailing edge WRITE operations, falling edge indicates that output data valid.
(Output, Active Low).
Address Strobe pulsed once beginning each machine cycle. Address output through Port external programs. Memory address transfers valid trailing edge Under program control, placed high-impedance state along with Ports Data Strobe, Read/Write.
XTAL2, XTAL1
Crystal Crystal (time-based input output, respectively). These pins connect parallel-resonant crystal, ceramic resonator, external singlephase clock on-chip oscillator buffer.
(Output, Write Low).
Read/Write signal when writing external program data memory.
RESET (Input, Active Low).
avoid asynchronous noisy reset problems, Z86E61/E63 equipped with reset filter four external clocks (4TpC). external RESET signal less than 4TpC duration, reset occurs.
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
fifth clock after RESET detected, internal signal latched held internal register count external clocks, duration external RESET, whichever longer. During reset cycle, held active while cycles rate TpC/2. When RESET deactivated, program execution begins location 000C (HEX). Power-up reset time must held until stable, whichever longer.
Port (P07-P00)
Port 8-bit, nibble programmable, bidirectional, compatible port. These eight lines configured under software control nibble port, address port interfacing external memory. When used port, Port placed under handshake control. this configuration, Port lines used handshake control DAV0 RDY0 (Data Available Ready). Handshake signal assignment dictated direction upper nibble P07-P04. lower nibble must have same direction upper nibble under handshake control. external memory references, Port provide address bits A11-A8 (lower nibble) A15-A8 (lower upper nibbles) depending required address space. address range requires bits less, upper nibble Port programmed independently while lower nibble used addressing. both nibbles needed operation, they must configured writing Port Mode register. ROMless mode, after hardware reset, Port lines defined address lines A15-A8, extended timing accommodate slow memory access. initialization routine include reconfiguration eliminate this extended timing mode (Figure
Port (P17-P10)
Port 8-bit, byte programmable, bidirectional, compatible port. multiplexed Address (A7-A0) Data (D7-D0) ports. Z86E61/E63, these eight lines programmed input output lines configured under software control address/data port interfacing external memory. When used port, Port placed under handshake control. this configuration, Port lines, P34, used handshake controls RDY1 DAV1. Memory locations greater than 16384 (E61) 32768 (E63) referenced through Port interface external memory, Port must programmed multiplexed Address/ Data mode. more than external locations required, Port must output additional lines.
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Port placed high-impedance state along with Port R/W, allowing share common resources multiprocessor applications. Data transfers controlled assigning Acknowledge input, Request output (Figure
Port (I/O)
Z86E61 /E63
Handshake controls DAV0 RDY0 (P32 P35)
Level Shifter
Auto Latch
Figure Port Configuration
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Z86E61 /E63 Handshake controls DAV1 RDY1 (P33 P34) Port (AD7-AD0)
Level Shifter
Auto Latch
Figure Port Configuration
Port (P27-P20). Port 8-bit, programmable, bi-directional, CM0S compatible port. Each these eight lines independently programmed input output, globally open-drain output. Port always available operation. When used port, Port placed under handshake control. this configuration, Port lines used handshake control lines DAV2 RDY2. handshake signal assignment Port lines, P36, dictated direction (input output) assigned (Figure Table page 16).
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Z86E61 /E63
Port (I/O)
Handshake controls DAV2 RDY2 (P31 P36)
Open-Drain
Level Shifter
Auto Latch
Figure Port Configuration
Port (P37-P30). Port 8-bit, CMOS compatible four-fixed input fourfixed output port. These eight lines have four-fixed (P33-P30) input fourfixed (P37-P34) output ports. Port when used serial I/O, programmed serial serial out, respectively (Figure
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Z86E61 /E63
Port (I/O Control)
Figure Port Configuration
Port configured under software control provide following control functions: handshake Ports (DAV RDY); four external interrupt request signals (IRQ3-IRQ0); timer input output signals (TIN TOUT) Data Memory Select (/DM) EPROM control signals (P30 VPP).
Table Port Assignments CTCI TOUT TOUT TOUT TOUT IRQ4 IRQ5 Serial Int. IRQ3 IRQ2 IRQ0 IRQ1 UART Serial EPROM
Handshake Signals Data Available Ready
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
UART OPERATION
Port lines, P30, programmed serial lines full-duplex serial asynchronous receiver/transmitter operation. rate controlled Counter/ Timer0. Z86E61/E63 automatically adds start stop bits transmitted data (Figure 10). parity also available option. Eight data bits always transmitted, regardless parity selection. parity enabled, eighth parity bit. interrupt request (IRQ4) generated transmitted characters. Received data must have start bit, eight data bits, least stop bit. parity received data replaced parity error flag. Received characters generate IRQ3 interrupt request.
Transmitted Data Parity) Start Eight Data Bits Stop Bits Received Data Parity) Start Eight Data Bits Stop
Transmitted Data (With Parity) Start Parity Stop Bits
Received Data (With Parity) Start Seven Data Bits Parity Error Flag Stop
Figure Serial Data Formats
Auto Latch Auto Latch puts valid CMOS levels CMOS inputs that externally driven. This reduces excessive supply current flow input buffer when driven source. Note: P33-P30 inputs differ from Z86C61/C63 that there clamping diode because EPROM high voltage detection circuits. Exceeding maximum specification during standard operating mode cause device enter EPROM mode.
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
ADDRESS SPACE
Program Memory. Z86E61/E63 address Kbytes (E61) Kbytes (E63) external program memory (Figure 11). first bytes program memory reserved interrupt vectors. These locations contain 16-bit vectors that correspond available interrupts. EPROM mode, byte byte 16383 (E61) 32767 (E63) consists on-chip EPROM. addresses 16384 (E61) 32768 (E63) above, Z86E61/E63 executes external program memory fetches. ROMless mode, Z86E61/E63 address Kbytes program memory. Program execution begins external location 000C (HEX) after reset.
65535 16384 (E61) 32768 (E63) 16383 (E61) 32767 (E63) External
On-Chip PROM
Location First Byte Instruction Executed After RESET Interrupt Vector (Lower Byte) Interrupt Vector (Upper Byte)
IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0
Figure Program Memory Configuration
Data Memory (DM)
EPROM version address Kbytes (E61) Kbytes (E63) external data memory space beginning location 16384 (E61) 32768 (E63). ROMless version address Kbytes external data memory. External data memory included with, separated from, external program memory space. optional function that programmed appear P34, used distinguish between data program memory
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
space (Figure 12). state signal controlled type instruction being executed. opcode references PROGRAM inactive) memory, instruction references DATA active Low) memory.
Register File
register file consists four port registers, general-purpose registers, control status registers (Figure 13). instructions access registers directly indirectly through 8-bit address field. Z86E61/E63 also allows short 4-bit register addressing using Register Pointer (Figure 14). 4-bit mode, Register File divided into working register groups, each occupying continuous locations. Register Pointer addresses starting location active working register group. Stack Z86E61/E63 16-bit Stack Pointer (R255-R254) used external stacks that reside anywhere data memory ROMless mode, only from 16384 (E61) 32768 (E63) 65535 EPROM mode. 8-bit Stack Pointer (R255) used internal stack that resides within general-purpose registers (R239-R4). high byte Stack Pointer (SPH Bits 15-8) general purpose register when using internal stack only.
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
65535
External Data Memory
32768 (E63) 16384 (E61) 16383 (E61) 32767 (E63)
Addressable
Figure Data Memory Configuration
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
LOCATION R255 R254 R253 R252 R251 R250 R249 R248 R247 R246 R245 R244 R243 R242 R241 R240 R239 General Purpose Registers Port Port Port Port Stack Pointer (Bits 7-0) Stack Pointer (Bits 15-8) Register Pointer Program Control Flags Interrupt Mask Register Interrupt Request Register Interrupt Priority Register Port Mode Port Mode Port Mode Prescaler Timer/Counter0 Prescaler Timer/Counter1 Timer Mode Serial
IDENTIFIERS FLAGS P01M PRE0 PRE1
Figure Register File
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
R253 (Register Pointer)
upper nibble register file address provided register pointer specifies active working-register group.
Specified Working Register Group
lower nibble register file address provided instruction points specified register.
Register Group Register Group Ports
Figure Register Pointer
FUNCTIONAL DESCRIPTION
Counter/Timers
There 8-bit programmable counter/timers (T0-T1), each driven 6-bit programmable prescaler. prescaler driven internal external clock sources; however, prescaler driven internal clock only (Figure 15). 6-bit prescalers divide input frequency clock source integer number from Each prescaler drives counter, which decrements value 256) that been loaded into counter. When both counters prescalers reach count, timer interrupt request, IRQ4 (T0) IRQ5 (T1), generated. counter programmed start, stop, restart continue, restart from initial value. counters also programmed stop upon reaching zero
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
(single pass mode) automatically reload initial value continue counting (modulo-n continuous mode). counter, prescalers, read time without disturbing their value count mode. clock source user-definable either internal microprocessor clock divided-by-four, external signal input through Port Timer Mode register configures external timer input (P31) external clock, trigger input that retriggerable non-retriggerable, gate input internal clock. Port line also serves timer output (TOUT) through which internal clock output. counter/ timers cascaded connecting output input
Internal Data Write PRE0 Initial Value Register Write Initial Value Register Read Current Value Register
6-Bit Down Counter 8-Bit Down Counter
Internal Clock
IRQ4 Serial Clock TOUT
External Clock Clock Logic 6-Bit Down Counter 8-Bit Down Counter
IRQ5
Internal Clock Gated Clock Triggered Clock
PRE1 Initial Value Register Write Write
Initial Value Register Read
Current Value Register
Internal Data
Figure Counter/Timers Block Diagram
Interrupts
Z86E61/E63 different interrupts from eight different sources. interrupts maskable prioritized. eight sources divided follows: four sources claimed Port lines P33-P30, Serial Out, Serial counter/timers (Figure 16). Interrupt Mask Register globally
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
individually enables disables interrupt requests. When more than interrupt pending, priorities resolved programmable priority encoder that controlled Interrupt Priority register (refer Table page 16). Z86E61/E63 interrupts vectored through locations program memory. When interrupt machine cycle activated, interrupt request granted. Thus, this disables subsequent interrupts, saves Program Counter Status Flags, then branches program memory vector location reserved that interrupt. This memory location next byte contain 16bit address interrupt service routine that particular interrupt request. accommodate polled interrupt systems, interrupt inputs masked Interrupt Request register polled determine which interrupt requests need service. Software initialized interrupts supported setting appropriate Interrupt Request Register (IRQ). Internal interrupt requests sampled falling edge last cycle every instruction, interrupt request must valid 5TpC before falling edge last clock cycle currently executing instruction.
IRQ0-IRQ5
Global Interrupt Enable
Interrupt Request
PRIORITY LOGIC
Vector Select
Figure Interrupt Block Diagram
ROMless mode, when device samples valid interrupt request, next (external) clock cycles used prioritize interrupt, push bytes FLAG register stack. following nine cycles used fetch interrupt vector from external memory. first byte interrupt service routine fetched beginning 58th cycle following inter-
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
sample point, which corresponds 63rd cycle following external interrupt sample point.
Clock Z86E61/E63 on-chip oscillator high gain, parallel resonant amplifier connection crystal, ceramic resonator, suitable external clock source (XTAL1 Input, XTAL2 Output). crystal should cut, max; series resistance (RS) less than equal Ohms. crystal should connected across XTAL1 XTAL2 using recommended capacitors from each ground (Figure 17). Note: Actual capacitor value specified crystal manufacturer.
XTAL1 XTAL2 Ceramic Resonator Crystal
XTAL1
XTAL1
XTAL2 Clock
XTAL2
External Clock
Figure Oscillator Configuration
HALT Turns internal clock XTAL oscillation. counter/timers external interrupts IRQ0, IRQ1, IRQ2, IRQ3 remain active. devices recovered interrupts, either externally internally generated. interrupt request must executed (enabled) exit HALT mode. After interrupt service routine, program continues from instruction after HALT. STOP This instruction turns internal clock external crystal oscillation, reduces standby current (typical) less. STOP mode terminated reset, which causes processor restart application program address 000Ch. order enter STOP HALT) mode, necessary first flush instruction pipeline avoid suspending execution mid-instruction. this, user
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
must execute (opcode 0FFH) immediately before appropriate SLEEP instruction. i.e.,
STOP HALT clear pipeline enter STOP mode clear pipeline enter HALT mode
PROGRAMMING
Z86E61/E63 User Modes
Z86E61/E63 uses separate timing cycles different User Modes available. Table page shows Z86E61/E63 User Modes. Table page shows timing programming waveforms. User MODE EPROM Read Z86E61 /E63 EPROM read cycle provided that user read Z86E61 /E63 standard 27128 (E61) 27256 (E63) EPROM. This accomplished driving (P32) activating remains inactive. This mode valid after execution EPROM protect cycle. Timing EPROM read cycle shown Figure User MODE EPROM Program Z86E61/E63 Program function conforms Intelligent programming algorithm. device programmed with Vcc, 6.0V 12.5V. Programming pulses applied increments maximum pulses before proper verification. After verification, programming pulse three times duration cycles necessary program device issued ensure proper programming. After addresses programmed, final data comparison executed programming cycle complete. Timing Z86E61/E63 programming cycle shown Figure
User Mode PROM Verify
Program Verify cycle used part intelligent programming algorithm insure data integrity under worst-case conditions. differs from EPROM Read cycle that active must driven 6.0V. Timing shown Figure
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
User Modes EPROM Protect
extend program security, EPROM protect cycles provided Z86E61/E63. Execution EPROM protect cycle prohibits proper execution EPROM Read, EPROM Verify, EPROM programming cycles. Execution protect cycle disables accesses upper bytes register memory (excluding mode configuration registers), first user's program must (R251). Timing shown Figure Figure User Modes. Table shows programming voltage each mode Z86E61/E63.
Table Programminga User/Test Mode Device User Modes EPROM Read Program Program Verify EPROM Protect Protect Device Pins VPPb VPPb VPPb VILd VIHe ADDR Addr Addr Addr 5.0V 6.0V 6.0V 6.0V 6.0V Port CNFG Data
during programming maximum. during programming, verify, read maximum. 12.0 12.0 Irrelevant.
Z86E63 Signal Description EPROM Program/Read
following signals required correctly program read Z86E63 device.
ADDR
address must remain stable throughout program read cycle.
DATA
data must stable during programming High, Low, High). During read data outputs data.
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
XCLK
clock required clock RESET signal into registers before programming. constant clock applied, XCLK input toggled minimum cycles before programming verify function begins. maximum clock frequency applied when EPROM mode MHz. RESET reset input held constant High value throughout normal programming. must held High program EPROM protect option bit. Also, time RESET input changes state XCLK must clocked minimum times clock RESET through reset filter. When device placed EPROM mode, input also serves precharge sense amp. precharge signal should first half stable address High second half. PRECHG signal inverted from signal should High first half second half, stable address. EPROM output data should sampled during second half stable address. access time EPROM defined later sections. This part calculation access time required because this precharged sense with precharge clock.
Table Timing Programming Waveforms Parameters Name Address Setup Time Data Setup Time Setup Setup Time Chip Enable Setup Time Program Pulse Width Data Hold Time Setup Time Data Access Time Data Output Float Time 0.95 Units
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table Timing Programming Waveforms (Continued) Parameters Name Over program Pulse Width Setup Time Setup Time Address Setup Time Option Program Pulse Width 2.85 Units
Address Data Invalid Valid Invalid Valid Address Stable Address Stable
Figure EPROM Read
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Address Stable Data Stable Data Valid
Program Cycle Verify Cycle
Figure EPROM Program Verity
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Address Data Protect Programming Protect Programming Address
Figure Programming EPROM, Protect, Size Selection
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Address Data Protect Programming Protect Programming Address
Figure Programming EPROM, Protect, Size Selection
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Start
Addr First Location
12.5
Program Pulse
Increment
Fail Verify Byte Pass Prog. Pulse Duration Fail
Verify Byte Pass
Increment Address
Last Addr? VCC=VPP=4.5V
Verify Bytes
Fail
VCC=VPP=5.5V
Device Failed
Verify Bytes Pass Device Passed
Fail
Figure Intelligent Programming Flowchart
ABSOLUTE MAXIMUM RATINGS
Table Absolute Maximum Ratings Symbol Description TSTG Supply Voltagea Storage Temp -0.3 +150 Units
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table Absolute Maximum Ratings (Continued) Symbol Description Operating Ambient Temperature Noteb Units
Voltages pins with respect GND. "ORDERING INFORMATION" page
Stresses greater than those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; operation device condition above those indicated operational sections these specifications implied. Exposure absolute maximum rating conditions extended period affect device reliability.
STANDARD TEST CONDITIONS
characteristics listed below apply standard test conditions noted. voltages referenced GND. Positive current flows into referenced (Figure 23).
From Output Under Test
Figure Test Load Diagram
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
CHARACTERISTICS
Table Characteristics +70°C Parameter Input Voltage Input Voltage ICC1 ICC2a Clock Input High Voltage Clock Input Voltage -0.3 Input High Voltage Input Voltage Output High Voltage Output Voltage Reset Input High Voltage Reset Input Voltage -0.3 Input Leakage Output Leakage Reset Input Current Supply Current -0.3 Standby Current Standby Current
Typical
Units Conditions 5.25 5.25 5.25 HALT Mode HALT Mode STOP Mode STOP Mode -2.0 +2.0 P33-P30 Only Driven External Clock Generator Driven External Clock Generator
ICC2 requires loading (F1Hh) with value prior STOP execution. this sequence: TMR,#00 STOP
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Port Port A7-A0 (Read) D7-D0
Port
A7-A0
D7-D0
(Write)
Figure External Memory Read/Write Timing
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
CHARACTERISTICS
Table External Memory Read Write Timing +70°C MHza
Units Notes Noteb,c,d Noteb,c,d Noteb,c,d Noteb,c Noteb,c Noteb,c Noteb,c Noteb,c Noteb,c Noteb,c Noteb,c,d Noteb,c Noteb,c Noteb,c Noteb,c Noteb,c,d Noteb,c
Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TdAZ(DS) TwDSR TwDSW TdDSR(DR) ThDR(DS) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS)AS TdDM(AS)
Parameter Address Valid Rise Delay Rise Address Float Delay Rise Read Data Req'd Valid Width Address Float Fall (Read) Width (Write) Width Fall Read Data Req'd Valid
Read Data Rise Hold Time Rise Address Active Delay Rise Fall Delay Valid Rise Delay Rise R//W Valid
Write Data Valid Fall (Write) Delay Rise Write Data Valid Delay Address Valid Read Data Req'd Valid Rise Fall Delay Valid Fall Delay
timing references 2.0V logic 0.8V logic Timing numbers given minimum TpC. Table When using extended memory timing TpC.
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table Clock Dependent Formulas Number Symbol TdA(AS) TdAS(A) TdAS(DR) TwAS TwDSR TwDSW TdDSR(DR) TdDS(A) TdDS(AS) TdR/W(AS) TdDS(R/W) TdDW(DSW) TdDS(DW) TdA(DR) TdAS(DS) TdDM(AS) Equation 0.40 0.32 0.59 3.25 2.83 6.14 0.66 1.65 2.33 10.56 1.27 1.67 1.97 42.5 0.59 3.14 sTpC 0.88 0.91 10.7 26.3
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Clock
IRQN
Figure Additional Timing
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
CHARACTERISTICS
Table Additional Timing +70°C
1000 Units Notes 1000 5TpC 8TpC 5TpC 5TpC Notea Notea Notea Noteb Noteb Noteb Noteb Noteb,c Noteb,d Noteb,e
Symbol TrC,TfC TwTinL TwTinH TpTin TrTin,TfTin TwIL TwIL TwIH
Parameter Input Clock Period Clock Input Rise Fall Times Input Clock Width Timer Input Width Timer Input High Width Timer Input Period Timer Input Rise Fall Times
62.5
5TpC 8TpC
Interrupt Request Input Times Interrupt Request Input Times 5TpC Interrupt Request Input High Times 5TpC
Clock timing references 3.8V logic 0.8V logic Timing references 2.0V logic 0.8V logic Interrupt request through Port (P33-P31). Interrupt request through Port Interrupt references request through Port
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Data
Data Valid
Next Data Valid
(Input)
Delayed
(Output)
Delayed
Figure Input Handshake Timing
Data
Data Valid
Next Data Valid
(Output) Delayed
(Input)
Delayed
Figure Output Handshake Timing
Table Handshake Timing +70°C Symbol TsDI(DAV) ThDI(DAV) TwDAV TdDAVI(RDY) TdDAVId(RDY) TdRDY0(DAV) TdD0(DAV) Parameter Data Setup Time Data Hold Time Data Available Width Fall Fall Delay Rise Rise Delay Rise Fall Delay Data Fall Delay Data Direction
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table Handshake Timing (Continued) +70°C Symbol TdDAV0(RDY) TdRDY0(DAV) TwRDY TdRDY0d(DAV) Parameter Fall Fall Delay Fall Rise Delay Width Rise Fall Delay Data Direction
CONTROL REGISTER DIAGRAMS
R240
Serial Data LSB)
Figure Serial Register (F0H: Read/Write)
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
R241
Function Load Disable Count Enable Count Function Load Disable Count Enable Count Modes External Clock Input Gate Input Trigger Input (Non-retriggerable) Trigger Input (Regriggerable)
TOUT Modes Used Internal Clock
Figure Timer Mode Register (F1H: Read/Write)
R242
Intial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) Current Value (When Read)
Figure Counter/Timer Register (F2H: Read/Write)
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
R243 PRE1
Count Mode Single Pass Modulo
Clock Source Internal External Timing Input (TIN) Mode
Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
Figure Prescaler Register (F3H: Write Only)
R244
Initial Value (When Written) (Range: 1-256 Decimal 01-00 HEX) Current Value (When Read)
Figure Counter/Timer Register (F4H: Read/Write)
R245 PRE0
Count Mode Single Pass Modulo
Reserved (Must Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)
Figure Prescaler Register (F5H: Write Only)
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
R246
Definition Defines Output Defines Input
Figure Port Mode Register (F6H: Write Only)
R247
Port Pull-Ups Open Drain Port Pull-Ups Active Reserved (Must Input Output DAV0/RDY0 RDY0/DAV0
Input Output Input DAV1/RDY1 RDY1/DAV1
Input (TIN) Output (TOUT) DAV2/RDY2 RDY2/DAV2
Input Output Serial Serial
Parity Parity
Figure Port Mode Register (F7H: Write Only)
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
R248 P01M
Mode Output Input A11-A8
Stack Selection External Internal
Mode Byte Output Byte Input High-Impedance DA0, R/W, A11-A8 A15- A12, Selected
External Memory Timing Normal Extended
Mode Output Input
Figure Port Mode Register (F8H: Write Only)
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
R249
Interrupt Group Priority Reserved Reserved
IRQ1, IRQ4 Priority (Group IRQ1 IRQ4 IRQ4 IRQ1 IRQ0, IRQ2 Priority (Group IRQ2 IRQ0 IRQ0 IRQ2 IRQ3, IRQ5 Priority (Group IRQ5 IRQ3 IRQ3 IRQ5
Reserved (Must
Figure Interrupt Priority Register (F9H: Write Only)
R250
IRQ0 Input IRQ0) IRQ1 Input IRQ2 Input IRQ3 Input, Serial Input IRQ4 Serial Output IRQ5 Reseserved (Must
Figure Interrupt Request Register (FAH: Read/Write)
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
R251
Enables IRQ5-IRQ0 IRQ0)
Enables Protect Enables Interrupts
Figure Interrupt Mask Register (FBH: Read/Write)
R252 FLAGS
User Flag User Flag Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag Zero Flag Carry Flag
Figure Flag Register (FCH: Read/Write)
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
R253
Reserved (Must
Register Pointer
Figure Register Pointer Register (FDH: Read/Write)
R254
Stack Pointer Lower Byte (SP15 SP8)
Figure Stack Pointer Register (FEH: Read/Write)
R255
Stack Pointer Lower Byte (SP7 SP0)
Figure Stack Pointer Register (FFH: Read/Write)
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
CHARACTERISTICS
Supply Current
(mA)
Frequency (MHz)
Legend: 5.6V 5.0V 4.4V
Figure Typical Frequency
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Standby Current
ICC1 (mA)
Frequency (MHz)
Legend: 5.6V 5.0V 4.4V
Figure Typical ICC1 Frequency
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
INSTRUCTION NOTATION
Addressing Modes. following notation used describe addressing modes instruction operations shown instruction summary (Table 14).
Table Instruction Notation
Symbol Meaning Indirect register pair indirect working register pair address Indirect working register pair only Indexed address Direct address Relative address Immediate Register working register address Working register address only Indirect register indirect working register address Indirect working register address only Register pair working register pair address
Symbols. following symbols used describing instruction set.
Symbol FLAGS Meaning Destination location contents Source location contents Condition Code Indirect address prefix Stack Pointer Program Counter Flag Register (Control Register 252) Register Pointer (R253) Interrupt Mask Register (R251)
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Flags. Control register (R252) contains following flags:
Symbol Meaning Carry flag Zero flag Sign flag Overflow flag Decimal-adjust flag Half-carry flag
Affected flags indicated
Symbol Meaning Clear zero clear according operation Unaffected Undefined
CONDITION CODES
Table Condition Codes Value 1000 0111 1111 0110 1110 1101 0101 0100 1100 0110 1110 1001 Mnemonic Meaning Always True Carry Carry Zero Zero Plus Minus Overflow Overflow Equal Equal Greater Than Equal Flags
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table Condition Codes (Continued) Value 0001 1010 0010 1111 0111 1011 0011 0000 Mnemonic Meaning Less than Greater Than Less Than Equal Unsigned Greater Than Equal Unsigned Less Than Unsigned Greater Than Flags
Unsigned Less Than Equal Never True (Always False)
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
INSTRUCTION FORMATS
CCF, IRET, NOP, RCF, RET,
One-Byte Instructions
MODE 1110 dst/src
dst/src
CLR, CPL, DEC, DECW, INC, INCW, POP, PUSH, RLC, RRC, SRA, SWAP CALL (Indirect)
MODE 1110 1110
ADC, ADD, AND, SBC, SUB, TCM,
1110
MODE 1110
ADC, ADD, AND, SBC, SUB, TCM,
VALUE
VALUE
MODE MODE ADC, ADD, AND, SBC, SUB, TCM, LDE, LDEI, LDC, LDCI MODE dst/src
1110 1110
MODE dst/src
src/dst
ADDRESS dst/src 1110 VALUE dst/CC DJNZ, CALL
src/dst
STOP/HALT
Two-Byte Instructions
Three-Byte Instructions
Figure Instruction Formats
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
INSTRUCTION SUMMARY
Note: Assignment value indicated symbol example:
indicates that source data added destination data result stored destination location. notation "addr (n)" used refer given operand location. example:
refers destination operand
Table Instruction Summary Instruction Operation dst, dstdst dst, dstdst dst, dstdst CALL SPSP-2 @SPPC, PCdst CNOT dst0 dstNOT dst, dstDA Notea Notea Notea Address Mode Notea Opcode Byte (Hex) Flags Affected
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table Instruction Summary (Continued) Instruction Operation dstdst DECW dstdst-1 IMR(7)0 DJNZr, PCPC Range: +127, -128 IMR(7)1 HALT dstdst INCW dstdst IRET FLAGS@SP; SPSP PC@SP; SPSP IMR(7)1 r=0-F Address Mode Opcode Byte (Hex) Flags Affected
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table Instruction Summary (Continued) Instruction Operation true, PCdst true, PCPC Range: +127, -128 dst, dstsrc dst, dstsrc LDCI dst, dstsrc rrrr dst, Note
Address Mode
Opcode Byte (Hex) c=0-F
Flags Affected
c=0-F
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table Instruction Summary (Continued) Instruction Operation dstdst dst@SP; SPSP PUSH SPSP-1; @SPsrc PC@SP; SPSP
Address Mode
Opcode Byte (Hex)
Flags Affected
Notea
dst, dstdstsrcC
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Table Instruction Summary (Continued) Instruction Operation RPsrc STOP dst, dstdstsrc SWAP
Address Mode
Opcode Byte (Hex)
Flags Affected
Notea
Notea
dst, (NOT dst) dst, dst, dstdst
Notea
Notea
These instructions have identical addressing modes, which encoded brevity. first Code nibble found instruction table above. second nibble expressed symbolically this table, value found following table left applicable addressing mode pair. example, opcode instruction using addressing modes (destination) (source)
Address Mode
Lower Opcode Nibble
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
OPCODE
IRR1 10.5 10.5
Lower Nibble (Hex)
10.5 10.5 10.5 10.5 IR2, 10.5 10.5 10.5 IR2,R1
r1,R2
12/10.5 12/0.0 DJNZ
12/10.0
10.5
10.5 10.5 10.5 10.5 IR2, IR1, 10.5 10.5 10.5 10.5 IR2, IR1, 10.5 10.5 10.5 IR2, 10.5 10.5 10.5 10.5 IR2, IR1, 10.5 10.5 10.5 10.5 IR2, IR1, 10.5 10.5 10.5 10.5 IR2, IR1, STOP HALT 10.5 10.5 10.5 10.5 IR2, IR1, 10.5 10.5 10.5 10.5 IR2, IR1, 10.5 20.0 CALL* IRR1 20.0 10.5 CALL 14.0 16.0 IRET
Upper Nibble (Hex)
10/12.1 10/12.1 PUSH PUSH 10.5 DECW 10.5 INCW 10.5 DECW 10.5 INCW
12.0 18.0 LDEI Irr2 Irr2 12.0 Irr2 18.0 LDEI Irr2
12.0 18.0 Irr2 Ir1, Irr2 18.0 12.0 LDCI Irr2 Ir1, Irr2 Ir1,
10.5 10.5 10.5 10.5 IR2, IR1, 10.5
SWAP SWAP
Bytes Instruction
Execution Cycles Upper Opcode Nibble First Operand
Lower Opcode Nibble
10.5
Pipeline Cycles Mnemonic
Legend: 8-bit Address 4-bit Address Address Address Sequence: Opcode, First Operand, Second Operand Note: Blank areas defined *2-byte instruction appears 3-byte instruction
Second Operand
Figure Opcode
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
PACKAGE INFORMATION
Figure 40-Pin Package Diagram
Figure 44-Pin PLCC Package Diagram
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
Figure 44-Pin Package Diagram
ORDERING INFORMATION
Z86E61 40-Pin 44-Pin PLCC 40-Pin 44-Pin PLCC Z86E6116PSC Z86E6116VSC Z86E6120PSC Z86E6120VSC Z86E63 40-Pin 44-Pin PLCC 40-Pin 44-Pin PLCC Z86E6316PSC Z86E6316VSC Z86E6320PSC Z86E6320VSC
fast results, contact your local Zilog sales office assistance ordering part desired.
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
CODES
Preferred Package Plastic Plastic Chip Carrier Temperature +70°C Speeds Environmental Plastic Standard
Example:
86E61
Z86E61, MHz, PLCC, Plastic Standard Flow Environmental Flow Temperature Package Speed Product Number Zilog Prefix
PS014401-1001
Z86E61/E63 CMOS 16K/32K EPROM Microcontroller
PS014401-1001
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