PPMC8240 PPMC8245 SMD0603 MPC8240 98APR22 98OCT04 99OCT20 00FEB22 Am29DL323 - Datasheet Archive
Unity PPMC8240 PPMC8245 PRELIMINARY VERSION This schematic is provided for reference purposes only. All information is subject to
* X4 Unity PPMC8240 PPMC8240 PPMC8245 PPMC8245 PRELIMINARY VERSION This schematic is provided for reference purposes only. All information is subject to change without notice. No warranty, expressed or applied, is made as to the accuracy of the information contained herein. Contact Motorola Sale/FAEs to obtain the latest information on this product. You're not really paying attention, are you, I could write anything here and you'd never notice. *Digital DNA from Motorola GARY MILLIORN Schematic Notes 1. Page Contents Unless otherwise specified: All resistors are SMD0603 SMD0603, in ohms, 0.08W, +/-5% All capacitors are SMD0603 SMD0603, in microfarads (uF), +/-20%. All inductances are in microhenries (uH). All ferrites are Z=50 ohms at 100 MHz. All fuses are self-resetting polyswitch (PTC) devices. Board impedance is 50-60 ohms. 01 Cover Page 02 03 General Information Block Diagram 2. Integrated circuits have default connections to power and ground unless explicitly shown otherwise. Global power connections are: GND VCC_2.5V VCC_3.3V VCORE VCC_5V 04 05 Routing and Layout Information Power Supply 3. Part numbers used are for reference only; compatible parts may be used; refer to the bill of materials. 4. Motorola and the Motorola logo are registered trademarks of Motorola. PowerPC is a trademark of IBM. Other trademarks are the respective property of their respective copyright holders. I've got good news! That gum you like is going to come back in style. All rights reserved. 06 07 System Configuration MPC8240 MPC8240 System Interface; I2C 5. The sheet-to-sheet cross reference format is: Sheet "-" VertZoneLetter HorizZoneNumber Components surrounded by a dashed/crossed-out box are not to be installed by default; they are for test or manufacturing purposes only: 08 09 MPC8240 MPC8240 Memory; SODIMM Socket MPC8240 MPC8240 PCI Interface; Power 10 11 Dual Flash ROMs UART; Standalone Support 12 13 Miscellany; LEDs; Mode Mux PMC Connectors P1, P2 6. 7. All buses follow big-endian bit numbering order (bit 0 is the most-significant bit), except where industry standards apply (i.e. PCI). Little-endian numbering is noted at the source component. * X4 Unity REV DATE CHANGES X1 X2 98APR22 98APR22 98OCT04 98OCT04 Original X3 X4 99OCT20 99OCT20 00FEB22 00FEB22 MPC8240 MPC8240 II Support; VITA PPMC changes; More Flash; I2C; Delete debug headers Chip pinout changes; COP tweak. PCB Changes only. UART Power Supply 5V->2.5V Switcher 64-bit 100 MHz Local Bus Configuration PLL Modes Board Modes Boot Flash ROM Auxillary ROM Processor SDRAM Motorola MPC8240 MPC8240 200-266 MHz SODIMM 16-64 MByte Monitors and Modes LEDs Mot/VITA PMC Mode 32-bit 33/66 MHz PCI Bus Standalone Support Clock: 33 MHz Reset PMC Connector 32 bit PPMC Extensions GARY MILLIORN Layout/Routing Instructions 05 Use split power plane to connect VCC_2.5 from power supply to CPU core. Place 820 uF low-ESR capacitors near CPU. Place VID pulldown resistors in order shown. Use split power plane or very heavy traces for power path: +5V => MOSFET Qx => Inductor Lx => Low-Ohm Res. Rx => VCC_2.5 Plane Keep trace from 68 uF low-ESR capacitors within 2 cm of high-side MOSFET (Q2). Keep MOSFET gate drive lines < 2 cm. Keep VCCA/VCCP attachment within 2 cm of input filter location. Keep VCC_2.5 power flowing point-to-point through MOSFETs, inductor, resistor and output filter capacitors. Use short traces throughout. 06 Place slide switches in vertical orientation and do not swap PLL config pins. 07 No special restrictions 08 Place series termination resistors very near source, < 1.5 cm. Route terminated traces using equal trace lengths towards SDRAM array. Route SDRAM_SYNC_OUT => SDRAM_SYNC_IN path to equal longest clock trace. Route all control, address and data traces to equal lengths. 09 Place PLL filters on bottom of PCB beneath MPC8240 MPC8240 Use short heavy traces on PLL filter power. Surround MPC8240 MPC8240 with bypass caps shown to provide additional ground-return paths; use two ground-attach vias. Place bulk capacitance near BGA IVDD and +3.3V ground planes. 10 Place SODIMM socket within 3.5cm of MPC6xx (center-to-center). 11 No special instructions. Place LEDs so they are visible on the top and legends are nearby. Maximum trace length for PCI signals to MPC8240 MPC8240 is 1.5" per the PCI specification. Reset Serial Port SODIMM Socket FLASH Am29DL323 Am29DL323 VDD OVDD LEDs STAT PCI ROM RAM iSP COP P2 13 P1 12 i i VCC_2.5 OUTPUT 4 O O O O O O O O O O O O O O O O I I I I I I I I I I I I I I I I VID 3 2 O O O O O O O O O I O I O I O I I O I O I O I O I I I I I I I I O O O O O O O O O I O I O I O I I O I O I O I O I I I I I I I I 1 O O I I O O I I O O I I O O I I O O I I O O I I O O I I O O I I 0 O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I VCORE 2.05V 2.00V 1.95V 1.90V 1.85V 1.80V 1.75V 1.70V 1.65V 1.60V 1.55V 1.50V 1.45V 1.40V 1.35V 1.30V 3.5V 3.4V 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.3V 2.2V 2.1V 0.00V i MPC824X MPC824X BULK CAPACITANCE Distribute around the board. i VOLTAGE SEQUENCING Restricts power supplies to specification limits. Not needed if ramp < 500 uS. VCC_2.5 OUTPUT Nominal voltage; actual output may be programmed from 1.8V to 3.6V. i SYSTEM SPEED SETTINGS P0 P1 P2 P3 P4 PCI Clock Memory Clock Processor C C C C C P2 P3 P4 C C C C - C C C C C 33 MHz 25 MHz 33 MHz 33 MHz 33 MHz 100 MHz 50 MHz 33 MHz 66 MHz 66 MHz 250 MHz 100 MHz 100 MHz 166 MHz 200 MHz C C C C - C C C C C C C C C C C 33 MHz 66 MHz 33 MHz 33 MHz 33 MHz 100 MHz 100 MHz 66 MHz 66 MHz 83 MHz 200 MHz 200 MHz 233 MHz 266 MHz 250 MHz C - P1 C C - - P0 C C - C - C - C C - C C X X 66 MHz 50 MHz 66 MHz Bypass Off 66 MHz 75 MHz 100 MHz Bypass 0 266 MHz 225 MHz 250 MHz Bypass 0 DEBUG ENABLE i BUS WIDTH Install to enable debug mode. PCI HOLD TIME PH0 PH1 PH0 PH1 PCI Hold 0 0 1 1 PD 0.5 - 0.9 ns 1.3 - 1.7 ns 2.1 - 2.5 ns 2.9 - 3.3 ns 0 1 0 1 PCI DRIVE STRENGTH D2 i PD 0 1 D1 PCI Bus 50 ohm 25 ohm MEMORY DRIVE STRENGTH D2 D1 i Memory 0 0 1 1 40 ohm 20 ohm 13 ohm 8 ohm 0 1 0 1 ROM LOCATION RL ON - ROM LOCATION ROM on PCI Bus ROM on Local Bus ADDRESS MAP SELECT AM ON - ADDRESS MAP MAP "A": PREP MAP "B": CHRP PPMC TYPE RL PT ON - AM PT AG DATA BUS SIZE Motorola PPMC VITA PPMC AGENT MODE PM AM AGENT MODE RS ON - Wait for initialization (Peripheral Mode) Free Agent Mode P66 PROGRAM MODE SR PM ON - PROGRAM MODE Enable local ROM alias. Normal mode. ROM SELECT RS ON - ROM SELECT Select alternate ROM Select normal ROM PCI 66 MHz ENABLE P66 ON - PCI 66 MHz Enable 66 MHz operation 33 MHz only. SYSTEM RESET SR ON - i DEFINITION COP can reset target system. COPonly resets local CPU/MPC107 CPU/MPC107. COP Connector Processor debug access port. NOTE: Connector should be routed to look as appears below. Install for 32-bit bus mode. i BOARD ID i CLOCK TRACE ROUTING Route all clock traces from MPC8240 MPC8240 to series resistors in equal trace lengths. Route from series resistors to destination in equal lengths plus any additional trace length needed to compensate for high speeds or high loads. Refer to AN1722/D AN1722/D for details. i i PCI Clock Trace Must equal exactly 2.5" from connector pin to MPC824X MPC824X pin, per specifications. PCI Clamp Voltage 3.3V or 5V depending upon VIO selection (see page 15). i SECTOR PROTECT/UNPROTECT Apply 12V to activate or override the boot sector protection. Resistor need not be removed. i i STAND ALONE CLOCK Install oscillator or socket for standalone operation. STAND ALONE RESET Install jumper to enable on-board reset switch. i V(I/O) SELECTION Select 3.3V or 5V V(I/O) option. ONE ONLY!