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PGA370 Processor Terminator Design Guidelines
April, 2000 Order Number: 248693-001
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Introduction Termination Package Reference Schematics Stack-up. AGTL+ Guidelines Termination Package Physical Description. Termination Package Retention.
Intel Pentium processor termination circuitry processor's AGTL+ bus. twoprocessor platform, each must properly terminated, whether both processor socket locations have processors installed. This document describes design considerations PGA370 termination package occupy second PGA370 socket location terminate when there only processor installed two-processor platform. Although there other possible methods implement termination package, Intel recommends that designs adhere guidelines Section resistor decoupling network schematics this document examples only. Other resistor decoupling designs also feasible. This document does provide detail variations specific design solution presented.
TERMINATION PACKAGE REFERENCE SCHEMATICS
Figures shows names corresponding signals that interface through PGA370 socket. Figures examples 68-ohm termination resistor networks implemented with four-resistor packages that have separate connections each resistor element. Note that maximum power each resistor 0.06 (i.e., 0.20 W/four-pack resistors) that this maximum power resistor that will need dissipated. Figure capacitor decoupling network between ground prevent noise interference (voltage drop) signals. This interference caused potentially large current draw through power distribution plane trace) termination resistors.
Figure Signals PGA370 Connector
Figure 68-Ohm Termination Resistors
Figure 68-Ohm Termination Resistors
Figure Termination Decoupling
This section defines thickness functionality (type) each layer. section routing provides specific routing rules each group nets. preferable stack-up 4-layer substrate (shown Figure below). thicknesses metal dielectric layers given Table below. These thicknesses representative altered various substrate suppliers long characteristic impedance (Zo) target Ohms met. total thickness substrate shall 0.063 0.007/- 0.005 inches. Layer Layer
Figure Reference Substrate Stack-Up Material Thickness (mils) Layer Type
Metal: 1-oz copper Dielectric: FR4-CORE Metal: 1-oz copper Dielectric: PRE-PREG Metal: 1-oz copper Dielectric: FR4-CORE Metal: 1-oz copper
6.0* 44.0* 6.0*
Table Thickness Metals Dielectrics Substrate Stack-Up *This whatever thickness required reach target Ohms. Even copper thickness long condition met. total board thickness mils. this less than mils, PRE_PREG thickness decreased accordingly.
design should follow AGTL+ layout guidelines specified Pentium® Processor Developer's Manual. Some these guidelines include: four layer stack-up desired controlled impedance. Route highest frequency signal traces bottom signal layer (BCLK must). ground plane will prevent signals bottom from radiating during testing. Limit trace routing package from inch. capacitor ends BCLK, PICCLK, TCLK clock lines, after 0.5" trace. Distribute dedicated plane. plane recommended; however, minimum width trace also used. Closely control characteristic line impedance, range. ground plane will needed maintain proper characteristic line impedance. This impedance reflects motherboard target impedance Pentium® FC-PGA processor. R-packs(for terminating AGTL+ lines) must distributed equally either side substrate inside socket cavity area with minimum spacing mils from pins secondary side. capacitors must also distributed equally. space constraints while routing, 1206 resistor packs 0603 capacitors recommended. Make sure power routings decoupled correctly. severe space constraints, necessary decoupling capacitor every R-packs. signal velocity ns/ft should used signal layers fast microstrips. following have termination package: have connected together. signals have no-connects. (1.5V) Vcmos pins have shorted through wide trace (preferably about 1000 wide, least width rings). pins R-packs have close capacitors. short wide traces escapes signal layers. VcoreDet CPUPreset have tied ground. SELFSB pins must no-connects. VRMEN# (AG1) must no-connect. RESET# (AH4, must no-connects. CLKREF (Y33 X34) must no-connects.
Minimize cross talk: Maximize line-to-line spacing least mils between traces). 5/15 rule where possible. Keep dielectric constant used termination card between 4.6. Minimize cross sectional area traces, lines with ounce/ft2 copper beware higher resistively traces). Isolate AGTL+ signals groups. That route data signals group, control signals group, address signals another group. groups routed together over plane, provide least mils separation between groups.
Conventional "pull-up" resistor networks suitable termination. These networks have common power ground extreme package, shared resistors (for 14and 20-pin components). packages generally have much inductance maintain voltage current needed each resistive load. Platforms usually better results with discrete resistors, resistor packages with separate pins each resistor, other resistor networks with acceptable characteristics. additional information properly route AGTL+ bus, please refer Pentium® Processor AGTL+ Guidelines.
Termination Package Physical Description
terminator pins must properly mate with PGA370-pin socket shown Figure (see PGA370 Connector Design Guidelines). Figure shows physical format template termination package.
Figure PGA-370 socket
TERMINATION PACKAGE RETENTION
Original Equipment Manufacturers (OEM) install retention mechanisms their platforms ensure mechanical integrity systems with PGA370 socket processors. Depending OEMs' specific shock vibration specifications, termination package require retention mechanism remain secure. requirements such mechanism determined each computer OEM. termination package should physically compatible with same retention mechanism used current PGA370 processors. specifics Intel-defined retention mechanisms, OEMs should request appropriate drawings from their preferred suppliers.
Figure Termination Package Dimensions
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