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OMAP5912 Multimedia Processor Initialization Reference Guide
Literature Number: SPRU752A March 2004
Products Amplifiers Data Converters Interface Logic Power Mgmt Microcontrollers amplifier.ti.com dataconverter.ti.com dsp.ti.com interface.ti.com logic.ti.com power.ti.com microcontroller.ti.com Applications Audio Automotive Broadband Digital Control Military Optical Networking Security Telephony Video Imaging Wireless www.ti.com/audio www.ti.com/automotive www.ti.com/broadband www.ti.com/digitalcontrol www.ti.com/military www.ti.com/opticalnetwork www.ti.com/security www.ti.com/telephony www.ti.com/video www.ti.com/wireless
Mailing Address:
Texas Instruments Post Office 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
Preface
Read This First
About This Manual
This document describes reset architecture, configuration, initialization, boot OMAP5912 multimedia processor.
Notational Conventions
This document uses following conventions.
Hexadecimal numbers shown with suffix example,
following number hexadecimal (decimal 64): 40h.
Related Documentation From Texas Instruments
following documents describe OMAP5910 device related peripherals. Copies these documents available Internet www.ti.com. Tip: Enter literature number search provided www.ti.com. OMAP5912 Multimedia Processor Device Overview Architecture Reference Guide (literature number SPRU748) introduces setup, components, features OMAP5912 multimedia processor provides high-level view device architecture. OMAP5912 Multimedia Processor OMAP Subsystem Reference Guide (literature number SPRU749) introduces briefly defines main features OMAP3.2 subsystem OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Sybsystem Reference Guide (literature number SPRU750) describes OMAP5912 multimedia processor subsystem. digital signal processor (DSP) subsystem built around core processor peripherals that interface with: ARM926EJS microprocessor unit interface (MPUI); Various standard memories external memory interface (EMIF); Various system peripherals peripheral (TIPB) bridge.
SPRU752A OMAP5912
Related Documentation From Texas Instruments
OMAP5912 Multimedia Processor Clocks Reference Guide (literature number SPRU751) describes clocking mechanisms OMAP5912 multimedia processor. OMAP5912, various clocks created from special components such digital phase locked loop (DPLL) analog phase-locked loop (APLL). OMAP5912 Multimedia Processor Initialization Reference Guide (literature number SPRU752) describes reset architecture, configuration, initialization, boot OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Power Management Reference Guide (literature number SPRU753) describes power management OMAP5912 multimedia processor. ultralow-power device (ULPD) generates manages clocks reset signals OMAP3.2 some peripherals. controls chip-level power-down modes handles chip-level wake-up events. deep sleep mode, this module still active monitor wake-up events.This book describes ULPD module outline architecture. OMAP5912 Multimedia Processor Security Features Reference Guide (literature number SPRU754) describes security features OMAP5912 multimedia processor. OMAP5912 security scheme relies OMAP3.2 secure mode. distributed security OMAP3.2 platform Texas Instruments solution address m-commerce security issues within mobile phone environment. OMAP3.2 secure mode developed bring hardware robustness overall OMAP5912 security scheme. OMAP5912 Multimedia Processor Direct Memory Access (DMA) Support Reference Guide (literature number SPRU755) describes direct memory access support OMAP5912 multimedia processor. OMAP5912 processor three DMAs:
system embedded OMAP3.2. handles transfers associated with shared peripherals. embedded OMAP3.2. handles transfers associated with peripherals. generic distributed (GDD) OMAP5912 resource attached peripheral. handles only transfers associated with peripheral.
OMAP5912
SPRU752A
Related Documentation From Texas Instruments
OMAP5912 Multimedia Processor Memory Interfaces Reference Guide (literature number SPRU756) describes memory interfaces OMAP5912 multimedia processor. SDRAM (external memory interface fast, EMIFF) Asynchronous synchronous burst memory (external memory interface slow, EMIFS) NAND flash (hardware controller software controller) CompactFlash EMIFS interface Internal static OMAP5912 Multimedia Processor Interrupts Reference Guide (literature number SPRU757) describes interrupts OMAP5912 multimedia processor. Three level interrupt controllers used OMAP5912: level interrupt handler (also referred interrupt level implemented outside OMAP3.2 handle interrupts. level interrupt handler (also referred interrupt level 2.1) instantiated outside OMAP3.2 handle interrupts. OMAP3.2 level interrupt handler (referenced interrupt level 2.0) handle interrupts. OMAP5912 Multimedia Processor Peripheral Interconnects Reference Guide (literature number SPRU758) describes various periperal interconnects OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Timers Reference Guide (literature number SPRU759) describes various timers OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Serial Interfaces Reference Guide (literature number SPRU760) describes serial interfaces OMAP5912 multimedia processor. OMAP5912 Multimedia Processor Universal Serial (USB) Reference Guide (literature number SPRU761) describes universal serial (USB) host OMAP5912 multimedia processor. OMAP5912 processor provides several varieties functionality. Flexible multiplexing signals from OMAP5912 host controller, OMAP5912 function controller, other OMAP5912 peripherals allow wide variety system-level capabilities. Many OMAP5912 pins used USB-related signals signals from other OMAP5912 peripherals. OMAP5912 top-level multiplexing
SPRU752A OMAP5912
Related Documentation From Texas Instruments
controls each individually select several possible internal signal interconnections. When these shared pins programmed signals, OMAP5912 signal multiplexing selects signals associated with three OMAP5912 host ports OMAP5912 function controller brought OMAP5912 pins. OMAP5912 Multimedia Processor Multi-channel Buffered Serial Ports (McBSPs) Reference Guide (literature number SPRU762) describes three multi-channel buffered serial ports (McBSPs) available OMAP5912 device. OMAP5912 device provides multiple highspeed multichannel buffered serial ports (McBSPs) that allow direct interface codecs other devices system. OMAP5912 Multimedia Processor Camera Interface Reference Guide (literature number SPRU763) describes camera inerfaces implemented OMAP5912 multimedia processor: compact serial camera port camera parallel interface. OMAP5912 Multimedia Processor Display Interface Reference Guide (literature number SPRU764) describes display interface OMAP5912 multimedia processor. module data conversion module pulse generator Display interface OMAP5912 Multimedia Processor Multimedia Card (MMC/SD/SDIO) (literature number SPRU765) describes multimedia card (MMC) interface OMAP5912 multimedia processor. multimedia card/secure data/secure digital (MMC/SD/SDIO) host controller provides interface between local host, such microprocessor unit (MPU) digital signal processor (DSP), either memory card, plus four serial flash cards. host controller handles MMC/SD/SDIO serial port interface (SPI) transactions with minimal local host intervention. OMAP5912 Multimedia Processor Keyboard Interface Reference Guide (literature number SPRU766) describes keyboard interface OMAP5912 multimedia processor. MPUIO module enables direct communication between (through public TIPB) external devices. types used: specific I/Os dedicated keyboard connection, general-purpose I/Os. OMAP5912 Multimedia Processor General-Purpose Interface Reference Guide (literature number SPRU767) describes general-purpose OMAP5912 SPRU752A
Related Documentation From Texas Instruments
terface OMAP5912 multimedia processor. There four GPIO modules OMAP5912. Each GPIO peripheral controls dedicated pins configurable either input output general purposes. Each independent control direction programmable register. two-edge control registers configure events (rising edge, falling edge, both edges) input trigger interrupts wake-up requests (depending system mode). addition, interrupt mask register masks specified pins. Finally, GPIO peripherals provide clear capabilities data output registers interrupt mask registers. After detection, event sources merged single synchronous interrupt (per module) generated active mode, whereas unique wake-up line issued idle mode. Eight data output lines GPIO3 ORed together generate global output line OMAP5912 boundary. This global output line used conjunction with provide CMT-APE interface OMAP5912. OMAP5912 Multimedia Processor VLYNQ Serial Communications Interface Reference Guide (literature number SPRU768) describes VLYNQ OMAP5912 multimedia processor. VLYNQ serial communications interface that enables extension internal segment more external physical devices. external devices mapped into local, physical address space appear they internal OMAP 5912. external devices must also have VLYNQ interface. VLYNQ module serializes transactions device, transfers serialized data between devices VLYNQ port, de-serializes transaction external device. OMAP5912 includes VLYNQ module connected OCPT2 target port OCPI initiator port. These connections configured static switch, which selects either VLYNQ module. This switch, forbids simultaneous GDD/SSI VLYNQ. switch controlled VLYNQ_EN OMAP5912 configuration control register (CONF_5912_CTRL). OMAP5912 Multimedia Processor Pinout Reference Guide (literature number SPRU769) provides pinout OMAP5912 multimedia processor. After power-up reset, user change configuration default interfaces. another interface available default, possible enable interface each ball setting corresponding 3-bit field associated FUNC_MUX_CTRL register. also possible configure on-chip pullup/pulldown. This document
SPRU752A OMAP5912
Trademarks
also describes various power domains that user apply different interfaces seamlessly with external components. OMAP5912 Multimedia Processor Window Tracer (WT) Reference Guide (literature number SPRU770) describes window tracer module used capture memory transactions from four interfaces: EMIFF, EMIFS, OCP-T1, OCP-T2. This module located OMAP3.2 traffic controller (TC). OMAP5912 Multimedia Processor Real-Time Clock Reference Guide (literature number SPRUxxx) describes real-time clock OMAP5912 multimedia processor. real-time clock (RTC) block embedded real-time clock module directly accessible from TIPB interface.
Trademarks
OMAP OMAP symbol trademarks Texas Instruments.
OMAP5912
SPRU752A
Contents
Contents
Reset Architecture Reset Modes Clocking Options OMAP5912 Resets 1.2.1 Split Power 1.2.2 Global Reset 1.2.3 OMAP Resets 1.2.4 OMAP5912 Peripheral Resets 1.2.5 Peripheral Reset Table OMAP5912 Input/Output OMAP5912 Configuration Configuration Register Capabilities Multiplexing Pullups/Pulldowns 2.2.1 Multiplexing Considerations with Respect RESET_MODE GPIO1 2.2.2 Multiplexing Considerations with Respect Internal Boot Code 2.2.3 Multiplexing Exceptions with Host Client 2.2.4 Configuration Ports 2.2.5 Procedure Setting Multiplexing Parallel Observability During Functional Mode OMAP5912/OMAP1510/OMAP1509 Software Hardware Compatibility Configuration Registers
OMAP5912 External Intefaces External Interface Descriptions OMAP5912 Duplicated Interfaces OMAP5912 Reset/Boot Overview Boot Mode Control EMIFS Multiplexing Control Generation Configuration Interfaces Internal Boot Boot Hardware Considerations 5.1.1 Device Types 5.1.2 Reset Considerations 5.1.3 Boot Code Hardware Polling Detection 5.1.4 Boot Code Multiplexing 5.1.5 Boot Code Flash Loaders 5.1.6 Boot Code Booting 5.1.7 Boot Versions OMAP5912 Chip Versions
OMAP Device Identification Registers
OMAP5912
SPRU752A
Tables
Tables
Clocking Options with respect Reset Modes External Reset Global Resets OMAP Resets Reset Sources Peripherals OMAP5912 Input/Output Clock Reset OMAP5912 Configuration Registers Functional Multiplexing Modes Parallel Observability MultiplexingSignals Configuration Registers Functional Multiplexing Control Register (FUNC_MUX_CTRL_0) Functional Multiplexing Control Register (FUNC_MUX_CTRL_1) Functional Multiplexing Control Register (FUNC_MUX_CTRL_2) Compatibility Mode Control Register (COMP_MODE_CTRL_0) Functional Multiplexing Control Register (FUNC_MUX_CTRL_3) Functional Multiplexing Control Register (FUNC_MUX_CTRL_4) Functional Multiplexing Control Register (FUNC_MUX_CTRL_5) Functional Multiplexing Control Register (FUNC_MUX_CTRL_6) Functional Multiplexing Control Register (FUNC_MUX_CTRL_7) Functional Multiplexing Control Register (FUNC_MUX_CTRL_8) Functional Multiplexing Control Register (FUNC_MUX_CTRL_9) Functional Multiplexing Control Register (FUNC_MUX_CTRL_A) Functional Multiplexing Control Register (FUNC_MUX_CTRL_B) Functional Multiplexing Control Register (FUNC_MUX_CTRL_C) Functional Multiplexing Control Register (FUNC_MUX_CTRL_D) Pulldown Control Register (PULL_DWN_CTRL_0) Pulldown Control Register (PULL_DWN_CTRL_1) Pulldown Control Register (PULL_DWN_CTRL_2) Pulldown Control Register (PULL_DWN_CTRL_3) Gate Inhibit Control Register (GATE_INH_CTRL_0) Configuration Revision Register (CONF_REV) Voltage Control Register (VOLTAGE_CTRL_0) Transceiver Control Register (USB_TRANSCEIVER_CTRL) Powerdown Control Register (LDO_PWRDN_CNTRL) Test Debug Control Register (TEST_DBG_CTRL_0) Module Configuration Control Register (MOD_CONF_CTRL_0)
OMAP5912
SPRU752A
Tables
Functional Multiplexing Control Register (FUNC_MUX_CTRL_E) Functional Multiplexing Control Register (FUNC_MUX_CTRL_F) Functional Multiplexing Control Register (FUNC_MUX_CTRL_10) Functional Multiplexing Control Register (FUNC_MUX_CTRL_11) Functional Multiplexing Control Register (FUNC_MUX_CTRL_12) Pulldown Control Register (PULL_DWN_CTRL_4) Pullup/Pulldown Selection Register (PU_PD_SEL_0) Pullup/Pulldown Selection Register (PU_PD_SEL_1) Pullup/Pulldown Selection Register (PU_PD_SEL_2) Pullup/Pulldown Selection Register (PU_PD_SEL_3) Pullup/Pulldown Selection Register (PU_PD_SEL_4) Module Configuration Control Register (MOD_CONF_CTRL_1) PWRDN Bits MOD_CONF_CTRL_1 Secure Mode Control Register (SECCTRL) Summary Possible Accesses SECCTRL Normal/Emulation Devices Configuration Status Register (CONF_STATUS) Reset Control Register (RESET_CONTROL) OMAP5912 Configuration Control Register (CONF_5912_CTRL) Example Duplicated Interfaces Configuration After Programming EMIFS Multiplexing Control MPU_BOOT Mode Signal Generation Reset Mode 0108 External Pins Affecting EMIFS Configuration Boot code Behavior Power-on Reset. OMAP Register (OMAP_DIE_ID_0) OMAP Register (OMAP_DIE_ID_1) OMAP Register (OMAP_PRODUCTION_ID_0) OMAP Register (OMAP_PRODUCTION_ID_1) OMAP32_ID Register (OMAP32_ID) Revision Table
SPRU752A
OMAP5912
OMAP5912
SPRU752A
Initialization
This document describes reset architecture, configuration, initialization, boot OMAP5912 multimedia processor.
Reset Architecture
OMAP5912 reset architecture describes reset signal distribution peripherals.
Reset Modes Clocking Options
Reset mode several clocking options while reset mode much more restrictive. important examine Table when determining which reset mode use.
Table
Clocking Options with respect Reset Modes
Reset Mode 19.2 19.2
OSC1_IN support crystal? OSC1_IN support w/external clock source? SYS_CLK_IN support w/external clock source?
Reset Mode
OSC1_IN support crystal? OSC1_IN support w/external clock source? SYS_CLK_IN support w/external clock source?
critical understand that certain systems functionalities available both reset modes. selection between reset modes should made early stage development cycle. Generally, reset mode flexible while reset mode more restrictive. Reset mode based value RESET_MODE (sampled rising edge PWRON_RESET). addition affecting clocking options, reset mode affects many other features such multiplexing reset time, direction impedance
SPRU752A Initialization
Reset Architecture
reset time, boot execution paths, more. Throughout this chapter, reset mode will specified when relevant discussion.
OMAP5912 Resets
OMAP5912 three external reset pins depending reset mode. PWRON_RESET cold reset entire chip. MPU_RST subsystem reset (this special setup requirements reset mode RTC_ON_NOFF software controlled, power-on reset (unavailable reset mode
Table
External Reset
Description Notes Reset Mode
External Reset
PWRON_RESET
Power-up reset
used, must considered battery power-up reset. Pulse duration must periods kHz.
Reset Mode (Continued) RTC_ON_NOFF Power-up reset Gated RTC_CTRL_REG. RTC_ON_NOFF gated (i.e. disabled) PWRON_RESET. Cold reset subsystem. Does reset chip DPLL Reset Mode PWRON_RESET Power-up reset Cold reset Pulse duration must periods kHz. RTC_ON_NOFF MPU_RST used reset Gated reset mode Proper functionality must configured (this defaults MPUIO4)
MPU_RST
reset
reset mode split-power functionality cannot used, since RTC_ON_NOFF inactive. real-time clock functionality works correctly both modes. following sections:
Table summarizes sources status bits global resets. Table covers resets specific OMAP3.2 (MPU subsystem). Table summarizes OMAP5912 peripheral resets both DSP.
SPRU752A
Initialization
Reset Architecture
1.2.1
Split Power
split power available with reset mode only. power domain split from OMAP5912 core power domain that real-time clock associated oscillator continue battery while subsystem completely powered off. With split power, PWRON_RESET acts battery power-on reset while RTC_ON_OFF used subsequently reset subsystem without disrupting time stored RTC.
1.2.2
Global Reset
Table summarizes sources status bits global resets. table groups some peripherals into general classes. Peripheral classes group peripherals based source reset input. example, Class-1 module resets directly from cold, power-on reset while Class-2 peripheral (module) resets from subsystem. Figure Table more information peripheral classes.
SPRU752A
Initialization
Reset Architecture
Table
Reset Cold reset
Global Resets
Source External PWRON_ RESET Event PWRON_ RESET Reset Description Reset controller System port interface Window tracer initiator controller Traffic controller TIPB bridge peripherals Shared peripherals Status (bit clock reset status register (ARM_SYSST)
EXT_RST (bit clock reset status register (ARM_SYSST)
RESET_MODE sole reset source GLOB_SWRST (bit1) Class1 modules: secure RAM, boot clock reset status ROM, ULPD, OMAP5912 conf, STI, register (ARM_SYSST) sync counter, secure sole reset source External RTC_ON_ NOFF RTC_ON_ NOFF split power (bit RTC_ CTRL_REG) Reset controller System port interface Window tracer initiator controller Traffic controller TIPB bridge peripherals Shared peripherals Reset source Class modules secure RAM, boot ROM,ULPD, OMAP5912 conf, STI, sync counter, secure applicable RESET_MODE RESET_MODE does reset RTC. (bit5 clock reset status register (ARM_SYSST)
EXT_RST (bit clock reset status register (ARM_SYSST)
GLOB_SWRST (bit clock reset status register (ARM_SYSST)
Initialization
SPRU752A
Reset Architecture
Table
Reset Warm reset
Global Resets (Continued)
Source External MPU_RST Event MPU_RST Reset Description Reset controller System port interface Window tracer initiator controller Traffic controller TIPB bridge peripherals Shared peripherals Class class modules. SDRAM refresh mode switched self-refresh previously autorefresh state. applicable RESET_MODE Security violation normal device security violation, ULPD generates system reset OMAP3.2. Reset controller System port interface Window tracer initiator controller Traffic controller SDRAM refresh mode switched self-refresh previously autorefresh state, MMU, TIPB bridge peripherals, shared peripherals. Class class modules. Production eFuse eFuse programmed value Warm reset permanently asserted ULPD EXT_RST (abit clock reset status register (ARM_SYSST) emulation devices, debug request sent GLOB_SWRST (bit clock reset status register (ARM_SYSST) EXTERNAL_RESET_ SOURCE_2 (bit ULPD status register EXT_RST (bit clock reset status register (ARM_SYSST) GLOB_SWRST (bit clock reset status register (ARM_SYSST) Status EXT_RST (bit clock reset status register (ARM_SYSST)
GLOB_SWRST (bit clock reset status register (ARM_SYSST)
SPRU752A
Initialization
Reset Architecture
Table
Reset Warm reset
(continued)
Global Resets (Continued)
Source 32-kHz reset Event 32-kHz time-out default configuration leads time-out with 32-kHz input frequency. Reset Description Reset controller System port interface Window tracer initiator controller Traffic controller SDRAM refresh mode switched self-refresh previously autorefresh state, MMU, TIPB bridge peripherals, shared peripherals Class class modules. Status EXT_RST (bit clock reet status register (ARM_SYSST) Reset Done (bit watchdog system status register (WD_SYSSTATUS) GOB_SWRST (bit clock reset status register (ARM_SYSST) EXTERNAL_RESET_ SOURCE_3 (bit ULPD status register EXT_RST (bit clock reset status register (ARM_SYSST) ResetDone (bit Watchdog system status register (WD_SYSSTATUS) GLOB_SWRST (bit clock reset status register (ARM_SYSST) EXTERNAL_RESET_ SOURCE_1 (bit ULPD status register
Secure reset
Secure time-out default configuration leads time-out system clock MHz.
Reset controller System port interface Window tracer initiator controller Traffic controller TIPB bridge peripherals Shared peripherals Class class modules.
Initialization
SPRU752A
Reset Architecture
Table
Reset Warm reset
Global Resets (Continued)
Source Event SW_RST (bit ARM_ RSTCT1 ARM_RST (bit ARM_RSTC1 clear DSP_EN (bit ARM_RSTC1 Reset Description Reset controller System port interface Window tracer initiator controller Traffic controller TIPB bridge peripherals Shared peripherals SDRAM refresh mode switched self-refresh previously autorefresh state Class class modules. reset underflow Reset controller System port interface Window tracer initiator controller Traffic controller TIPB bridge peripherals Shared peripherals SDRAM refresh mode switched self-refresh previously autorefresh state Class class modules. ARM_WDRST (bit clock reset status register (ARM_SYSST) Status GLOB_SWRST (bit clock reset status register (ARM_SYSST)
Global system reset (continued) (software)
GLOB_SWRST (bit clock reset status register (ARM_SYSST)
reset
timeout
Underflow
Reset system peripheral modules wrapper switches. Reset WD_PER_EN (bit DSP_RSTCT2.
DSP_WDRST (bit clock reset status register (ARM_SYSST)
software reset
Software
ARM_RST Reset MPU. (bit ARM_RSTC1
ARM_MCRST (bit clock reset status register (ARM_SYSST)
SPRU752A
Initialization
Reset Architecture
Table
Reset
Global Resets (Continued)
Source Event Reset Description Status
Software peripheral reset
PER_EN Reset peripheral class modules (bit peripheral modules wrapper switches. ARM_RSTC2 cleared DSP_EN (bit ARM_RSTC1 cleared Reset DSP, excluding configuration settings (config registers EMIF internal MPUI control logic internal DSP).
core software reset
Software
Software peripheral reset
DSP_PEREN Reset peripheral Class modules. (bit DSP_RSTC2 cleared DSP_RST Reset priority registers (TIPB) (bit module, EMIF configuration register, ARM_RSTC1 MPUI control logic DSP.
Software Reset
Software
conjunction with reset status register OMAP3.2, user poll ULPD reset status register determine whether reset caused security violation, secure watchdog time-out, watchdog time-out. Table
1.2.3
OMAP Resets
Table shows OMAP3.2 components affected various reset sources. peripheral resets included this table they part OMAP3.2 (See Table peripheral resets).
Table
OMAP Resets
Type Cold Resets Warm Resets Reset Software Reset Core Software Reset Software Reset
Components
CLKM_1 CLKM_2
DSP-MMU reset CNTL_REG DSP-MMU module must also correctly DSP-MMU reset. SDRAM self-refresh; some registers controlled SDRAM reset. Table listing cold/warm resets.
Initialization
SPRU752A
Reset Architecture
Table
OMAP Resets (Continued)
Type Cold Resets Warm Resets Note Reset Software Reset Core Software Reset core only, EMIF config regs MPUI control logic Software Reset Only EMIF config regs MPUI control logic DSP, core
Components
CLKM_3 DPLL_1 ARM926EJS EMPU timer timer timer timer INTH controller
timer timer timer timer INTIF INTH Maibox
DSP-MMU reset CNTL_REG DSP-MMU module must also correctly DSP-MMU reset. SDRAM self-refresh; some registers controlled SDRAM reset. Table listing cold/warm resets.
SPRU752A
Initialization
Reset Architecture
Table
OMAP Resets (Continued)
Type Cold Resets Warm Resets Reset Software Reset Core Software Reset Software Reset
Components
MPUI System controller TIPB bridge EMIFF EMIFS L3/OCP/T1 (target) L3/OCP/T2 (target) L3/OCP(initiator)
Self-Ref
DSP-MMU reset CNTL_REG DSP-MMU module must also correctly DSP-MMU reset. SDRAM self-refresh; some registers controlled SDRAM reset. Table listing cold/warm resets. Note: DPLL reset MPU_RST secure 32-kHz security violation resets. Other warm resets reset DPLL.
1.2.4
OMAP5912 Peripheral Resets
Figure shows resets distributed peripherals. Table description different peripheral classes.
Initialization
SPRU752A
Reset Architecture
Figure
Boot
Reset Distribution Peripherals
Syst/secure Sync counter INTH MCSI2 MCSI1 McBSP1 OMAP3.2 Warm Reset Cold Reset ULPD GPIO(x4) MPUIO Camera HDQ1_Wire DSPPER_RST ARMPER_RST Class Modules LPG2 Memory Stick DES/3DES MOD_CONF_CTRL_1[23] power split SoSSI Exception timer LPG1 µWire Watchdog MMC-SDIO1 Gptimer(x8) NAND Flash Class Modules McBSP3
Secure OMAP5912 conf Class Modules CHIP_RESET_IN Warm Resets Security violation Secure MPU_RST ULPD_RESET
Class Modules VLYNQ -SDIO2 SHA1/MD5 Compact flash controller interconnect Test SRAM INTH
Cold Resets
PWRON_RESET_CORE
UART1,2,3 McBSP2
PWRON_RESET SPLIT_POWER
RTC_ON_NOFF RESET_MODE
Note that Figure peripheral classes group peripherals based source reset input. ULPD charge generating functional reset signals subsystem (OMAP3.2 core): cold reset (PIPORN) warm reset (PICHIPNRST). then task subsystem reset processors peripherals. addition, there five input resets ULPD. these resets external pins: PWRON_RESET (cold reset ball R12) MPU_RST (warm reset ball U20). other three resets warm resets: secure watchdog reset, security violation reset, 32-kHz watchdog timer reset.
1.2.5
Peripheral Reset Table
Table shows various reset sources each peripheral. Many OMAP peripherals (external subsystem) have module wrappers switches that facilitate conversion between different protocols (wrapper) control access that peripheral (switch).
SPRU752A
Initialization
Reset Architecture
example, UART1 peripheral TIPB, internal protocol UART1 OCP. UART1 wrapper that converts between TIBP protocols. wrapper must released from reset before access UART1 peripheral possible. This wrapper also acts switch that determines whether control over UART1. peripherals with wrappers/switches, functionality gated reset wrapper/switch. Consequently, wrapper/switch must released from reset before peripheral becomes available. Table details which peripherals have wrappers switches. addition, Chapter discusses specific types wrappers switches those peripherals. also important understand that there types switches, each with distinct default behaviors when released from reset. Chapter details such behaviors.
Table
Reset Sources Peripherals
Reset Reset Class Modules Wrapper/ Switch Wrapper/Switch Reset
Peripheral Name
Real-time clock (RTC) OMAP5912configuration Boot Secure
Cold reset Cold reset Cold reset Cold reset Cold reset
SWRST
Dynamic switch
Cold reset/Warm reset ARM_WD/DSP_WD/S Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3#/ SWRST2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
32-kHz synchro counter
Cold reset
Dynamic switch
Secure watchdog
Cold reset
SWRST
wrapper
SWRST: Reset software done corresponding module. SWRST1: PER_EN (bit ARM_RSTC2 cleared SWRST2: ARM_RST (bit ARM_RSTCT1 clear DSP_EN (bit ARM_RSTCT1. SWRST3: DSP_PEREN (bit DSP_RSTCT2 cleared Warm reset: Source MPU_RST, global software reset, 32-kHz watchdog time-out, secure watchdog time-out. control RESET_CONTROL register (see Table 53). control MOD_CONF_CTRL_1[23].
Initialization
SPRU752A
Reset Architecture
Table
Reset Sources Peripherals (Continued)
Reset Reset Class Modules Wrapper/ Switch Wrapper/Switch Reset
Peripheral Name
µWire
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
HDQ/1-Wire
Camera
LPG1
LPG2
interconnect
Frame Buffer
SWRST: Reset software done corresponding module. SWRST1: PER_EN (bit ARM_RSTC2 cleared SWRST2: ARM_RST (bit ARM_RSTCT1 clear DSP_EN (bit ARM_RSTCT1. SWRST3: DSP_PEREN (bit DSP_RSTCT2 cleared Warm reset: Source MPU_RST, global software reset, 32-kHz watchdog time-out, secure watchdog time-out. control RESET_CONTROL register (see Table 53). control MOD_CONF_CTRL_1[23].
SPRU752A
Initialization
Reset Architecture
Table
Reset Sources Peripherals (Continued)
Reset Reset Class Modules (Continued) Wrapper/ Switch Wrapper/Switch Reset
Peripheral Name
CompactFlash controller
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
Memory Stick interface
Partial
Async. OCP2VIA wrapper wrapper
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/ SWRST2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/ SWRST2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/ SWRST2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/ SWRST2/SWRST1
SWRST
GPIO1
SWRST
Dynamic switch
GPIO2
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Dynamic switch
GPIO3
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Dynamic switch
GPIO4
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Dynamic switch
SWRST: Reset software done corresponding module. SWRST1: PER_EN (bit ARM_RSTC2 cleared SWRST2: ARM_RST (bit ARM_RSTCT1 clear DSP_EN (bit ARM_RSTCT1. SWRST3: DSP_PEREN (bit DSP_RSTCT2 cleared Warm reset: Source MPU_RST, global software reset, 32-kHz watchdog time-out, secure watchdog time-out. control RESET_CONTROL register (see Table 53). control MOD_CONF_CTRL_1[23].
Initialization
SPRU752A
Reset Architecture
Table
Reset Sources Peripherals (Continued)
Reset Reset Class Modules (Continued) Wrapper/ Switch Wrapper/Switch Reset
Peripheral Name
On-the-Go
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1
UART1
SWRST
Static switch
UART2
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
UART3
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
NAND flash controller
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
multi-master/slave
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
master/ slave
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
SWRST: Reset software done corresponding module. SWRST1: PER_EN (bit ARM_RSTC2 cleared SWRST2: ARM_RST (bit ARM_RSTCT1 clear DSP_EN (bit ARM_RSTCT1. SWRST3: DSP_PEREN (bit DSP_RSTCT2 cleared Warm reset: Source MPU_RST, global software reset, 32-kHz watchdog time-out, secure watchdog time-out. control RESET_CONTROL register (see Table 53). control MOD_CONF_CTRL_1[23].
SPRU752A
Initialization
Reset Architecture
Table
Reset Sources Peripherals (Continued)
Reset Reset Class Modules (Continued) Wrapper/ Switch Wrapper/Switch Reset
Peripheral Name
MMC/SDIO2
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1
General-purpose timer
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
General-purpose timer
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
General-purpose timer
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
General-purpose timer
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
General-purpose timer
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
General-purpose timer
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
SWRST: Reset software done corresponding module. SWRST1: PER_EN (bit ARM_RSTC2 cleared SWRST2: ARM_RST (bit ARM_RSTCT1 clear DSP_EN (bit ARM_RSTCT1. SWRST3: DSP_PEREN (bit DSP_RSTCT2 cleared Warm reset: Source MPU_RST, global software reset, 32-kHz watchdog time-out, secure watchdog time-out. control RESET_CONTROL register (see Table 53). control MOD_CONF_CTRL_1[23].
Initialization
SPRU752A
Reset Architecture
Table
Reset Sources Peripherals (Continued)
Reset Reset Class Modules (Continued) Wrapper/ Switch Wrapper/Switch Reset
Peripheral Name
General-purpose timer (sleep timer)
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST 2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
General-purpose timer (32K DSP)
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
Static switch
McBSP2
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
Partial
Static switch
level interrupt handler MMC/SDIO1
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST
wrapper
SWRST
wrapper
32-kHz watchdog
SWRST
wrapper
SWRST
wrapper
SHA-1/MD5
SWRST
wrapper
SWRST: Reset software done corresponding module. SWRST1: PER_EN (bit ARM_RSTC2 cleared SWRST2: ARM_RST (bit ARM_RSTCT1 clear DSP_EN (bit ARM_RSTCT1. SWRST3: DSP_PEREN (bit DSP_RSTCT2 cleared Warm reset: Source MPU_RST, global software reset, 32-kHz watchdog time-out, secure watchdog time-out. control RESET_CONTROL register (see Table 53). control MOD_CONF_CTRL_1[23].
SPRU752A
Initialization
Reset Architecture
Table
Reset Sources Peripherals (Continued)
Reset Reset Class Modules (Continued) Wrapper/ Switch Wrapper/Switch Reset
Peripheral Name
DES/3DES
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1/ 32-kHz WD/SEC
SWRST
wrapper
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
VLYNQ
VLYNQ_ CONFIG[0] register
VLYNQ2OCP
pvci2rhea
Timer
TIPB
Sync. OCP2VIA wrapper wrapper
Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1 Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
CCP|
MPUIO||
SWRST: Reset software done corresponding module. SWRST1: PER_EN (bit ARM_RSTC2 cleared SWRST2: ARM_RST (bit ARM_RSTCT1 clear DSP_EN (bit ARM_RSTCT1. SWRST3: DSP_PEREN (bit DSP_RSTCT2 cleared Warm reset: Source MPU_RST, global software reset, 32-kHz watchdog time-out, secure watchdog time-out. control RESET_CONTROL register (see Table 53). control MOD_CONF_CTRL_1[23].
Initialization
SPRU752A
Reset Architecture
Table
Reset Sources Peripherals (Continued)
Reset Reset Class Modules Wrapper/ Switch Wrapper/Switch Reset
Peripheral Name
Interrupt handler
Cold reset/Warm reset/ARM_WD/SWRS T3/SWRST2
SWRST
wrapper
Cold reset/Warm reset/ARM_WD/ DSP_WD/SWRST3/S WRST2 Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST Cold reset/Warm reset/ARM_WD/DSP_ WD/SWRST3/SWRST
McBSP1
Cold reset/Warm reset/ARM_WD/SWRS T3/SWRST2
Partial
wrapper
McBSP3
Cold reset/Warm reset/ARM_WD/SWRS T3/SWRST2
Partial
wrapper
MCSI1
Cold reset/Warm reset/ARM_WD/SWRS SWRST2/ 32-kHz /SEC Cold reset/Warm reset/ARM_WD/SWRS T3/SWRST2/ 32-kHz WD/SEC
Partial
TIPB
MCSI2
Partial
TIPB
Exceptions SoSSIk MOD_CONF_ CTRL_1[23] wrapper Cold reset/Warm reset/ARM_WD/SWRS T2/SWRST1
SWRST: Reset software done corresponding module. SWRST1: PER_EN (bit ARM_RSTC2 cleared SWRST2: ARM_RST (bit ARM_RSTCT1 clear DSP_EN (bit ARM_RSTCT1. SWRST3: DSP_PEREN (bit DSP_RSTCT2 cleared Warm reset: Source MPU_RST, global software reset, 32-kHz watchdog time-out, secure watchdog time-out. control RESET_CONTROL register (see Table 53). control MOD_CONF_CTRL_1[23].
Note:
DSP_WD controlled DSP_RSTCT2.WD_PER_EN.
SPRU752A
Initialization
Reset Architecture
OMAP5912 Input/Output
Table lists OMAP5912 I/Os that related clock reset module.
Table
Name RESET_ MODE PWRON_ RESET
OMAP5912 Input/Output Clock Reset
Dir. Ball Description Reset_ mode Power-up reset Default Mode RESET_MODE Default Mode RESET_MODE Notes Sampled power-up reset. battery asserted only once when split power backup used. chapter RTC_ CTRL_REG must
RTC_ON_ NOFF MPU_RST RST_OUT OSC32K_IN
Power-up reset Warm reset
AA20 32-kHz oscillator
external 32-kHz clock used, must tied high. external 32-kHz clock used, must tied low. Must tied on-chip 32-kHz oscillator used. external SYS_CLK_IN used, must tied low.
OSC32K_OUT
AA13 32-kHz oscillator 32-kHz clock 12-MHz oscillator
CLK32K_IN
OSC1_IN
OSC1_OUT
12-MHz oscillator 12-MHz 19.2-MHz clock
SYS_CLK_IN
Must tied on-chip oscillator used. Must select mode Ball with software.
Initialization
SPRU752A
Reset Architecture
Table
Name EXT_CLK
OMAP5912 Input/Output Clock Reset (Continued)
Dir. Ball Description External clock timers Backup 48-MHz clock Default Mode RESET_MODE Default Mode RESET_MODE Notes
EXT_48M
Through GPIO14 input pin. Used on-chip APLL disabled.
BCLKREQ
Request BCLK Request MCLK 32-kHz clock Request external clock Modem shut down battery fails
MCLKREQ
CLK32K_OUT
EXT_MASTER _REQ
RST_HOST_
controlled software (POWER_CTRL_ REG[3] POWER_CTRL_ REG[2]=0) divided further setting SDW_CLK_DIV_C TRL_SEL[7:2]
BCLK
System clock derived from APLL clock System clock derived from APLL clock Derived from APLL clock
MCLK
When 48MHz, divided further setting COM_RATIO_ SEL[7:2] 96-MHz APLL clock divided
USB.CLK0
SPRU752A
Initialization
OMAP5912 Configuration
Table
Name SYS_CLK_ CAM.EXCLK
OMAP5912 Input/Output Clock Reset (Continued)
Dir. Ball Description System clock output Derived from CK_REF Output from APLL Low-voltag mode Default Mode RESET_MODE Default Mode RESET_MODE Notes Same frequency DPLL1 input (CK_REF) Camera clock output test/observability mode only High deep sleep high software (POWER_CTRL_ REG[1] POWER_CTRL_ REG[0]=1) deep sleep mode
ULPD_ DPLL48M LOW_PWR
LOW_PWR
Low-voltag mode
OMAP5912 Configuration
OMAP5912 configuration module allows software control various static modes supported device. This module primary point control following areas OMAP5912 device:
Functional multiplexing Debug observation multiplexing gating inhibiting power-down modes Pullup pulldown enable selection Interface voltage selection Static module configuration Control clock multiplexing Secure mode configuration Multiplexing mode status Control integrated transceivers bypassing control Reset control
SPRU752A
Initialization
OMAP5912 Configuration
Configuration Register Capabilities
OMAP5912 configuration module bank 32-bit registers that read written software. module reset only with cold reset. This bank registers broken down into following sections:
Table
OMAP5912 Configuration Registers
Legacy configuration registers multiplex enable register Generic multiplexing registers Pullup/pulldown enable registers Pullup/pulldown select registers Gating inhibiting registers Voltage control registers Test debug registers Configuration module version number Module configuration registers request multiplex registers FUNC_MUX_CTRL(0-2) COMP_MODE_CTRL_0 FUNC_MUX_CTRL(3-12) PULL_DWN_CTRL(0-4) PU_PD_SEL(0-4) GATE_INH_CTRL_0 VOLTAGE_CTRL_0 TEST_DBG_CTRL_0 CONF_REV MOD_CONF_CTRL(0-1) FUNC_MUX_DSP_DMA(A-D)
Table
OMAP5912 Configuration Registers (Continued)
request multiplex registers Security control register Status register bypassing control register Transceivers control register Reset control register OMAP5912 control register FUNC_MUX_ARM_DMA(A-G) SECCTRL CONF_STATUS LDO_PWRDN_CTRL USB_TRANSCEIVER_CTRL RESET_CONTROL CONF_5912_CTRL
Multiplexing Pullups/Pulldowns
Each that multiplexing function assigned 3-bit field register FUNC_MUX_CTRL(3-12), thus creating eight possible multiplexing options pin. reset (PWRON_RESET low), multiplexing each asynchronously forced RESET_MODE pin, regardless value written FUNC_MUX_CTRL(3-12) registers.
SPRU752A
Initialization
OMAP5912 Configuration
Most pins configured either pullup pulldown. PULL_DWN_CTRL (0-4) registers control whether pullup pulldown enabled. pulls down) disabled setting corresponding field. PU_PD_SEL(0-4) registers configure pin-by-pin whether pullup pulldown selected. reset, pin-for-pin, pullup/pulldown state forced consistent with OMAP5912 reset state. pullups pulldowns remain this forced state until 0x0000EAEF written COMP_MODE_CTRL_0 register.
2.2.1
Multiplexing Considerations with Respect RESET_MODE GPIO1
RESET_MODE sampled rising edge PWRON_RESET. When PWRON_RESET low, RESET_MODE affects impedance state direction some pins because intended these pins differs between reset modes. RESET_MODE affects initial mulitplexing state some pins irrespective FUNC_MUX_CTRL registers affects initial state EMIFS interface. Finally, RESET_MODE affects boot code execution path. Note: Choosing between reset modes critical understand that changing RESET_MODE, certain systems functionalities available both modes. decision choose between reset mode should made early stage development cycle. Generally, reset mode flexible while reset mode more restrictive. important distinguish between functionalities before after writing 0x0000EAEF COMP_MODE_CTRL_0:
Prior writing 0x0000EAEF, multiplexing pins depends solely RESET_MODE latched rising edge PWRON_RESET. GPIO1 latched rising edge PWRON_RESET RESET_MODE
After writing 0x0000EAEF, multiplexing depends FUNC_MUX_CTRL registers pins.
Initialization
SPRU752A
OMAP5912 Configuration
Even though FUNC_MUX_CTRL registers reset 0x0000, reset mode causes some pins default mode other than 000. maintain same mode such pins, appropriate FUNC_MUX_CTRL register must programmed prior writing 0x0000EAEF COMP_MODE_CTRL_0.
example, reset mode defaults SYS_CLK_IN mode rather than UART2.BCLK (mux mode However, FUNC_MUX_CTRL_D(2:0) bits their reset value 000. FUNC_MUX_CTRL_D(2:0) bits must (mux mode prior writing 0x0000EAEF COMP_MODE_CTRL_0 order SYS_CLK_IN maintain functionality. Otherwise, system clock killed when 0x0000EAEF written COMP_MODE_CTRL_0 (because default mode UART2.BCLK, takes effect). similar manner, reset mode determines pullup/pulldown configuration set. Finally, important note that GPIO1 affects default multiplexing some EMIFS pins reset mode pins
2.2.2
Multiplexing Considerations with Respect Internal Boot Code
boot code change multiplexing depending variety circumstances. Section more details.
2.2.3
Multiplexing Exceptions with Host Client
muxing overridden JTAG sequence. host client multiplexing exception previously described multiplexing pullup-/pulldown-enable generation. more information contact your representative.
2.2.4
Configuration Ports
port integrated transceiver cell able operate UART transactions (3-V mode). also programmed enable external pullup. default mode mode. Programming UART, modes, control external pullup done USB_TRANSCEIVER_CTRL register.
SPRU752A
Initialization
OMAP5912 Configuration
ports configured operate with transceivers, whose interfaces either bidirectional unidirectional. Configuration done with USB_TRANSCEIVER_CTRL[8:7] register bits. Multiplexing section Chapter Universal Serial Bus, additional information.
2.2.5
Procedure Setting Multiplexing
value RESET_MODE read CONF_RESET_MODE_STAT_R field CONF_STATUS register:
mode registers (FUNC_MUX_CTRL(3-12)) reset regardless RESET_MODE input status. pullup/pulldown enable registers (PULL_DWN_CTRL(0-4)) reset regardless RESET_MODE input status. However, actual states pulldowns does depend values PULL_DWN_CTRL(0-4) registers until programming 0x0000EAEF COMP_MODE_CTRL_0 register. pullup/pulldown select registers (PU_PD_SEL(0-4)) reset regardless RESET_MODE input status.
chapter default states multiplexing pulls. Note: Register values ignored until 0x0000EAEF written COMP_MODE_CTRL_0 register.
When configuring pinout device: Determine desired values each FUNC_MUX_CTRL (3-12), PU_PD_SEL(0-4), PULL_DWN_CTRL (0-4) configuration register. Program desired values writing appropriate register. Program COMP_MODE_CTRL_0 register 0x0000EAEF. This procedure allows user make multiplex configuration settings enable modes once. values they correspond multiplexing modes shown Table desired multiplexing pullup/pulldown modes then activated. Once 0x0000EAEF written COMP_MODE_CTRL_0, must changed because device will revert original multiplexing pullup/down states.
Initialization SPRU752A
OMAP5912 Configuration
Table
Functional Multiplexing Modes
Corresponding Multiplexing Mode Configuration Default configuration/functional multiplexing Functional multiplexing mode Functional multiplexing mode Functional multiplexing mode Functional multiplexing mode Functional multiplexing mode Functional multiplexing mode Functional multiplexing mode
FUNC_MUX_CTRL 3-Bit Value
given interface, values FUNC_MUX_CTRL bits vary from pin. example, USB1_HOST port split between functional multiplexing functional multiplexing columns. this case, four pins have mode value 001, other four have mode value 010.
Note: programming mode that defined Chapter Pinout, leads undefined operation pin, thus must strictly avoided.
Parallel Observability During Functional Mode
debug purposes, various internal OMAP5912 signals brought OMAP5912 boundary during functional mode. software procedure enabling observability internal signals follows:
depending signal that must observed (see Table FUNC_MUX_CTRL_0.OBS_288_1
There need write 0xEAEF COMP_MODE_CTRL_0 observability mode. Table gives observable signals, their locations OMAP5912 boundary, depending CONF_OBS_MUX_SEL_R.
SPRU752A Initialization
OMAP5912 Configuration
Table
Parallel Observability MultiplexingSignals
CONF_OBS_MUX_SEL_R Value
Ball Reserved Reserved
ARMXOR_CK DSPXOR_CK
LDO_SLEEP LDO_STEADY
ULPD_DPLL48M ULPD_ USBW2FCCLK12M OMAP3.2 functional clock Reserved
Ball
ARMPER_CK
LDO_PWRDN
RXDP
DSPPER_CK
UART3 functional clock UART2 functional clock UART1 functional clock
RXDM
Reserved
Reserved
Reserved
Reserved
Reserved
Ball Reserved
Reserved
MMC2 functional clock MMC1 functional clock Reserved
Reserved
Reserved
Reserved
MCLK BCLK
DPLL2 clock Reserved
sleep observable observable interrupt observable interrupt observable BIST FAIL
APLL PWRDN APLL SYNC
BCLK
Reserved
OMAP3.2 warmreset CLK12M STABLE
functional clock host functional clock Camera functional clock CAM.OUTCLK
Reserved
DPLL1 clock
APLL output clock
INTH functional clock OMAP3.2 Idle
WKUP_NREQ
BIST DONE
APLL LOCK
Initialization
SPRU752A
OMAP5912 Configuration
Table
Parallel Observability MultiplexingSignals (Continued)
CONF_OBS_MUX_SEL_R Value
SYS_CLK_OUT
OMAP3.2 DPLL enable ULPD clock switch status UART2 functional clock (from system clock) Internal clock (distributed peripherals) Internal system clock Internal clock (feeding ULPD) oscillator PWRDN
BIST
CHIP_NWAKEUP
DLL_PMT_DCB[7]
functional clock
DLL_PMT_DCB[6]
Reserved
DLL_PMT_DCB[5]
Reserved
DLL_PMT_DCB[4] DLL_PMT_DCB[3]
Reserved Reserved
DLL_PMT_DCB[2]
Reserved
DLL_PMT_DCB[1] DLL_PMT_DCB[0]
12-MHz oscillator Reserved 12-MHz oscillator PWRDN Reserved
OMAP5912/OMAP1510/OMAP1509 Software Hardware Compatibility
significant hardware change from OMAP1510 OMAP5912 configuration module removal OMAP1509 compatibility mode. OMAP5912 device does reset OMAP1509 mode, OMAP1510 device. Instead, device resets based RESET_MODE forced either functional multiplexing mode 000, with appropriate pullups pulldowns configured enabled preserve OMAP1510 pinout reset condition, reset mode OMAP5912 multiplexing remains software compatible with OMAP1510 controlled same 3-bit field (eight modes possible). functionality OMAP1509 compatibility mode multiplexing control registers been removed registers themselves remain memory space.
SPRU752A
Initialization
OMAP5912 Configuration
Pullup pulldown control changed from OMAP1510 OMAP5912. applicable, OMAP1510 device either pullup pulldown pin, 1-bit register enables disables pullup pulldown. OMAP5912 device, however, both pullup pulldown available each pin. Thus, OMAP5912 register implemented (PU_PD_SEL (0-4)) allow software select between pullup pulldown each pin. reset condition PU_PD_SEL(0-4) determined, keep compatibility with OMAP1510 reset condition. OMAP1510 pullup/pulldown enable register remains (PULL_DWN_CTRL (0-3). reset state, however, changed match what pinout requires reset. OMAP1510, programming following registers does take effect until COMP_MODE_CTRL_0 register written with 0x0000EAEF. OMAP5912, however, these registers have this restriction, programming register takes effect immediately, regardless state COMP_MODE_CTRL_0 register.
GATE_INH_CTRL_0 VOLTAGE_CTRL_0 TEST_DBG_CTRL_0 MOD_CONF_CTRL_0
OMAP5912, power supplies have low- high-voltage mode OMAP1510, only EMIFS, EMIFF, communication processor interface have dual voltage interfaces. OMAP5912 reset, voltage mode changed default low-voltage mode, whereas OMAP1510 high-voltage mode. OMAP5912 software/hardware compatibility multiplexing configuration follows:
OMAP1509 compatibility mode removed. device resets functional multiplexing mode with appropriate
summary
pullups pulldowns configured enabled preserve OMAP1510 pinout reset condition RESET_MODE
Multiplexing-per-pin stays same OMAP1510 mode. More
pins multiplexed OMAP5912 that there additional FUNC_MUX_CTRL registers.
PULL_DWN_CTRL register remains unchanged. responsible
pullup pulldown enable, determined state newly created PU_PD_SEL register set. Because there additional pins
Initialization SPRU752A
OMAP5912 Configuration
requiring pullup/pulldown capability, extra PULL_DWN_CTRL registers have been added. Because pins need pullup pulldown function, determine whether pullup/pulldown implemented. Table lists configuration registers. Table through Table describe register bits.
Configuration Registers
Table Configuration Registers
Base Address 0xFFFE 1000 Name FUNC_MUX_CTRL_0 FUNC_MUX_CTRL_1 FUNC_MUX_CTRL_2 COMP_MODE_CTRL_0 FUNC_MUX_CTRL_3 FUNC_MUX_CTRL_4 FUNC_MUX_CTRL_5 FUNC_MUX_CTRL_6 FUNC_MUX_CTRL_7 FUNC_MUX_CTRL_8 FUNC_MUX_CTRL_9 FUNC_MUX_CTRL_A FUNC_MUX_CTRL_B FUNC_MUX_CTRL_C FUNC_MUX_CTRL_D PULL_DWN_CTRL_0 PULL_DWN_CTRL_1 PULL_DWN_CTRL_2 PULL_DWN_CTRL_3 GATE_INH_CTRL_0 Description Functional multiplexing control Functional multiplexing control Functional multiplexing control Compatibility mode control Functional multiplexing control Functional multiplexing control Functional multiplexing control Functional multiplexing control Functional multiplexing control Functional multiplexing control Functional multiplexing control Functional multiplexing control Functional multiplexing control Functional multiplexing control Functional multiplexing control Pulldown control Pulldown control Pulldown control Pulldown control Gate inhibit control Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x40 0x44 0x48 0x4C 0x50
SPRU752A
Initialization
OMAP5912 Configuration
Table Configuration Registers (Continued)
Base Address 0xFFFE 1000 Name CONF_REV VOLTAGE_CTRL_0 USB_TRANSCEIVER_CTRL LDO_PWRDN_CBTRK TEST_DBG_CTRL_0 MOD_CONF_CTRL_0 FUNC_MUX_CTRL_E FUNC_MUX_CTRL_F FUNC_MUX_CTRL_10 FUNC_MUX_CTRL11 FUNC_MUX_CTRL_12 PULL_DWN_CTRL_4 PU_PD_SEL_0 PU_PD_SEL_1 PU_PD_SEL_2 PU_PD_SEL_3 PU_PD_SEL_4 FUNC_MUX_DSP_DMA_A FUNC_MUX_DSP_DMA_B FUNC_MUX_DSP_DMA_C FUNC_MUX_DSP_DMA_D FUNC_MUX_ARM_DMA_A FUNC_MUX_ARM_DMA_B FUNC_MUX_ARM_DMA_C FUNC_MUX_ARM_DMA_D Description Configuration revision Voltage control transceiver control powerdown control Test debug control Module configuration control Functional multiplexing control Functional multiplexing control Functional multiplexing control Functional multiplexing control Functional multiplexing control Pulldown control Pullup/pulldown selection Pullup/pulldown selection Pullup/pulldown selection Pullup/pulldown selection Pullup/pulldown selection Functional multiplexing Functional multiplexing Functional multiplexing Functional multiplexing Functional multiplexing Functional multiplexing Functional multiplexing Functional multiplexing Offset 0x58 0x60 0x64 0x68 0x70 0x80 0x90 0x94 0x98 0x9C 0xA0 0xAC 0xB4 0xB8 0xBC 0xC0 0xC4 0xD0* 0xD4* 0xD8* 0xDC* 0xEC* 0xF0* 0xF4* 0xF8*
Initialization
SPRU752A
OMAP5912 Configuration
Table Configuration Registers (Continued)
Base Address 0xFFFE 1000 Name FUNC_MUX_ARM_DMA_E FUNC_MUX_ARM_DMA_F FUNC_MUX_ARM_DMA_G MOD_CONF_CTRL_1 SECCTRL CONF_STATUS RESET_CONTROL CONF_5912_CTRL
Note:
Description Functional multiplexing Functional multiplexing Functional multiplexing Module configuration control Secure mode control Configuration status Reset control register OMAP5912 configuration control
Offset 0xFC* 0x100* 0x104* 0x110 0x120 0x130
0x140 0x150
Register descriptions functional registers Chapter
Table
Functional Multiplexing Control Register (FUNC_MUX_CTRL_0)
Base Address 0xFFFE 1000, Offset Address 0x00
Name CTRL_288_1
Function This configures control mode 288_1, which enables control OMAP CHIP_NWAKEUP signal from RTCK pad. Functional mode. ULPD controls OMAP CHIP_NWAKEUP signal. Debug. RTCK controls OMAP CHIP_NWAKEUP signal.
Reset
Notes:
OBS_288_2 OBS_600_1
note note
This function been removed. Writing this register acceptable. However, recommended write case functions added this register space future.
SPRU752A
Initialization
OMAP5912 Configuration
Table
Functional Multiplexing Control Register (FUNC_MUX_CTRL_0) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x00
Name OBS_288_1
Function Configures observation mode multiplexing camera interface (See Section 2.3). Observation mode disabled camera interface functional mode. Enables observation mode Programming sequence: Configure CONF_OBS_MUX_CTRL_R (See Section details) Enable observability multiplexing programming OBS_288_1
Reset
UWIRE_HIZ_DISABLE GIGA_UART_GATING BT_UART_GATING COM_UART_GATING USB_TRANS_MUX LB_RESET_DISABLE HSAB_RESET_DISABLE LRU_SEL
Note Note Note Note Note Note Note This field configures OMAP traffic controller arbitration algorithm. priority scheme used arbitration. Fixed priority scheme used arbitration. This changed only when reset.
17:16
Notes:
VBUS_CTRL VBUS_MODE UWIRE_DCD OS_TYPE
Note Note Note Reserved
This function been removed. Writing this register acceptable. However, recommended write case functions added this register space future.
Initialization
SPRU752A
OMAP5912 Configuration
Table
Functional Multiplexing Control Register (FUNC_MUX_CTRL_0) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x00
Name NRESET_ENABLE
Function Allows gating outputs with OMAP CHIP_NRESET_OUT Disabled Enabled This register enables Inhibit2 function. Depending status GPIO(9) ARMIO(3), subject inputs gated internally when this function enabled. Enable gating inputs combination COM_PWR_REQ (GPIO(9)) COM_STS (MPUIO(3)) input pins. Disable gating inputs combination COM_PWR_REQ (GPIO(9)) COM_STS (MPUIO(3)) input pins. This control function called Inhibit2 pinout document.
Reset
PWR_MASK_IN
PWR_MASK_OUT
This register enables Gated2 function. Depending status GPIO(9) ARMIO(3), subject outputs gated when this function enabled. Enable gating outputs with COM_PWR_REQ (GPIO(9)) COM_STS (MPUIO(3)) input pins. Disables gating outputs with COM_PWR_REQ (GPIO(9)) COM_STS (MPUIO(3)) input pins. This function called Gated2 pinout document.
Notes:
This function been removed. Writing this register acceptable. However, recommended write case functions added this register space future.
SPRU752A
Initialization
OMAP5912 Configuration
Table
Functional Multiplexing Control Register (FUNC_MUX_CTRL_0) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x00
Name BVLZ_MASK_IN
Function This register enables Inhibit1 function. Depending status BVLZ input pin, subject inputs gated internally when this function enabled. Enables gating inputs with BVLZ input pin. Disables gating inputs with BVLZ input pin. This function called Inhibit1 pinout document.
Reset
BVLZ_MASK_OUT
This register enables Gated1 function. Depending status BVLZ, subject outputs gated when this function enabled. Enables gating outputs with BVLZ input pin. Disables gating outputs with BVLZ input pin. This function called Gated1 pinout document.
Notes:
BLUETOOTH CAMERA USB.CLK0 COM_SHUT GIGA_UART MEDIA_HIZ_DISABLE NFCS2 LB_HSAB_RHEA
Note Note Note Note Note Note Note Note Note
This function been removed. Writing this register acceptable. However, recommended write case functions added this register space future.
Initialization
SPRU752A
OMAP5912 Configuration
This register primarily controls legacy functional multiplexing. Many modes have been removed made more generic. When function been removed, noted register description.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_1)
Base Address 0xFFFE 1000, Offset Address 0x04 31:0 Name RESERVED Function Reserved Reset 0x0000
register functions have been removed. Writing this register acceptable. However, recommended write case functions added this register space future.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_2)
Base Address 0xFFFE 1000, Offset Address 0x08 31:28 27:24 Name RESERVED CONF_OBS_MUX_SEL_R Function Reserved Sets parallel observation multiplexing mode. These bits determine which observation multiplexing modes selected (See Section details). 23:19 CONF_DSP_DMA_REQ_ Maps DMA_REQUEST observability. configuration each observation mode specified (See Section 2.3). Observability request(i) done before crossbar. 18:13 CONF_ARM_DMA_SEL_ REQ31 Maps DMA_REQUEST observability. configuration each observation mode specified (See Section 2.3). Observability request(i) done before crossbar. 0x00 0x00 Reset
SPRU752A
Initialization
OMAP5912 Configuration
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_2)
Base Address 0xFFFE 1000, Offset Address 0x08 12:7 Name CONF_DSP_INT_SEL_R Function Select level interrupts observed. configuration each observation mode specified (See Section 2.3). Observing interrupts done after multiplexers that select between level edge activity. CONF_ARM_INT_SEL_R Select level interrupts observed. configuration each observation mode specified (See Section 2.3). Observing interrupts done after multiplexers that select between level edge activity. 0x00 Reset 0x00
Table Compatibility Mode Control Register (COMP_MODE_CTRL_0)
Base Address 0xFFFE 1000, Offset Address 0x0C 31:16 Name CONF_COMP_ RESERVED_R CONF_MUX_EN_R Function Reserved future expansion. These bits must written 0x0000h value 0xEAEF must written this register enable multiplexing controlled registers FUNC_MUX_CTRL (3-12), PU_PD_SEL(0-4), PULL_DWN_CTRL (0-4). boot code must configure multiplexing registers FUNC_MUX_CTRL (3-12), PU_PD_SEL(0-4), PULL_DWN_CTRL (0-4) first. Writing 0xEAEF enables multiplexing take effect simultaneously. Reset 0x0000
15:0
0x0000
This multiplex enable register. reset, value written registers FUNC_MUX_CTRL (3-12), PU_PD_SEL(0-4), PULL_DWN_CTRL (0-4) does change configuration pins. However, setting COMP_MODE_CTRL_0 register 0x0000EAEF activates:
Generic multiplexing registers: FUNC_MUX_CTRL_x, {3.12} Pullup/pulldown enable registers: PULL_DWN_CTRL_y, {0.4} Pullup/pulldown select registers: PU_PD_SEL_z, {0.4} Initialization SPRU752A
OMAP5912 Configuration
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_3)
Base Address 0xFFFE 1000, Offset Address 0x10 31:30 29:27 26:24 23:21 20:18 17:15 14:12 11:9 Name RESERVED CONF_F19 CONF_H14 CONF_E20 CONF_E19 CONF_F18 CONF_D20 CONF_D19 CONF_E18 CONF_C21 CONF_G19 Function Reserved future expansion Controls multiplexing F19. Formerly, CONF_KBR_1_R. Controls multiplexing H14. Formerly, CONF_KBR_2_R. Controls multiplexing E20. Formerly, CONF_KBR_3_R. Controls multiplexing E19. Formerly, CONF_KBR_4_R. Controls multiplexing F18. Formerly, CONF_KBC_0_R. Controls multiplexing D20. Formerly, CONF_KBC_1_R. Controls multiplexing D19. Formerly, CONF_KBC_2_R. Controls multiplexing E18. Formerly, CONF_KBC_3_R. Controls multiplexing C21. Formerly, CONF_KBC_4_R. Controls multiplexing G19. Formerly, CONF_KBC_5_R. Reset
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEFh this register control functional multiplexing. Table bit-field values.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_4)
Base Address 0xFFFE 1000, Offset Address 0x14 31:30 29:27 26:24 23:21 20:18 17:15 Name RESERVED CONF_J18 CONF_J15 CONF_H19 CONF_H20 CONF_H18 Function Reserved future expansion Controls multiplexing J18. Formerly CON_CAM_D_7_R. Controls multiplexing J15. Formerly CONF_CAM_LCLK_R. Controls multiplexing H19. Formerly CONF_CAMEXCLK_R. Controls multiplexing H20. Formerly CONF_MCBSP1_DIN_R. Controls multiplexing H18. Formerly CONF_MCBSP1_DOUT_R. Controls multiplexing H15. Formerly CONF_MCBSP1_SYNC_R. Reset
14:12
CONF_H15
SPRU752A
Initialization
OMAP5912 Configuration
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_4) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x14 11:9 Name CONF_G21 Function Controls multiplexing G21. Formerly CONF_MCBSP1_BCLK_R. Controls multiplexing G20. Formerly CONF_MCBSP1_CLKS_R. Reserved future expansion Controls multiplexing G18. Formerly CONF_KBR_0_R. Reset
CONF_G20
RESERVED CONF_G18
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEFh this register control functional multiplexing. Table field values.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_5)
Base Address 0xFFFE 1000, Offset Address 0x18 31:30 29:27 Name RESERVED CONF_M19 Function Reserved future expansion Controls multiplexing M19. Formerly, CONF_CAM_RSTZ_R. Controls multiplexing L15. Formerly, CONF_CAM_HS_R. Controls multiplexing L18. Formerly, CONF_CAM_VS_R. Controls multiplexing L19. Formerly, CONF_CAM_D_0_R. Controls multiplexing K14. Formerly, CONF_CAM_D_1_R. Controls multiplexing K15. Formerly, CONF_CAM_D_2_R. Controls multiplexing K19. Formerly, CONF_CAM_D_3_R. Controls multiplexing K18. Formerly, CONF_CAM_D_4_R. Controls multiplexing J14. Formerly, CONF_CAM_D_5_R. Controls multiplexing J19. Formerly, CONF_CAM_D_6_R. Reset
26:24 23:21 20:18 17:15 14:12 11:9
CONF_L15 CONF_L18 CONF_L19 CONF_K14 CONF_K15 CONF_K19 CONF_K18 CONF_J14 CONF_J19
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEFh this register control functional multiplexing. Table field values.
Initialization SPRU752A
OMAP5912 Configuration
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_6)
Base Address 0xFFFE 1000, Offset Address 0x1C 31:30 29:27 26:24 23:21 20:18 17:15 14:12 11:9 Name RESERVED CONF_P20 CONF_P19 CONF_M15 CONF_N20 CONF_N18 CONF_N19 CONF_N21 CONF_M20 CONF_L14 CONF_M18 Function Reserved future expansion Controls multiplexing P20. Formerly, CONF_GPIO_4_R. Controls multiplexing P19. Formerly, CONF_GPIO_6_R. Controls multiplexing M15. Formerly, CONF_GPIO_7_R. Controls multiplexing N20. Formerly, CONF_GPIO_11_R. Controls multiplexing N18. Formerly, CONF_GPIO_11_R. Controls multiplexing N19. Formerly, CONF_GPIO_11_R. Controls multiplexing N21. Formerly, CONF_GPIO_11_R. Controls multiplexing M20. Formerly, CONF_GPIO_11_R. Controls multiplexing L14. Formerly, CONF_RX3_R. Controls multiplexing M18. Formerly, CONF_TX3_R. Reset
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEFh this register control functional multiplexing. Table field values.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_7)
Base Address 0xFFFE 1000, Offset Address 0x20 31:30 29:27 26:24 23:21 20:18 17:15 14:12 11:9 Name RESERVED CONF_V20 CONF_T18 CONF_U19 CONF_N15 CONF_T19 CONF_T20 CONF_R18 Function Reserved future expansion Controls multiplexing V20. Formerly, CONF_SDA_R. Controls multiplexing T18. Formerly, CONF_SCL_R. Controls multiplexing U19. Formerly, CONF_ARMIO_1_R. Controls multiplexing N15. Formerly, CONF_ARMIO_2_R. Controls multiplexing T19. Formerly, CONF_ARMIO_4_R. Controls multiplexing T20. Formerly, CONF_ARMIO_5_R. Controls multiplexing R18. Formerly, CONF_GPIO_0_R. Reset
SPRU752A
Initialization
OMAP5912 Configuration
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_7) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x20 Name CONF_R19 CONF_M14 CONF_P18 Function Controls multiplexing R19. Formerly, CONF_GPIO_1_R. Controls multiplexing M14. Formerly, CONF_GPIO_2_R. Controls multiplexing P18. Formerly, CONF_GPIO_3_R. Reset
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEFh this register control functional multiplexing. Table field values.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_8)
Base Address 0xFFFE 1000, Offset Address 0x24 31:30 29:27 26:24 23:21 20:18 17:15 14:12 Name RESERVED CONF_J20 CONF_W17 CONF_V16 CONF_Y12 CONF_W19 CONF_P15 Function Reserved future expansion Controls multiplexing J20. Formerly, CONF_ARM_BOOT_R. Controls multiplexing W17. Formerly, CONF_NEMU1_R. Controls multiplexing V16. Formerly, CONF_NEMU0_R. Controls multiplexing Y12. Formerly, CONF_ON_OFF_R. Controls multiplexing W19. Formerly, CONF_BVLZ_R. Controls multiplexing P15. Formerly, CONF_WIRE_NSCS3_R. Controls multiplexing N14. Formerly, CONF_WIRE_NSCS0_R. Controls multiplexing V19. Formerly, CONF_WIRE_SCLK_R. Controls multiplexing W21. Formerly, CONF_WIRE_SDO_R. Controls multiplexing U18. Formerly, CONF_WIRE_SDI_R. Reset
11:9
CONF_N14
CONF_V19 CONF_W21 CONF_U18
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEFh this register control functional multiplexing. Table field values.
Initialization SPRU752A
OMAP5912 Configuration
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_9)
Base Address 0xFFFE 1000, Offset Address 0x28 31:30 29:27 Name RESERVED CONF_W15 Function Reserved future expansion Controls multiplexing W15. Formerly CONF_UARTS_CLKREQ_R. Controls multiplexing W14. Formerly CONF_MCSI1_DOUT_R. Controls multiplexing Y14. Formerly CONF_TX1_R. Controls multiplexing V14. Formerly CONF_RX1_R. Controls multiplexing R14. Formerly CONF_CTS1_R. Controls multiplexing AA15. Formerly CONF_RTS1_R. Controls multiplexing AA20. Formerly CONF_NRESET_OUT_R. Controls multiplexing U20. Formerly CONF_MPU_NRESET_R. Controls multiplexing W16. Formerly CONF_MCBSP3_CLK_R. Controls multiplexing W13. Formerly CONF_WAKEUP_INT_R. Reset
26:24
CONF_W14
23:21 20:18 17:15 14:12 11:9
CONF_Y14 CONF_V14 CONF_R14 CONF_AA15 CONF_AA20
CONF_U20
CONF_W16
CONF_W13
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEFh this register control functional multiplexing. Table field values.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_A)
Base Address 0xFFFE 1000, Offset Address 0x2C 31:30 29:27 26:24 23:21 20:18 Name RESERVED CONF_P11 CONF_V10 CONF_V11 CONF_W10 Function Reserved future expansion Controls multiplexing P11. Formerly CONF_MMC_CMD_R. Controls multiplexing V10. Formerly CONF_MMC_DAT1_R. Controls multiplexing V11. Formerly CONF_MMC_CLK_R. Controls multiplexing W10. Formerly CONF_MMC_DAT2_R. Reset
SPRU752A
Initialization
OMAP5912 Configuration
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_A) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x2C 17:15 14:12 11:9 Name CONF_P13 CONF_R13 CONF_V15 CONF_P14 CONF_AA17 CONF_Y15 Function Controls multiplexing P13. Formerly CONF_CLK32K_IN_R. Controls multiplexing R13. Formerly CONF_CLK32K_OUT_R. Controls multiplexing V15. Formerly CONF_MCSI1_DIN_R. Controls multiplexing P14. Formerly CONF_MCSI1_BCLK_R. Controls multiplexing AA17. Formerly CONF_MCSI1_SYNC_R. Controls multiplexing Y15. Formerly CONF_BCLK_R. Reset
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEFh this register control functional multiplexing. Table field values.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_B)
Base Address 0xFFFE 1000, Offset Address 0x30 31:30 29:27 26:24 23:21 20:18 Name RESERVED CONF_V8 CONF_Y8 CONF_W8 CONF_R10 Function Reserved future expansion Controls multiplexing Formerly CONF_ARMIO_3_R. Controls multiplexing Formerly CONF_GPIO_8_R. Controls multiplexing Formerly CONF_GPIO_9_R. Controls multiplexing R10. Formerly CONF_COM_MCLK_REQ_R. Controls multiplexing Formerly CONF_COM_MCLK_OUT_R. Controls multiplexing Formerly CONF_MCSI2_SYNC_R. Controls multiplexing Formerly CONF_MCSI2_DOUT_R. Controls multiplexing AA9. Formerly CONF_MCSI2_DIN_R. Controls multiplexing Y10. Formerly CONF_MCSI2_CLK_R. Controls multiplexing R11. Formerly CONF_MMC_DAT0_R. Reset
17:15
CONF_V5
14:12 11:9
CONF_V9 CONF_W9 CONF_AA9 CONF_Y10 CONF_R11
Initialization
SPRU752A
OMAP5912 Configuration
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEFh this register control functional multiplexing. Table field values.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_C)
Base Address 0xFFFE 1000, Offset Address 0x34 31:30 29:27 26:24 23:21 20:18 17:15 Name RESERVED CONF_V6 CONF_W5 CONF_Y5 CONF_R9 CONF_AA5 Function Reserved future expansion Controls multiplexing Formerly CONF_TX2_R. Controls multiplexing Formerly CONF_RTS2_R. Controls multiplexing Formerly CONF_CTS2_R. Controls multiplexing Formerly CONF_RX2_R. Controls multiplexing AA5. Formerly CONF_MCBSP2_DOUT_R. Controls multiplexing Formerly CONF_MCBSP2_RSYNC_R. Controls multiplexing Formerly CONF_MCBSP2_CLKX_R. Controls multiplexing Formerly CONF_MCBSP2_CLKR_R. Controls multiplexing Formerly CONF_MCBSP2_XSYNC_R. Controls multiplexing P10. Formerly CONF_MCBSP2_DIN_R. Reset
14:12
CONF_W6
11:9
CONF_Y6 CONF_V7 CONF_W7
CONF_P10
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEFh this register control functional multiplexing. Table field values.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_D)
Base Address 0xFFFE 1000, Offset Address 0x38 31:30 29:27 26:24 23:21 Name RESERVED CONF_G13 CONF_A17 CONF_C16 Function Reserved future expansion Controls multiplexing G13. Formerly CONF_LCD_PIXEL_12_R. Controls multiplexing A17. Formerly CONF_LCD_PIXEL_13_R. Controls multiplexing C16. Formerly CONF_LCD_PIXEL_14_R. Reset
SPRU752A
Initialization
OMAP5912 Configuration
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_D) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x38 20:18 17:15 14:12 11:9 Name CONF_D15 CONF_C15 CONF_C20 CONF_B15 CONF_M4 CONF_W4 CONF_Y4 Function Controls multiplexing D15. Formerly CONF_LCD_PIXEL_15_R. Controls multiplexing C15. Formerly CONF_LCD_PCLK_R. Controls multiplexing C20. Formerly CONF_LDC_HSYNC_R. Controls multiplexing B15. Formerly CONF_LCD_AC_R. Controls multiplexing Formerly CONF_NFCS2_R. Controls multiplexing Formerly CONF_USB_PUEN_R. Controls multiplexing Formerly CONF_BDCLK2_R. Reset
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEFh this register control functional multiplexing. Table field values.
Table Pulldown Control Register (PULL_DWN_CTRL_0)
Base Address 0xFFFE 1000, Offset Address 0x40 Name CONF_PDEN_L14 CONF_PDEN_M18 CONF_PDEN_M19 CONF_PDEN_L15 CONF_PDEN_L18 CONF_PDEN_L19 CONF_PDEN_K14 CONF_PDEN_K15 CONF_PDEN_K19 CONF_PDEN_K18 CONF_PDEN_J14 CONF_PDEN_J19 Function Enables pullup pulldown L14. Enables pullup pulldown M18. Enables pullup pulldown M19. Enables pullup pulldown L15. Enables pullup pulldown L18. Enables pullup pulldown L19. Enables pullup pulldown K14. Enables pullup pulldown K15. Enables pullup pulldown K19. Enables pullup pulldown K18. Enables pullup pulldown J14. Enables pullup pulldown J19. Reset
Initialization
SPRU752A
OMAP5912 Configuration
Table Pulldown Control Register (PULL_DWN_CTRL_0) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x40 Name CONF_PDEN_J18 CONF_PDEN_J15 CONF_PDEN_H19 CONF_PDEN_H20 CONF_PDEN_H18 CONF_PDEN_H15 CONF_PDEN_G21 CONF_PDEN_G20 RESERVED CONF_PDEN_G18 CONF_PDEN_F19 CONF_PDEN_H14 CONF_PDEN_E20 CONF_PDEN_E19 CONF_PDEN_F18 CONF_PDEN_D20 CONF_PDEN_D19 CONF_PDEN_E18 CONF_PDEN_C21 CONF_PDEN_G19 Function Enables pullup pulldown J18. Enables pullup pulldown J15. Enables pullup pulldown H19. Enables pullup pulldown H20. Enables pullup pulldown H18. Enables pullup pulldown H15. Enables pullup pulldown G21. Enables pullup pulldown G20. Reserved future expansion Enables pullup pulldown G18. Enables pullup pulldown F19. Enables pullup pulldown H14. Enables pullup pulldown E20. Enables pullup pulldown E19. Enables pullup pulldown F18. Enables pullup pulldown D20. Enables pullup pulldown D19. Enables pullup pulldown E18. Enables pullup pulldown C21. Enables pullup pulldown G19. Reset
This register controls enable disable combined pullup/pulldown cell enabled, disabled). When enabling cell, user must corresponding PU_PD_SEL_0 select either pullup pulldown. pinout documentation must consulted determine whether pullup pulldown exists specified I/O. COMP_MODE_CTRL_0 must programmed 0xEAEF that programming taken into account corresponding tactical cell.
SPRU752A Initialization
OMAP5912 Configuration
Table Pulldown Control Register (PULL_DWN_CTRL_1)
Base Address 0xFFFE 1000, Offset Address 0x44 Name CONF_PDEN_AA20 CONF_PDEN_U20 CONF_PDEN_W16 CONF_PDEN_W13 CONF_PDEN_J20 CONF_PDEN_W17 CONF_PDEN_V16 CONF_PDEN_Y12 CONF_PDEN_W19 CONF_PDEN_P15 CONF_PDEN_N14 CONF_PDEN_V19 CONF_PDEN_W21 CONF_PDEN_U18 Reserved Reserved CONF_PDEN_U19 CONF_PDEN_N15 CONF_PDEN_T19 CONF_PDEN_T20 CONF_PDEN_R18 CONF_PDEN_R19 CONF_PDEN_M14 CONF_PDEN_P18 CONF_PDEN_P20 Function Enables pullup pulldown AA20. Enables pullup pulldown U20. Enables pullup pulldown W16. Enables pullup pulldown W13. Enables pullup pulldown J20. Enables pullup pulldown W17. Enables pullup pulldown V16. Enables pullup pulldown Y12. Enables pullup pulldown W19. Enables pullup pulldown P15. Enables pullup pulldown N14. Enables pullup pulldown V19. Enables pullup pulldown W21. Enables pullup pulldown U18. Reserved Reserved Enables pullup pulldown U19. Enables pullup pulldown N15. Enables pullup pulldown T19. Enables pullup pulldown T20. Enables pullup pulldown R18. Enables pullup pulldown R19. Enables pullup pulldown M14. Enables pullup pulldown P18. Enables pullup pulldown P20. Reset
Initialization
SPRU752A
OMAP5912 Configuration
Table Pulldown Control Register (PULL_DWN_CTRL_1) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x44 Name CONF_PDEN_P19 CONF_PDEN_M15 CONF_PDEN_N20 CONF_PDEN_N18 CONF_PDEN_N19 CONF_PDEN_N21 CONF_PDEN_M20 Function Enables pullup pulldown P19. Enables pullup pulldown M15. Enables pullup pulldown N20. Enables pullup pulldown N18. Enables pullup pulldown N19. Enables pullup pulldown N21. Enables pullup pulldown M20. Reset
This register controls enable disable combined pullup/pulldown cell enabled, disabled). When enabling cell, user must corresponding PU_PD_SEL_1 select either pullup pulldown. pinout documentation must consulted determine whether pullup pulldown exists specified I/O. COMP_MODE_CTRL_0 must programmed 0xEAEF that programming taken into account corresponding tactical cell.
Table Pulldown Control Register (PULL_DWN_CTRL_2)
Base Address 0xFFFE 1000, Offset Address 0x48 Name CONF_PDEN_AA5 CONF_PDEN_W6 CONF_PDEN_Y6 CONF_PDEN_V7 CONF_PDEN_W7 CONF_PDEN_P10 CONF_PDEN_V8 CONF_PDEN_Y8 CONF_PDEN_W8 CONF_PDEN_R10 Function Enables pullup pulldown AA5. Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown P10. Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown R10. Reset
SPRU752A
Initialization
OMAP5912 Configuration
Table Pulldown Control Register (PULL_DWN_CTRL_2) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x48 Name CONF_PDEN_V5 CONF_PDEN_V9 CONF_PDEN_W9 CONF_PDEN_AA9 CONF_PDEN_Y10 CONF_PDEN_R11 CONF_PDEN_P11 CONF_PDEN_V10 CONF_PDEN_V11 CONF_PDEN_W10 CONF_PDEN_P13 CONF_PDEN_R13 CONF_PDEN_V15 CONF_PDEN_P14 CONF_PDEN_AA17 CONF_PDEN_Y15 CONF_PDEN_W15 CONF_PDEN_W14 CONF_PDEN_Y14 CONF_PDEN_V14 CONF_PDEN_R14 CONF_PDEN_AA15 Function Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown AA9. Enables pullup pulldown Y10. Enables pullup pulldown R11. Enables pullup pulldown P11. Enables pullup pulldown V10. Enables pullup pulldown V11. Enables pullup pulldown W10. Enables pullup pulldown P13. Enables pullup pulldown R13. Enables pullup pulldown V15. Enables pullup pulldown P14. Enables pullup pulldown AA17. Enables pullup pulldown Y15. Enables pullup pulldown W15. Enables pullup pulldown W14. Enables pullup pulldown Y14. Enables pullup pulldown V14. Enables pullup pulldown R14. Enables pullup pulldown AA15. Reset
Initialization
SPRU752A
OMAP5912 Configuration
This register controls enable disable combined pullup/pulldown cell enabled, disabled). When enabling cell, user must corresponding PU_PD_SEL_2 select either pullup pulldown. pinout documentation must consulted determine whether pullup pulldown exists specified I/O. COMP_MODE_CTRL_0 must programmed 0xEAEF that programming taken into account corresponding tactical cell.
Table Pulldown Control Register (PULL_DWN_CTRL_3)
Base Address 0xFFFE 1000, Offset Address 0x4C Name CONF_PDEN_W2 CONF_PDEN_V4 CONF_PDEN_Y1 CONF_PDEN_Y17 CONF_PDEN_D18 CONF_PDEN_B21 CONF_PDEN_C19 CONF_PDEN_G14 CONF_PDEN_H13 CONF_PDEN_A20 CONF_PDEN_B19 CONF_PDEN_C18 Reserved CONF_PDEN_D17 CONF_PDEN_D16 CONF_PDEN_C17 CONF_PDEN_B17 CONF_PDEN_G13 CONF_PDEN_A17 CONF_PDEN_C16 Function Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Y17. Enables pullup pulldown D18. Enables pullup pulldown B21. Enables pullup pulldown C19. Enables pullup pulldown G14. Enables pullup pulldown H13. Enables pullup pulldown A20. Enables pullup pulldown B19. Enables pullup pulldown C18. Reserved Enables pullup pulldown D17. Enables pullup pulldown D16. Enables pullup pulldown C17. Enables pullup pulldown B17. Enables pullup pulldown G13. Enables pullup pulldown A17. Enables pullup pulldown C16. Reset
SPRU752A
Initialization
OMAP5912 Configuration
Table Pulldown Control Register (PULL_DWN_CTRL_3) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x4C Name CONF_PDEN_D15 Reserved Reserved CONF_PDEN_W11 Reserved CONF_PDEN_M4 CONF_PDEN_W4 CONF_PDEN_Y4 CONF_PDEN_V6 CONF_PDEN_W5 CONF_PDEN_Y5 CONF_PDEN_R9 Function Enables pullup pulldown D15. Reserved Reserved Enables pullup pulldown W11. Reserved Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Reset
This register controls enable disable combined pullup/pulldown cell enabled, disabled). When enabling cell, assumed that user cleared corresponding PU_PD_SEL_3 select pullup pulldown. pinout chapter should consulted determine whether pullup pulldown exists specified I/O. COMP_MODE_CTRL_0 must programmed 0xEAEF that programming taken into account corresponding tactical cell.
Table Gate Inhibit Control Register (GATE_INH_CTRL_0)
Base Address 0xFFFE 1000, Offset Address 0x50 31:6 Name CONF_GATE_INH_ RESERVED RESERVED1 RESERVED Function Reserved future expansion Reset 0x0000000
Reserved future expansion Reserved future expansion
Initialization
SPRU752A
OMAP5912 Configuration
Table Gate Inhibit Control Register (GATE_INH_CTRL_0) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x50 Name CONF_HIGH_IMP3 Function Controls high impedance MCSI1.DOUT. Normal function Hi-Z CONF_SOFTWARE_PWR Controls software gating inhibiting I/O, which gated inhibited COM_PWR status. gating inhibiting logic enabled FUNC_MUX_CTRL_0 bits) CONF_SOFTWARE_GATE_ENA_R this controls com_pwr gating inhibiting, instead device pins. CONF_SOFTWARE_BVLZ This controls software gating inhibiting I/O, which gated inhibited BFAIL/EXT_FIQ signal. gating inhibiting logic enabled FUNC_MUX_CTRL_0(10 -13)bits CONF_SOFTWARE_GATE_ENA_R this controls BFAIL/EXT_FIQ gating inhibiting, instead device pins. CONF_SOFTWARE_GATE _ENA_R This controls software gating I/O, which gated inhibited. gating inhibiting logic enabled FUNC_MUX_CTRL_0(10 -13) bits, software enabled control gating inhibiting, instead device pins. Reset
This register controls software gating inhibiting functionality device. pinout chapter Appendix should consulted understand which pins affected Gated1, Gated2, Inhibit1, Inhibit2 functions device.
SPRU752A
Initialization
OMAP5912 Configuration
Table Configuration Revision Register (CONF_REV)
Base Address 0xFFFE 1000, Offset Address 0x58 31:8 Name CONF_REV_RESERVED CONF_REV_R Function Reserved future expansion This 8-bit field indicates revision number current module. This value fixed hardware. 4-bit LSBs indicate minor revision. 4-bit MSBs indicate major revision. Example: 0x10 Version Reset effect value returned. Reset 0x000000 0x10
This read-only register that contains revision number module. write this register effect.
Table Voltage Control Register (VOLTAGE_CTRL_0)
Base Address 0xFFFE 1000, Offset Address 0x60 31:14 Name CONF_VOLTAGE_ RESERVED SUBLVDS_CONF_VALID_ Function Reserved future expansion Reset 0x00000
This protects cells comparator after reset, regardless VDDS level (either This when configuration voltage domains valid. Setting this before valid values voltage domains configuration bits, damage 1.8-V transistors cell. Differential comparators protected. CMOS function differential comparator selected. differential comparator must selected only corresponding voltage domains VDDS equal
EMIFS EMIFF 3.0-V 3.3-V operation, 2.75V setting. Note: description 1.8-V 2.75-V nominal voltage ranges OMAP1610 Data Manual (SWPS012).
Initialization
SPRU752A
OMAP5912 Configuration
Table Voltage Control Register (VOLTAGE_CTRL_0) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x60 Name CONF_VOLTAGE_RTC_R Function This controls drive strength DVDD10 voltage domain. controls low/high voltage mode. voltage range supported defined pinout document. Low-voltage mode drive strength nominal (nominal 1.80-V range). Interface high-voltage mode drive strength (nominal 2.75-V range). CONF_VOLTAGE_ VDDSHV9_R This controls drive strength DVDD9 voltage domain. controls low/high voltage mode. voltage range supported defined pinout document. Low-voltage mode drive strength nomina (nominal 1.80-V range). Interface high-voltage mode drive strength (nominal 2.75-V range). CONF_VOLTAGE_ VDDSHV8_R This controls drive strength DVDD8 voltage domain. controls low/high voltage mode. voltage range supported defined pinout document. Low-voltage mode drive strength nominal (nominal 1.80-V range). Interface high-voltage mode drive strength (nominal 2.75-V range). CONF_VOLTAGE_ VDDHSV7_R This controls drive strength DVDD7 voltage domain. controls low/high voltage mode. voltage range supported defined pinout document. Low-voltage mode drive strength nominal (nominal 1.80-V range). Interface high-voltage mode drive strength (nominal 2.75-V range).
EMIFS EMIFF 3.0-V 3.3-V operation, 2.75V setting. Note: description 1.8-V 2.75-V nominal voltage ranges OMAP1610 Data Manual (SWPS012).
Reset
SPRU752A
Initialization
OMAP5912 Configuration
Table Voltage Control Register (VOLTAGE_CTRL_0) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x60 Name CONF_VOLTAGE_ VDDHSV6_R Function This controls drive strength DVDD6 voltage domain. controls low/high voltage mode. voltage range supported defined pinout document. Low-voltage mode drive strength nominal (nominal 1.80-V range). Interface high-voltage mode drive strength (nominal 2.75-V range). CONF_VOLTAGE_ VDDSHV2_R This controls drive strength DVDD2 voltage domain. controls low/high voltage mode. voltage range supported defined pinout document. Low-voltage mode drive strength nominal (nominal 1.80-V range). Interface high-voltage mode drive strength (nominal 2.75-V range). CONF_VOLTAGE_ VDDSHV1_R This controls drive strength DVDD1 voltage domain. controls low/high voltage mode. voltage range supported defined pinout document. Low-voltage mode drive strength nominal (nominal 1.80-V range). Interface high-voltage mode drive strength (nominal 2.75-V range). RESERVED1 Reserved potential low-power operation control Reserved potential low-power operation control Reserved potential low-power operation control Reset
RESERVED2
RESERVED
EMIFS EMIFF 3.0-V 3.3-V operation, 2.75V setting. Note: description 1.8-V 2.75-V nominal voltage ranges OMAP1610 Data Manual (SWPS012).
Initialization
SPRU752A
OMAP5912 Configuration
Table Voltage Control Register (VOLTAGE_CTRL_0) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x60 Name CONF_VOLTAGE_ COMIF_R Function This controls drive strength DVDD3 communication processor interface voltage domain. controls low/high voltage mode. voltage range defined pinout document. Low-voltage mode drive strength nominal (nominal 1.80-V range). Interface high-voltage mode drive strength (nominal 2.75-V range). CONF_VOLTAGE_ SDRAM_R This controls drive strength DVDD4 SDRAM interface voltage domain. controls low/high voltage mode. voltage range supported defined pinout document. Low-voltage mode drive strength nominal (nominal 1.80-V range). Interface high-voltage mode drive strength (nominal 2.75-V range). CONF_VOLTAGE_ FLASH_R This controls drive strength DVDD5 flash interface voltage domain. controls low/high voltage mode. voltage range supported defined pinout document. Low-voltage mode drive strength nominal (nominal 1.80-V range). Interface high-voltage mode drive strength (nominal 2.75-V range).
EMIFS EMIFF 3.0-V 3.3-V operation, 2.75V setting. Note: description 1.8-V 2.75-V nominal voltage ranges OMAP1610 Data Manual (SWPS012).
Reset
SPRU752A
Initialization
OMAP5912 Configuration
This register controls low- high-voltage mode each power supply domain. Low-voltage mode defined 1.8-V range, high-voltage mode defined 2.75-V range. exact voltage ranges supported interfaces device specified OMAP1610 Data Manual (SWPS012). After reset, device interfaces configured low-voltage mode, software must adjust programming this register match actual voltages applied each power supply domain. effect applying 2.75 while interface low-voltage mode, example, simply that faster more powerful than usually required.
Table Transceiver Control Register (USB_TRANSCEIVER_CTRL)
Base Address 0xFFFE 1000, Offset Address 0x64 31:9 Name UNUSED CONF_USB2_UNI_R Function These bits implemented. This configures port interfaces with external transceiver. Bidirectional mode USB2.SE0 bidirectional I/O, rather than output only. Input USB2.SE0 bidirectional connected usb2_vm port module. USB2.TXD bidirectional I/O, ratther than output only. Input USB2.TXD bidirectional connected USB2.VP port module. Unidirectional mode Reset 0x000000
Initialization
SPRU752A
OMAP5912 Configuration
Table Transceiver Control Register (USB_TRANSCEIVER_CTRL) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x64 Name CONF_USB1_UNI_R Function This configures port interfaces with external transceiver. Bidirectional mode USB1.SE0 bidirectional I/O, rather than output only. Input USB1.SE0 bidirectional connected USB1.VM port module. USB1.TXD bidirectional I/O, rather than output only. Input USB1.TXD bidirectional connected USB1.VP port module. Unidirectional mode CONF_USB_PORT0_R These bits control themultiplexing I/O, which defaults USB.DP USB.DM reset. These bits configure port alternate operation. COMP_MODE_CTRL_0 must programmed 0xEAEF this register control functional multiplexing. 000: USB.DP/USB.DM 100: I2C.SDA/I2C.SCl 101: UART1.RX/UART1.TX 111: USB2.PUEN/HI-Z Other values allowed. Programming this field some other value produces unpredictable results. CONF_USB0_ISOLATE_R Isolates port controller from integrated transceiver. Normal mode Isolation mode Reset
SPRU752A
Initialization
OMAP5912 Configuration
Table Transceiver Control Register (USB_TRANSCEIVER_CTRL) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x64 Name CONF_USB_PWRDN_DM Function Enable/disable pulldown Enable pulldown Disable pulldown Reset
CONF_USB_PWRDN_DP_ Enable/disable pulldown Enable pulldown Disable pulldown RESERVED Reserved future expansion
Table Powerdown Control Register (LDO_PWRDN_CNTRL)
Base Address 0xFFFE 1000, Offset Address 0x68 31:1 Name UNUSED CONF_LDO_PWRDN_ CNTRL_R Function These bits implemented. user sets LDO_PWRDN powered-down bypassed. Reset 0x00000000
This 1-bit register bypasses LDO.
Table Test Debug Control Register (TEST_DBG_CTRL_0)
Base Address 0xFFFE 1000, Offset Address 0x70 31:22 Name CONF_TEST_DBG_ RESERVED CONF_RNG_TEST_OSC CONF_RNG_SELECT_ CONF_DSP_BRTE_ WRITE_R CONF_DSP_BRTE_ READ_R Function Reserved future expansion Reset 0x0000
Ring oscillator divider enable Ring oscillator selection characterization Active high WRITE signal control BRTE memories READ signal control BRTE memories
Initialization
SPRU752A
OMAP5912 Configuration
Table Test Debug Control Register (TEST_DBG_CTRL_0) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x70 17:8 Name CONF_TDBG_RESERVED CONF_TEST_DBG_ RESERVED1 Function These reserved test debug bits device. They must times avoid errant behavior. Reserved future expansion Reset 0x000
CONF_TEST_VBUS_CELL This tests UIS480 VBUS detect cell. When output VBUS detect logic outputs CONF_DPLL_EXT_SEL This selects between internal 48-MHz clock generated APLL external 48-MHz clock source. When this GPIO14 becomes source device. OMAP VBOX test enable. This register must enable writing fields CONF_VBOX1 CONF_VBOX2, CONF_DSP_BRTE_READ_R, CONF_DSP_BRTE_WRITE_R. OMAP VBOX WRITE signal control BRTE memories OMAP VBOX READ signal control BRTE memories
CONF_VBOX_EN
CONF_VBOX2
CONF_VBOX1
SPRU752A
Initialization
OMAP5912 Configuration
Table Module Configuration Control Register (MOD_CONF_CTRL_0)
Base Address 0xFFFE 1000, Offset Address 0x80 Name CONF_MOD_UART3_CLK _MODE_R Function This determines 48-MHz clock request UART3. 48-MHz clock request inactive. 48-MHz clock request active. CONF_MOD_UART2_CLK _MODE_R This determines clock source UART2. UART_MCLKO from ULPD that either system clock kHz, depending system state ULPD register programming. CONF_MOD_UART1_CLK _MODE_R This determines whether 48-MHz clock request UART1 active. 48-MHz clock request inactive. 48-MHz clock request active. 27:24 RESERVED MOD_32KOSC_SW_R CONF_MOD_MMC_SD_ CLK_REQ_R Note Note This functional 48-MHz clock request MMCSDIO1 interface. This resets This corresponds MMCSDIO1 clock being requested. user must request clock MMCSDIO1 interface. CONF_MOD_DPRAM_ ENABLE_R CONF_MOD_MSMMC_ VSS_HIZ_OVERRIDE CONF_MOD_MMC_SD2_ CLK_REQ_R Note Reset
Note
This functional 48-MHz clock request device MMC/SD interface. This resets This corresponds MMC/SD clock being requested. user must request clock MMC/SD interface.
Notes:
This function been removed. Writing this register acceptable. However, recommended write case functions added this register space future.
Initialization
SPRU752A
OMAP5912 Configuration
Table Module Configuration Control Register (MOD_CONF_CTRL_0) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x80 Name CONF_MOD_MCBSP3_ CLK_SEL_R Function This determines method frame sync wrap-around used MCBSP3. Wrap-around done hardware external McBSP pins mode). Wrap-around disabled. Wrap-around performed within McBSP module pins mode). This also selects Interface clock used McBSP3 module: DSPXOR_CLK selected. DSPPER_CLK selected. CONF_MOD_MCBSP1_ CLKS_SEL_R This register selects clock used McBSP1 clocks input: McBSP1.CLKS device OMAP DPLL1 clockout CONF_MOD_USB_W2FC_ This determines method used VBUS_MODE_R VBUS detection. VBUS detection controlled GPIO_0 state muxed mode VBUS detection controlled DVDD2 detection line. CONF_MOD_I2C_SELECT Note CONF_MOD_UART3_ IRDA_MODE_R CONF_MOD_MCBSP1_ CLK_SEL_R Note Reset
This register selects clock used McBSP1 module: DSPXOR_CLK selected. DSPPER_CLK selected.
Notes:
This function been removed. Writing this register acceptable. However, recommended write case functions added this register space future.
SPRU752A
Initialization
OMAP5912 Configuration
Table Module Configuration Control Register (MOD_CONF_CTRL_0) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x80 Name Function Reset
CONF_MOD_MMC2_CLK_ This register selects clock used SEL_R MMC/SD2 module: 48-MHz MMC2_DPLL_CLK from ULPD ARM_XOR_CLK from OMAP clock module
CONF_MOD_COM_MCLK _12_48_SEL_R
This determines whether MCLK device outputs system clock 48-MHz clock (selection must accordance ULPD IO_CTRL). MCLK system clock. MCLK 48-MHz clock divided down).
CONF_MOD_USB_HOST_ UART_SELECT_R
Disables UART multiplexing port Enables UART multiplexing port
CONF_MOD_USB_HOST_ LB_ARB_EN_R CONF_MOD_USB_HOST_ HHC_UHOST_EN_R
used currently
Enable input functional-mode clocking USB_HHC. Internal functional mode 48-MHz 12-MHz clocks disabled. USB_HHC cannot function host. Internal functional mode 48-MHz 12-MHz clocks enabled.
Notes:
This function been removed. Writing this register acceptable. However, recommended write case functions added this register space future.
Initialization
SPRU752A
OMAP5912 Configuration
Table Module Configuration Control Register (MOD_CONF_CTRL_0) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x80 Name CONF_MOD_USB_HOST_ HMC_TLL_SPEED_R Function Transceiverless link logic (TLL) speed control. modes defined HMC_MODE_I HMC_JTAG_EN_I) where used, this determines whether modeling device pullup resistor internal internal signal. pullup modeled only when HMC_TLL_ATTACH_I active. This signal ignored when either device driving data, whenever HMC_MODE HMC_JTAG_EN_I specify that being used. When HMC_TLL_ATTACH_I high enabled neither host external device attempts drive, pullup modeled signal indicate low-speed device. When HMC_TLL_ATTACH_I high enabled neither host external device attempts drive, pullup modeled signal indicate full-speed device.
Notes: This function been removed. Writing this register acceptable. However, recommended write case functions added this register space future.
Reset
SPRU752A
Initialization
OMAP5912 Configuration
Table Module Configuration Control Register (MOD_CONF_CTRL_0) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x80 Name CONF_MOD_USB_HOST_ HMC_TLL_ATTACH_R Function Transceiverless link logic (TLL) attach control. modes defined HMC_MODE_I HMC_JTAG_EN_I) where used, this determines whether models internal representation differential data signals with without pullup when neither internal host external device attempting drive signals. This signal ignored when either device driving data. When neither host external device attempts drive, pullup modeled. associated host port interprets this device attached. When neither host external device attempts drive, pullup modeled either internal representation associated host port interprets this attached device with idle condition. CONF_MOD_USB_HOST_ HMC_MODE_R USB_HHC port multiplexing control. This resets following configuration. 000000b: port controlled USB_W2FC, ports held benign states. CONF_MOD_USB_HOST_ EXTCLKENI_R Note Reset
Notes:
This function been removed. Writing this register acceptable. However, recommended write case functions added this register space future.
Initialization
SPRU752A
OMAP5912 Configuration
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_E)
Base Address 0xFFFE 1000, Offset Address 0x90 31:30 29:27 Name RESERVED CONF_G14 Function Reserved future expansion. Controls multiplexing G14. Formerly CONF_LCD_PIXEL_3_R. Controls multiplexing H13. Formerly CONF_LCD_PIXEL_4_R. Controls multiplexing A20. Formerly CONF_LCD_PIXEL_5_R. Controls multiplexing B19. Formerly CONF_LCD_PIXEL_6_R. Controls multiplexing C18. Formerly CONF_LCD_PIXEL_7_R. Controls multiplexing D17. Formerly CONF_LCD_PIXEL_8_R. Controls multiplexing B18. Formerly CONF_LCD_VSYNC_R. Controls multiplexing D16. Formerly CONF_LCD_PIXEL_9_R. Controls multiplexing C17. Formerly CONF_LCD_ PIXEL_10_R. Controls multiplexing B17. Formerly CONF_LCD_ PIXEL_11_R. Reset
26:24
CONF_H13
23:21
CONF_A20
20:18
CONF_B19
17:15
CONF_C18
14:12
CONF_D17
11:9
CONF_B18 CONF_D16
CONF_C17
CONF_B17
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEF this register control functional multiplexing. Table bit-field values.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_F)
Base Address 0xFFFE 1000, Offset Address 0x94 31:30 29:27 26:24 Name RESERVED CONF_V2 CONF_U4 Function Reserved future expansion Controls multiplexing Formerly CONF_FRDY_R. Controls multiplexing Formerly CONF_NFOE_R. Reset
SPRU752A
Initialization
OMAP5912 Configuration
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_F) (Continued)
Base Address 0xFFFE 1000, Offset Address 0x94 23:21 20:18 17:15 14:12 11:9 Name CONF_W1 CONF_W2 CONF_V4 CONF_Y1 CONF_Y17 CONF_D18 CONF_B21 CONF_C19 Function Controls multiplexing Formerly CONF_NFRP_R. Controls multiplexing Formerly CONF_NFWE_R. Controls multiplexing Formerly CONF_NFWP_R. Controls multiplexing Formerly CONF_NFCS_1B_R. Controls multiplexing Y17. Formerly CONF_RTCK_R. Controls multiplexing D18. Formerly CONF_LCD_PIXEL_0_R. Controls multiplexing B21. Formerly CONF_LCD_PIXEL_1_R. Controls multiplexing C19. Formerly CONF_LCD_PIXEL_2_R. Reset
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEF this register control functional multiplexing. Table bit-field values.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_10)
Base Address 0xFFFE 1000, Offset Address 0x98 31:30 29:27 26:24 23:21 20:18 17:15 14:12 Name RESERVED CONF_M3 CONF_N8 CONF_N3 CONF_P3 CONF_W11 RESERVED CONF_L4 CONF_L3 CONF_M8 CONF_M7 Function Reserved future expansion Controls multiplexing Formerly CONF_NFCS_1_R. Controls multiplexing Formerly CONF_NFCS_3_R. Controls multiplexing Formerly CONF_FCLK_R. Controls multiplexing Formerly CONF_NFCS_2B_R. Controls multiplexing W11. Formerly CONF_MMC_DAT3_R. These reserved bits allow future expansion. Reset
11:9
Controls multiplexing Formerly CONF_NFADV_R. Controls multiplexing Formerly CONF_NFBE_0_R. Controls multiplexing Formerly CONF_NFBE_1_R. Controls multiplexing Formerly CONF_GPIO_1_R.
Initialization
SPRU752A
OMAP5912 Configuration
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEF this register control functional multiplexing. Table bit-field values.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_11)
Base Address 0xFFFE 1000, Offset Address 0x9C 31:30 29:27 26:24 23:21 20:18 17:15 14:12 11:9 Name RESERVED RESERVED CONF_F3 CONF_G4 CONF_G3 CONF_G2 CONF_K8 CONF_H4 CONF_H3 CONF_K7 RESERVED Function Reserved future expansion Reserved future expansion Controls multiplexing Formerly CONF_FADD_9_R. Controls multiplexing Formerly CONF_FADD_10_R. Controls multiplexing Formerly CONF_FADD_11_R. Controls multiplexing Formerly CONF_FADD_12_R. Controls multiplexing Formerly CONF_FADD_13_R. Controls multiplexing Formerly CONF_FADD_14_R. Controls multiplexing Formerly CONF_FADD_15_R. Controls multiplexing Formerly CONF_FADD_16_R. Reserved future expansion Reset
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEF this register control functional multiplexing. Table bit-field values.
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_12)
Base Address 0xFFFE 1000, Offset Address 0xA0 31:30 29:27 26:24 23:21 20:18 17:15 Name RESERVED RESERVED CONF_J8 CONF_D3 CONF_C1 CONF_E4 Function Reserved future expansion Reserved future expansion Controls multiplexing Formerly CONF_FADD_1_R. Controls multiplexing Formerly CONF_FADD_2_R. Controls multiplexing Formerly CONF_FADD_3_R. Controls multiplexing Formerly CONF_FADD_4_R. Reset
SPRU752A
Initialization
OMAP5912 Configuration
Table Functional Multiplexing Control Register (FUNC_MUX_CTRL_12) (Continued)
Base Address 0xFFFE 1000, Offset Address 0xA0 14:12 11:9 Name CONF_D2 CONF_F4 CONF_E3 CONF_J7 RESERVED Function Controls multiplexing Formerly CONF_FADD_5_R. Controls multiplexing Formerly CONF_FADD_6_R. Controls multiplexing Formerly CONF_FADD_7_R. Controls multiplexing Formerly CONF_FADD_8_R. Reserved future expansion Reset
This register controls functional multiplexing. COMP_MODE_CTRL_0 must programmed 0xEAEF this register control functional multiplexing. Table bit-field values.
Table Pulldown Control Register (PULL_DWN_CTRL_4)
Base Address 0xFFFE 1000, Offset Address 0xAC Name CONF_PDEN_Y18 CONF_PDEN_W18 CONF_PDEN_V17 CONF_PDEN_Y19 CONF_PDEN_V18 CONF_PDEN_L3 CONF_PDEN_M8 CONF_PDEN_M7 CONF_PDEN_M3 CONF_PDEN_N8 CONF_PDEN_N3 CONF_PDEN_J8 CONF_PDEN_D3 CONF_PDEN_C1 Function Enables pullup pulldown Y18. Enables pullup pulldown W18. Enables pullup pulldown V17. Enables pullup pulldown Y19. Enables pullup pulldown V18. Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Reset
Initialization
SPRU752A
OMAP5912 Configuration
Table Pulldown Control Register (PULL_DWN_CTRL_4) (Continued)
Base Address 0xFFFE 1000, Offset Address 0xAC Name CONF_PDEN_E4 CONF_PDEN_D2 CONF_PDEN_F4 CONF_PDEN_E3 CONF_PDEN_J7 CONF_PDEN_F3 CONF_PDEN_G4 CONF_PDEN_G3 CONF_PDEN_G2 CONF_PDEN_K8 CONF_PDEN_H4 CONF_PDEN_H3 CONF_PDEN_K7 CONF_PDEN_L4 CONF_PDEN_V2 CONF_PDEN_P3 CONF_PDEN_U4 CONF_PDEN_W1 Function Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Enables pullup pulldown Reset
This register controls enable disable combined pullup/pulldown cell enabled, disabled). When enabling cell, user must corresponding PU_PD_SEL_4 select either pullup pulldown. pinout documentation (Chapter must consulted determine whether pullup pulldown exists specified I/O. COMP_MODE_CTRL_0 must programmed 0xEAEF that programming taken into account corresponding tactical cell.
SPRU752A
Initialization
OMAP5912 Configuration
Table Pullup/Pulldown Selection Register (PU_PD_SEL_0)
Base Address 0xFFFE 1000, Offset Address 0xB4 Name CONF_PU_PD_L14 CONF_PU_PD_M18 CONF_PU_PD_M19 CONF_PU_PD_L15 CONF_PU_PD_L18 CONF_PU_PD_L19 CONF_PU_PD_K14 CONF_PU_PD_K15 CONF_PU_PD_K19 CONF_PU_PD_K18 CONF_PU_PD_J14 CONF_PU_PD_J19 CONF_PU_PD_J18 CONF_PU_PD_J15 CONF_PU_PD_H19 CONF_PU_PD_H20 CONF_PU_PD_H18 CONF_PU_PD_H15 CONF_PU_PD_G21 CONF_PU_PD_G20 RESERVED CONF_PU_PD_G18 CONF_PU_PD_F19 CONF_PU_PD_H14 CONF_PU_PD_E20 Function Configure pullup (=1) pulldown (=0) L14. Configure pullup (=1) pulldown (=0) M18. Configure pullup (=1) pulldown (=0) M19. Configure pullup (=1) pulldown (=0) L15. Configure pullup (=1) pulldown (=0) L18. Configure pullup (=1) pulldown (=0) L19. Configure pullup (=1) pulldown (=0) K14. Configure pullup (=1) pulldown (=0) K15. Configure pullup (=1) pulldown (=0) K19. Configure pullup (=1) pulldown (=0) K18. Configure pullup (=1) pulldown (=0) J14. Configure pullup (=1) pulldown (=0) J19. Configure pullup (=1) pulldown (=0) J18. Confi

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