MXED301
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MXED301
Column OLED Advance Information Driver with Controller
Subject Change Without Notice
FEATURES
Standard Control Data Interfaces Parallel: 8-Bit Motorola 68xx Intel 80xx Serial: I2C, 3-Line, 3-Line 4-Line 6.5MHz maximum data rate Chip Select Interface Mode Select Display Data (DDRAM) 4bit Frame Buffer Horizontal/Vertical Write Addressing Virtual DDRAM Windowing Display Operating Modes Frame Rate adjustable from 64-row scan Binary Grey Scale Mirroring 16-row partial display with Split Screen Screen Saver Flash Mode OLED Drive Global Current (Brightness) Control: 6-bit setting 10µA-350µA Current Matching 3.5% 4-bit pixel Gamma Grayscale Adaptive Precharge Sequential Interdigitized addressing
Hardware Functions External Power Supply Options DC-DC converter controller/regulator Pixel-Adaptive Power Management Power Reset Power Down (DDRAM preserved) Internal oscillator/External clock Battery Voltage Range: Volts Logic Voltage Range: Volts Voltage Analog Supply Range: Volts Mechanical Gold-Bumped pitch COG, COB, Assemblies simplified prototyping
OVERVIEW
MXED301 combines Clare Micronix's advanced OLED column- row-driver designs with versatile controller, which supports standard digital system interfaces connects directly OLED display panels. MXED301's well-matched current drivers, user provisions accommodate specific display panel characteristics, ensure uniform luminance high-quality gray-scale operation. Active pixel monitoring supply voltage control options guarantee minimum power dissipation over lifetime display module.
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MXED301
Column OLED Advance Information Driver with Controller
Subject Change Without Notice
REVISON CONTROL REVISON
Features: Minium 50Hz Maximum Supply 3.6V Deleted package option Figure Added ROWSEL DCDC Converter: Changed maximum. Oscillator: Corrected "SELEXT" name corrected logic polarity. Frame Rate: Added Table Frame Rate ROSC Figure Added S(6:0) B(6:0) vector pictoral. Horizontal Mirroring: Clarified verbage that only changes memory addressing. Vertical Mirroring: Corrected Driver sequencing Table Corrected polarity Figure Corrected Start Line Blank Line vector naming. Active Drive: Specified minum current 10uA N=17. Table Changed Imax VC(2:0) Table VPP: Deleted VROFF reference. Table SELEXT: Corrected logic polarity. Table SDATA/SDO: Corrected definition. Table 26A, Blank Row: Corrected nomenclature. Table Corrected spelling. Table Corrected default values: TPC=07h IPC=1Fh Table Corrected linear Gamma defaults start increments Read Product Code/Table Changed code: B(7:6) Product B(5:1) Revision; B(0) MUX80: various places corrected that rows addressed when MUX80=0. Precharge Current Amplitude: Correct register size IPC(6:0). Partial Display Mode Line Offset, B(6:0): Corrected maximum range MUX80=1: Maximum lines MUX80=0: Maximum lines Table Changed nominal ROSC=140K 60Hz. Added 60K<ROSC<180K Table ICOL: Corrected equation: ICOL 2.744uA*(1.08)^^N Changed Global Brightness matching condition from N=48 N=63 Added RROW minimum typical values. Table FCLK_Internal: Corrected limits 2.4576MHZ nom., 2.0-2.95MHz ROSC=140K FCLK_External: Corrected limits 1.024-2.4576MHz Frame Rate=60Hz Frame: Changed minimum 50Hz typical Frow: Changed limits 4.0-9.6 Frame Rate limits. Table Pads 157-158: Corrected name RGND. 161: Changed name from "Dummy" "DGND" force test GND. Application Information: Added section. Figure Configuration Examples: Added typical application connections MXED301. Added Programming samples Write RAM, Flash, Partial/Split Screen Screen Saver modes.
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Preliminary
MXED301
MXED301 ELECTRICAL DATA SHEET
FEATURES OVERVIEW FUNCTIONAL DESCRIPTION
Microcontroller Interface Instruction Decoder/Controller/Scanner Display Data (DDRAM) Gamma Lookup Table DDRAM Address Controller Gray-Scale Counter Column Current Converter Column Drivers Drivers. Column Monitor DC/DC Controller Oscillator
MODES OPERATION
Frame Rate Binary/Gray Scale Display Formats Screen Saver Mode Flash Mode Normal/Inverse Image Horizontal Mirroring Vertical Mirroring Sequential Interleaved Scanning White Field Test Pattern Pixel Aging Compensation Power Down
WRITING
Parameters That Affect Writing RAM. Writing Data RAM, Binary Mode Writing Data RAM, Gray Scale Mode Virtual Window
DISPLAY SCANNING READING DDRAM
Display Scanning Columns, Binary Mode Display Scanning Columns, Gray Scale Mode Display Scanning Rows Scanning Screen Saver Mode Unconnected Columns
INTERFACING MICROCONTROLLER
Intel 8080-Series Interface Motorola 6800-series Interface
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MXED301
Preliminary
Interface Standard Serial Bus, 3-Wire Interfaces 3-Line Nokia Interface 3-Line (Serial Peripheral Interface) 4-Line (Serial Peripheral Interface) Column Driver Circuit Waveforms Column Precharge Active Drive Active Discharge Strong Discharge Null
COLUMN DRIVER OPERATION
DRIVER OPERATION OPERATING DC/DC CONVERTER
Compliance Voltage Theory Operation Inductor Selection Diode Selection Selection Output Capacitor Selection Input Capacitor Selection Inductor Selection Example Layout Note
DEFINITIONS CONTROL INSTRUCTIONS COMMAND DEFINITIONS
Gamma Start Stream Screen Saver Start Stream Read Status Read Product Code Black White Binary Mode WHT: Pixels INV: Inverse Video mode DOR: Data order Memory addressing mode bit; display bit; vertical mirroring Pon: partial display mode Timing RR2: Reversing Rows SAV: Screensaver FLS: Flash mode TPC[3:0]: Precharge Time IPC[5:0]: Precharge Current Amplitude S[6:0]; Display Start Line B[6:0]: Partial Display Mode Line Offset VC[2:0]: Compliance Voltage
DESCRIPTIONS CONTROL BITS
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MXED301
ELECTRICAL SPECIFICATIONS ERRATA MECHANICAL SPECIFICATIONS
Figure Specification Figure Specification
ORDERING INFORMATION. APPLICATION INFORMATION FIGURE CONFIGURATION EXAMPLES FIGURE PROGRAMMING EXAMPLES.
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MXED301
Figure Block Diagram
D[7:0] CMDn SCLH SCLK SCEn SDATA RREF DVDD DGND AVDD AGND ROWsel RESn MUX80 UNC[4:0] VGATE VPPSEL SERsel MPUsel PS[1:0] NOKIA SA[1:0]
SELEXT
RGND dc-dc Voltage Multiplier/ Regulator
Rows
Interface Configuration Rows 40-79
Serial Interface
Parallel Interface
Rosc
Oscillator
Column Monitor
DDRAM Address Controller Instruction Decoder/Controller/Scanner
Preliminary
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Column Exposure Current
Dual Port DDRAM
Gray-Scale Counter
8-Bit Gamma Look-Up Table
MXED
Control Status Registers
VROFF
Generator Column Precharge Current Linear Control
CGND
Columns
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Preliminary
FUNCTIONAL DESCRIPTION
MXED301 power OLED timing controller driver single provides integrated flexible solution driving passive OLED displays either monochrome 4-bit gray scale mode. Additional features include integrated DC-DC converter controller, internal oscillator, Display Data (DDRAM), partial display mode, screensaver mode, low-power standby mode. flexibility, device incorporates parallel interfaces five serial interfaces. Output currents range from 350uA. MXED301 provides current precharge discharge periods during each time obtain optimal grayscale linearity power consumption. addition, critical circuit parameters such DC-DC converter output voltage modified compensate display aging. Typical applications that would this embedded circuitry would small format displays intended mobile hand-held purposes. Following discussion block diagram shown Figure Microcontroller Interface Microcontroller Interface serves multiple functions. used write pixel data into Display Data (DDRAM), program control registers, read status register. divided into three sections, which Interface Configuration, Serial Interface, Parallel Interface. Interface Configuration section used select interface options. There serial interfaces parallel interfaces available user. serial interfaces consist I2C, 3-Line (serial peripheral interface), 4-Line SPI, standard 3-Line, 3-Line Nokia. parallel interfaces available 8-bit Motorola 6800-Series standard, 8-bit Intel 8080-Series standard.
MXED301
DDRAM. This block also responsible controlling scanning rows columns. Control Timing block generates signals needed internal operation driver controls scanning PLED display. Display Data (DDRAM) Display Data 2-port mechanism, intended store video frame. MXED301 control 128-column 80-row display with bits grayscale, DDRAM organized bytes. gray-scale mode, each byte holds pixels worth data bits each). monochrome mode, only bytes used, with 1-bit pixel. Gamma Lookup Table This user programmable lookup table takes 4-bit gray-scale pixel data converts 8-bit exposure data control time column current drivers. This table defaults linear scale, programmed according user's needs. Table Gamma Start Stream section default gray-scale values. DDRAM Address Controller This address controller interfaces Controller with DDRAM, providing both read write addresses dual-port memory. Gray-Scale Counter gray-scale mode, pulse width modulation (PWM) algorithm implemented control period time which column driven. This period time based comparing 8-bit Lookup Table output with Gray-Scale Counter value.
Column Current Converter converter converts 6-bit Global Brightness programmed values into analog current current drivers each column driver. Instruction Decoder/Controller/Scanner external resistor connected allows This block decodes incoming messages from user fine-tune column current. This microcontroller interface. control mesuseful when making integrated display modules sage setting, instruction gets stored which displays well matched terms proper register. display data gets stored brightness. adjusting display brightness www.claremicronix.com
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MXED301
Preliminary
tor. external oscillator used connecting pad. SELEXT (0=Internal,1=External) switches between internal external oscillator.
Commonly Used Frame Rates (Hz, +/-10%) ROSC Standard Value 169K 140K 110K 105K 82.5K 68.1K
optimized require changes software settings. Therefore, completed display modules will have same characteristics. RREF used setting other internal bias currents should adjusted. Column Drivers chip column driver outputs. detailed description column drivers, please Column Driver section. Drivers chip driver outputs. detailed description drivers, please Driver section. Column Monitor Column Monitor monitors average voltage column outputs. This measurement made during active drive period output current sources (outside precharge discharge portions time). detected voltage used dynamically adjust DC/DC converter output voltage, VROFF, compensate aging off-state voltage Drivers. DC/DC Controller DC/DC Controller provides control portion DC/DC converter which used generate VPP. DC/DC converter generates high voltage (VPP) necessary OLED display driver from battery voltage input. high voltage output converter dynamic range from VBATT volts. select (SelVPP;0=Internall DCDC, 1=External Supply) been provided allow external converter. converter includes feedback loop adjust based average diode voltage detected display. DC/DC controller requires external inductor, diode, capacitor, NMOS transistor. controller provides gate drive NMOS transistor. Oscillator on-chip oscillator provides clock signal drive internal logic functions driver. external resistor required internal oscilla8
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Preliminary
MODES OPERATION
User-Defineable Start Position, S(6:0) Lines User-Defineable Space, B(6:0)
MXED301
MXED301 features several different modes operation that allows user flexibility system design well access number spe8 Lines cial effects. Most modes operation affect data either written DDRAM, read from DDRAM, both. more detailed information these modes these modes operate, please refer sections "Writing DDRAM" "Display Scanning Reading From DDRAM." Overviews various modes Figure Partial Split Display operation outlined below. this split-display mode blank space rows (B(6:0) vector) inserted between first Frame Rate MXED301 supports frame scanning rates from lines following lines. These modes affect 120Hz. There direct correlation data read from DDRAM. partial distween frame rate system clock, given play modes determine what pieces DDRAM accessed updating display. Also, when equation internal display controller scanning through FFRAME=FCLK/40960. output rows, works rows being accessed, blanking unused rows. this internal oscillator runs nominal 2.4576 manner display changed from full screen frame rate with ROSC=150Kohm. partial screen without affecting duty cycle, internal oscillator frequency, FCLK, which means that there will change external resistor, ROSC, connected ana- brightness display. ground, AGND. Screen Saver Mode Other frame rates within 50-120 range Screen Saver Mode (SAV=1)provides achievable using external oscillator (OSC means uniform pixel aging during standby periwith EXTSEL=1) setting frequency accord- moving image stored DDRAM around ingly. display. Screen Saver Mode, image automatically scrolls, pongs, with motion Binary/Gray Scale image being bound invisible, user-deThe MXED301 configured support monoShaded boundary upper-left chrome displays with either single-bit pixel corner scrolling image bit=1 black white binary) 4-bits pixel (gray-scale, BW=0). This feature under software control affects both data writ5 read from DDRAM. Display Formats MXED301 supports several different display formats. configured output full screen either lines, configured partial display mode (PON=1) which will output ,16, (P(1:0) bits) lines (Figure
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Start Position
Figure Screensaver
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MXED301
Preliminary
DDRAM written from Column128 Column0. This function affects data written DDRAM detailed that section. user will high (DVDD) (DGND) part system design. Vertical Mirroring Register (Mirror enables mirroring image vertical direction. does this reversing order which rows display turned Please section "Display Scanning" more information. Sequential Interleaved Scanning ROWsel makes possible scan outputs either sequentially, i.e. interleaved mode, i.e. 39,40, 42,.0, This feature makes system layout easier depending display built, much space layout area, etc. White Field Test Pattern all-white field test pattern available under software control (WHT=1). This allows user test display without having supply test patterns. Pixel Aging Compensation OLED displays age, pixel threshold voltage increase much volts. order optimally drive display throughout life, MXED301 continually monitors number parameters makes adjustments with built-in control loop. monitoring average diode voltage "on" pixels: voltage adjusted maintain adequate reverse bias pixels. DC/DC converter output voltage (VPP) adjusted modulating Vgate) maintain adequate voltage head room column current sources.
fined, box. size image determined display partial display) mode selected. full display area subset. Figure shows basic concept. Various registers define movement image discussed more "Display Scanning" section. control available which will allow scrolling image either absorbed into right-hand wall (CW=0) wrap back around (CW=1) left-hand side display. rate scrolling also specified programming Flash-ON (FON) Flash-OFF (FOFF) timing. screensaver used normal partial-scan display modes. Flash Mode user direct display flash predefined intervals under software control.
Normal Image
Inverse Image
Figure Normal Inverse Images more information using this feature refer Instruction Set. Flash Time (FON(3:0)) Flash Time (FOFF(3:0)) defined prior enabling flash mode (FLS=1). outputs ground during flash interface remains active update. Normal/Inverse Image user select either normal image inverse image, shown Figure This feature under software control. With inverse image (INV=1), pixel data stored DDRAM inverted upon readout, causing reverse-image effect.
Horizontal Mirroring (Mirror external that causes mirroring (column) address. When voltage detector determines average voltMX=0=DGND (default), DDRAM written from that occurs across pixels they driven. Column0 Column128. When MX=1=DVDD, drive voltage measured during Active Drive time.
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Average Diode Voltage Detector circuit will work effectively with displays having fewer than columns ignoring unused columns. Also, columns with gray-scale setting used determining average pixel voltage. Power Down active-low that places part power-down mode. this mode, column drivers ground, DC/DC converter turned off, power input internally disconnected that capacitor supply discharged. memory content DDRAM registers effected. WRITING Writing accomplished microcontroller interface. total matrix bytes, however, amount used determined selected display mode operation. Internal write-address pointers access cells byte time. address pointer corresponds display row. pointer reference pixels (binary mode) pixels (gray-scale mode). Additionally, desired write only subset DDRAM, user program start addresses (Xs,
MXED301
start addresses (Ys, Ye). DDRAM write pointers, Xwptr Ywptr, updated automatically after every data-byte write bound start values.
D0[7:0] D1[7:0] D2[7:0]
Data Byte Order
Figure Data Byte Order Once addresses (Xend,Yend) have been reached, pointers will automatically wrap around START adress (Xstart,Ystart) continue write commanded. Parameters That Affect Writing addition selecting Gray-Scale Binary mode, there number other parameters that control data written DDRAM. Data Order software control (DOR) switches order which data byte written RAM. Tables show effects Binary Mode Gray-Scale Mode. Note DDRAM bits correspond particular pixels different modes. following discussions tables this section, data assumed written device order D0[7:0], D1[7:0], etc., shown Figure (Mirror external that controls horizontal direction which data written into memory. low, data written into DDRAM
Table Data Order Table Black White Mode
Pixel DDRAM DOR=1 DOR=0 D[0] D[7] D[1] D[6] D[2] D[5] D[3] D[4] D[4] D[3] D[5] D[2] D[6] D[1] D[7] D[0]
Table Data Order Table Gray-Scale Mode
Pixel DDRAM DOR=1 DOR=0
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D[2] D[5] D[3] D[4] D[4] D[3]
Pixel D[5] D[2]
D[6] D[1] D[7] D[0]
D[0] D[7]
D[1] D[6]
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MXED301
Preliminary
quentially before moving next row. I.e. Xwptr incremented after each write until reached. When reached, Xwptr returns beginning row, Ywptr incremented next row. vertical mode, single byte data written, then Ywptr incremented next row, After first byte rows have been written, Ywptr returns Xwptr incremented, sequence resumes.
left-to-right fashion, i.e. beginning continuing (binary) (gray-scale). high then data written from right-to-left, i.e. from (binary) (gray-scale) This results image being mirrored direction. Normally, user will high part system design. Horizontal vertical addressing modes selected software control. horizontal mode bytes memory written seX0[7:0] D0[7:0] D16[7:0 D1275[7:0] X1[7:0] D1[7:0] D17[7:0 D1276[7:0] X2[7:0] D2[7:0] D18[7:0] D1277[7:0]
Table Writing DDRAM Horizontal Addressing, Binary Mode, MX=0
X14[7:0] D14[7:0] D30[7:0] D1278[7:0] X15[7:0] D15[7:0] D31[7:0] D1279[7:0]
Table Writing DDRAM Horizontal Addressing, Binary Mode, MX=1
X0[7:0] D15[7:0] D31[7:0 D1279[7:0] X1[7:0] D14[7:0] D30[7:0 D1278[7:0] X2[7:0] D13[7:0] D29[7:0] D1277[7:0] X14[7:0] D1[7:0] D17[7:0] D1265[7:0] X15[7:0] D0[7:0] D16[7:0] D1264[7:0]
Table Writing DDRAM Vertical Addressing, Binary Mode, MX=0
X0[7:0] D0[7:0] D1[7:0 D79[7:0] X1[7:0] D80[7:0] D81[7:0 D159[7:0] X2[7:0] D160[7:0] D161[7:0] D239[7:0] X14[7:0] D1120[7:0] D11217:0] D1199[7:0] X15[7:0] D1200[7:0] D1201[7:0] D1279[7:0]
Table Writing DDRAM Vertical Addressing, Binary Mode, MX=1
X0[7:0] D1200[7:0] D1201[7:0] D1279[7:0] X1[7:0] D1120[7:0] D11217:0] D1199[7:0] X2[7:0] D1040[7:0] D1041[7:0] D1119[7:0] X14[7:0] D80[7:0] D81[7:0 D159[7:0] X15[7:0] D0[7:0] D1[7:0 D79[7:0]
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Writing Data RAM, Binary Mode binary display mode, address ranges bytes bits byte bits) (for rows). addresses outside these ranges allowed. Tables show various Binary Addressing Modes.
MXED301
Writing Data RAM, Gray Scale Mode gray-scale display mode, address ranges pixels byte) Y79. addresses outside these ranges allowed. Tables show various GrayScale Addressing Modes.
Table Writing DDRAM Horizontal Addressing, Gray-Scale Mode, MX=0 X0[7:0] X1[7:0] X2[7:0] X62[7:0] X63[7:0]
D0[7:0] D64[7:0] D5056[7:0] D1[7:0] D65[7:0 D5057[7:0] D2[7:0] D66[7:0] D5058[7:0] D62[7:0] D126[7:0] D5118[7:0] D63[7:0] D127[7:0] D5119[7:0]
Table Writing DDRAM Horizontal Addressing, Gray-Scale Mode, MX=1
X0[7:0] X1[7:0] X2[7:0] X62[7:0] D1[7:0] D65[7:0] D5057[7:0] X63[7:0] D0[7:0] D64[7:0] D5056[7:0] D63[7:0] D127[7:0] D5119[7:0] D62[7:0] D126[7:0 D5118[7:0] D61[7:0] D125[7:0] D5117[7:0]
Table Writing DDRAM Vertical Addressing, Gray-Scale Mode, MX=0
X0[7:0] D0[7:0] D1[7:0] D79[7:0] X1[7:0] D80[7:0] D81[7:0 D159[7:0] X2[7:0] D160[7:0] D161[7:0] D239[7:0] X62[7:0] D4960[7:0] D4961[7:0] D5039[7:0] X63[7:0] D5040[7:0] D5041[7:0] D5119[7:0]
Table Writing DDRAM Vertical Addressing, Gray-Scale Mode, MX=1
X0[7:0] D5040[7:0] D5041[7:0] D5119[7:0] X1[7:0] X2[7:0] X62[7:0] D80[7:0] D81[7:0 D159[7:0] X63[7:0] D0[7:0] D1[7:0] D79[7:0]
D4960[7:0] D4880[7:0] D4961[7:0] D4881[7:0]
D5039[7:0] D4959[7:0]
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MXED301
Preliminary
Virtual Window partial area sequentially written virtual window defined. address coordinate that defines upper left corner virtual window, address coordinate that defines lower right corner virtual window. Default coordinates both binary gray scales modes X0,Y0. Default coordinates binary mode X15, default coordinates gray scale mode X63, Y79. Vertical horizontal addressing modes, data order, horizontal vertical mirroring have same effect when defining virtual window. memory data outside Virtual Window remains unchanged. example shown Table Table Writing DDRAM Horizontal Addressing, Gray-Scale Mode, MX=0, Xs=9,Xe=55,Ys=19,Ye=60
X0[7:0] D0[7:0] D47[7:0] D1786[7:0] D1833[7:0] D1[7:0] D48[7:0 D1787[7:0] D1834[7:0] D45[7:0] D92[7:0] D1831[7:0] D1878[7:0] D46[7:0] D93[7:0 D1832[7:0] D1879[7:0] X9[7:0] X10[7:0] X54[7:0] X55[7:0] X63[7:0]
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DISPLAY SCANNING READING DDRAM
While there number parameters that affect data written DDRAM, there also number parameters that determine data read from DDRAM that data used. Binary/Gray-Scale mode, vertical mirroring, partial display, screensaver affect data read from DDRAM. understand data read from memory, easiest first look individually display columns rows read memory.
MXED301
display rows. Data always read from beginning memory, when set, drivers turned reverse order, thereby causing mirroring effect. display modes, partial-display full display, data read beginning from first rows memory. That means that mode, data read from first rows memory. partial display modes data read from contiguous block memory. example, 16-line mode data read from first rows memory. Table provides settings display modes memory locations that they access.
Display Scanning Columns, Binary Mode Register S[6:0] offset pointer which determines binary mode, data memory col- what display will access (Y0) umns maps display shown Table where shown that least significant maps left-most column each 8column group. Table Reading Display Scanning Columns, Gray Scale From DDRAM Mode Bytes MY=0 MY=1 gray scale mode, data memory Byte columns X0-X63 maps display shown Table where shown that least signifiY0 cant nibble maps left-most column each column group. Display Scanning Rows Another parameter that effects scanning Vertical Mirroring (MY). This control determines order rows memory corresponds rows display. Tables show effect relationship between memory rows
Table Reading From DDRAM Binary Mode, Column Bits
Byte Column
Table Reading From DDRAM Gray-Scale Mode, Column Bits
Byte Column
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MXED301
Preliminary
Table Sequence Options:
OUTPUT ORDER
(8,9.38,39)-(40,41.70,71) (39,38.9,8)-(40,41.70,71) (8,9.38,39)-(71,70.41,40) (39,38.9,8)-(71,70.41,40) (71,70.41,40)-(39,38.9,8) (71,70.41,40)-(8,9.38,39) (40,41.70,71)-(39,38.9,8) (40,41.70,71)-(8,9.38,39) 39,40,38,41.9,70,8,71 40,39,41,38.70,9,71,8 40,39,41,38.70,9,71,8 40,39,41,38.70,9,71,8 71,8,70,9.41,38,40,39 8,71,9,70.38,41,39,40 8,71,9,70.38,41,39,40 8,71,9,70.38,41,39,40 (0,1.38,39)-(40,41.78,79) (39,38.1,0)-(40,41.78,79) (0,1.38,39)-(79,78.41,40) (39,38.1,0)-(79,78.41,40) (79,78.41,40)-(39,38.1,0) (79,78.41,40)-(0,1.38,39) (40,41.78,79)-(39,38.1,0) (40,41.78,79)-(0,1.38,39) 39,40,38,41.1,78,0,79 40,39,41,38.78,1,79,0 40,39,41,38.78,1,79,0 40,39,41,38.78,1,79,0 79,0,78,1.41,38,40,39 0,79,1,78.38,41,39,40 0,79,1,78.38,41,39,40 0,79,1,78.38,41,39,40
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Preliminary
Table Partial Display Mode Register Settings
Rows DRAM ccessed
MXED301
DDRAM. instance, S[6:0]=0 then display will correspond display memory. S[6:0]=8, then display will correspond DDRAM. desired, S[6:0] periodically incremented create vertical scrolling effect. partial display mode B[6:0] used number blank lines between first group lines second group lines. Figure shows relationships S[6:0] B[6:0] with display lines.
S[6:0] Lines B[6:0] Lines
possible reverse output order rows each these blocks. setting output order Block reversed, outputs rows order 39-0. setting RRS2 output order Block reversed, outputting rows order 79-40. This function works changing order data read memory, rather changing order which rows turned This feature useful simplifying system layout.
Output Order Internal Output RR1=0 MXED301 (viewed facing pads) Output Order Internal Output RR2=0
Output Order Internal Output RR1=1 MXED301 (viewed facing pads)
Output Order Internal Output RR2=0
Figure Relationships S[6:0], B[6:0], Display Lines Another feature MXED301 ability reverse order scanning blocks rows. Please refer Figure TAbles remainder this discussion. When viewing physical seen that outputs occupy blocks area. first block, Block contains outputs Rows 0-39. second block, Block contains outputs Rows 40-79. using registers RR2,
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Output Order Internal Output RR1=0 MXED301 (viewed facing pads)
Output Order Internal Output RR2=1
Figure RR2, Reversal
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MXED301
Preliminary
reverse direction, bouncing between upper lower "walls." (column wrap) then when right-hand edge image edge display, will wrap around left-hand side display. cleared then columns past edge display will displayed will look have disappeared. move rate, display update, specified using Flash Time, FON[3:0], Flash Time, FOFF[3:0] instructions. display updates according relationship below: Display update interval 0.2*FON(3:0) 0.4* FOFF(3:0) seconds Note that while screen saver function utilizes Flash Flash Time registers, display itself will flashing unless set. valid Flash Mode Screen Saver Mode same time. order enable Screen Saver Mode active after eight screen saver movement registers plus move rate registers plus column wrap register programmed. While Screen Saver mode microcontroller interface remains active. normal partial-mode display, rows scanned, resulting change duty cycle, hence change brightness. Note that screen-saver mode used normal scan mode well partial display modes. Following example sequence frames screensaver mode. Figure shows display picture appears memory). picture this example group arrows. Figure shows projected movement pointer (PosX,PosY). Following Figure showing movement picture when CW=1. Look carefully this sequence pieces arrows wrapped around this display, both horizontally vertically. Next Figure showing movement picture when CW=0. Note this mode picture does wrap horizon15280C
Scanning Screen Saver Mode Screen Saver Mode another parameter that affects data read from DDRAM. this mode internal controller automatically scrolls image memory around display, binding upper left-hand corner image within user-defined pixels display. size image determined display partial display) mode selected. that binds movement image full display area subset thereof. Figure shows basic concept parameters which must specified. Eight registers define movement image loaded prior enabling Screen Saver control bit. Xmin Ymin define upper left corner scrolling area, while Xmax Ymax define lower right corner scrolling area. StartX StartY define initial location internal pointers PosX PosY (Position Position which will display location upper left-hand corner image resides memory. Note that StartX StartY must within defined box. Register settings DelX DelY define much PosX PosY incremented each subsequent display cycle. When PosX reaches limit Xmax, instead being incremented DelX, PosX will decremented DelX. When PosX hits other wall will again reverse direction. same true PosY that when reaches Ymax will
Xmin,Ymin StartY StartX, StartY StartX DelX Xmax,Ymax DelY
Figure Screen-Saver Mode
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Preliminary
MXED301
Start
Figure Image resides memory
Figure Position Vector Movement
Frame
Frame
Frame
Frame
Frame
Frame
Figure Screensaver Sequence, CW=1
Frame
Frame
Frame
Frame
Frame
Frame
Figure Screensaver Sequence, CW=0
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MXED301
Preliminary
tally around display, rather disappears edge. picture, however, does continue wrap vertically. Unconnected Columns Pads UNC[4:0] make possible turn number columns display. These pads hardwired value ranging from through setting number unused columns. Unused columns begin right-hand side display, i.e. column 127, work backwards, going column While data written these corresponding columns DDRAM, when data read will treated were keeping unused column outputs ground.
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Preliminary
INTERFACING MICROCONTROLLER
control information (except some configuration bits which controlled external pads) display data enters MXED301 seven available interfaces. interface options, Motorola 6800-Series 8-bit parallel Intel 8080-Series 8-bit parallel, allow device treated memory-mapped device. other five interface options serial, consist I2C, standard 3-wire, modified 3wire protocol found Nokia devices, 3-Line (serial peripheral interface), 4-Line SPI. Table shows required programming select seven interface protocols. Intel 8080-Series Interface this 8-bit parallel mode, RDn, WRn, activated transfer data/status from controller. Commands transferred controller asserting A0=1. When A0=0, transfer will interpreted data. Refer Figure Table Motorola 6800-series Interface this 8-bit parallel mode, R/Wn, activated transfer data/status from controller. Commands transferred controller asserting A0=0. When A0=1, transfer will interpreted pixel data written
MXED301
Display (DDRAM). Refer Figure Table Interface interface (Figure follows standard protocol timing defined Philips. complete information this bus, refer acrobat/various/ I2C_BUS_SPECIFICATION_3.pdf (Note: This link case sensitive.) MXED301 acts slave device compatible with both (High Speed) Mode Fast Mode formats. primary function receiver, receiving both command data pixel data from master device. will transmitter after receiving status read command. When receiving non-broadcast message, MXED301 will respond with acknowledge bit, which pulls data appropriate time. Data packets begin with Master issuing START command with Master issuing STOP command (P). Restart command simply another START command that issued before STOP command. Note that with START STOP commands that SDAH transitions while SCLH high. Conversely, other bits, SDAH only allowed transition while SCLH Write command data MXED301, master device will first issue Start Bit. will then
Table Interface Configuration
SERsel MPUsel NOKIA INTERFACE Intel 8080 Motorla 6800 3-Line 4-Line 3-Line standard 3-Line Nokia
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MXED301
Figure 8080 PARALLEL
Preliminary
TAW8 TAH8
TCCLR,TCCLW TCYC8
WRn,RDn
TCCHR,TCCHW
WRn,RDn
TDS8 TDH8
D[7:0] (Write)
TACC8 TOH8
D[7:0] (Read)
8080 Read/Write Cycle Timing
Table 8080 Timing Parameters Symbol Parameter TCYC8 TAW8 TAH8 TCCLW TCCHW TCCLR TCCHR TDS8 TDH8 TACC8 TOH8
Unit Condition Electrical Characteristics
Minimum cycle time Address setup time Address hold time pulse width high pulse width pulse width high pulse width Data setup time Data hold time Read access time Read output disable time www.claremicronix.com
L=100pF CL=100pF
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Preliminary
Figure 6800 PARALLEL
MXED301
R/Wn
TAW6 TAH6
TEHR,TEHW TCYC6
TELR,TELW
TDS6 TDH6
D[7:0] (Write)
TACC6 TOH6
D[7:0] (Read)
6800 Read/Write Cycle Timing
Table 6800 Timing Parameters Symbol Parameter TCYC6 TAW6 TAH6 TEHW TELW TEHR TELR TDS6 TDH6 TACC6 TOH6
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Unit Condition Electrical Characteristics
Minimum cycle time Address setup time Address hold time high width write width write high width read width read Data setup time Data hold time Read access time Read output disable time www.claremicronix.com
L=100pF CL=100pF
MXED301
Figure
Preliminary
SDAH TI2C-CS SCLH START DATA stable during high period SCLH STOP TI2C-SC TI2C-DS TI2C-DH TI2C-CP TI2C-PC
Unshaded boxes represent bits sourced master.
Shaded boxes represent bits sourced MXED301.
START
R/Wn
D/Cn
STOP
Slave Address
Control Bits ignored
upper bits slave address internally fixed 01111b. LSB's user.
Data Byte interpreted command because D/Cn
Write Sequence Overview
D/Cn
When Co=1, will followed D/Cn bit, group control bits (which ignored), single data byte. data byte will interpreted MXED301 command pixel data depending setting D/Cn bit. Another will then follow.
Control Bits ignored
Data Byte interpreted command because D/Cn
When Co=0, then more D/Cn more control word will follow. After that number Data Bytes will sent, they will interpreted data command according D/Cn bit. Only STOP another START terminate sequence.
Writing Command Example
START
R/Wn
D/Cn
STOP
Slave Address Slave address 011_1101b.
Control Bits ignored
Data Byte Start Address Command
Data Byte Sets Start Address
START
R/Wn
D/Cn
STOP
Status Read Sequence
Slave Address Slave address 011_1101b.
Control Bits ignored
Data Byte Read Status Command.
START
R/Wn
STOP
Slave Address Slave address 011_1101b.
Data Byte Status placed MXED301.
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Preliminary
transmit 7-bit address. MXED301, upper bits address, A[6:2], internally 0_1111b, while lower address bits, A[1:0] user with pads SA[1:0]. address message corresponds address MXED301, then device will issue acknowledge. That will followed (Continue) then D/Cn (data/command) bit. Next will control bits, which have effect chip. MXED301 will issue Acknowledge, then master will send bits data. These bits will interpreted either command Cn=0) data (D/Cn=1). Another Acknowledge will follow. previous then another will appear, followed another D/Cn another data bits Acknowledge. previous there will another D/Cn bit, next byte data will interpreted same manner last data byte. Both overview write sequence specific example shown. specific example, controller setting Start Address value read sequence with somewhat different than with other serial modes. First, master must write MXED301, writing command Read Status. Next, master issues read command setting R/Wn bit. master will then tri-state data while MXED301 outputs data. example figures. Standard Serial Bus, 3-Wire Interfaces standard 3-wire bidirectional serial interface available (Figure 16). inputs serial clock, SCLK, serial data line, SDATA, serial chip enable, SCEn. serial output SDO. serial data output must externally connected serial data line. Write mode microcontroller writing either command data MXED301. Each packet data contains D/Cn (data/command) 8-bit transmission byte. D/Cn following bits data interpreted command. D/Cn high following bits data interpreted pixel data stored DDRAM.
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MXED301
When SCEn goes low, next rising edge SCLK clocks D/Cn bit. next bits clocked each subsequent edge SCLK, first. transmission byte, controller either bring SCEn high, thus terminating write process, keep SCEn transmit another data packet, again beginning with D/Cn. SCEn must remain during entire transmission byte. Read mode command received which tells MXED301 output status. MXED301 will output bits status beginning first falling edge SCLK after rising edge SCLK which last transmission clocked this manner, first status will available microcontroller next rising edge SCLK. SCEn must remain while MXED301 outputting data, going high after MXED301 output last bit. While device outputting data, SDATA must high impedance state SDATA connected together externally. 3-Line Nokia Interface This interface differs from standard 3-Line Serial only that during readback, bits output instead bit, D[0], truncated. Refer Figure 3-Line (Serial Peripheral Interface) 3-Line mode, Figure uses same input output pins standard 3-Line, differs slightly from standard 3-Line interface. Instead using 9-bit data packet which data/command bit, 3-Line uses only 8-bit data packets. data received assumed command. display data sent (received MXED301) then special command, called Display Data Length instruction, issued. next byte after that will tell many bytes data sent, followed appropriate number display data bytes. before, number instructions issued long SCEn held low. Again, SDATA must connected together externally.
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MXED301
Preliminary
4-Line (Serial Peripheral Interface) 4-Line SPI, Figure uses pin, CMDn, addition SCEn, SDATA, SCLK, SDO. Transmission bytes bits long, CMDn used differentiate between command display data being written MXED301. SDATA must connected together externally.
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Preliminary
Figure 3-LINE SERIAL
SCEn SCLK D/Cn TCYCS
MXED301
SDATA
Write Cycle Timing
SCEn
SCLK
SDATA D/Cn
Read Cycle Timing
SCEn TSHR SDATA TACCS TOHS
Read Cycle Timing Detailed
SCEn
SCLK
SDATA
D/Cn
D/Cn
D/Cn
Multiple Write Cycles
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MXED301
Figure 3-LINE SERIAL NOKIA
SCEn
Preliminary
SCLK
SDATA D/Cn
Read Cycle Timing
Table Serial Interface Timing Symbol Parameter TCYCS THI,TLO TR,TF TACCS TOHS TSHR TI2C_CS TI2C_SC TI2C_DS TI2C_DH TI2C_CP TI2C_PC
Unit
Condition Electrical Characteristics
Cycle time Pulse width Rise Fall time, 10-90% Data setup time Data hold time SCEn setup time SCEn hold time CMDn setup time CMDn hold time Access time read mode Output disable time read mode SCEn hold time read mode Clock High Start Start Clock Data Valid Clock High Clock Data Invalid Clock High Stop Stop Clock www.claremicronix.com
CL=100pF CL=100pF
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Preliminary
Figure 3-LINE
MXED301
SCEn SCLK SDATA TCYCS
Write Cycle Timing
SCEn
SCLK
SDATA
Read Cycle Timing
SCEn TSHR SDATA TACCS TOHS
Read Cycle Timing Detailed
SCEn
SCLK
SDATA
Instruction Byte Display Data Length Instruction
Data Length Byte
Data Bytes
Next Instructions
Multiple Write Cycles beginning with Display Data Length instruction
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MXED301
Figure 4-LINE
SCEn SCLK
Preliminary
TCYCS
CMDn SDATA
Write Cycle Timing
SCEn
SCLK
CMDn
SDATA
Read Cycle Timing
SCEn TSHR SDATA TACCS SCEn TOHS
Read Cycle Timing Detailed
CMDn
SCLK
SDATA
Instruction Byte
Data Byte
Multiple Write Cycles
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Preliminary
COLUMN DRIVER OPERATION
Column Driver Circuit Waveforms column driver special 5-state analog driver circuit shown Figure provides precharge current, active drive current, active discharge current, strong pull down device (strong discharge), high impedance state. period divided into counts, kept track internal gray-scale counter. timing diagram column driver shown Figure Each five column states occurs within these clock cycles. first period Precharge, which globally programmed from 1-16 clock cycles (when APC=0). Next Active Drive period, with time ranging from determined output gamma correction table, whose input DDRAM. next period Active Discharge period (minimum clock cycles) lasts from Active Drive period start Strong Pull Down period. strong Pull Down period lasts clock cycles. Lastly Null state, which column output high impedance. This lasts clock cycle, after which time begins. Column Precharge Column Precharge quickly brings OLED display "on" threshold diodes charging parasitic capacitances. Column Precharge modes operation, selectable pad.
MXED301
(2.5mA) voltage source. Adaptive Precharge Mode, precharge time always clock cycles (unless pixel data which case precharge time will Registers TPC[3:0] (Precharge Time) IPC[5:0] (Precharge Current) have effect. APC=0 device Non-Adaptive Precharge Mode. this mode, user externally connects (the high voltage supply). Precharge time precharge current programmed user. Precharge time from clock cycles registers TPC[3:0]. Note that value TPC[3:0] incremented actual Precharge Time. Precharge current registers IPC[5:0] linear steps 39uA, from 39uA 2.5mA, shown Table user effectively adjust precharge voltage adjusting register settings TPC[3:0] IPC[5:0]. Note that pixel particular column illuminated, then precharge will occur that column. Active Drive Active Drive state begins immediately precharge. duration this period determined gray-scale value written DDRAM corresponding output gamma correction table. case monochrome mode, active drive period will last clock cycles. Active Drive current globally 6-bit register external calibration
When APC=1 device Adaptive Precharge Mode. this mode, user externally connects (the precharge generator supply Active Drive Current-Controlled voltage) VRowOff. VRowOff internally generCurrent Source Precharge Source ated average diode "on" voltage display, measured MXED301. DurColumn precharge cycle column outputs will Output Strong source maximum current possible, 2.5mA. Pulldown column voltage gets within approximately Active Discharge VRowOff current source will taper-off, reducing Current Sink current until column voltage equals VRowOff, which time current will this sense, precharge output acts current-limited Figure Column Driver
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MXED301
Preliminary
illuminated pixel turn off. This current source remains active through Strong Discharge period, turning start Null period. Active Discharge circuit nominally sinks Strong Discharge During last Event Counts, strong pulldown device (strong discharge) turned hold anodes ground potential. strong pulldown applies maximum switch ground, thus ensuring that charge removed from display. Null NULL last time period during which drive currents removed column driver high impedance state. NULL period always clock cycle long.
resistor, RGG. current exponential function programmed value approximating relationship: 2.744uA (1.08)**N, where such that 10uA 350uA Values less than yield inaccurate current settings should used. active drive current offset much ±10% selecting value calibration resistor, RGG, which used normalize drive current displays with various luminance efficiencies. nominal value 20K. Thus, overall drive current expressed 20K* (2.744uA (1.08)**N)/ RGG, where Table provides list register settings corresponding current values. Active Discharge Immediately after active drive current been applied column appropriate amount time, active current sink used discharge
Total Clock Pulses Column Output State Output State Precharge, 0-16 Active Drive, 0-225 Active Discharge Strong Discharge, Null,
Figure Output Timing, APC=0
Total Clock Pulses Column Output State Output State Precharge, Active Drive, Active Discharge, Strong Discharge, Null
Figure Output Timing Example, APC=0
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Preliminary
Table Precharge Current (uA,APC=0)
MXED301
1014 1053 1092 1131 1170 1209 1248
1287 1326 1365 1404 1443 1482 1521 1560 1599 1638 1677 1716 1755 1794 1833 1872
1911 1950 1989 2028 2067 2106 2145 2184 2223 2262 2301 2340 2379 2418 2457 2496
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MXED301
Preliminary
Table Active Drive Currents (uA)
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Preliminary
DRIVER OPERATION
drivers special 2-state analog driver circuit shown Figure state forces output VRowOff, while state provides low-impedance connection ground. Only driver active (low) given time. start period, driver output remains high until precharge. then switches ground same column Active Drive state begins. output returns VRowOff beginning Null period.
VROFF
Vgate
MXED301
OPERATING DC/DC CONVERTER
MXED301 contains circuitry DC-DC converter controller. user only needs supply external switching FET, inductor, diode, capacitor, shown Figure This makes easy generate supply voltage VPP, which used power column drivers.
Vbat
Output
Figure DC/DC Converter Circuit Compliance Voltage monitoring average display "on" voltage, DC-DC controller maintains voltage that slightly higher than average detected voltage. difference between average detected voltage called "compliance" voltage. TABLE Recommended Compliance Voltage Settings Various Column Currents.
Column Current (uA) Compliance Voltage 1.25 1.50 1.75 2.00 (Default) 2.25 2.50 2.75 3.00
Figure Driver
VC[2]
VC[1]
VC[0]
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MXED301
Preliminary
Compliance voltage required across column driver current source FET's that they look like high-impedance current source. Normally, time this compliance voltage around compliance voltage output drivers changes acT=1/f cording programmed output current, rec- Figure Inductor Current ommended follow settings Table compliance voltage. deadtime, since energy being stored inductor being delivered load. This Theory Operation type operation, which inductor current reThe converter operates with terminal turns each cycle, referred ductor connected input other ter- "discontinuous mode." minal connected switch ground, this case FET. When turned effectively given inductor value, converter's output grounding inductor, inductor current ramps current capability lowest when lowup. When switch turned off, voltage est. Other significant parameters calculating switch node flies inductor seeks inductor value switching frequency, path current. diode, also connected lowest duty cycle (ratio switch on-time switching node, provides path conduction total cycle time), diode forward voltage. inductor current boost converter's out- Other parameters, such inductor's reput capacitor. MXED301 monitors volt- sistance, series resistance input source, output capacitor (Vpp) modulates series resistance will considered on-time switch maintain this output volt- equations that follow, keep mind that age. output capacitor charges their values will have large effect converter efsired maintained there provided cir- ficiency. cuit provide enough current load. output current boost converter given primary task, then, designing boost converter equation determine inductor value (and peak current rating prevent inductor core saturation problems) which will provide amount current needed guarantee that output voltage will input voltage (battery voltage) able maintain regulation specified maxi- on-time duty cycle load current. Secondary necessary tasks also include choosing diode, FET, out- switching frequency capacitor. Additional output filtering inductor value quired user's requirements. output voltage (VPP) MXED301 runs with fixed oscillator frequency 200kHz, regulates output voltage diode forward voltage modulating duty cycle, on-time, switch. Figure shows inductor current over com- maintain discontinuous mode operation plete switching cycle. time switch turns VIN<=(VO+VF)(1-D). Solving this yields inductor current begins ramping until DMAX=1-(VIN(MIN)/(VO+VF)). switch turns off. When switch turns off, current flows from inductor into load. When above equation rearranged current dissipated more current flows until switch turned again. This last period known
dead
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Preliminary
solve maximum value yielding Lmax= Following guide selecting components DC/DC converter. begin component selection, some parameters system must known. Determine VPP(MAX).
MXED301
Determine current inductor. Choose inductor that handle peak currents calculated. Also, choose inductor with small resistance (less than possible), resistance goes converter efficiency goes down.
Diode Selection Choose diode that handle peak current calculated above, forward voltage. VPP(MAX)=VDISPLAY VCOMPLIANCE VAGING. Typically Schottky diode selected. Note that system designer must know what OLED forward voltage, diode differdisplay operating voltage also decide than approximated above, need much compliance voltage have. VAGING over- recalculate equations based forward head voltage account aging display, voltage. Also make sure that diode handle wherein operating voltage likely rise. reverse voltage VR=VO+VF. Determine supply. approximation #columns*(ICOL*DPIXEL IPC*0.063). #columns number display columns, DPIXEL percentage time column IPC=precharge current. multiplier 0.063 on-time duty cycle precharge source. Inductor Selection Calculate maximum duty cycle converter remain discontinuous mode operation using above equation DMAX. typical approximation around 0.4V, this number should suitable starting point. Using Dmax, determine maximum inductor value, LMAX, using above equation LMAX. Selection Choose NMOS that handle peak current (IPK calculated above), well peak voltage (VO+VF) that will seen drain. channel resistance important, channel resistance goes efficiency goes down. Output Capacitor Selection output capacitor's function average current pulses delivered from inductor while holding relatively smooth voltage converter load. Output ripple given equation DeltaVo=Io*(1-D)/f*Co Ipk*RESR
RESR equivalent series resistance capacitor typically dominating component Choose standard inductor value, that slightly this equation. Tantalum capacitors usually make less than calculated LMAX. good choice output capacitor. Note that Determine actual Duty Cycle, using cho- voltage rating tantalum capacitors goes typically goes down. also value effect efficiency, lower better. capacitance values would 1-10uF Determine peak current inductor. range. this calculation maximum input voltage Input Capacitor Selection VIN. DC/DC converter draws current periodic bursts. output impedance battery IPK=VIN(MIN)*D/(f*L)
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MXED301
Preliminary
enough, voltage droop will occur battery supply, which could turn affect converter operation. smooth input ripple, best bypass battery with tantalum capacitor with significantly lower than battery. Again, 110uF should sufficient. Inductor Selection Example This example meant provide user guide inductor selection, meant design suitable system applications. Start with following parameters. VPP=16V, VIN(MIN)=2.7V, VIN(MAX)=3.3V, VF=0.4V, IO=50mA Using equations yields DMAX=1-(2.7/(16+0.4))=0.84 =2.7 *0.84 this example, L=15uH chosen. Recalculating with L=15uH yields D=0.75. IPK=3.3*0.75/(200k*15uH) IRMS 800mA. Therefore, have chosen 15uH inductor that must handle peak current 825mA without saturating, must also handle current 800mA. Layout Note with DC-DC converters, good layout practice essential. Make sure that ground nodes low-impedance ground keep trace lengths minimum.
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Preliminary
DEFINITIONS
Table Power Bias NAME AGND DGND CGND RGND AVDD DVDD VBATT VROFF RREF ROSC DESCRIPTION Analog ground Digital Ground. Column driver ground. driver ground. voltage analog supply. Logic supply. High voltage analog supply column driver.
MXED301
This system battery voltage that powers DC/DC converter external inductor actual chip pin. Internally generated voltage. Must bypassed ground with capacitor. Precharge Generator Supply Voltage. tied VROFF depending operation. External resistor ground internal bias currents. External resistor ground fine tune column current. External resistor ground bias internal oscillator.
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MXED301
Table Configuration NAME PDNn RESn MUX80 ROWSEL UNC[4:0] SELEXT SELVPP VGATE DESCRIPTION
Preliminary
This signal fully disables driver, with rows columns ground unaffected. Active reset. 80/64 Select. 0=64 Rows enabled, 1=80 Rows enabled. Note than 64row mode that outputs R(0-7) R(72-79) used. Therefore, 64row display should connected outputs R(8-71). 0=Sequential scan, 1=Interleaved scan. Selects number unused column outputs from 0-31. Selects Internal Oscillator. 1=external oscillator, 0=internal oscillator. External oscillator input. Leave open using internal oscillator. Adaptive Precharge. 1=Adaptive Precharge, 0=User Programmable Precharge Selects mirroring direction data being written frame buffer RAM. 1=Mirror, 0=no Mirror. Selects internal external DC/DC converter controller. 0=internal DC/DC controller. 1=external power supply. DC/DC controller output that connects gate external NMOS transistor.
line. used test point. Frame. used test point.
Table DISPLAY OUTPUTS NAME DESCRIPTION COL_OUT[127:0] R[79:0] column driver outputs that connect OLED anodes. These driver outputs that connected OLED cathodes.
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Preliminary
Table INTERFACE
NAME DESCRIPTION INTERFACE CONFIGURATION SERsel MPUsel NOKIA
MXED301
Selects family serial interfaces family parallel interfaces. Selects parallel interface modes. Used with select serial mode. Used with select serial mode. 3-wire mode selects standard Nokia interface. Least significant address serial interface. Second order address serial interface. SERIAL INTERFACE
CMDn SCLH SCLK SCEn SDATA
Data/Command serial mode. 0=serial input contains command 1=serial input contains pixel data. Clock. Serial Input Clock. Serial Chip Enable Bidirectional mode. connect ACK. serial mode, this data input. mode. serial mode connect this output data. PARALLEL INTERFACE
Parallel mode chip select. 0=select, select. Parallel mode command select. 0=D[7:0] contains command 1=D[7:0] contains pixel data. Parallel mode: Intel mode: strobe. mode: R/Wn select. Parallel mode: Intel mode: strobe. mode: clock.
D[7:0]
Parallel data bus.
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MXED301
CONTROL INSTRUCTIONS
Table Instruction
Instruction Precharge Timing Precharge Current LSBs Read Product Code CMDn Precharge Current MSBs Flash timing Flash timing Exposure Current Initial Display Line (scroll mode) Pixels normal Video Mode Data order addressing Number Blank Lines Partial Display Mode Display control Compliance voltage Column Wrap
Preliminary
TPC3 IPC3 Fon3 Foff3
TPC2 IPC2 Fon2 Foff2
TPC1 IPC1 IPC5 Fon1 Foff1
TPC0 IPC0 IPC4 Fon0 Foff0
Description Precharge Time from 1-16 clock cyles (register value+1) Precharge Current settings Read Product Code Reserved Reserved Reserved Reserved Reserved Reserved Precharge Current MSB's setting memory start address memory start address address address Reserved Flash time Flash time Black White (Binary) Gray-Scale Column Driver Current Setting start output address 0<=S<=79 Turn pixels user test mode Inverse Video Mode Data order Vertical addressing Number Blank rows between fields Split Screen Mode. 0<=B<=79 Reserved Display compliance voltage Enable Column Wrap Partial Display Reserved Reserved Reserved
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Preliminary
Table Instruction (continued)
Instruction Vertical mirroring partial display timing CMDn Read Status Gamma start stream Reverse Reset Display Data Length Screen saver start stream Screen saver Reverse Flash Write Data Description Mirror partial display timing Reserved Reserved Reserved Reserved
MXED301
Return status byte microcontroller Next bytes load gamma correction table Reverse ROW0 ROW39 Internal reset operation Reserved Only used 3-Line mode 0<=DL<=255 Next bytes screen saver registers. Screen saver mode Reverse ROW40 ROW79 Flash display mode Reserved Write data
Table Single Register Control Bits
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Grayscale mode; 4bits column Normal display mode Normal display mode Horizontal addressing Display mirroring Full display selected after precharge Bottom block reversed Screen saver Bottom block reversed Driver Flash mode
Monochrome mode; 1bit column pixels Inverse video mode Vertical addressing Display mirroring Partial display mode selected before precharge Bottom block reversed Screen saver Bottom block reversed Driver Flash mode
Default
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MXED301
Preliminary
Table Multi-Register Control Bits
Bits TPC[3:0] IPC[5:0] Xs[5:0] Ys[6:0] Xe[5:0] Ye[6:0] S[6:0] Fon[3:0] Foff[3:0] Ix[5:0] B[6:0] VC[2:0] P[1:0] DL[7:0] D[7:0] Definition Precharge Time Precharge Current Sets horizontal starting position write pointer memory map; 00h<=Xs[5:0]<=32h Sets vertical starting position write pointer memory map; 00h<=Ys[6:0]<=4Fh Sets horizontal ending position write pointer memory map; <=Xe[5:0]<=3Fh Sets vertical ending position write pointer memory map; 00h<=Ye[6:0]<=4Fh display start line; 0<=L[6:0]<=79 Flash time 0.2*FON[3:0] seconds Flash time= 0.4*FOFF[3:0] seconds Sets amplitude column currents. Sets space between display fields partial split-display modes. 0<=C[6:0]<=71 compliance voltage from 1.25V steps 0.25V partial display mode. Display Data Length 3-line SPI; determines number bytes burst Data Default 0111b 0011111b 000000b 0000000b 111111b 1001111b 0000000b 0000b 0000b 111111b 0000000b 011b
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Preliminary
COMMAND DEFINITIONS
There basically types commands instruction set. first type contains single 8bit byte which comprised instruction itself also contain data values internal registers same byte. Precharge Timing command example this. Data Bits D[7:4] tell that this precharge timing command, while data bits [3:0] value precharge timing. other type command contains more bytes, which byte instruction, subsequent byte bytes contain data. GlobBright command good example. first byte specific value, indicates that next byte will contain brightness value. Most commands Instruction table selfexplanatory. few, however, need more clarification discussed below. Gamma Start Stream This instruction, "Gamma Start Stream" (11011111b tells controller that next bytes data used fill gamma correction tables bytes beginning with byte first entry gamma table (Gamma[0]) always zero cannot defined. entries must increasing minimum value with Gamma[1] being minimum value Gamma[15] being maximum value 225. Note that when transmitting this gamma data that interface determining data command must still command, erroneously interpreted pixel data. After reset, table defaults linear scale shown Table Screen Saver Start Stream After instruction "Screen Saver Start Stream" (E9h), driver expecting bytes setting registers defining screen saver variables shown Table eight registers outlined section discussing Screen Saver operation. Internally controller will keep track shift amount additional registers: SHFTX, SHFTY.
MXED301
Table Data Bytes follow "Gamma Start Stream" Command
Gamma Register Gamma1[7:0] Gamma2[7:0] Gamma3[7:0] Gamma4[7:0] Gamma5[7:0] Gamma6[7:0] Gamma7[7:0] Gamma8[7:0] Gamma9[7:0] Gamma10[7:0] Gamma11[7:0] Gamma12[7:0] Gamma13[7:0] Gamma14[7:0] Gamma15[7:0] D/Cn Reset State decimal Reset State binary 00001111b 00011110b 00101101b 00111100b 01001011b 01011010b 01101001b 01111000b 10000111b 10010110b 10100101b 10110100b 11000011b 11010010b 11100001b
Read Status Issuing Status Readback command (DEh) will result MXED301 returning status data bus. data returned shown Table Read Product Code Issuing Read Product Code command (20h) will result MXED301 returning product code data bus. This word consists bits product code, bits version code. Table
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MXED301
Preliminary
Table Registers written immediately following "screen saver start stream" command. Internal
Register Xmin Xmax Ymin Ymax STARTX STARTY DELX DELY D/Cn Reset State Xmin6 Xmax6 Ymin6 Ymax6 Xmin5 Xmax5 Ymin5 Ymax5 Xmin4 Xmax4 Ymin4 Ymax4 Xmin3 Xmax3 Ymin3 Ymax3 Xmin2 Xmax2 Ymin2 Ymax2 Xmin1 Xmax1 Ymin1 Ymax1 Xmin0 Xmax0 00000000b 00110000b
Ybmin0 00000000b Ymax0 01000000b 00110000b 00000000b 00000001b 00000001b
Table Data Returned following "Status Read" Command
Variable
Table Data Returned following "Product Code Read" Command
ariable Product Product alue eturned
DESCRIPTIONS CONTROL BITS
Following definitions control bits found instruction set. Black White Binary Mode defines memory written. Normally driver works 4-bit Grayscale mode. Therefore every 8-bit byte contains information about pixels. BW=1 part operates binary mode, each memory stores single each pixel. Note that this mode memory will used. This unused portion memory available user. WHT: Pixels
Setting results device outputting full gray-scale levels every pixel. Setting this effect contents DDRAM. This mode useful testing purposes, only when display modes 80:1 64:1. amplitude current defined GlobBright setting. Columns used defined Unused columns pads UC[4:0]. INV: Inverse Video mode will invert pixel data being read DDRAM. This will result inverse video effect display. effect valid multiplex modes.
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15280C
Preliminary
DOR: Data order defines incoming serial data transferred memory. incoming data byte will come with first. DOR=0 then incoming will placed into DDRAM's LSB. DOR=1 then incoming will placed DDRAM's MSB. Note that byte contains information about pixels when Grayscale mode. Setting will therefore swap pixels placed memory. Memory addressing mode defines incoming serial data will written horizontally vertically memory. data will written horizontally will increment after each byte. data will written vertically will increment after each byte. Note that binary mode eight horizontally adjacent pixels written when V=1. Gray-Scale mode horizontally adjacent pixels written when V=1. bit; display Setting activates display. DON=0 display off. state, Rows Columns switched ground, thus saving power. DDRAM remains active written DC/DC converter turned (since needed power display), increasing power savings. input internally disconnected that charge will bled from external capacitor. bit; vertical mirroring When MY=1, display mirrored vertically. Setting this does affect data DDRAM, rather turns drivers reverse order, thereby having immediate effect display. Pon: partial display mode defines display scan mode driver. Pon=0 number rows scanned determined MUX80 will either rows. Pon=1 number rows scanned determined register P[0]. section Display Scanning complete table partial display modes.
15280C
MXED301
Timing determines active output will grounded before after precharge. default, RT=0, sets output ground precharge, resulting very accurate grayscale control. With RT=1, output switches ground beginning period, coincident with start precharge. This useful monochrome mode increase display brightness small percentage. RR2: Reversing Rows bits will output order blocks with materially defined bottom pads. whole block turned around from user point view. This means that scanning order block reversed. more details, "Display Scanning" section. SAV: Screensaver defines Screensaver mode will activated. Before this asserted eight screen saver registers must written. FLS: Flash mode Setting enables flash mode. TPC[3:0]: Precharge Time Bits TPC[3:0] Precharge Time when APC=0. This time number clock pulses that Precharge will active. Turning Precharge particular column will only occur nonzero data stored DDRAM. IPC[5:0]: Precharge Current Amplitude This 6-bit register sets Precharge current amplitude using internal linear current converter. step size approximately total current adjusted step sizes from 39uA 2.5mA. S[6:0]; Display Start Line S[6:0] forms vertical offset between being displayed accessed memory. range pointer S[6:0] determined MUX80 either pointer S[6:0] outside range informa47
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MXED301
Preliminary
tion display wraps vertically. value S[6:0] effect contents DDRAM. B[6:0]: Partial Display Mode Line Offset B[6:0] stores offset between first field partial display (which always lines long) start line second field partial display. This pointer only active 16-line partial display mode. range register B[6:0] rows MUX80=0 rows MUX80=1 VC[2:0]: Compliance Voltage VC[2:0] sets compliance voltage Column Driver Active Driver. table "Operating DC/DC Converter" section.
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15280C
Preliminary
ELECTRICAL SPECIFICATIONS
MXED301
Table Absolute Maximum Conditions Stresses beyond "Absolute Maximum Ratings" cause damage device. These stress ratings only functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods permanently affect device reliability.
Symbol AVDD DVDD VBAT VROFF Parameter High Voltage Supply Analog Supply Digital Supply dc-to-dc converter supply Inactive return voltage Logic Level Inputs Ambient Temperature Storage Human Body Model -0.5 -0.5 -0.5 -0.5 -0.4 16.5 VPP-2 VDD+0.4 +150 Unit degC
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MXED301
Preliminary
Using on-board DC-DC controller Using external voltage supply 19.8 18.0 Frame Rate 120, VDDA =2.7V, 80:1 ICol 250µA VDDA =2.7V, ICol 50µA VDDA =2.7V, VDDA =2.7V, PWRDNn '0', 25°C VDDD =1.8V, 80:1 VDDD =1.8V, ICol 50µA VDDD =1.8V, VDDD =1.8V, '0', 25°C 20.0 20.0 20.2 22.0 VPP1.25 Unit degC KOhm KOhm kOhm
Table Recommended Operating Conditions
Symbol AVDD DVDD VBAT VROFF VROFF AGND, DGND, RGND, CGND RREF ROSC IDDA IDDA IDDA IDDA IDDD IDDD IDDD IDDD Parameter High Voltage Supply Analog Supply Digital Supply dc-to-dc converter supply Inactive return voltage Inactive return voltage Grounds Ambient Temperature Bias Setting Resistor Global Brightness Trim Internal Oscillator Bias Resistor Analog Supply Current Consumption Analog Supply Current Consumption Analog Supply Current Consumption Analog Supply Current Consumption Logic Supply Current Consumption Logic Supply Current Consumption Logic Supply Current Consumption Logic Supply Current Consumption
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15280C
Preliminary
Table Column Outputs
Symbol Parameter olumn urrent 2.744µA 1.08N Intra-chi olumn urrent absolute smatch olumn urrent mperature oeffi Resi stance Resi stance VPP=10V, IROW=20mA off, output connected VRowOff
IROW=10mA
MXED301
Operati ondi 4V<VC OL<VPP-1.5V; GloBrt 4V<VC OL<VPP-1.5V; GloBrt
OLmatch
OLTC
-0.5
+0.5
degC ohms
RROW
RROW
ohms
Table Digital Interface
Symbol Parameter Digital Input Logic High Level Digital Input Logic Level MXED301 Clock (CLK) frequency MXED301 Clock (CLK) frequency Serial Interface Clock Frequency (bits sec) Parallel Interface Clock Frequency (bytes sec) Frame Scan Rate Scan Rate High Output Output FRAME=F /(80*256*2)@ ROW=FFRAME A0.2 ROSC KOhm; Internal Oscillator Selected External Oscillator Selected Operating Conditions 0.8* -0.4 1.024 2.458 +0.4 0.2* 2.95 2.458 Unit
fCLK
fCLK
FRAME GATE GATE
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MXED301
Waiver Number Status current current previous Item Engineering Samples AVDD Column Driver: Exposure Current Setting Current
Preliminary
Description Parts delivered under shipper designation have been trimmed Datasheet conformance have been tested qualified. 3.3<=AVDD<=3.6V. DCDC start-up with lower AVDD. Approximately sample have DCDC fail AVDD<3.2V. setting (code A2h) value lower than previous setting must first (code A2/00) then value programmed. settings value greater than previous setting programmed specified. off-state current (PD=1,DON=0) typically 0.6mA prototype units. This process error. must limited maximum Rev.A prototypes. Prior turning display (code AFh), DCDC Converter must Power Mode (code 33h). Operation Normal DCDC Mode (code 30h) destroyed prototypes. power efficiency will less than ripple 1-2V. DCDC used (SELEXT=0,code=33h), Pre-Charge high voltage supply, VHB, must connected DCDC output VPP. Prior turning display (code AFh) ,the Precharge Time must programmed maximum (code 0Fh). lower Precharge Time will result display. External Supply used lieu DCDC (SELEXT=1); Adaptive Precharge used (APC=1,VHB=VROFF) VPP=VROFF Partial Display mode operate using chip DCDC converter, capacitor across must >47uF. external high voltage supply used (SELVPP=DVDD) instead, which case capacitor 4.7uF specified. range Partial Display Mode Line Offset, B(6:0), limited maximum value MUX80*16 specification 71d. Ymin=0 valid. other values Ymin operate correctly. Gamma values result value greater than programmed. RT=1, Gamma values will programmed. Read-Back: Cannot read back because MXED301 cannot drive needed 4mA. first buffered, then read will work. 6800: perform write, signal must held while R/Wn low. Interleave addressing assumes "Odd" addressing. That assumed that first row, then R40,R38,R41. cannot used display (MUX80=0). Pre-Charge Current: APC=0, pre-charge current, IPC, reflect current programmed into DAC. This fixed design released soon. APC=1 works well. Null: There null time between Strong-Discharge next Pre-Charge where Column Driver goes into high-Z specified 15280A, Figures Instead, Weak-Discharge current (3Ma AGND) remains until next Pre-Charge. does function. Parallel port does read back write requires 15mA drive D(7:0) With display (MUX80=1), ROW0 data will re-written with ROW79 data. MUX64 mode (MUX80=0) works fine. limited maximum operation.
previous
previous
DCDC Initialization
previous
Pre-Charge Initialization
previous
DCDC Operation
previous previous previous
Split Screen Line Offset Screen Saver Ymin Gamma Values
previous
Parallel Port
previous
Driver
previous
Column Driver
current
Interface
current current
Row0 Display Data Voltage
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15280C
Preliminary
Table Locations Referenced Origin Pads Labelled "N/C" Must Left Unconnected
RGND RGND R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31) R(32) R(33) R(34) R(35) R(36) R(37) BUMP SIZE (mm) X(mm) Y(mm) .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 6.320 -1.193 6.240 -1.193 6.160 -1.193 6.080 -1.193 6.000 -1.193 5.920 -1.193 5.840 -1.193 5.760 -1.193 5.680 -1.193 5.600 -1.193 5.520 -1.193 5.440 -1.193 5.360 -1.193 5.280 -1.193 5.200 -1.193 5.120 -1.193 5.040 -1.193 4.960 -1.193 4.880 -1.193 4.800 -1.193 4.720 -1.193 4.640 -1.193 4.560 -1.193 4.480 -1.193 4.400 -1.193 4.320 -1.193 4.240 -1.193 4.160 -1.193 4.080 -1.193 4.000 -1.193 3.920 -1.193 3.840 -1.193 3.760 -1.193 3.680 -1.193 3.600 -1.193 3.520 -1.193 3.440 -1.193 3.360 -1.193 3.280 -1.193 3.200 -1.193 R(38) R(39) DUMMY RGND RGND DGND AGND VROFF VROFF DUMMY VGATE AVDD AVDD DVDD DVDD ROWSEL MUX80 SELVPP UNC0 UNC1 UNC2 UNC3 UNC4 MPUsel NOKIA SERsel SELEXT D(0) D(1) D(2) D(3)
MXED301
BUMP SIZE (mm) X(mm) Y(mm) .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 3.120 -1.193 3.040 -1.193 2.960 -1.193 2.880 -1.193 2.800 -1.193 2.720 -1.193 2.640 -1.193 2.560 -1.193 2.480 -1.193 2.400 -1.193 2.320 -1.193 2.240 -1.193 2.160 -1.193 2.080 -1.193 2.000 -1.193 1.920 -1.193 1.840 -1.193 1.760 -1.193 1.680 -1.193 1.600 -1.193 1.520 -1.193 1.440 -1.193 1.360 -1.193 1.280 -1.193 1.200 -1.193 1.120 -1.193 1.040 -1.193 0.960 -1.193 0.880 -1.193 0.800 -1.193 0.720 -1.193 0.640 -1.193 0.560 -1.193 0.480 -1.193 0.400 -1.193 0.320 -1.193 0.240 -1.193 0.160 -1.193 0.080 -1.193 0.000 -1.193
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MXED301
D(4) D(5) D(6) D(7) SCLH SDATA SCLK DGND CMDn SCEn RESn DGND DGND DGND DGND DGND ROSC RREF AGND DGND DVDD VROFF VROFF RGND RGND RGND R(40) R(41) R(42)
Preliminary
R(43) R(44) R(45) R(46) R(47) R(48) R(49) R(50) R(51) R(52) R(53) R(54) R(55) R(56) R(57) R(58) R(59) R(60) R(61) R(62) R(63) R(64) R(65) R(66) R(67) R(68) R(69) R(70) R(71) R(72) R(73) R(74) R(75) R(76) R(77) R(78) R(79) RGND RGND Dummy BUMP SIZE (mm) X(mm) Y(mm) .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 -3.280 -1.193 -3.360 -1.193 -3.440 -1.193 -3.520 -1.193 -3.600 -1.193 -3.680 -1.193 -3.760 -1.193 -3.840 -1.193 -3.920 -1.193 -4.000 -1.193 -4.080 -1.193 -4.160 -1.193 -4.240 -1.193 -4.320 -1.193 -4.400 -1.193 -4.480 -1.193 -4.560 -1.193 -4.640 -1.193 -4.720 -1.193 -4.800 -1.193 -4.880 -1.193 -4.960 -1.193 -5.040 -1.193 -5.120 -1.193 -5.200 -1.193 -5.280 -1.193 -5.360 -1.193 -5.440 -1.193 -5.520 -1.193 -5.600 -1.193 -5.680 -1.193 -5.760 -1.193 -5.840 -1.193 -5.920 -1.193 -6.000 -1.193 -6.080 -1.193 -6.160 -1.193 -6.240 -1.193 -6.320 -1.193 -6.320 1.193 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 -0.080 -1.193 -0.160 -1.193 -0.240 -1.193 -0.320 -1.193 -0.400 -1.193 -0.480 -1.193 -0.560 -1.193 -0.640 -1.193 -0.720 -1.193 -0.800 -1.193 -0.880 -1.193 -0.960 -1.193 -1.040 -1.193 -1.120 -1.193 -1.200 -1.193 -1.280 -1.193 -1.360 -1.193 -1.440 -1.193 -1.520 -1.193 -1.600 -1.193 -1.680 -1.193 -1.760 -1.193 -1.840 -1.193 -1.920 -1.193 -2.000 -1.193 -2.080 -1.193 -2.160 -1.193 -2.240 -1.193 -2.320 -1.193 -2.400 -1.193 -2.480 -1.193 -2.560 -1.193 -2.640 -1.193 -2.720 -1.193 -2.800 -1.193 -2.880 -1.193 -2.960 -1.193 -3.040 -1.193 -3.120 -1.193 -3.200 -1.193
BUMP SIZE (mm) X(mm) Y(mm)
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15280C
Preliminary
DGND COL_OUT(127) COL_OUT(126) COL_OUT(125) COL_OUT(124) COL_OUT(123) COL_OUT(122) COL_OUT(121) COL_OUT(120) COL_OUT(119) COL_OUT(118) COL_OUT(117) COL_OUT(116) COL_OUT(115) COL_OUT(114) COL_OUT(113) COL_OUT(112) COL_OUT(111) COL_OUT(110) COL_OUT(109) COL_OUT(108) COL_OUT(107) COL_OUT(106) COL_OUT(105) COL_OUT(104) COL_OUT(103) COL_OUT(102) COL_OUT(101) COL_OUT(100) COL_OUT(99) COL_OUT(98) COL_OUT(97) COL_OUT(96) CGND COL_OUT(95) COL_OUT(94) COL_OUT(93) COL_OUT(92) COL_OUT(91) COL_OUT(90) BUMP SIZE (mm) X(mm) Y(mm) .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 -6.240 1.193 -6.160 1.193 -6.080 1.193 -6.000 1.193 -5.920 1.193 -5.840 1.193 -5.760 1.193 -5.680 1.193 -5.600 1.193 -5.520 1.193 -5.440 1.193 -5.360 1.193 -5.280 1.193 -5.200 1.193 -5.120 1.193 -5.040 1.193 -4.960 1.193 -4.880 1.193 -4.800 1.193 -4.720 1.193 -4.640 1.193 -4.560 1.193 -4.480 1.193 -4.400 1.193 -4.320 1.193 -4.240 1.193 -4.160 1.193 -4.080 1.193 -4.000 1.193 -3.920 1.193 -3.840 1.193 -3.760 1.193 -3.680 1.193 -3.600 1.193 -3.520 1.193 -3.440 1.193 -3.360 1.193 -3.280 1.193 -3.200 1.193 -3.120 1.193 COL_OUT(89) COL_OUT(88) COL_OUT(87) COL_OUT(86) COL_OUT(85) COL_OUT(84) COL_OUT(83) COL_OUT(82) COL_OUT(81) COL_OUT(80) COL_OUT(79) COL_OUT(78) COL_OUT(77) COL_OUT(76) COL_OUT(75) COL_OUT(74) COL_OUT(73) COL_OUT(72) COL_OUT(71) COL_OUT(70) COL_OUT(69) COL_OUT(68) COL_OUT(67) COL_OUT(66) COL_OUT(65) COL_OUT(64) CGND CGND DGND DGND AGND DVDD DVDD AVDD AVDD
MXED301
BUMP SIZE (mm) X(mm) Y(mm) .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 -3.040 1.193 -2.960 1.193 -2.880 1.193 -2.800 1.193 -2.720 1.193 -2.640 1.193 -2.560 1.193 -2.480 1.193 -2.400 1.193 -2.320 1.193 -2.240 1.193 -2.160 1.193 -2.080 1.193 -2.000 1.193 -1.920 1.193 -1.840 1.193 -1.760 1.193 -1.680 1.193 -1.600 1.193 -1.520 1.193 -1.440 1.193 -1.360 1.193 -1.280 1.193 -1.200 1.193 -1.120 1.193 -1.040 1.193 -0.960 1.193 -0.880 1.193 -0.800 1.193 -0.720 1.193 -0.640 1.193 -0.560 1.193 -0.480 1.193 -0.400 1.193 -0.320 1.193 -0.240 1.193 -0.160 1.193 -0.080 1.193 0.000 0.080 1.193 1.193
15280C
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MXED301
DVDD DVDD AGND AGND DGND DGND CGND CGND COL_OUT(63) COL_OUT(62) COL_OUT(61) COL_OUT(60) COL_OUT(59) COL_OUT(58) COL_OUT(57) COL_OUT(56) COL_OUT(55) COL_OUT(54) COL_OUT(53) COL_OUT(52) COL_OUT(51) COL_OUT(50) COL_OUT(49) COL_OUT(48) COL_OUT(47) COL_OUT(46) COL_OUT(45) COL_OUT(44) COL_OUT(43) COL_OUT(42) COL_OUT(41) COL_OUT(40) COL_OUT(39) COL_OUT(38) COL_OUT(37) COL_OUT(36) COL_OUT(35)
Preliminary
COL_OUT(34) COL_OUT(33) COL_OUT(32) CGND COL_OUT(31) COL_OUT(30) COL_OUT(29) COL_OUT(28) COL_OUT(27) COL_OUT(26) COL_OUT(25) COL_OUT(24) COL_OUT(23) COL_OUT(22) COL_OUT(21) COL_OUT(20) COL_OUT(19) COL_OUT(18) COL_OUT(17) COL_OUT(16) COL_OUT(15) COL_OUT(14) COL_OUT(13) COL_OUT(12) COL_OUT(11) COL_OUT(10) COL_OUT(9) COL_OUT(8) COL_OUT(7) COL_OUT(6) COL_OUT(5) COL_OUT(4) COL_OUT(3) COL_OUT(2) COL_OUT(1) COL_OUT(0) BUMP SIZE (mm) X(mm) Y(mm) .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 3.360 3.440 3.520 3.600 3.680 3.760 3.840 3.920 4.000 4.080 4.160 4.240 4.320 4.400 4.480 4.560 4.640 4.720 4.800 4.880 4.960 5.040 5.120 5.200 5.280 5.360 5.440 5.520 5.600 5.680 5.760 5.840 5.920 6.000 6.080 6.160 6.240 6.320 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 .050 .090 0.160 0.240 0.320 0.400 0.480 0.560 0.640 0.720 0.800 0.880 0.960 1.040 1.120 1.200 1.280 1.360 1.440 1.520 1.600 1.680 1.760 1.840 1.920 2.000 2.080 2.160 2.240 2.320 2.400 2.480 2.560 2.640 2.720 2.800 2.880 2.960 3.040 3.120 3.200 3.280 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193 1.193
BUMP SIZE (mm) X(mm) Y(mm)
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15280C
Preliminary
Figure Specification
MXED301
DIGIT ASSEMBLY DATE CODE
°CHAMFER
SYMBOL 0.085 0.020 0.064 0.024 0.094 0.098 2.17 0.024 0.028 0.50 0.068 0.072 0.031 0.035 0.60 2.38 0.60 2.59 0.70
0.79 0.90 35.00 35.10 34.90 29.85 30.00 30.15 34.90 35.00 35.10 29.85 30.00 31.75 30.15
JEDEC
0.05 0.025 0.025 31.75 0.635 0.635
15280C
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MXED301
Preliminary
BALL AF13 AC15 AE13 AC14 AD13 AF12 AE12 AD12 AC13 AF11 AE11 AD11 AC12 AF10 AC10 AE10 AC11 AD10 R(43) R(44) R(45) R(46) R(47) R(48) R(49) R(50) R(51) R(52) R(53) R(54) R(55) R(56) R(57) R(58) R(59) R(60) R(61) R(62) R(63) R(64) R(65) R(66) R(67) R(68) R(69) R(70) R(71) R(72) R(73) R(74) R(75) R(76) R(77) R(78) R(79) RGND RGND BALL
Table Locations Pads Labelled "N/C" Must Left Unconnected. Pads listed bonded.
RGND RGND R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31) R(32) R(33) R(34) R(35) R(36) R(37) BALL AC26 AC25 AC24 AD26 AD25 AD24 AE26 AE25 AD23 AE24 AF26 AF25 AD22 AE23 AD21 AE22 AA26 AD20 AA25 AF24 AE21 AF23 AD19 AE20 R(38) R(39) RGND RGND DGND AGND VROFF VROFF VGATE AVDD AVDD DVDD DVDD MUX80 SELVPP UNC0 UNC1 UNC2 UNC3 UNC4 MPUsel NOKIA SERsel SELEXT D(0) D(1) D(2) D(3) BALL AF22 AD18 AE19 AF20 AF19 AD17 AB23 AE18 AC23 AF18 AE17 AC21 AD16 AC20 AE16 AC19 AF17 AF16 AD15 AE15 AC18 AF15 AC16 AD14 AE14 AC17 AF14 D(4) D(5) D(6) D(7) SCLH SDATA SCLK DGND; CMDn SCEn RESn DGND DGND DGND DGND DGND ROSC RREF AGND; DGND; DVDD VROFF VROFF RGND RGND RGND R(40) R(41) R(42)
ROWSEL AC22
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15280C
Preliminary
COL_OUT(127) COL_OUT(126) COL_OUT(125) COL_OUT(124) COL_OUT(123) COL_OUT(122) COL_OUT(121) COL_OUT(120) COL_OUT(119) COL_OUT(118) COL_OUT(117) COL_OUT(116) COL_OUT(115) COL_OUT(114) COL_OUT(113) COL_OUT(112) COL_OUT(111) COL_OUT(110) COL_OUT(109) COL_OUT(108) COL_OUT(107) COL_OUT(106) COL_OUT(105) COL_OUT(104) COL_OUT(103) COL_OUT(102) COL_OUT(101) COL_OUT(100) COL_OUT(99) COL_OUT(98) COL_OUT(97) COL_OUT(96) CGND COL_OUT(95) COL_OUT(94) COL_OUT(93) COL_OUT(92) COL_OUT(91) COL_OUT(90) BALL COL_OUT(89) COL_OUT(88) COL_OUT(87) COL_OUT(86) COL_OUT(85) COL_OUT(84) COL_OUT(83) COL_OUT(82) COL_OUT(81) COL_OUT(80) COL_OUT(79) COL_OUT(78) COL_OUT(77) COL_OUT(76) COL_OUT(75) COL_OUT(74) COL_OUT(73) COL_OUT(72) COL_OUT(71) COL_OUT(70) COL_OUT(69) COL_OUT(68) COL_OUT(67) COL_OUT(66) COL_OUT(65) COL_OUT(64) CGND CGND DGND DGND AGND DVDD DVDD AVDD AVDD BALL DVDD DVDD AGND AGND DGND DGND CGND CGND COL_OUT(63) COL_OUT(62) COL_OUT(61) COL_OUT(60) COL_OUT(59) COL_OUT(58) COL_OUT(57) COL_OUT(56) COL_OUT(55) COL_OUT(54) COL_OUT(53) COL_OUT(52) COL_OUT(51) COL_OUT(50) COL_OUT(49) COL_OUT(48) COL_OUT(47) COL_OUT(46) COL_OUT(45) COL_OUT(44) COL_OUT(43) COL_OUT(42) COL_OUT(41) COL_OUT(40) COL_OUT(39) COL_OUT(38) COL_OUT(37) COL_OUT(36) COL_OUT(35) BALL
MXED301
COL_OUT(34) COL_OUT(33) COL_OUT(32) CGND COL_OUT(31) COL_OUT(30) COL_OUT(29) COL_OUT(28) COL_OUT(27) COL_OUT(26) COL_OUT(25) COL_OUT(24) COL_OUT(23) COL_OUT(22) COL_OUT(21) COL_OUT(20) COL_OUT(19) COL_OUT(18) COL_OUT(17) COL_OUT(16) COL_OUT(15) COL_OUT(14) COL_OUT(13) COL_OUT(12) COL_OUT(11) COL_OUT(10) COL_OUT(9) COL_OUT(8) COL_OUT(7) COL_OUT(6) COL_OUT(5) COL_OUT(4) COL_OUT(3) COL_OUT(2) COL_OUT(1) COL_OUT(0) BALL
15280C
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MXED301
ORDERING INFORMATION
Ordering Number 15201-00 15226-00 15239-00 Package
Preliminary
Gold Bumped Waffle Trays Gold Bumped Wafer Form prototype only
Clare Micronix Integrated Systems, Inc., Clare, Inc., assume responsibility this product infringements patents trademarks other rights third parties resulting from use. license granted under patents, patent rights trademarks Clare Micronix Integrated Systems, Inc., Clare, Inc., company(s) reserve right make changes specifications time without notice. Accordingly, reader cautioned verify that data sheet current before placing orders.
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15280C
Preliminary
APPLICATION INFORMATION
Figure Configuration Examples
MXED301
Voltage Analog Supply Logic Supply
DVDD DGND DVDD DGND
AVDD DVDD SELEXT MUX80 SERsel CMDn SCEn SCLK NOKIA SA0, SDAOUT SDAIN MPUSEL RESn
Rref
RREF
VDDD
High
COL(0 -127) COLGND
High
Microcontroller
MXED301 Polymer Display
ROW(0 -79) RGND
High
D(0-7) EOF,
VBATT
Connect High
PADS(110-111,317-318)
Rosc VROFF Parts List 100nF, X7R, 16WVDC 4.7uF, 35WVDC
ROSC
4.7uF, 35WVDC TBDuF, 35WVDC TBDuF, 35WVDC =SchottkyDiode, 20V, Semi SL02 Toshiba CRS02
VGATE
VPPSEL Pads(98-102) UNC(4:0) AGND DGND
VROFF
10uH, Rdc=0.4ohm,Toko974AS -100M
NMOS FET, 20V, 0.25ohm, Vgs(1A)=2.5 VishaySil400DL Fairchild FDG311N RREF 20K,1% 20K, ROSC SELECT
Series Microcontroller System Interface Diagram; with Internal Oscillator DCDC Converter Supply
15280C
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MXED301
Preliminary
Voltage Analog Supply Logic Supply
DVDD
High
Connect High VDDD D(0-7) Connect
AVDD DVDD ROWSEL PWRDNn OSCSel SerialSel CMDn SCEn SCLK NOKIA SA0, SDAOUT SDAIN MPUSEL RESETn D(0-7) EOF, PADS(110-111)
Rref
RREF
COL(0 -127) COLGND
MXED301 Polymer Display
ROW(0 -79) RGND
Decode
6800 Series Microcontroller
VBATT
PADS(317-318)
High Rosc VROFF
Parts List 100nF, X7R, 16WVDC 4.7uF, 35WVDC 4.7uF, 35WVDC TBDuF, 35WVDC TBDuF, 35WVDC VROFF
VGATE
SelVPP PADS(98-102) UNC(4:0) AGND DGND
=SchottkyDiode, 20V, Semi SL02 Toshiba CRS02 10uH, Rdc=0.4ohm,Toko974AS -100M NMOS FET, 20V, 0.25ohm,Vgs(1A)= VishaySil400DL Fairchild FDG311N RREF 20K,1% 20K,1% ROSC Select Resistor
6800 Series Microcontroller System Interface Diagram; External Oscillator Internal DCDC Converter Supply
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15280C
Preliminary
MXED301
Voltage Analog Supply Logic Supply
DGND DGND DGND DVDD
High
Connect High DGND RESETn
AVDD DVDD ROWSEL PWRDNn SelEXT SerialSel CMDn SCEn SCLK NOKIA SA0, SDAOUT SDAIN MPUSEL RESETn D(0-7)
Rref
RREF
COL(0 -127) COLGND
MXED301 Polymer Display
ROW(0 -79) RGND
8080 Series Microcontroller
D(0-7) Connect High
EOF, PADS(110-111) PADS(317-318) Rosc
Parts List VROFF
used used used 35WVDC 35WVDC
Connect High Voltage Analog Supply DVDD
VGATE
SelVPP PADS(98-102)
VROFF
used used used RREF ROSC Select Resistor
UNC(4:0)
AGND DGND
8080 Series Microcontroller System Interface Diagram; with External Oscillator External High Voltage Power Supply
15280C
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MXED301
Preliminary
APPLICATION INFORMATION
Figure Programming Examples Write data RAM: First define mirror pins. Load data written: BW/Gray, Inverse(E), DOR, ,Xe, Write data D(7;0). This done time while display running (DON=1). display will updated after completing previous scan ROW(0) display (DON=0), data will displayed upon DON=1, starting ROW(0). Write DON=1, already Code Example: Gray Scale =1=MSB first Xe=Column 127, NOTE: defaults Column0 Ye=Row79, NOTE: defaults Row0 DATA D/C=1=Data DON=1=Turn display Flash mode: Write data above. Write FON, FOFF Write FLS=1 Write DON=1, already Code Example: FLS=1=Turn Flash mode. NOTE: Using default FON,FOFF. Turn display.
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15280C
Preliminary
MXED301
Partial Display/Split Screen Format: Write data above. Write P(0), L(6:0), C(6;0)
Write Pon=1
Write DON=1, already Code Example: first line offset between Field Field rows. Partial Display mode Fields
Screen Saver Mode:
Write data above. Write parameters: (CW, FON, FOFF). Send command start stream 011101001; controller expects next bytes follows: Xboxmin
Xboxmax
Yboxmin Yboxmax StartX StartY DeltaX DeltaY Send Command, 011101011. Write DON=1, already Code Example: Start Screen Saver registers Xboxmin=0 Xboxmax=32 Yboxmin=0 Yboxmax=20 Start Column must between Start must between Delta Delta Screen Saver
15280C
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Worldwide Sales Offices
AMERICAS Headquarters Clare Micronix Columbia Aliso Viejo, 92656-1490 Tel: 1-949-831-4622 Fax: 1-949-831-4628
EUROPE European Headquarters Clare Bampslaan B-3500 Hasselt (Belgium) Tel: 32-11-300868 Fax: 32-11-300890 France Clare France Sales Lead route Versailles 91160 Champlan France Tel: Fax: Germany ELrep Kieshofstrasse D-71522 Backnang Germany Tel: 7191 7333 Fax: 7191 7333 Italy C.L.A.R.E.s.a.s. Colombo 10/A 1-20066 Melzo (Milano) Tel: 39-02-95737160 Fax: 39-02-95738829 Sweden Clare Sales Comptronic S-16329 Spanga Tel: 46-862-10370 Fax: 46-862-10371 United Kingdom Clare Sales Marco Polo House Cook Bindon Road Taunton UK-Somerset Tel: 44-1-823 352541 Fax: 44-1-823 352797 ASIA PACIFIC Asian Headquarters Clare Room N1016, Chia-Hsin, Bldg. 10F, Sec. Chung Shan North Road Taipei, Taiwan R.O.C. Tel: 886-2-2523-6368 Fax: 886-2-2523-6369 Japan Unidux 5-1-21, Kyonan-cho Musahino-Shi Tokyo, 180-8611 Japan Tel: 81-422-32-4500 Fax: 81-422-31-2050 Korea Lumitech Kumho Livingstel Sungnam-si, Kyounggi-Do Pundang, 463-050 Korea Tel: 82-31-709-6513 Fax: 82-31-709-6514
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