MX67L12816J3 MX67L9632J3 MX67L9632J3 MX67L12816J3
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ADVANCED INFORMATION MX67L12816J3/MX67L9632J3
32M-BIT [4Mb Flash Plus 96M-BIT [12Mb CMOS, 16M-BIT [2Mb Flash Plus 128M-BIT [16Mb CMOS Flash Plus MonoChip
2.7V 3.6V operation voltage (Output power supply 1.65V-1.95V 2.7V-3.6V through VCCQ pin) Separate banks data code MX67L9632J3: 32Mb(x8/x16) Flash Bank data 96Mb(x8/x16) Bank code MX67L12816J3: 16Mb(x8/x16) Flash Bank data 128Mb(x8/x16) Bank code Block Structure Flash Bank MX67L9632J3 Thirty-two 128K byte blocks Bank MX67L9632J3 Ninety-six 128K byte blocks Flash Bank MX67L12816J3 Sixteen 128K byte blocks Bank MX67L12816J3 Hundred Twenty-eight 128K byte blocks Fast random page mode access time 150/25 Read Access Time 128-bit Protection Register 64-bit Unique Device Identifier 64-bit User Programmable Cells 32-Byte Write Buffer us/byte Effective Programming Time Enhanced Data Protection Features Absolute Protection with VPEN Flexible Block Locking Block Erase/Program Lockout during Power Transitions Operation Temperature:-40° Buffer Command) Program/Erase Cycles MX67L12816J3 160K Total Min. Erase Cycle (for Flash Bank) Minimum Erase Cycles Block 128K Total Min. Erase Cycle Bank 1,000 Minimum Erase Cycles block MX67L9632J3 320K Total Min. Erase Cycle (for Flash Bank) Minimum Erase Cycles Block Total Min. Erase Cycle Bank 1,000 Minimum Erase Cycles block
SOFTWARE FEATURE
Suppor Common Flash Interface (CFI) (for MX67L9632J3) Flash device parameters stored device provide host system access. Automation Suspend Options Block Erase Suspend Read Block Erase Suspend Program Program Suspend Read
HARDWARE FEATURE
Select byte address when device byte mode. used word mode. Indicates status internal state machine. VPEN Erase /Program/ Block Look enable. VCCQ output buffer power supply, control device output voltage.
PERFORMANCE
power dissipation 10mA active current 50uA standby current deep power-down current High Performance Block erase time: typ. Byte programming time: 210us typ. Block programming time: 0.8s typ. (using Write
PACKAGING
56-Lead TSOP 64-ball Flip Chip
TECHNOLOGY
0.25u 2bits cell NBit Flash Technology
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GENERAL DESCRIPTION
MX67L9632J3 single chip which consists Flash EPROM MX67L12816J3 single chip which consists Flash 128M EPROM. MX67L9632J3 organized 32Mb(x8/x16) flash bank 96Mb(x8/ x16) bank; MX67L12816J3 organized 16Mb(x8/x16) flash bank 128Mb(x8/x16) bank. MXIC's Flash plus MonoChip offers most costeffective reliable read/write non-volatile random access memory. MX67L12816J3 MX67L9632J3 packaged TSOP 64-ball CSP. designed reprogrammed erased system standard EPROM programmers. standard MX67L12816J3 MX67L9632J3 offers random access time fast 120ns page mode read fast 25ns, allowing operation high-speed microprocessors without wait states. eliminate conten-
tion, MX67L12816J3 MX67L9632J3 three separate chip enable (CE0, CE1, CE2) output enable controls. MXIC's MonoChip augment EPROM functionality with in-circuit electrical erasure programming. MX67L12816J3 MX67L9632J3 uses command register manage this functionality. MXIC's MonoChip technology reliably stores memory contents even after 10,000 erase program cycles Flash bank 1,000 cycles bank. MXIC cell designed optimize erase program mechanisms utilizing dielectric's character trap release charges from layer. MX67L12816J3 MX67L9632J3 uses 2.7V 3.6V supply perform High Reliability Erase auto Program/ Erase algorithms. highest degree latch-up protection achieved with MXIC's proprietary non-epi process. Latch-up protection proved stresses milliamps address data from +1V.
CONFIGURATION TSOP(14mm 20mm)
VPEN RESET A24* VCCQ BYTE
Notes: exists MX67L12816J3. connect (NC) MX67L9632J3.
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ball Easy (10x13x1.2mm, 1.0mm-ball pitch)
VPEN
RESET
BYTE
VCCQ
A24*
10mm
Notes: Address only valid MX67L12816J3. Otherwise, connect (NC). Don't (DU) pins refer pins that should connected.
DESCRIPTION
SYMBOL A1~A24 Q0~Q15 RESET BYTE VPEN VCCQ
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NAME Byte Select Address Address Input (MX67L9632J3:A0~A23, MX67L12816J3:A0~A24) Data Inputs/Outputs Write Enable Input Output Enable Input Reset/Deep Power Down mode STATUS Byte Mode Enable ERASE/PROGRAM/BLOCK Lock Enable Output Buffer Power Supply Device Power Supply Device Ground Connected Internally Don't
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CE0, CE1, Chip Enable Input
MX67L12816J3/MX67L9632J3
BLOCK DIAGRAM
RESET
CONTROL INPUT LOGIC
PROGRAM/ERASE HIGH VOLTAGE
WRITE STATE MACHINE (WSM)
Flash ARRAY ARRAY
ARRAY SOURCE
STATE REGISTER
X-DECODER
ADDRESS LATCH
A0-A24
BUFFER
Y-PASS GATE
COMMAND DATA DECODER
Y-DECODER
SENSE AMPLIFIER
DATA
COMMAND DATA LATCH
PROGRAM DATA LATCH
Q0-Q15
BUFFER
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FIGURE Block Architecture
Flash memory reads erases writes in-system local CPU. cycles from flash memory conform standard microprocessor cycles.
A[23-0]: MX67L9632J3 FFFFFF FE0000 128-Kbyte Block A[23-1]: MX67L9632J3 7FFFFF 7F0000 64-Kword Block Mbit Flash bank
BFFFFF BE0000 128-Kbyte Block 5FFFFF 5F0000
64-Kword Block
03FFFF 020000 01FFFF 000000 128-Kbyte Block 128-Kbyte Block 01FFFF 010000 00FFFF 000000
64-Kword Block 64-Kword Block
Mbit bank
Byte Mode (x8)
Word Mode (x16)
A[24-0]: MX67L12816J3 11FFFFF 11E0000 128-Kbyte Block
A[24-1]: MX67L12816J3 8FFFFF 8F0000 64-Kword Block Mbit Flash bank
FFFFFF FE0000 128-Kbyte Block 7FFFFF 7F0000
64-Kword Block
03FFFF 020000 01FFFF 000000 128-Kbyte Block 128-Kbyte Block 01FFFF 010000 00FFFF 000000
64-Kword Block 64-Kword Block
Mbit bank
Byte Mode (x8)
Word Mode (x16)
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TABLE Chip Enable Truth Table
DEVICE Enabled Disabled Disabled Disabled DEVICE Enabled Enabled Enabled Disabled
NOTE: Single-chip applications, strapped GND.
TABLE Operations
Mode Notes RESET 0,1,2 Read Array Output Disable Standby Reset/Power-Down Mode Read Identifier Codes Read Query Read Status (WSM off) Read Status (WSM Enabled Enabled Enabled Enabled Figure Table Q7=D Q15-8=High Q6-0= High Write 6,10,11 Enabled VPENH Note High Z(7) Note High Z(7) 4,5,6 Enabled Enabled Disabled Address VPEN High High High (default mode) High Z(7) High Z(7)
NOTES: Table page valid configurations. should never enabled simultaneously. refers Q0-Q7 BYTE Q0-Q15 BYTE high. Refer Characteristics. When VPEN VPENLK memory contents read, altered. control address pins, VPENLK VPENH VPEN Characteristics VPENLK VPENH voltages. default mode, when executing internal block erase, program, lock-bit configuration algorithms. when busy, block erase suspend mode (with programming inactive), program suspend mode, reset/power-down mode. High will with external pull-up resistor. Section "Read Identifier Codes" read identifier code data. Section "Read Query Mode Command" read query data. 10.Command writes involving block erase, program, lock-bit configuration reliably executed when VPEN= VPENH within specification. 11.Refer Table page valid during write operation.
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FUNCTION
device includes on-chip program/erase control circuitry. Write State Machine (WSM) controls block erase byte/word/page program operations. Operational modes selected commands written Command User Interface (CUI). Status Register indicates status when successfully completes desired program block erase operation. Deep Power-down mode enabled when RESET GND, minimizing power consumption.
OUTPUT DISABLE
When VIH, output from devices disabled. Data input/output high-impedance(High-Z) state.
STANDBY
When CE0, disable device (see table1) place standby mode. power consumption this device reduced. Data input/output highimpedance(High-Z) state. memory deselected during block erase, program lock-bit configuration, internal control circuits remain active device consume normal active power until operation completes.
READ
device three read modes, which accesses memory array, Device Identifier Status Register independent VPEN voltage. appropriate read command required written CUI. Upon initial device power after exit from deep power down, device automatically resets read array mode. read array mode, level input CE0, CE1, high level input RESET, address signals address inputs (A24-A0) output data addressed location data input/ output (Q15~Q0). When reading information read array mode, device defaults asynchronous page mode. this state, data internally read stored high-speed page buffer. A2:0 addresses data page buffer. page size words bytes. Asynchronous word/byte mode supported with additional commands required. MX67L12816J3, please aware trying access non-existed array (out 144Mb) will result output tri-state.
DEEP POWER-DOWN
When RESET VIL, device deep powerdown mode power consumption substantially low. During read modes, memory deselected data input/output high-impedance(High-Z) state. After return from power-down, reset Read Array Status Register value 80H. During block erase program lock-bit configuration modes, RESET will abort either operation. Memory array data block being altered become invalid. default mode, transitions remains maximum time tPLPH+tPHRH until reset operation complete. Memory contents being altered longer valid; data partially corrupted after program partially altered after erase lockbit configuration. Time tPHWL required after RESET goes logic-high (VIH) before another command written.
WRITE
Writes enables reading memory array data, device identifiers reading clearing Status Register when VPEN=VPENH block erasure program lock-bit configuration. written when device enable, active high level. Address data latched earlier rising edge Standard micro-processor write timings used.
READ QUERY
read query operation outputs block status information, (Common Flash Interface) string, system interface information, device geometry information MXIC extended query information.
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COMMAND DEFINITIONS
Device operations selected writing specific address data sequences into CUI. Table defines valid register command sequences. When VPEN<VPENLK only read operations from status register, query, indentifier code blocks enabled. When VPEN=VPENH enables block erase program lock-bit configuration operations.
TABLE Command Definitions
Command Cycles Req'd. Oper(2) Read Array Read Identifier Codes Read Query Read Status Register Clear Status Register Write Buffer Word/Byte Program Block Erase Block Erase, Program Suspend Block Erase, Program Resume Configuration Block Lock-Bit Clear Block Lock-Bit Protection Program Write Write Write Write Write Write Write Write Write 8,9,10 11,12 Write Write Write Write Write Write Write Write Write Addr(3) Data(4,5) Write Write Write Read Read Read Oper(2) Addr(3) Data(4,5) Notes First Cycle Second Cycle
NOTES: operations defined Table valid address within device. Address within block. Identifier Code Address: Figure Table Query database Address. Address memory location programmed. Data written read configuration register. This data presented device 16-1 other address inputs ignored. Data read from Identifier Codes. Data read from Query database. Data read from status register. Table description status register bits.
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Data programmed location Data latched rising edge Configuration Code. upper byte data (Q8-Q15) during command writes "Don't Care" operation. Following Read Identifier Codes command, read operations access manufacturer, device block lock codes. Section read identifier code data. running, only valid; Q15-Q8 Q6-Q0 float, which places them high impedance state. After Write Buffer command issued check make sure buffer available writing. 8.The number bytes/words written Write Buffer where byte/word count argument. Count ranges this device byte mode word mode 0000H =000FH. third consecutive cycles, determined writing data into Write Buffer. Confirm command (D0H) expected after exactly write cycles; other command that point sequence aborts write buffer operation. Please Figure "Write Buffer Flowchart" additional information. write buffer erase operation does begin until Confirm command (D0h) issued. 10.Attempts issue block erase program locked block. 11.Either recognized byte/word program setup. 12.Program suspends issued after either Write-to-Buffer Word-/Byte-Program operation initiated. 13.The clear block lock-bits operation simultaneously clears block lock-bits.
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FIGURE 2-1. Device Identifier Code Memory Map(MX67L9632J3)
A[23-1]:MX67L9632J3
Word Address 7FFFFF
Block Reserved Future Implementation
7F0003 Block Lock Configuration 7F0002 Reserved Future Implementation 7F0000 7EFFFF 5FFFFF (Block through 126) Block Reserved Future Implementation 5F0003 Block Lock Configuration 5F0002 Reserved Future Implementation 5F0000 5EFFFF 01FFFF Reserved Future Implementation 010003 010002 Block Lock Configuration Reserved Future Implementation Block Reserved Future Implementation 000004 000003 000002 000001 Manufacturer Code 000000 Block Lock Configuration Device Code (Block through Block 128Mbit 32Mbit Flash Bank
96Mbit Bank
010000 00FFFF
NOTE: used either mode when obtaining these identifier codes. Data always given byte mode (upper byte contains 00h).
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FIGURE 2-2. Device Identifier Code Memory Map(MX67L12816J3)
A[24-1]:MX67L12816J3
Word Address 8FFFFF
Block Reserved Future Implementation
8F0003 Block Lock Configuration 8F0002 Reserved Future Implementation 8F0000 8EFFFF 7FFFFF (Block through 142) Block Reserved Future Implementation 7F0003 Block Lock Configuration 7F0002 Reserved Future Implementation 7F0000 7EFFFF 01FFFF Reserved Future Implementation 010003 010002 Block Lock Configuration Reserved Future Implementation Block Reserved Future Implementation 000004 000003 000002 000001 Manufacturer Code 000000 Block Lock Configuration Device Code (Block through 126) Block 128Mbit 16Mbit Flash Bank
128Mbit Bank
010000 00FFFF
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Read Array Command
device Read Array mode initial device power after exit from deep power down, writing Command User Interface. read configuration register defaults asynchronous read page mode. device remains enabled reads until another command written. Read Array command functions independently VPEN voltage.
Read Query Mode Command
This section defines data structure "Database" returned Common Flash Interface (CFI) Query command. System software should parse this structure gain critical information such block size, density, x8/x16, electrical specifications. Once this information been obtained, software will know which command sets enable flash writes, block erases, otherwise control flash component.
Query Structure Output
Query Database allows system software gain information controlling flash component. This section describes device CFI-compliant interface that allows host system access Query data. Query data always presented lowest-order data outputs 0-7) only. numerical offset value address relative maximum width supported device. this family devices, Query table device starting address 10h, which word address devices. word-wide (x16) device, first bytes Query structure, ASCII, appear byte word addresses 11h. This CFI-compliant device outputs data upper bytes. Thus, device outputs ASCII byte high byte 8-15 Query addresses containing more bytes information, least significant data byte presented lower address, most significant data byte presented higher address.
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following tables, addresses data represented hexadecimal notation, suffix been dropped. addition, since upper byte word-wide devices always "00h"," leading "00" been dropped from table notation only lower byte value shown. device outputs assumed have upper byte this mode.
TABLE Summary Query Structure Output Function Device Mode
Device Type/Mode Query start location maximum device width addresses Query data with maximum device width addressing Offset Code 0051 0052 0059 ASCII Value Query data with byte addressing Offset Code ASCII Value "Null"
device mode device mode
NOTE: system must drive lowest order addresses access device's array data when device configured mode. Therefore, word addressing, where these lower addresses toggled system, "Not Applicable" x8-configured devices.
TABLE Example Query Structure Output x16- x8-Capable Device
Offset A15-A0 0010h 0011h 0012h 0013h 0014h 0015h 0016h 0017h 0018h Word Addressing Code Value 0051 0052 0059 P_IDLO PrVendor P_IDHI PrVendor TblAdr A_IDLO AltVendor A_IDHI Offset A7-A0 Byte Addressing Code Value P_IDLO PrVendor P_IDLO P_IDHI
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Query Structure Overview
Query command causes flash component display Common Flash Interface (CFI) Query structure "database". structure sub-sections address locations summarized below.
TABLE Query Structure
Offset (BA+2)h 04-0Fh Block Status Register Reserved Query Identification String System Interface Information Device Geometry Definition Primary MXIC-Specific Extended Query Table Sub-Section Name Description Manufacturer Code Device Code Block-Specific Information
Reserved Vendor-Specific Information Reserved Vendor-Specific Information
Command Vendor Data Offset Flash Device Layout Vendor-Defined Additional Information Specific Primary Vendor Algorithm
NOTES: Refer Query Structure Output section offset detailed definition offset address function device width mode. Block Address beginning location (i.e., 02000h block beginning location when block size Kbyte). Offset defines which points Primary Intel-Specific Extended Query Table.
Block Status Register
block status register indicates whether erase operation completed successfully whether given block locked accessed flash program/erase operations.
TABLE Block Status Register
Offset (BA+2)h Length Description Block Lock Status Register BSR.0 Block Lock Status Unlocked Locked 1-7: Reserved Future BA+2: (bit 1-7): NOTE: beginning location Block Address (i.e., 008000h block (64-KB block) beginning location word mode). BA+2: (bit Address BA+2: Value
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Query Identification String
Query Identification String provides verification that component supports Common Flash Interface specification. also indicates specification version supported vendor-specified command set(s).
TABLE Identification
Offset Length Description Query-unique ASCII string "QRY" Add. Code Value
Primary vendor command control interface code. 16-bit code vendor-specified algorithms Extended Query Table primary algorithm address Alternate vendor command control interface code. 0000h means second vendor-specified algorithm exists Secondary algorithm Extended Query Table address. 0000h means none exists
System Interface Information
following device information optimize system interface software.
TABLE System Interface Information
Offset Length Description logic supply minimum program/erase voltage bits bits volts logic supply maximum program/erase voltage bits bits volts [programming] supply minimum program/erase voltage bits bits volts [programming] supply maximum program/erase voltage bits bits volts such that typical single word program time-out such that typical max. buffer write time-out such that typical block erase time-out such that typical full chip erase time-out such that maximum word program time-out times typical such that maximum buffer write time-out times typical such that maximum block erase time-out times typical such that maximum chip erase time-out times typical Add. Code Value
0.0V
0.0V 128us 128us
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Device Geometry Definition
This field provides critical details flash device geometry.
TABLE Device Geometry Definition
Offset Length Description such that device size number bytes Flash device interface: async(28:00,29:00), async(28:01,29:00), x8/x16 async(28:02,29:00) such that maximum number bytes write buffer Number erase block regions within device: means erase blocking; device erases "bulk" specifies number device partition regions with more contiguous same-size erase blocks Symmetrically blocked partitions have blocking region Partition size (total blocks) (individual block size) Erase Block Region Information bits 0-15 number identical-size erase blocks bits 16-31 region erase block(s) size bytes Code Table Below x8/x16
Device Geometry Definition
Address MX67L9632J3
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Primary-Vendor Specific Extended Query Table
Certain flash features commands optional. Primary Vendor-Specific Extended Query table specifies this other similar information.
TABLE Primary Vendor-Specific Extended Query
Offset(1) Length P=31h (P+0)h (P+1)h (P+2)h (P+3)h (P+4)h (P+5)h (P+6)h (P+7)h (P+8)h Description (Optional Flash Features Commands) Primary extended query table Unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Optional feature command support (1=yes, 0=no) bits 9-31 reserved; undefined bits "0". then another field optional features follows bit-30 field. Chip erase supported Suspend erase supported Suspend program supported Legacy lock/unlock supported Queued erase supported Instant Individual block locking supported Protection bits supported Page-mode read supported Synchronous read supported Supported functions after suspend: read Array, Status,Query Other supported operations are: bits reserved; undefined bits Program supported after erase suspend Block status register mask bits 2-15 Reserved; undefined bits Block Lock-Bit Status register active Block Lock-Down Status active logic supply highest performance program/erase voltage bits value bits value volts optimum program/erase supply voltage bits value bits value volts Add. Code 1(1) Value
Yes(1)
(P+9)h
(P+A)h (P+B)h
3.3V
(P+C)h
(P+D)h
0.0V
NOTE: Future devices support described "Legacy Lock/Unlock" function. Thus would have value "0".
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TABLE Protection Register Information
Offset(1) Length P=31h (P+E)h Description (Optional Flash Features Commands) Number Protection register fields JEDEC space. "00h," indicates that protection bytes available Protection Field Protection Description This field describes user-available Time Programmable (OTP) protection register bytes. Some pre-programmed with device-unique serial numbers. Others user-programmable. Bits 0-15 point protection register lock byte, section's first byte. following bytes factory pre-programmed user-programmable. bits Lock/bytes JEDEC-plane physical address bits 8-15 Lock/bytes JEDEC-plane physical high address bits 16-23 such that factory pre-programmed bytes bits 24-31 such that user-programmable bytes Add. Code Value
(P+F)h (P+10)h (P+11)h (P+12)h
NOTE: variable pointer which defined offset 15h.
TABLE Page Read Information
Offset(1) Length P=31h Description (Optional Flash Features Commands) Page Mode Read capability bits such that value represents number read-page bytes. offset device word width determine page-mode data output width. indicates read page buffer. Number synchronous mode read configuration fields that follow. indicates burst capability. Reserved future Add. Code Value
(P+13)h
byte
(P+14)h (P+15)h
NOTE: variable pointer which defined offset 15h.
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DEVICE OPERATION SILICON READ
Silicon Read mode allows reading binary code from device will identify manufacturer type. This mode intended programming equipment purpose automatically matching device programmed with corresponding programming algorithm. This mode functional over entire temperature range device. activate this mode, cycle "Silicon Read" command requested. (The command sequence illustrated Table During "Silicon Read" Mode, manufacturer's code (MXIC=C2H) read setting A0=VIL device identifier read setting A0=VIH. terminate operation, necessary write read/reset command. "Silicon Read" command functions independently VPEN voltage. This command valid only when device suspended.
TABLE MX67L12816J3/MX67L9632J3 Silicon Codes
Type Manufacturer code Device Code MX67L9632J3 MX67L12816J3 Address(1) 00000 00001 00001 X0002(2) DQ0=0 DQ0=1 DQ1-7 Code(Hex) (00)9CH (00)9DH
Block Lock Configuration Block Unlocked Block Locked Reserved Future
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TABLE Status Register Definitions
High Symbol When Status Busy? SR.7 WRITE STATE MACHINE STATUS SR.6 ERASE SUSPEND STATUS SR.5 SR.4 SR.3 ERASE CLEAR LOCK-BITS STATUS PROGRAM LOCK-BIT STATUS PROGRAMMING VOLTAGE STATUS Definition Ready Block Erase Suspended Error Block Erasure Clear Lock-Bits Error Setting Lock-Bit Programming Voltage Detected, Operation Aborted Program suspended Block Lock-Bit Detected, Operation Abort Busy Block Erase Progress/Completed Successful Block Erase Clear Lock-Bits Successful Block Lock Programming Voltage Program progress/ completed Unlock
SR.2 SR.1 SR.0
PROGRAM SUSPEND STATUS DEVICE PROTECT STATUS RESERVED
Notes Check SR.7 determine block erase, program, lock-bit configuration completion. SR.6-SR.0 driven while SR.7 both SR.5 SR.4 after block erase lock-bit configuration attempt, improper command sequence entered. SR.3 does provide continuous programming voltage level indication. interrogates indicates programming voltage level only after Block Erase, Program, Block Lock-Bit, Clear Block Lock-Bits command sequences. SR.1 does provide continuous indication block lock-bit values. interrogates block lock-bits only after Block Erase, Program, Lock-Bit configuration command sequences. informs system, depending attempted operation, block lock-bit set. Read block lock configuration codes using Read Identifier Codes command determine block lock-bit status. SR.0 reserved future should masked when polling status register.
TABLE Extended Status Register Definitions
High Symbol When Status Busy? XSR.7 WRITE BUFFER STATUS XSR.6- RESERVED XSR.0 Definition Write buffer available Write buffer available
Notes: After Buffer-Write command, XSR.7 indicates that Write Buffer available. XSR.6-XSR.0 reserved future should masked when polling status register.
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READ STATUS REGISTER COMMAND
Status Register read after writing Read Status Register command Command User Interface. Also, after starting internal operation device Read Status Register mode automatically. contents Status Register latched later falling edge first edge CE0, CE1, that enables device must toggle device must disable before further reads update status register latch. Read Status Register command functions independently VPEN voltage. "1". default mode, will also transition VOH. this time, read array/program command sequence also issued during erase suspend read program data other blocks. During program operation with block erase suspended, status register SR.7 will return output default mode) will transition will continue run, idling SUSPEND state, regardless state input control pins. only other valid commands while block erase suspended Read Query, Read Status Register, Clear Status Register, Configure, Block Erase Resume. After Block Erase Resume command written flash memory, will continue block erase process. Status register bits SR.6 SR.7 will automatically clear default mode) will return VOL. VPEN must remain VPENH (the same VPEN level used block erase) while block erase suspended. Block erase cannot resume until program operations initiated during block erase suspend have completed.
CLEAR STATUS REGISTER COMMAND
Erase Status, Program Status, Block Status bits protect status Write State Machine only reset Clear Status Register command 50H. These bits indicates various failure conditions.
BLOCK ERASE COMMAND
Automated block erase initiated writing Block Erase command followed Confirm command D0H. address within block erased required (erase changes block data FFH). Block preconditioning, erase, verify handled internally (invisible system). detect block erase completion analyzing output status register SR.7. Toggle update status register. remains read status register mode until command issued. Also, reliable block erasure only occur when valid VPEN VPENH
WRITE BUFFER COMMAND
program device, Write Buffer command issue first. variable number bytes, buffer size, loaded into buffer written flash device. First, Write Buffer Setup command issued along with Block Address (see Figure Write Buffer Flowchart page After command issued, extended Status Register (XSR) read when VIL. XSR.7 indicates Write Buffer available. buffer available, number words/bytes program written device. Next, start address given along with write buffer data. Subsequent writes provide additional device addresses data, depending count. After last buffer data given, Write Confirm command must issued. beginning copy buffer data flash array. error occurs while writing, device will stop writing, status register SR.4 will indicate program failure. internal verify only detects errors that successfully program program error detected, status register should cleared. time SR.4 and/or SR.5 set,
BLOCK ERASE SUSPEND COMMAND
This command only meaning while executing Block erase operation, therefore will only responded during Block erase operation. After this command been executed, suspend erase operations, then return Read Status Register mode. will "1". Once reached Suspend state, will
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device will accept more Write Buffer commands. Reliable buffered writes only occur when valid VPEN VPENH. Also, successful programming requires that corresponding block lock-bit reset.
BYTE/WORD PROGRAM COMMANDS
Byte/Word program executed two-command sequence. Byte/Word Program Setup command written Command Interface, followed second write specifying address data written. controls program pulse application verify operation. detect completion program event analyzing status register SR.7. byte/word program attempted while VPEN_V PENLK, status register bits SR.4 SR.3 will "1". Successful byte/word programs require that corresponding block lock-bit cleared. byte/ word program attempted when corresponding block lockbit set, SR.1 SR.4 will "1".
SUSPEND/RESUME COMMAND
Writing Suspend command during block erase operation interrupts block erase operation allows read from another block memory. Writing Suspend command during program operation interrupts program operation allows read from another block memory. Block address required when writing Suspend/Resume Command. device continues output Status Register data when read, after Suspend command written Polling Status Suspend Status bits will determine when erase operation program operation been suspended. When SR.7 SR.2 should also "1", indicating that device program suspend mode. level RY/BY mode will also transition VOH. this time, writing Read Array command enables reading data from blocks other than that which suspended. only other valid commands while programming suspended Read Query, Read Status Register, Clear Status Register, Configure, Program Resume. When Resume command written CUI, will continue with erase program processes. Status register bits SR.2 SR.7 will automatically clear RY/BY mode will return VOL.
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Read Configuration
device will support both asynchronous page mode standard word/byte reads. configuration required. Status register identifier only support standard word/byte single read operations.
TABLE Read Configuration Register Definition
16(A16) Notes Read mode configuration effects reads from flash array. Status register, query, identifier reads support standard word/byte read cycles. These bits reserved future use. these bits "0".
RCR.16 READ MODE (RM) Standard Word/Byte Reads Enabled (Default) Page-Mode Reads Enabled RCR.15-1= RESERVED FUTURE ENHANCEMENTS
Configuration Command
Status (STS) configured different states using Configuration command. Once been configured, remains that configuration until another configuration command issued asserted low. Initially, defaults RY/BY operation where RY/BY indicates that state machine busy. RY/BY high indicates that state machine ready operation suspended. Table "Configuration Coding Definitions" page displays possible configurations. re-configure Status (STS) other modes, Configuration command given followed desired configuration code. three alternate configurations pulse mode system interrupt described below. these configurations, controls Erase Complete interrupt pulse, controls Program Complete interrupt pulse. Supplying configuration code with Configuration command resets default RY/BY level mode. possible configurations their usage described Table "Configuration Coding Definitions" page Configuration command only given when device busy suspended. Check SR.7 device status. invalid configuration code will result both status register bits SR.4 SR.5 being "1"." When configured pulse modes, pulses with typical pulse width
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TABLE Configuration Coding Definitions
Reserved Pulse Program Complete Pulse Erase Compete
bits7-2 Reserved Configuration Codes default, level mode RY/BY (device ready) indication pulse Erase complete pulse Program complete pulse Erase Program Complete Configuration Codes 01b, 10b, pulse mode such that pulses then high when operation indicated given configuration completed. Configuration Command Sequences configuration (masking bits 00h) follows: Default RY/BY level mode: B8h, (Erase Interrupt): B8h, Pulse-on-Erase Complete (Program Interrupt): B8h, Pulse-on-Program Complete ER/PR (Erase Program Interrupt): B8h, Pulse-on-Erase Program Complete
reserved future use. default (Q1-Q RY/BY, level mode used control HOLD memory controller prevent accessing flash memory subsystem while flash device's busy. configuration INT, pulse mode used generate system interrupt pulse when flash device array completed Block Erase. Helpful reformatting blocks after file system free space reclamation "cleanup" configuration INT, pulse mode -used generate system interrupt pulse when flash device array complete Program operation. Provides highest performance servicing continuous buffer write operations. configuration ER/PR INT, pulse mode -used generate system interrupts trigger servicing flash arrays when either erase program operations completed when common interrupt service routine desired.
NOTE: When device configured pulse modes, pulses with typical pulse width
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Block Lock-Bit Commands
This device provided block lock-bits, lock unlock individual block. block lock-bit, cycle Block Lock-Bit command requested. This command invalid while running device suspended. Writing block lock-bit command followed confirm command appropriate block address. After command written, device automatically outputs status register data when read. detect completion lockbit event analyzing output status register SR.7. Also, reliable operations occur only when VPEN valid. With VPEN _VPENLK lockbit contents protected against alteration. tion. return read array mode, write Read Array command (FFH).
Programming Protection Register
protection register bits programmed using two-cycle Protection Program command. 64-bit number programmed bits time word-wide parts eight bits time byte-wide parts. First write Protection Program Setup command, C0H. next write device will latch address data program specified location. attempt address Protection Program commands outside defined protection register address space will result status register error. Attempting program locked protection register segment will result status register error.
Clear Block Lock-Bits Command
block lock-bits clear Clear Block LockBits command. This command invalid while running device suspended. Clear block lock-bits, cycle command requested device automatically outputs status register data when read. detect completion clear block lock-bits event analyzing output status register SR.7. clear block lock-bits operation aborted transitioning valid range, block lock-bit values left undetermined state. repeat clear block lock-bits required initialize block lock-bit contents known values.
Locking Protection Register
user-programmable segment protection register lockable programming PR-LOCK location this location programmed Intel factory protect unique device number. using Protection Program command program "FFFD" PR-LOCK location. After these bits have been programmed, further changes made values stored protection register. Protection Program commands locked section will result status register error. Protection register lockout state reversible.
Protection Register Program Command
device offer 128-bit protection register increase security system design. 128-bits protection register divided into 64-bit segments. programmed factory with unique 64-bit number, which unchangeable. other left blank customer designers program desired. Once customer segment programmed, locked prevent reprogramming.
Reading Protection Register
protection register read identification read mode. device switched this mode writing Read Identifier command 90H. Once this mode, read cycles from addresses retrieve specified informa-
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FIGURE Protection Register Memory
A[24 -1]: MX67L12816J3 A[23 -1]: MX67L9632J3
Word Address
Words User Programmed Words Factory Programmed Word Lock
NOTE: used mode when accessing protection register (See Table addressing). mode used (See Table addressing).
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TABLE Word-Wide Protection Register Addressing
Word LOCK Both Factory Factory Factory Factory User User User User
NOTE: address lines specified above table must when accessing Protection Register, i.e., A24-A9
TABLE Byte-Wide Protection Register Addressing
Word LOCK LOCK Both Both Factory Factory Factory Factory Factory Factory Factory Factory User User User User User User User User
NOTE: address lines specified above table must when accessing Protection Register, i.e., A24-A9
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FIGURE Write Buffer Flowchart
Start
Time-Out
Write Block Address
Read Extended Status Register
XSR.7=1
Write Buffer Time-Out
Write Word Byte Count Block Address
Write Buffer Data, Start Address
Check
Abort Write Buffer Command? Write Next Buffer Data, Device Address
Write Another Block Address
Write Buffer Failed
Program Buffer Flash Confirm
Another Write Buffer Read Status Register
Issue Read Status Command
SR.7=1?
Full Status Check Desired
Programming Complete
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FIGURE Byte/Word Program Flowchart
Start
Write 40H, Address
Write Data Address
Read Status Register
SR.7=
Full Status Check Desired
Byte/Word Program Complete
Command Comments Operation Write Setup Byte/ Data=40H Word Program Addr=Location Programmed Write Data=Data Byte/Word Programmed Program Addr=Location Programmed Read Status Register Data (Note Standby Check SR.7 1=WSM Ready 0=WSM Busy Toggling (low high low) updates status register. This done place issuing Read Status Register command. Repeat subsequent programming operations. full status check done after each program after sequence program operations. Write after last program operation reset device read array mode. Command Operation Standby Comments
FULL STATUS CHECK PROCEDURE
Read Status Register Data(See Above)
SR.3=
Range Error
SR.1=
Device Protect Error
SR.4=
Programming Error
Byte/Word Program Successful
Check SR.3 1=Programming Voltage Error Detect Standby Check SR.1 1=Device Protect Detect RP=VIH, Block Lock-Bit Only required system implementing lockbit configuration Standby Check SR.4 1=Programming Error Toggling (low high low) updates status register. This done place issuing Read Status Register command. Repeat subsequent programming operations. SR.4, SR.3, SR.1 only cleared Clear Status Register command cases where multiple programmed before full status checked. error detected, clear status register before attempting retry other error recovery.
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FIGURE Program Suspend/Resume Flowchart
Start
Write
Read Status Register
SR.7=1
SR.2=1 Programming Completed
Write
Read Array Data
Done Reading
Write Write
Programming Resumed
Read Array Data
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FIGURE Block Erase Flowchart
Start
Write Block Address
Write Confirm Block Address
Read Status Register
SR.7=1
Write B0H?
Full Status Check Desired
Suspend Loop Write
Erase Flash Block(s) Completed
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FIGURE Block Erase Suspend/Resume Flowchart
Start
Operation Write
Command Erase Suspend
Comments Data=B0H Addr=X Status Register Data Addr=X Check SR.7 1=WSM Ready 0=WSM Busy
Write
Read
Read Status Register
Standby
SR.7=
Erase Completed
Standby
Check SR.6 1=Block Erase Suspend 0=Block Erase Completed
SR.6=
Write
Erase Resume
Data=D0H Addr=X
Read
Read Program?
Program
Read Array Data
Program Loop
Done
Write Write
Block Write Resumed
Read Array Data
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FIGURE Block Lock-Bit Flowchart
Start
Write 60H, Block Address
Write 01H, Block Address
Read Status Register
SR.7=1
Full Status Check Desired
Lock-Bit Completed
FULL STATUS CHECK PROCEDURE
Read Status Register Data (See Above)
SR.3=0
Voltage Range Error
SR.4,5=1
Command Sequence Error
SR.4=0
Lock-Bit Error
Lock-Bit Successful
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FIGURE Clear Lock-Bit Flowchart
Start
Write
Write
Read Status Register
SR.7=1
Full Status Check Desired
Lock-Bit Completed
FULL STATUS CHECK PROCEDURE
Read Status Register Data (See Above)
SR.3=0
Voltage Range Error
SR.4,5=1
Command Sequence Error
SR.5=0
Clear Block Lock-Bits Error
Clear Block Lock-Bit Successful
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FIGURE Protection Register Programming Flowchart
Start
Write (Protection Reg. Program Setup)
Write Protect. Register Address/Data
Read Status Register
SR.7=1
Full Status Check Desired
Program Completed
FULL STATUS CHECK PROCEDURE
Read Status Register Data (See Above)
SR.3, SR.4=
VPEN Range Error
SR.1, SR.4=
Protection Register Programming Error
SR.1, SR.4=
Attempted Program Locked Register-Aborted
Program Successful
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ABSOLUTE MAXIMUM RATINGS
Storage Temperature Plastic Packages -65oC +150oC Ambient Temperature with Power Applied. -65oC +125oC Voltage with Respect Ground (Note -0.5 +4.0 RESET (Note .-0.5 +12.5 other pins (Note -0.5 +0.5 Output Short Circuit Current (Note Notes: Minimum voltage input pins -0.5 During voltage transitions, input pins overshoot -2.0 periods Figure Maximum voltage input pins +0.5 During voltage transitions, input pins overshoot +2.0 periods Figure Minimum input voltage pins RESET -0.5 During voltage transitions, RESET overshoot -2.0 periods Figure Maximum input voltage +12.5 which overshoot 14.0 periods more than output shorted ground time. Duration short circuit should greater than second. Stresses above those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational sections this data sheet implied. Exposure device absolute maximum rating conditions extended periods affect device reliability.
OPERATING RATINGS
Commercial Devices Ambient Temperature .-40° +85°C Supply Voltages full voltage range. +2.7
Operating ranges define those limits between which functionality device guaranteed.
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Characteristics
Symbol Parameter Input Load Current Output Leakage Current Notes Unit Test Conditions Max; VCCQ VCCQ VCCQ Max; VCCQ VCCQ VCCQ CMOS Inputs, Max, Device enabled (see table RESET=VCCQ±0.2V Inputs, VCC=VCC max, Device enable (see table RESET=VIH RESET=GND±0.2V, IOUT(STS)=0mA CMOS Inputs, VCC=VCC Max, VCCQ=VCCQ Device enabled (see Table f=5MHz, IOUT=0mA CMOS Inputs, VCC=VCC Max, VCCQ=VCCQ Device enabled (see Table f=33MHz, IOUT=0mA CMOS Inputs, VCC=VCC Max, VCCQ=VCCQ Device enabled (see Table f=5MHz, IOUT=0MA CMOS Inputs, VPEN=VCC Inputs, VPEN=VCC CMOS Inputs, VPEN=VCC Inputs, VPEN=VCC Device disabled (see Table
ICC1
Standby Current
1,2,3
0.71
ICC2
Power-Down Current
ICC3 Page Mode Read Current
ICC4
Byte Mode Read Current
ICC5 ICC6 ICC7
Program Lock-Bit Current Block Erase Clear Block Lock-Bits Current Program Suspend Block Erase Suspend Current
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Characteristics, Continued
Symbol Parameter Input Voltage Input High Voltage Notes -0.5 VCCQ+0.5 0.85 VCCQ VCCQ-0.2 Unit Test Conditions
Output Voltage
Output High Voltage
VCCQ=VCCQ2/3 IOL=2mA VCCQ=VCCQ2/3 IOL=100uA VCCQ=VCCQ IOH=-2.5mA VCCQ=VCCQ IOH=-100uA
VPENLK VPEN Lockout during Program, 4,6,7 Erase Lock-Bit Operations VPENH VPEN during Block Erase, Program, Lock-Bit Operations VLKO Lockout Voltage
NOTES: currents unless otherwise noted. These currents valid product versions (packages speeds). Includes STS. CMOS inputs either inputs either Sampled, 100% tested. ICCWS ICCES specified with device de-selected. device read written while erase suspend mode, device's current draw Block erases, programming, lock-bit configurations inhibited when PENLK guaranteed range between VPENLK (max) VPENH (min), above VPENH (max). Typically, VPEN connected (2.7 Block erases, programming, lock-bit configurations inhibited when VLKO guaranteed range between VLKO (min) (min), above (max).
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FIGURE 12.Transient Input/Output Reference Waveform VCCQ=3.0V-3.6V VCCQ=2.7V-3.6V
VCCQ Input VCCQ/2
Note:AC test inputs driven VCCQ Logic 0.0V Logic "0". Input timing being, output timing ends, VCCQ/2V (50% VCCQ). Input rise fall times (10% 90%)<5ns.
TEST POINTS
VCCQ/2 Output
FIGURE Transient Equivalent Testing Load Circuit
1.3V 1N914
RL=3.3K
Device Under Test
NOTE: Includes Capacitance
Test Configuration VCC1=2.7 3.6V VCC2=2.7 3.3V VCCQ1=2.7 3.6V VCCQ2=1.65 1.95V
(pF)
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Characteristics -Read-Only Operations (1,2)
Versions (All units unless otherwise noted) tAVAV tAVQV tELQV tGLQV tPHQV tELQX tGLQX tEHQZ tGHQZ tELFL/tELFH tFLQZ tEHEL tAPA tGLQV Parameter Read/Write Cycle Time Address Output Delay Output Delay Non-Array Output Delay RESET High Output Delay Output Output High Output High High Output High Output Hold from Address, CEX, Change, Whichever Occurs First BYTE High BYTE Output High High Page Address Access Time Array Output Delay 1000 1000 1000 1000 tFLQV/tFHQV BYTE Output Delay VCCQ Notes 2.7V-3.6V(3) 2.7V-3.6V(3) 2.7V-3.6V(3) 1.65V-1.95V(3)
NOTES: defined first edge that enables device. high defined first edge CE0, CE1, that disables device (see Table Input/Output Reference Waveforms maximum allowable input slew rate. delayed ELQV GLQV after first edge CE0, CE1, that enables device (see Table without impact ELQV Figures 14-16, Transient Input/Output Reference Waveform VCCQ 3.0V 3.6V VCCQ 2.7V-3.6 Transient Equivalent Testing Load Circuit testing characteristics. When reading flash array faster tGLQV (R16) applies. Non-array reads refer status register reads, query reads, device identifier reads. Sampled, 100% tested. devices configured standard word/byte read mode, (tAPA) will equal (tAVQV).
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FIGURE Waveform Both Page-Mode Standard Word/Byte Read Operations
Address (A24-A3)
tAVAV
Address (A2-A0)
Valid Address
Valid Address Valid Address
Valid Address
tEHEL
Disable
CEx[E]
Enable tAVQV tEHQZ
tELQV tGHQZ
tPHQV
tGLQV tAPA tELQX
DATA[D/Q]
High
Valid Output
tGLQX
Valid Valid Output Output
Valid Output
High
RESET[P]
tELFL/tELFH
tFLQV/tFHQV tFLQZ
BYTE
NOTE: defined first edge that enables device. high defined first edge CE0, CE1, that disables device (see Table standard word/byte read operations, tAPA will equal tAVQV. When reading flash array faster tGLQV applies. Non-array reads refer status register reads, query reads, device identifier reads.
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Characteristics-Write Operations (1,2)
Versions Symbol tPHWL (tPHEL tELWL (tWLEL tDVWH (tDVEH tAVWH (tAVEH tWHEH (tEHWH) tWHDX (tEHDX) tWHAX (tEHAX) tWPH tVPWH (tVPEH) tWHGL (tEHGL) tWHRL (tEHRL) tQVVL Parameter RESET High Recovery WE(CEX) Going (WE) WE(CEX) Going Write Pulse Width Data Setup WE(CEX) Going High Address Setup WE(CEX) Going High (WE) Hold from WE(CEX) High Data Hold from WE(CEX) High Address Hold from WE(CEX) High Write Pulse Width High VPEN Setup WE(CEX) Going High Write Recovery before Read WE(CEX) High Going VPEN Hold from Valid SRD, Going High 3,8,9 75/85 0.70 75/90 35/40 Notes Valid Speeds Unit
tWHQV5 (tEHQV5) Lock-Bit Time tWHQV6 (tEHQV6) Clear Block Lock-Bits Time tWHRH1 (tEHRH1) Program Suspend Latency Time Read tWHRH (tEHRH) Erase Suspend Latency Time Read
NOTES: defined first edge CE0, CE1, that enables device. high defined first edge CE0, CE1, that disables device (see Table Read timing characteristics during block erase, program, lock-bit configuration operations same during read-only operations. Refer Characteristics-Read-Only Operations. write operation initiated terminated with either Sampled, 100% tested. Write pulse width (tWP) defined from going (whichever goes last) going high (whichever goes high first). Hence, tWLWH tELEH tWLEH tELWH. Refer Table valid block erase, program, lock-bit configuration. Write pulse width high WPH) defined from going high (whichever goes high first) going (whichever goes first). Hence, tWPH tWHWL tEHEL tWHEL tEHWL array access, tAVQV required addition tWHGL accesses after write. timings based configured RY/BY default mode. VPEN should held VPENH until determination block erase, program, lock-bit configuration success (SR.1/3/4/5=0).
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FIGURE Waveform Write Operations
Address
tAVWH (tAVEH)
Disable
tWHAX (tEHAX)
CEx,(WE)[E(W)]
Enable tPHWL (tPHEL) tWHEH (tEHWH) tWHGL (tEHGL)
Disable
tELWL (tWLEL)
tWPH
tWHQZ/tWHRH
WE,(CEx)[W(E)]
Enable tOVWH (tDVEH)
tWHDX (tEHDX)
DATA[D/Q]
tWHRL (tEHRL)
Valid
STS[R]
RESET
tVPWH (tVPEH) tQVVL
VPENH
VPEN[V] VPENLK
NOTES: defined first edge that enables device. high defined first edge CE0, CE1, that disables device (see Table shown default mode (RY/BY). power-up standby. Write block erase, write buffer, program setup. Write block erase write buffer confirm, valid address data. Automated erase delay. Read status register query data. Write Read Array command.
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FIGURE Waveform Reset Operation
tPHRH
tPLPH
NOTE: shown default mode (RY/BY).
Reset Specifications
tPLPH tPHRH Parameter RESET Pulse Time RESET tied this specification applicable) RESET High Reset during Block Erase, Program, Lock-Bit Configuration NOTES: These specifications valid product versions (packages speeds). RESET asserted while block erase, program, lock-bit configuration operation executing then minimum required RESET Pulse Time 100ns. reset time, tPHQV, required from latter RY/BY mode) RESET going high until outputs valid. Notes Unit
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ERASE PROGRAMMING PERFORMANCE
LIMITS PARAMETER Block Erase Time Write Buffer Byte Program Time (Time Program bytes/16 words Byte Program Time (Using Word/Byte Program Command) Block Program Time (Using Write Buffer Command) Block Erase/Program Cycles Flash Bank Bank Note: 10,000 1,000 Cycles MIN. TYP.(2) MAX. 15.0 UNITS
1.Not 100% Tested, Excludes external system level over head. 2.Typical values measured C,3.3V. Additionally programming typically assume checkerboard pattern.
LATCH-UP CHARACTERISTICS
MIN. Input Voltage with respect pins except pins Input Voltage with respect pins Current Includes pins except Vcc. Test conditions: 5.0V, time. -1.0V -1.0V -100mA MAX. 13.5V 1.0V +100mA
CAPACITANCE
COUT
TA=0° VCC=2.7V~3.6V
Parameter Description Input Capacitance Output Capacitance Test VIN=0 VOUT=0 UNIT
Parameter Symbol
Notes: Sampled, 100% tested. Test conditions TA=25°C, f=1.0MHz
DATA RETENTION
Parameter Minimum Pattern Data Retention Time Test Conditions
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Unit Years Years
REV. 0.2, NOV. 2002
MX67L12816J3/MX67L9632J3
ORDERING INFORMATION PLASTIC PACKAGE
PART MX67L9632J3XCC-15 MX67L9632J3XCI-15 MX67L9632J3TC-15 MX67L9632J3TI-15 MX67L12816J3XCC-15 MX67L12816J3XCI-15 MX67L12816J3TC-15 MX67L12816J3TI-15 Access Time/ Page Read (ns) 150/25 150/25 150/25 150/25 150/25 150/25 150/25 150/25 Temperature Range Commerical Industrial Commerical Industrial Commerical Industrial Commerical Industrial ball Flip Chip ball Flip Chip TSOP (14mm 20mm) TSOP (14mm 20mm) ball Flip Chip ball Flip Chip TSOP (14mm 20mm) TSOP (14mm 20mm) 1.0mm 1.0mm 1.0mm 1.0mm Package type Ball Pitch
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PACKAGE INFORMATION
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REVISION HISTORY
Revision Description Renamed: MX67L12816/MX67L9632 MX67L12816J3/ MX67L9632J3 Normal read access time: 120ns ->150ns Endurance cycles bank: cycles ->1,000 cycles note read mode MX67L12816J3 modify Package Information Page P1,40 P1,2,45 P47,48 Date JUN/19/2002
NOV/22/2002
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