MT48LC32M4A2 MT48LC16M8A2 MT48LC8M16A2
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128Mb: SDRAM Features
MT48LC32M4A2 banks MT48LC16M8A2 banks MT48LC8M16A2 banks
latest data sheet, refer Micron's site: www.micron.com
Features
PC100- PC133-compliant Fully synchronous; signals registered positive edge system clock Internal pipelined operation; column address changed every clock cycle Internal banks hiding access/precharge Programmable burst lengths (BL): full page Auto precharge, includes concurrent auto precharge, auto refresh modes Self refresh mode; standard power 64ms, 4,096-cycle refresh (commercial industrial) 16ms, 4,096-cycle refresh (Automotive) LVTTL-compatible inputs outputs Single +3.3 ±0.3V power supply
Figure
54-Pin TSOP Assignment (Top View)
Options
Configurations banks) banks) banks) Write recovery (tWR) CLK"1 Package/Pinout Plastic package OCPL2 54-pin TSOP (400 mil) 54-pin TSOP (400 mil) Pb-free 60-ball FBGA (8mm 16mm) 60-ball FBGA (8mm 16mm) Pb-free 54-ball VFBGA (8mm 8mm) 54-ball VFBGA (8mm 8mm) Pb-free Timing (cycle time) 7.5ns (PC133) 7.5ns (PC133) 6.0ns (x16 only) Self refresh Standard power Design revision Operating temperature range Commercial (0°C +70°C) Industrial (-40°C +85°C) Automotive (-40°C +105°C)
Notes: Refer Micron technical note: TN-48-05. Off-center parting line. Consult Micron availability. only.
Designator
32M4 16M8 8M16
Notes:
VDDQ VssQ VDDQ VssQ DQML CAS# RAS#
DQ15 VssQ DQ14 DQ13 VDDQ DQ12 DQ11 VssQ DQ10 VDDQ DQMH
symbol indicates signal active LOW. dash indicates function same function.
None None
Table
Address Table
banks (A0-A11) (BA0, BA1) (A0-A9) banks (A0-A11) (BA0, BA1) (A0-A8) banks (A0-A11) (BA0, BA1) (A0-A9, A11)
Configuration Refresh count addressing Bank addressing Column addressing
Table
Timing Parameters
(Read) latency
Access Time
Speed Grade
Clock Frequency
5.4ns
5.4ns 5.4ns 5.4ns
Setup Time 1.5ns 1.5ns 1.5ns 1.5ns 1.5ns
Hold Time 0.8ns 0.8ns 0.8ns 0.8ns 0.8ns
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Products specifications discussed herein subject change Micron without notice.
128Mb: SDRAM General Description
Table 128Mb SDRAM Part Numbers
Part Number MT48LC32M4A2TG MT48LC32M4A2P MT48LC16M8A2TG MT48LC16M8A2P MT48LC16M8A2FB1 MT48LC16M8A2BB1 MT48LC8M16A2TG MT48LC8M16A2P MT48LC8M16A2B41 MT48LC8M16A2F41 Notes: Architecture
FBGA Device Decode:
General Description
Micron® 128Mb SDRAM high-speed CMOS, dynamic random access memory containing 134,217,728 bits. internally configured quad-bank DRAM with synchronous interface (all signals registered positive edge clock signal, CLK). Each x4's 33,554,432-bit banks organized 4,096 rows 2,048 columns bits. Each x8's 33,554,432-bit banks organized 4,096 rows 1,024 columns bits. Each x16's 33,554,432-bit banks organized 4,096 rows columns bits. Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select bank accessed (BA0, select bank; A0-A11 select row). address bits registered coincident with READ WRITE command used select starting column location burst access. SDRAM provides programmable read write burst lengths locations, full page, with burst terminate option. auto precharge function enabled provide self-timed precharge that initiated burst sequence. 128Mb SDRAM uses internal pipelined architecture achieve high-speed operation. This architecture compatible with rule prefetch architectures, also allows column address changed every clock cycle achieve high-speed, fully random access. Precharging bank while accessing other three banks will hide precharge cycles provide seamless high-speed, random-access operation. 128Mb SDRAM designed operate 3.3V memory systems. auto refresh mode provided along with power-saving, power-down mode. inputs outputs LVTTL-compatible. SDRAMs offer substantial advances DRAM operating performance, including ability synchronously burst data high data rate with automatic column-address generation, ability interleave between internal banks hide precharge time, capability randomly change column addresses each clock cycle during burst access.
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128Mb: SDRAM Automotive Temperature
Automotive Temperature
automotive temperature (AT) option adheres following specifications: 16ms refresh rate Self refresh supported Ambient case temperature cannot less than -40°C greater than +105°C
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128Mb: SDRAM Table Contents Table Contents
Features General Description Automotive Temperature FBGA Ball Assignments Functional Block Diagrams. Pin/Ball Descriptions Functional Description Initialization Register Definition Mode Register. Burst Length (BL). Burst Type Latency Operating Mode. Write Burst Mode. Commands COMMAND INHIBIT. OPERATION (NOP). LOAD MODE REGISTER (LMR) ACTIVE READ WRITE PRECHARGE Auto Precharge BURST TERMINATE AUTO REFRESH SELF REFRESH Operations Bank/row Activation Reads WRITEs PRECHARGE Power-Down Clock Suspend. BURST READ/SINGLE WRITE. Concurrent Auto Precharge READ with Auto Precharge WRITE with Auto Precharge Electrical Specifications. Temperature Thermal Impedance Notes Timing Diagrams. Package Dimensions
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128Mb: SDRAM List Figures List Figures
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 54-Pin TSOP Assignment (Top View) 60-Ball FBGA Ball Assignments (Top View), 16mm 54-Ball VFBGA Assignments (Top View), SDRAM SDRAM SDRAM Mode Register Definition Latency Activating Specific Specific Bank Example: Meeting tRCD (MIN) When tRCD (MIN)/tCK READ Command Latency Consecutive READ Bursts Random READ Accesses READ-to-WRITE READ-to-WRITE with Extra Clock Cycle READ-to-PRECHARGE Terminating READ Burst WRITE Command WRITE Burst WRITE-to-WRITE Random WRITE Cycles WRITE-to-READ WRITE-to-PRECHARGE Terminating WRITE Burst PRECHARGE Command Power-Down Clock Suspend During WRITE Burst Clock Suspend During READ Burst READ With Auto Precharge Interrupted READ READ With Auto Precharge Interrupted WRITE WRITE With Auto Precharge Interrupted READ WRITE With Auto Precharge Interrupted WRITE Example Temperature Test Point Location, 54-Pin TSOP: View Example Temperature Test Point Location, 54-Ball VFBGA: View Example Temperature Test Point Location, 60-Ball FBGA: View Initialize Load Mode Register Power-Down Mode Clock Suspend Mode Auto Refresh Mode Self Refresh Mode READ Without Auto Precharge READ With Auto Precharge Single READ Without Auto Precharge Single READ With Auto Precharge Alternating Bank Read Accesses READ Full-Page Burst READ Operation WRITE Without Auto Precharge WRITE With Auto Precharge Single WRITE Without Auto Precharge Single WRITE With Auto Precharge Alternating Bank Write Accesses WRITE Full-Page Burst WRITE Operation 54-Pin Plastic TSOP (400 mil)
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128Mb: SDRAM List Figures
Figure Figure 60-Ball FBGA "FB/BB" Package device), 16mm 54-Ball VFBGA "F4/B4" Package (x16 device),
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128Mb: SDRAM List Tables List Tables
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Address Table Timing Parameters 128Mb SDRAM Part Numbers Pin/Ball Descriptions. Burst Definition. Latency Truth Table Commands Operation Truth Table Truth Table Current State Bank Command Bank Truth Table Current State Bank Command Bank Absolute Maximum Ratings Temperature Limits Thermal Impedance Simulated Values Electrical Characteristics Operating Conditions. Specifications Conditions Capacitance Electrical Characteristics Recommended Operating Conditions Functional Characteristics
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128Mb: SDRAM FBGA Ball Assignments
FBGA Ball Assignments
Figure 60-Ball FBGA Ball Assignments (Top View), 16mm
VDDQ VDDQ
VssQ VssQ
VDDQ VDDQ RAS#
VssQ VssQ CAS#
Depopulated Balls
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128Mb: SDRAM FBGA Ball Assignments
Figure 54-Ball VFBGA Assignments (Top View),
DQ15
VSSQ
VDDQ
DQ14
DQ13
VDDQ
VSSQ
DQ12
DQ11
VSSQ
VDDQ
DQ10
VDDQ
VSSQ
DQML
DQMH
CAS#
RAS#
NC/A12
View (Ball Down)
Notes: balls physical package. They included drawing illustrate that rows exist contain solder balls.
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128Mb: SDRAM Functional Block Diagrams
Functional Block Diagrams
Figure
CAS# RAS# CONTROL LOGIC
BANK3 BANK2 BANK1
COMMAND DECODE
MODE REGISTER
REFRESH COUNTER
ROWADDRESS
BANK0 ROWADDRESS 4,096 LATCH DECODER
BANK0 MEMORY ARRAY (4,096 2,048
SENSE AMPLIFIERS
4,096
DATA OUTPUT REGISTER
A0-A11, BA0,
ADDRESS REGISTER
BANK CONTROL LOGIC
GATING MASK LOGIC READ DATA LATCH WRITE DRIVERS
DQ0-
2,048 (x4)
DATA INPUT REGISTER
COLUMN DECODER
COLUMNADDRESS COUNTER/ LATCH
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128Mb: SDRAM Functional Block Diagrams
Figure
CAS# RAS# CONTROL LOGIC
BANK3 BANK2 BANK1
COMMAND DECODE
MODE REGISTER
REFRESH COUNTER
ROWADDRESS
BANK0 ROWADDRESS LATCH DECODER
4,096
BANK0 MEMORY ARRAY (4,096 1,024
SENSE AMPLIFIERS
4,096
DATA OUTPUT REGISTER
A0-A11, BA0,
ADDRESS REGISTER
BANK CONTROL LOGIC
GATING MASK LOGIC READ DATA LATCH WRITE DRIVERS
DQ0-
1,024 (x8)
DATA INPUT REGISTER
COLUMN DECODER
COLUMNADDRESS COUNTER/ LATCH
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128Mb: SDRAM Functional Block Diagrams
Figure
CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1
COMMAND DECODE
MODE REGISTER
REFRESH COUNTER
ROWADDRESS
BANK0 ROWADDRESS 4,096 LATCH DECODER
BANK0 MEMORY ARRAY (4,096
DQML, DQMH
SENSE AMPLIFIERS 4,096
DATA OUTPUT REGISTER
A0-A11, BA0, ADDRESS REGISTER BANK CONTROL LOGIC
GATING MASK LOGIC READ DATA LATCH WRITE DRIVERS (x16)
DQ0- DQ15
DATA INPUT REGISTER
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH
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128Mb: SDRAM Pin/Ball Descriptions
Pin/Ball Descriptions
Table
54-Pin TSOP
Pin/Ball Descriptions
54-Ball VFBGA 60-Ball FBGA Symbol Type Input Description Clock: driven system clock. SDRAM input signals sampled positive edge CLK. also increments internal burst counter controls output registers. Clock enable: activates (HIGH) deactivates (LOW) signal. Deactivating clock provides PRECHARGE power-down SELF REFRESH operation (all banks idle), ACTIVE power-down (row active bank), CLOCK SUSPEND operation (burst/access progress). synchronous except after device enters power-down self refresh modes, where becomes asynchronous until after exiting same mode. input buffers, including CLK, disabled during power-down self refresh modes, providing standby power. tied HIGH. Chip select: enables (registered LOW) disables (registered HIGH) command decoder. commands masked when registered HIGH, READ/WRITE bursts already progress will continue operation will retain mask capability while HIGH. provides external bank selection systems with multiple banks. considered part command code. Command inputs: WE#, CAS#, RAS# (along with CS#) define command being entered. Input/Output mask: input mask signal write accesses output enable signal read accesses. Input data masked when sampled HIGH during WRITE cycle. output buffers placed High-Z state (2-clock latency) when sampled HIGH during READ cycle. DQML (pin DQMH DQM. x16, DQML corresponds DQ0- DQ7, DQMH corresponds DQ8-DQ15. DQML DQMH considered same state when referenced DQM. Bank address inputs: define which bank ACTIVE, READ, WRITE, PRECHARGE command being applied. Address inputs: A0-A11 sampled during ACTIVE command (row-address A0-A11) READ/WRITE command (column-address A0-A9, [x4]; A0-A9 [x8]; A0-A8 [x16]; with defining auto precharge) select location memory array respective bank. sampled during precharge command determine whether banks precharged (A10 [HIGH]) bank selected BA0, (A10 [LOW]). address inputs also provide op-code during LOAD MODE REGISTER (LMR) command.
Input
Input
WE#, CAS#, RAS# x16: DQML, DQMH
Input
Input
BA0,
Input
23-26,
A0-A11
Input
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128Mb: SDRAM Pin/Ball Descriptions
Table
54-Pin TSOP
Pin/Ball Descriptions (Continued)
54-Ball VFBGA 60-Ball FBGA Symbol DQ0- DQ15 Type Description
x16: Data input/output: Data (pins x4).
DQ0-DQ7
Data input/output: Data (pins balls x4). Data input/output: Data connect: These pins should left unconnected.
DQ0-DQ3
VDDQ VSSQ
Address input (A12) 256Mb 512Mb devices. Supply power: Isolated power improved noise immunity. Supply ground: Isolated ground improved noise immunity. Supply Power supply: +3.3 ±0.3V. Supply Ground.
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128Mb: SDRAM Functional Description
Functional Description
general, 128Mb SDRAMs banks, banks, banks) quad-bank DRAMs that operate 3.3V include synchronous interface (all signals registered positive edge clock signal, CLK). Each x4's 33,554,432-bit banks organized 4,096 rows 2,048 columns bits. Each x8's 33,554,432-bit banks organized 4,096 rows 1,024 columns bits. Each x16's 33,554,432-bit banks organized 4,096 rows columns bits. Read write accesses SDRAM burst oriented; accesses start selected location continue programmed number locations programmed sequence. Accesses begin with registration ACTIVE command, which then followed READ WRITE command. address bits registered coincident with ACTIVE command used select bank accessed (BA0 select bank, A0-A11 select row). address bits (x4: A0-A9, A11; A0-A9; x16: A0-A8) registered coincident with READ WRITE command used select starting column location burst access. Prior normal operation, SDRAM must initialized. following sections provide detailed information covering device initialization, register definition, command descriptions, device operation.
Initialization
SDRAMs must powered initialized predefined manner. Operational procedures other than those specified result undefined operation. After power applied VDDQ (simultaneously) clock stable (stable clock defined signal cycling within timing constraints specified clock pin), SDRAM requires 100µs delay prior issuing command other than COMMAND INHIBIT Starting some point during this 100µs period continuing least through this period, COMMAND INHIBIT commands must applied. After 100µs delay been satisfied with least COMMAND INHIBIT command having been applied, PRECHARGE command should applied. banks must then precharged, thereby placing device banks idle state. Once idle state, least AUTO REFRESH cycles must performed. After AUTO REFRESH cycles complete, SDRAM ready mode register programming. Because mode register will power unknown state, must loaded prior applying operational command. desired, AUTO REFRESH commands issued after command. recommended power-up sequence SDRAMs: Simultaneously apply power VDDQ. Assert hold LVTTL logic since inputs outputs LVTTLcompatible. Provide stable CLOCK signal. Stable clock defined signal cycling within timing constraints specified clock pin. Wait least 100µs prior issuing command other than COMMAND INHIBIT NOP. Starting some point during this 100µs period, bring HIGH. Continuing least through this period, more COMMAND INHIBIT commands must applied. Perform PRECHARGE command.
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128Mb: SDRAM Functional Description
Wait least time; during this time, NOPs DESELECT commands must given. banks will complete their precharge, thereby placing device banks idle state. Issue AUTO REFRESH command. Wait least tRFC time, during which only NOPs COMMAND INHIBIT commands allowed. Issue AUTO REFRESH command. Wait least tRFC time, during which only NOPs COMMAND INHIBIT commands allowed. SDRAM ready mode register programming. Because mode register will power unknown state, should loaded with desired values prior applying operational command. Using command, program mode register. mode register programmed MODE REGISTER command with retains stored information until programmed again device loses power. programming mode register upon initialization will result default settings, which desired. Outputs guaranteed High-Z after command issued. Outputs should High-Z already before command issued. Wait least tMRD time, during which only DESELECT commands allowed. this point, DRAM ready valid command. Note: desired, more than AUTO REFRESH commands issued sequence. After steps complete, repeat them until desired number AUTO REFRESH tRFC loops achieved.
Register Definition
Mode Register mode register used define specific mode operation SDRAM. This definition includes selection burst length (BL), burst type, latency (CL), operating mode, write burst mode, shown Figure page mode register programmed command will retain stored information until programmed again device loses power. Mode register bits M0-M2 specify specifies type burst (sequential interleaved), M4-M6 specify specify operating mode, specifies write burst mode, reserved future use. mode register must loaded when banks idle, controller must wait specified time before initiating subsequent operation. Violating either these requirements will result unspecified operation. Burst Length (BL) Read write accesses SDRAM burst oriented, with being programmable, shown Figure page determines maximum number column locations that accessed given READ WRITE command. locations available both sequential interleaved burst types, full-page burst available sequential mode. full-page burst used conjunction with BURST TERMINATE command generate arbitrary BLs. Reserved states cannot used because unknown operation incompatibility with future versions result.
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128Mb: SDRAM Functional Description
When READ WRITE command issued, block columns equal effectively selected. accesses that burst take place within this block, meaning that burst will wrap within block boundary reached. block uniquely selected A1-A9, (x4), A1-A9 (x8), A1-A8 (x16) when A2-A9, (x4), A2-A9 (x8), A2-A8 (x16) when A3-A9, (x4), A3-A9 (x8), A3-A8 (x16) when remaining (least significant) address bit(s) (are) used select starting location within block. Full-page bursts wrap within page boundary reached. Burst Type Accesses within given burst programmed either sequential interleaved; this referred burst type selected ordering accesses within burst determined burst type, starting column address, shown Table page
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128Mb: SDRAM Functional Description
Figure Mode Register Definition
Address
Mode Register (Ax)
Reserved
Mode
Latency
Burst Length
Program A11, ensure compatibility with future devices.
Burst Length Reserved Reserved Reserved Full Page Reserved Reserved Reserved Reserved
Write Burst Mode Programmed Burst Length Single Location Access
A6-A0 Defined
Operating Mode Standard Operation other states reserved
Burst Type Sequential Interleaved
Latency Reserved Reserved Reserved Reserved Reserved Reserved
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128Mb: SDRAM Functional Description
Table Burst Definition
Burst Length Starting Column Address Order Accesses Within Burst Type Sequential 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Type Interleaved 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 supported
Full page Notes:
A0-A11/9/8 (location 0-y)
full-page accesses: 2,048 (x4), 1,024 (x8), (x16). A1-A9, (x4), A1-A9 (x8), A1-A8 (x16) select block-of-two burst; selects starting column within block. A2-A9, (x4), A2-A9 (x8), A2-A8 (x16) select block-of-four burst; select starting column within block. A3-A9, (x4), A3-A9 (x8), A3-A8 (x16) select block-of-eight burst; select starting column within block. full-page burst, full selected A0-A9, (x4), A0-A9 (x8), A0-A8 (x16) select starting column. Whenever boundary block reached within given sequence above, following access wraps within block.
Latency delay, clock cycles, between registration READ command availability first piece output data. latency clocks. READ command registered clock edge latency clocks, data will available clock edge will start driving result clock edge cycle earlier provided that relevant access times met, data will valid clock edge example, assuming that clock cycle time such that relevant access times met, read command registered latency programmed clocks, will start driving after data will valid shown Figure page Table page indicates operating frequencies which each setting used. Reserved states should used unknown operation incompatibility with future versions result.
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128Mb: SDRAM Functional Description
Table Latency
Allowable Operating Frequency (MHz) Speed
Figure
Latency
COMMAND
READ
DOUT
COMMAND
READ
DOUT
DON'T CARE UNDEFINED
Operating Mode normal operating mode selected setting other combinations values reserved future and/or test modes. programmed applies both read write bursts. Test modes reserved states should used because unknown operation incompatibility with future versions result. Write Burst Mode When programmed M0-M2 applies both read write bursts; when programmed applies read bursts, write accesses singlelocation (nonburst) accesses.
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128Mb: SDRAM Commands
Commands
Table provides quick reference available commands. This followed written description each command. Three additional truth tables appear following "Operations" page these tables provide current state/next state information. Table Truth Table Commands Operation
HIGH commands shown except SELF REFRESH Name (Function) COMMAND INHIBIT (NOP) OPERATION (NOP) ACTIVE (Select bank activate row) READ (Select bank column, start READ burst) WRITE (Select bank column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate bank banks) AUTO refresh self refresh (Enter self refresh mode) Write enable/output enable Write inhibit/output High-Z Notes: RAS# CAS# L/H8 L/H8 ADDR Bank/ Bank/ Bank/ Code Opcode Valid Active Active High-Z Notes
A0-A11 provide address, BA0, determine which bank made active. A0-A9; (x4); A0-A9 (x8); A0-A8 (x16) provide column address; HIGH enables auto precharge feature (nonpersistent), while disables auto precharge feature; BA0, determine which bank being read from written LOW: BA0, determine bank being precharged. HIGH: banks precharged BA0, "Don't Care." This command AUTO REFRESH HIGH SELF REFRESH LOW. Internal refresh counter controls addressing; inputs I/Os "Don't Care" except CKE. A0-A11 define op-code written mode register. Activates deactivates during WRITEs (0-clock delay) READs (2-clock delay).
COMMAND INHIBIT
COMMAND INHIBIT function prevents commands from being executed SDRAM, regardless whether signal enabled. SDRAM effectively deselected. Operations already progress affected.
OPERATION (NOP)
OPERATION (NOP) command used perform SDRAM, which selected (CS# LOW). This prevents unwanted commands from being registered during idle wait states. Operations already progress affected.
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128Mb: SDRAM Commands LOAD MODE REGISTER (LMR)
mode register loaded inputs A0-A11 (A12 should driven LOW). "Mode Register" heading "Register Definition" section page command only issued when banks idle, subsequent executable command cannot issued until tMRD met.
ACTIVE
ACTIVE command used open activate) particular bank subsequent access. value BA0, inputs selects bank, address provided inputs A0-A11 selects row. This remains active open) accesses until PRECHARGE command issued that bank. PRECHARGE command must issued before opening different same bank.
READ
READ command used initiate burst read access active row. value BA0, inputs selects bank, address provided inputs A0-A9, (x4), A0-A9 (x8), A0-A8 (x16) selects starting column location. value input determines whether auto precharge used. auto precharge selected, being accessed will precharged read burst; auto precharge selected, will remain open subsequent accesses. Read data appears subject logic level inputs clocks earlier. given signal registered HIGH, corresponding will High-Z clocks later; signal registered LOW, will provide valid data.
WRITE
WRITE command used initiate burst write access active row. value BA0, inputs selects bank, address provided inputs A0-A9, (x4), A0-A9 (x8), A0-A8 (x16) selects starting column location. value input determines whether auto precharge used. auto precharge selected, being accessed will precharged write burst; auto precharge selected, will remain open subsequent accesses. Input data appearing written memory array subject input logic level appearing coincident with data. given signal registered LOW, corresponding data will written memory; signal registered HIGH, corresponding data inputs will ignored, write will executed that byte/column location.
PRECHARGE
PRECHARGE command used deactivate open particular bank open banks. bank(s) will available subsequent access specified time (tRP) after PRECHARGE command issued. Input determines whether banks precharged, case where only bank precharged, inputs BA0, select bank. Otherwise BA0, treated "Don't Care." After bank been precharged, idle state must activated prior READ WRITE commands being issued that bank.
Auto Precharge
Auto precharge feature that performs same individual-bank precharge function described above, without requiring explicit command. This accomplished using enable auto precharge conjunction with specific READ WRITE command.
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precharge bank/row that addressed with READ WRITE command automatically performed upon completion READ WRITE burst, except full-page burst mode, where auto precharge does apply. Auto precharge nonpersistent that either enabled disabled each individual READ WRITE command. Auto precharge ensures that precharge initiated earliest valid stage within burst. user must issue another command same bank until precharge time (tRP) completed. This determined explicit PRECHARGE command issued earliest possible time, described each burst type "Operations" section page
BURST TERMINATE
BURST TERMINATE command used either truncate fixed-length full-page bursts. most recently registered READ WRITE command prior BURST TERMINATE command will truncated, shown "Operations" section page BURST TERMINATE command does precharge row; will remain open until PRECHARGE command issued.
AUTO REFRESH
AUTO REFRESH used during normal operation SDRAM analogous CAS#-BEFORE-RAS# (CBR) refresh older DRAMs. This command nonpersistent, must issued each time refresh required. active banks must PRECHARGED prior issuing AUTO REFRESH command. AUTO REFRESH command should issued until minimum been after PRECHARGE command shown operation section. addressing generated internal refresh controller. This makes address bits "Don't Care" during AUTO REFRESH command. Regardless device width, 128Mb SDRAM requires 4,096 AUTO REFRESH cycles every 64ms (commercial industrial) 16ms (automotive). Providing distributed AUTO REFRESH command every 15.625µs (commercial industrial) 3.906µs (automotive) will meet refresh requirement ensure that each refreshed. Alternatively, 4,096 AUTO REFRESH commands issued burst minimum cycle rate (tRFC), once every 64ms (commercial industrial) 16ms (automotive).
SELF REFRESH
SELF REFRESH command used retain data SDRAM, even rest system powered down. When self refresh mode, SDRAM retains data without external clocking. SELF REFRESH command initiated like AUTO REFRESH command except disabled (LOW). After SELF REFRESH command registered, inputs SDRAM become "Don't Care" with exception CKE, which must remain LOW. After self refresh mode engaged, SDRAM provides internal clocking, causing perform auto refresh cycles. SDRAM must remain self refresh mode minimum period equal tRAS remain self refresh mode indefinite period beyond that.
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procedure exiting self refresh requires sequence commands. First, must stable (stable clock defined signal cycling within timing constraints specified clock pin) prior going back HIGH. After HIGH, SDRAM must have commands issued minimum clocks) tXSR because this amount time required completion internal refresh progress. Upon exiting self refresh mode, AUTO REFRESH commands must issued every 15.625µs less because both SELF REFRESH AUTO REFRESH utilize refresh counter. Self refresh supported automotive temperature (AT) devices.
Operations
Bank/row Activation
Before READ WRITE commands issued bank within SDRAM, that bank must "opened." This accomplished ACTIVE command, which selects both bank activated (see Figure page 25). After opening (issuing ACTIVE command), READ WRITE command issued that row, subject tRCD specification. tRCD (MIN) should divided clock period rounded next whole number determine earliest clock edge after ACTIVE command which READ WRITE command entered. example, tRCD specification 20ns with clock (8ns period) results clocks, rounded This reflected Figure page which covers case where tRCD (MIN)/tCK (The same procedure used convert other specification limits from time units clock cycles.) subsequent ACTIVE command different same bank only issued after previous active been "closed" (precharged). minimum time interval between successive ACTIVE commands same bank defined tRC. subsequent ACTIVE command another bank issued while first bank being accessed, which results reduction total row-access overhead. minimum time interval between successive ACTIVE commands different banks defined RRD.
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Figure Activating Specific Specific Bank
HIGH
RAS#
CAS#
A0-A10,
ADDRESS
BA0,
BANK ADDRESS
DON'T CARE
Figure
Example: Meeting tRCD (MIN) When tRCD (MIN)/tCK
COMMAND
ACTIVE
READ WRITE
tRCD
DON'T CARE
Reads
READ bursts initiated with READ command, shown Figure page starting column bank addresses provided with READ command, auto precharge either enabled disabled that burst access. auto precharge enabled, being accessed precharged completion burst. generic READ commands used following illustrations, auto precharge disabled. During READ bursts, valid data-out element from starting column address will available following after READ command. Each subsequent data-out element will valid next positive clock edge. Figure page shows general timing each possible setting. Upon completion burst, assuming other commands have been initiated, will High-Z. full-page burst will continue until terminated. page, will wrap column continue.)
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Figure READ Command
HIGH
RAS#
CAS#
A0-A9, A11: A0-A9: A0-A8: A11: A11:
ENABLE AUTO PRECHARGE
COLUMN ADDRESS
DISABLE AUTO PRECHARGE BANK ADDRESS
BA0,
Figure
Latency
COMMAND
READ
DOUT
COMMAND
READ
DOUT
DON'T CARE
UNDEFINED
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Data from READ burst truncated with subsequent READ command, data from fixed-length READ burst immediately followed data from READ command. either case, continuous flow data maintained. first data element from burst either follows last element completed burst last desired data element longer burst that being truncated. READ command should issued cycles before clock edge which last desired data element valid, where This shown Figure data element either last burst four last desired longer burst. 128Mb SDRAM uses pipelined architecture and, therefore, does require rule associated with prefetch architecture. READ command initiated clock cycle following previous READ command. Full-speed random read accesses performed same bank, shown Figure page each subsequent READ performed different bank. Figure Consecutive READ Bursts
COMMAND
READ
READ
cycle
ADDRESS
BANK,
BANK,
DOUT
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
READ
cycles
ADDRESS
BANK,
BANK,
DOUT
DOUT
DOUT
DOUT
DOUT
TRANSITIONING DATA
DON'T CARE
Notes:
Each READ command bank. LOW.
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Figure Random READ Accesses
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
BANK,
BANK,
BANK,
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
READ
READ
READ
ADDRESS
BANK,
BANK,
BANK,
BANK,
DOUT
DOUT
DOUT
DOUT
TRANSITIONING DATA
DON'T CARE
Notes:
Each READ command bank. LOW.
Data from READ burst truncated with subsequent WRITE command, data from fixed-length READ burst immediately followed data from WRITE command (subject turnaround limitations). WRITE burst initiated clock edge immediately following last last desired) data element from READ burst, provided that contention avoided. given system design, there possibility that device driving input data will Low-Z before SDRAM High-Z. this case, least single-cycle delay should occur between last read data WRITE command. input used avoid contention, shown Figure page Figure page signal must asserted (HIGH) least clocks prior WRITE command (DQM latency clocks output buffers) suppress data-out from READ. After WRITE command registered, will High-Z remain High-Z), regardless state signal, provided active clock just prior WRITE command that truncated READ command. not, second WRITE will invalid WRITE. example, during Figure then WRITEs would valid, while WRITE would invalid.
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signal must de-asserted prior WRITE command (DQM latency zero clocks input buffers) ensure that written data masked. Figure shows case where clock frequency allows contention avoided without adding cycle, Figure shows case where additional needed. Figure READ-to-WRITE
COMMAND ADDRESS
READ
WRITE
BANK,
BANK,
DOUT
TRANSITIONING DATA DON'T CARE
Notes:
used illustration. READ command bank, WRITE command bank. burst used, then required.
Figure
READ-to-WRITE with Extra Clock Cycle
COMMAND ADDRESS
READ
WRITE
BANK,
BANK,
DOUT
TRANSITIONING DATA
DON'T CARE
Notes:
used illustration. READ command bank, WRITE command bank.
fixed-length READ burst followed truncated with, PRECHARGE command same bank (provided that auto precharge activated), fullpage burst truncated with PRECHARGE command same bank. PRECHARGE command should issued cycles before clock edge which last
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desired data element valid, where This shown Figure each possible data element either last burst four last desired longer burst. Following PRECHARGE command, subsequent command same bank cannot issued until met. Note that part precharge time hidden during access last data element(s). case fixed-length burst being executed completion, PRECHARGE command issued optimum time described above) provides same operation that would result from same fixed-length burst with auto precharge. disadvantage PRECHARGE command that requires that command address buses available appropriate time issue command; advantage PRECHARGE command that used truncate fixed-length full-page bursts. Full-page READ bursts truncated with BURST TERMINATE command, fixed-length READ bursts truncated with BURST TERMINATE command, provided that auto precharge activated. BURST TERMINATE command should issued cycles before clock edge which last desired data element valid, where This shown Figure page each possible data element last desired data element longer burst. Figure READ-to-PRECHARGE
COMMAND
READ
PRECHARGE cycle
ACTIVE
ADDRESS
BANK
BANK all)
BANK
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
PRECHARGE
ACTIVE
cycles
ADDRESS
BANK
BANK all)
BANK
DOUT
DOUT
DOUT
DOUT
TRANSITIONING DATA
DON'T CARE
Notes:
LOW.
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Figure Terminating READ Burst
COMMAND
READ
BURST TERMIN cycle
ADDRESS
BANK,
DOUT
DOUT
DOUT
DOUT
COMMAND
READ
BURST TERMIN
cycles
ADDRESS
BANK,
DOUT
DOUT
DOUT
DOUT
TRANSITIONING DATA
DON'T CARE
Notes:
LOW.
WRITEs
WRITE bursts initiated with WRITE command, shown Figure page starting column bank addresses provided with WRITE command, auto precharge either enabled disabled that access. auto precharge enabled, being accessed precharged completion burst. generic WRITE commands used following illustrations, auto precharge disabled. During WRITE bursts, first valid data-in element will registered coincident with WRITE command. Subsequent data elements will registered each successive positive clock edge. Upon completion fixed-length burst, assuming other commands have been initiated, will remain High-Z additional input data will ignored (see Figure page 32). full-page burst will continue until terminated. page, will wrap column continue.)
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Figure WRITE Command
HIGH
RAS#
CAS#
A0-A9, A11: A0-A9: A0-A8: A11: A11:
ENABLE AUTO PRECHARGE
COLUMN ADDRESS
DISABLE AUTO PRECHARGE
BA0,
BANK ADDRESS
DON'T CARE
Figure
WRITE Burst
COMMAND
WRITE
ADDRESS
BANK,
TRANSITIONING DATA
DON'T CARE
Notes:
LOW.
Data WRITE burst truncated with subsequent WRITE command, data fixed-length WRITE burst immediately followed data WRITE command. WRITE command issued clock following previous WRITE command, data provided coincident with command applies command. example shown Figure page Data either last burst last desired element longer burst. 128Mb SDRAM uses pipelined architecture and, therefore, does require rule associated with
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prefetch architecture. WRITE command initiated clock cycle following previous WRITE command. Full-speed random write accesses within page performed same bank, shown Figure page each subsequent WRITE performed different bank. Data WRITE burst truncated with subsequent READ command, data fixed-length WRITE burst immediately followed READ command. After READ command registered, data inputs will ignored, writes will executed. example shown Figure page Data either last burst last desired element longer burst. Figure WRITE-to-WRITE
COMMAND
WRITE
WRITE
ADDRESS
BANK,
BANK,
TRANSITIONING DATA
DON'T CARE
Notes:
LOW. Each WRITE command bank.
Figure
Random WRITE Cycles
COMMAND
WRITE
WRITE
WRITE
WRITE
ADDRESS
BANK,
BANK,
BANK,
BANK,
TRANSITIONING DATA
DON'T CARE
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Figure WRITE-to-READ
COMMAND
WRITE
READ
ADDRESS
BANK,
BANK,
DOUT
DOUT
TRANSITIONING DATA
DON'T CARE
Data fixed-length WRITE burst followed truncated with, PRECHARGE command same bank (provided that auto precharge activated), full-page WRITE burst truncated with PRECHARGE command same bank. PRECHARGE command should issued after clock edge which last desired input data element registered. auto precharge mode requires least clock plus time (see note page 52), regardless frequency. addition, when truncating WRITE burst, signal must used mask input data clock edge prior clock edge coincident with, PRECHARGE command. example shown Figure page Data either last burst last desired longer burst. Following PRECHARGE command, subsequent command same bank cannot issued until met. case fixed-length burst being executed completion, PRECHARGE command issued optimum time described above) provides same operation that would result from same fixed-length burst with auto precharge. disadvantage PRECHARGE command that requires that command address buses available appropriate time issue command; advantage PRECHARGE command that used truncate fixed-length full-page bursts. Fixed-length full-page WRITE bursts truncated with BURST TERMINATE command. When truncating WRITE burst, input data applied coincident with BURST TERMINATE command will ignored. last data written (provided that that time) will input data applied clock previous BURST TERMINATE command. This shown Figure page where data last desired data element longer burst.
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Figure WRITE-to-PRECHARGE
tCLK 15ns
COMMAND
WRITE
PRECHARGE
ACTIVE
ADDRESS
BANK
BANK all)
BANK
tCLK 15ns
COMMAND ADDRESS
WRITE
PRECHARGE
ACTIVE
BANK
BANK all)
BANK
TRANSITIONING DATA
DON'T CARE
Notes:
could remain this example WRITE burst fixed length two.
Figure
Terminating WRITE Burst
COMMAND
WRITE
BURST TERMINATE
NEXT COMMAND
ADDRESS
BANK,
(ADDRESS)
(DATA)
TRANSITIONING DATA
DON'T CARE
Notes:
DQMs LOW.
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PRECHARGE command (see Figure used deactivate open particular bank open banks. bank(s) will available subsequent access some specified time (tRP) after PRECHARGE command issued. Input determines whether banks precharged, case where only bank precharged, inputs BA0, select bank. When banks precharged, inputs BA0, treated "Don't Care." After bank been precharged, idle state must activated prior READ WRITE commands being issued that bank. Figure PRECHARGE Command
HIGH
RAS#
CAS#
A0-A9
Banks
Bank Selected
BA0,
BANK ADDRESS
VALID ADDRESS
DON'T CARE
Power-Down
Power-down occurs registered coincident with COMMAND INHIBIT when accesses progress. power-down occurs when banks idle, this mode referred precharge power-down; power-down occurs when there active bank, this mode referred active power-down. Entering power-down deactivates input output buffers, excluding CKE, maximum power savings while standby. device remain power-down state longer than refresh period (tREF tREFAT since REFRESH operations performed this mode. power-down state exited registering COMMAND INHIBIT HIGH desired clock edge (meeting tCKS). Figure page
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Figure Power-Down
tCKS
tCKS
COMMAND
ACTIVE
banks idle Input buffers gated Enter power-down mode Exit power-down mode
tRCD tRAS DON'T CARE
Clock Suspend
clock suspend mode occurs when column access/burst progress registered low. clock suspend mode, internal clock deactivated, "freezing" synchronous logic. each positive clock edge which sampled LOW, next internal positive clock edge suspended. command data present input pins time suspended internal clock edge ignored; data present pins remains driven; burst counters incremented, long clock suspended. (See examples Figure Figure page 38.) Clock suspend mode exited registering HIGH; internal clock related operation will resume subsequent positive clock edge. Figure Clock Suspend During WRITE Burst
INTERNAL CLOCK
COMMAND
WRITE
ADDRESS
BANK,
TRANSITIONING DATA
DON'T CARE
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Figure Clock Suspend During READ Burst
INTERNAL CLOCK
COMMAND
READ
ADDRESS
BANK,
DOUT
DOUT
DOUT
DOUT
TRANSITIONING DATA
DON'T CARE
Notes:
this example, greater, LOW.
BURST READ/SINGLE WRITE
burst read/single write mode entered programming write burst mode (M9) mode register logic this mode, WRITE commands result access single column location (burst one), regardless programmed READ commands access columns according programmed sequence, just normal mode operation
Concurrent Auto Precharge
access command (READ WRITE) another bank while access command with auto precharge enabled executing allowed SDRAMs, unless SDRAM supports concurrent auto precharge. Micron SDRAMs support concurrent auto precharge. Four cases where concurrent auto precharge occurs defined below. READ with Auto Precharge Interrupted READ (with without auto precharge): READ bank will interrupt READ bank later. precharge bank will begin when READ bank registered (Figure page 39). Interrupted WRITE (with without auto precharge): WRITE bank will interrupt READ bank when registered. should used clocks prior WRITE command prevent contention. precharge bank will begin when WRITE bank registered (Figure page 39).
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Figure READ With Auto Precharge Interrupted READ
READ BANK READ BANK
COMMAND BANK
Page Active
READ with Burst
Interrupt Burst, Precharge BANK
Idle BANKm Precharge
Internal States
BANK
Page Active
READ with Burst
ADDRESS
BANK
BANK DOUT (BANK (BANK DOUT DOUT DOUT
TRANSITIONING DATA
DON'T CARE
Notes:
LOW.
Figure
READ With Auto Precharge Interrupted WRITE
READ BANK WRITE BANK
COMMAND BANK
Page READ with Burst Active
Interrupt Burst, Precharge BANK
Idle BANK Write-Bac
Internal States
BANK
BANK
Page Active
WRITE with Burst
ADDRESS DQM1
BANK
DOUT (BANK
TRANSITIONING DATA
DON'T CARE
Notes:
HIGH prevent DOUT from contending with
WRITE with Auto Precharge Interrupted READ (with without auto precharge): READ bank will interrupt WRITE bank when registered, with data-out appearing later. precharge bank will begin after met, where begins when READ bank registered. last valid WRITE bank will data-in registered clock prior READ bank (Figure page 40).
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Interrupted WRITE (with without auto precharge): WRITE bank will interrupt WRITE bank when registered. precharge bank will begin after met, where begins when WRITE bank registered. last valid data WRITE bank will data registered clock prior WRITE bank (Figure 33). Figure WRITE With Auto Precharge Interrupted READ
WRITE BANK READ BANK
COMMAND BANK
Page Active
WRITE with Burst
Interrupt Burst, Write-Back
Precharge
Internal States
BANK
BANK
BANK
BANK
Page Active
READ with Burst
ADDRESS
BANK
BANK DOUT (BANK DOUT
TRANSITIONING DATA
DON'T CARE
Notes:
LOW.
Figure
WRITE With Auto Precharge Interrupted WRITE
WRITE BANK WRITE BANK
COMMAND BANK
Page Active
WRITE with Burst
Interrupt Burst, Write-Back
Precharge
Internal States
BANK
BANK
BANK
BANK
Page Active
WRITE with Burst
Write-Bac
ADDRESS
BANK
BANK
TRANSITIONING DATA
DON'T CARE
Notes:
LOW.
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Table
CKEn
Truth Table
Notes: CKEn Current State Power-down Self refresh Clock suspend Power-down Self refresh Clock suspend banks idle banks idle Reading writing Notes: Commandn COMMAND INHIBIT COMMAND INHIBIT NOPX COMMAND INHIBIT AUTO REFRESH WRITE Table page Actionn Maintain power-down Maintain self refresh Maintain clock suspend Exit power-down Exit self refresh Exit clock suspend Power-down entry Self refresh entry Clock suspend entry Notes
CKEn logic state clock edge CKEn state previous clock edge. Current state state SDRAM immediately prior clock edge COMMANDn command registered clock edge ACTIONn result COMMANDn. states sequences shown illegal reserved. Exiting power-down clock edge will device banks idle state time clock edge (provided that tCKS met). Exiting self refresh clock edge will device banks idle state after tXSR met. COMMAND INHIBIT commands should issued clock edges occurring during tXSR period. minimum commands must provided during tXSR period. After exiting clock suspend clock edge device will resume operation recognize next command clock edge
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Table
Current State Idle
Truth Table Current State Bank Command Bank
Notes: 1-6; notes appear below next page Notes: RAS# CAS# Command (Action) COMMAND INHIBIT (NOP/continue previous operation) OPERATION (NOP/continue previous operation) ACTIVE (Select activate row) AUTO REFRESH PRECHARGE READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE (Deactivate bank banks) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE (Truncate READ burst, start precharge) BURST TERMINATE READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE (Truncate WRITE burst, start precharge) BURST TERMINATE Notes
active
Read (auto precharge disabled) Write (Aauto precharge disabled)
This table applies when CKEn HIGH CKEn HIGH (see Table page after tXSR been previous state self refresh). This table bank-specific, except where noted; that current state specific bank, commands shown those allowed issued that bank when that state. Exceptions covered notes below. Current state definitions: bank been precharged, been met. bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: READ burst been initiated, with auto precharge disabled, terminated been terminated. Write: WRITE burst been initiated, with auto precharge disabled, terminated been terminated. following states must interrupted command issued same bank. COMMAND INHIBIT commands allowable commands other bank should issued clock edge occurring during these states. Allowable commands other bank determined current state Truth Table according Truth Table Idle: active: Precharging: activating: Read w/auto precharge enabled: Write w/auto precharge enabled: Starts with registration PRECHARGE command ends when met. After met, bank will idle state. Starts with registration ACTIVE command ends when tRCD met. After tRCD met, bank will active state. Starts with registration READ command with auto precharge enabled ends when been met. After met, bank will idle state. Starts with registration WRITE command with auto precharge enabled ends when been met. After met, bank will idle state.
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following states must interrupted executable command; COMMAND INHIBIT commands must applied each positive clock edge during these states. Starts with registration AUTO REFRESH command ends when met. After met, SDRAM will banks idle state. Starts with registration command ends when tMRD Accessing mode been met. After tMRD met, SDRAM will banks register: idle state. Precharging all: Starts with registration PRECHARGE command ends when met. After met, banks will idle state. states sequences shown illegal reserved. bank-specific; requires that banks idle. bank-specific; banks precharged, must valid state precharging. bank-specific; BURST TERMINATE affects most recent READ WRITE burst, regardless bank. READs WRITEs listed Command (Action) column include READs WRITEs with auto precharge enabled READs WRITEs with auto precharge disabled. Does affect state bank acts that bank. Refreshing:
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Table
Current State Idle activating, active, precharging Read (auto precharge disabled) Write (auto precharge disabled) Read (with auto precharge) Write (with auto precharge)
Truth Table Current State Bank Command Bank
Notes: 1-6; notes appear below next page Notes: RAS# CAS# Command (Action) COMMAND INHIBIT (NOP/continue previous operation) OPERATION (NOP/continue previous operation) command otherwise allowed bank ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE ACTIVE (Select activate row) READ (Select column start READ burst) WRITE (Select column start WRITE burst) PRECHARGE Notes
This table applies when CKEn HIGH CKEn HIGH (see Table page after tXSR been previous state self refresh). This table describes alternate bank operation, except where noted; that current state bank commands shown those allowed issued bank (assuming that bank such state that given command allowable). Exceptions covered notes below. Current state definitions: bank been precharged, been met. bank been activated, tRCD been met. data bursts/accesses register accesses progress. Read: READ burst been initiated, with auto precharge disabled, terminated been terminated. Write: WRITE burst been initiated, with auto precharge disabled, terminated been terminated. Starts with registration READ command with auto precharge Read w/auto precharge enabled: enabled, ends when been met. After met, bank will idle state. Write w/auto Starts with registration WRITE command with auto precharge precharge enabled: enabled, ends when been met. After met, bank will idle state. AUTO REFRESH, SELF REFRESH, commands only issued when banks idle. Idle: active:
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BURST TERMINATE command cannot issued another bank; applies bank represented current state only. states sequences shown illegal reserved. READs WRITEs bank listed Command (Action) column include READs WRITEs with auto precharge enabled READs WRITEs with auto precharge disabled. Concurrent auto precharge: Bank will initiate auto precharge command when burst been interrupted bank burst. Burst bank continues initiated. READ without auto precharge interrupted READ (with without auto precharge), READ bank will interrupt READ bank later (Figure page 27). READ without auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt READ bank when registered (Figure page Figure page 29). should used clock prior WRITE command prevent contention. WRITE without auto precharge interrupted READ (with without auto precharge), READ bank will interrupt WRITE bank when registered (Figure page 34), with data-out appearing later. last valid WRITE bank will data-in registered clock prior READ bank WRITE without auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt WRITE bank when registered (Figure page 33). last valid WRITE bank will data-in registered clock prior READ bank READ with auto precharge interrupted READ (with without auto precharge), READ bank will interrupt READ bank later. precharge bank will begin when READ bank registered (Figure page 39). READ with auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt READ bank when registered. should used clocks prior WRITE command prevent contention. precharge bank will begin when WRITE bank registered (Figure page 39). WRITE with auto precharge interrupted READ (with without auto precharge), READ bank will interrupt WRITE bank when registered, with data-out appearing later. precharge bank will begin after met, where begins when READ bank registered. last valid WRITE bank will data-in registered clock prior READ bank (Figure page 40). WRITE with auto precharge interrupted WRITE (with without auto precharge), WRITE bank will interrupt WRITE bank when registered. precharge bank will begin after met, where begins when WRITE bank registered. last valid WRITE bank will data registered clock prior WRITE bank (Figure page 40).
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Electrical Specifications
Stresses greater than those listed Table cause permanent damage device. This stress rating only, functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability. Table
Parameter Voltage VDD/VDDQ supply relative Voltage inputs, pins relative Operating temperature (commercial) (industrial) (automotive) Storage temperature (plastic) Power dissipation
Absolute Maximum Ratings
+4.6 +4.6 +105 +150 Rating
Temperature Thermal Impedance
imperative that SDRAM device's temperature specifications, shown Table page maintained ensure junction temperature proper operating range meet data sheet specifications. important step maintaining proper junction temperature using device's thermal impedances correctly. thermal impedances listed Table page applicable revision packages being made available. These thermal impedance values vary according density, package, particular design used each device. Incorrectly using thermal impedances produce significant errors. Read Micron technical note TN-00-08, "Thermal Applications" prior using thermal impedances listed Table ensure compatibility current future designs, contact Micron Applications Engineering confirm thermal impedance values. SDRAM device's safe junction temperature range maintained when specification exceeded. applications where device's ambient temperature high, forced and/or heat sinks required satisfy case temperature specifications.
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Table
Parameter Operating case temperature: Commercial Industrial Automotive Junction temperature: Commercial Industrial Automotive Ambient temperature: Commercial Industrial Automotive Peak reflow temperature Notes:
Temperature Limits
Symbol Units Notes
TPEAK
operating case temperature, measured center package side device, shown Figure Figure Figure page Device functionality guaranteed device exceeds maximum during operation. temperature specifications must satisfied case temperature should measured gluing thermocouple center component. This should done with bead conductive epoxy, defined JEDEC EIA/JESD51 standards. Care should taken ensure thermocouple bead touching case. Operating ambient temperature surrounding package.
Table
Thermal Impedance Simulated Values
(°C/W) Airflow 0m/s 86.2 58.9 72.1 54.5 70.9 54.6 (°C/W) Airflow 1m/s 67.8 50.7 57.3 46.6 56.8 47.3 (°C/W) Airflow 2m/s 47.6 50.6 42.8 50.3 43.5
Revision
Package 54-pin TSOP 54-ball VFBGA 60-ball FBGA Notes:
Substrate 2-layer 4-layer 2-layer 4-layer 2-layer 4-layer
(°C/W) 46.9 41.5 35.5 36.3 36.3
(°C/W) 11.3
designs expected last beyond revision listed, contact Micron Applications Engineering confirm thermal impedance values. Thermal resistance data sampled from multiple lots, values should viewed typical. These estimates; actual results vary.
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Figure Example Temperature Test Point Location, 54-Pin TSOP: View
22.22mm 11.11mm Test point
10.16mm 5.08mm
Figure
Example Temperature Test Point Location, 54-Ball VFBGA: View
8.00mm 4.00mm Test point
8.00mm 4.00mm
Figure
Example Temperature Test Point Location, 60-Ball FBGA: View
8.00mm 4.00mm
Test point
16.00mm
8.00mm
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Table Electrical Characteristics Operating Conditions
Notes: notes appear page VDD/VDDQ +3.3 ±0.3V Parameter/Condition Supply voltage Input high voltage: Logic inputs Input voltage: Logic inputs Input leakage current: input (All other pins under test Output leakage current: disabled; VOUT VDDQ Output levels: Output high voltage (IOUT -4mA) Output voltage (IOUT 4mA) Symbol VDD/VDDQ -0.3 Units Notes
Table
Specifications Conditions
Notes: notes appear page VDD/VDDQ +3.3 ±0.3V
Parameter/Condition Operating current: Active mode; Burst READ WRITE; (MIN) Standby current: Power-down mode; banks idle; Standby current: Active mode; HIGH; HIGH; banks active after tRCD met; accesses progress Operating current: Burst mode; Page burst; READ WRITE; banks active tRFC tRFC (MIN) Auto refresh current: tRFC 15.625µs HIGH; HIGH tRFC 3.906µs(AT) Self refresh current: Standard 0.2V power
Symbol IDD1 IDD2 IDD3
Units
Notes
IDD4 IDD5 IDD6 IDD6 IDD7 IDD7
Table
Capacitance
Note: notes appear page Symbol Units Notes
Parameter TSOP "TG" Package Input capacitance: Input capacitance: other input-only pins Input/output capacitance: Parameter FBGA "FB" Input capacitance: Input capacitance: other input-only pins
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Table
Electrical Characteristics Recommended Operating Conditions
Notes: notes appear page Symbol AC(3) AC(2) tCK(3) tCK(2) tCKH tCKS tCMH tCMS tHZ(3) tHZ(2) tOHN tRAS tRCD tREF tREF
tRFC tRRD
Characteristics Parameter Access time from (positive edge) Address hold time Address setup time high-level width low-level width Clock cycle time
120,000
120,000 Units Notes
hold time setup time CS#, RAS#, CAS#, WE#, hold time CS#, RAS#, CAS#, WE#, setup time Data-in hold time Data-in setup time Data-out High-Z time Data-out Low-Z time Data-out hold time (load) Data-out hold time load) ACTIVE-to-PRECHARGE command ACTIVE-to-ACTIVE command period ACTIVE-to-READ WRITE delay Refresh period (4,096 rows) Refresh period Automotive (4,096 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank ACTIVE bank command Transition time WRITE recovery time
120,000
Exit SELF REFRESH ACTIVE command
tXSR
7.5ns
Table
Parameter
Functional Characteristics
Notes: notes appear page Symbol
tCCD tCKED
Units
Notes
READ/WRITE command READ/WRITE command clock disable power-down entry mode clock enable power-down exit setup mode input data delay
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tDQD
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Table
Parameter data mask during WRITEs data High-Z during READs WRITE command input data delay Data-in ACTIVE command Data-in PRECHARGE command Last data-in burst STOP command Last data-in READ/WRITE command Last data-in PRECHARGE command command ACTIVE REFRESH command Data-out High-Z from PRECHARGE command
Functional Characteristics
Notes: notes appear page Symbol tDPL ROH(3) tROH(2)
Units
Notes
Notes
voltages referenced VSS. This parameter sampled. VDD, VDDQ +3.3V; MHz, 25°C; under test biased 1.4V. dependent output loading cycle rates. Specified values obtained with minimum cycle time outputs open. Enables on-chip refresh address counters. minimum specifications used only indicate cycle time which proper operation over full temperature range (0°C +70°C (commercial), -40°C +85°C (industrial), -40°C +105°C (automotive) ensured. initial pause 100µs required after power-up, followed AUTO REFRESH commands, before proper device operation ensured. (VDD VDDQ must powered simultaneously. VSSQ must same potential.) AUTO REFRESH command wake-ups should repeated time tREF refresh requirement exceeded. characteristics assume 1ns. addition meeting transition rate specification, clock must transit between between VIH) monotonic manner. Outputs measured 1.5V with equivalent load:
50pF
defines time which output achieves open circuit condition; reference VOL. last valid data element will meet before going High-Z. timing tests have with timing referenced 1.5V crossover point. input transition time longer than then timing referenced (MAX) (MIN) longer 1.5V crossover point. should always 1.5V referenced crossover. Refer Micron technical note TN-48-09 more details.
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Other input signals allowed transition more than once every clocks otherwise valid levels. specifications tested after device properly initialized. Timing actually specified tCKS; clock(s) specified reference only minimum cycle rate. Timing actually specified plus tRP; clock(s) specified reference only minimum cycle rate. Timing actually specified tWR. Required clocks specified JEDEC functionality dependent timing parameter. current will increase decrease proportionally according amount frequency alteration test condition. Address transitions average transition every clocks. must toggled minimum times during this period. Based 7.5ns -75/-7E, -6A. overshoot: (MAX) VDDQ pulse width 3ns, pulse width cannot greater than one-third cycle rate. undershoot: (MIN) pulse width 3ns. clock frequency must remain constant (stable clock defined signal cycling within timing constraints specified clock pin) during access precharge states (READ, WRITE, including tWR, PRECHARGE commands). used reduce data rate. Auto precharge mode only. precharge timing budget (tRP) begins -6A, -7E, 7.5ns after first clock delay, after last WRITE executed. Precharge mode only. JEDEC PC100 specify clocks. -75/-7E with load 4.6ns guaranteed design. Parameter guaranteed design. PC100 specifies maximum 4pF. PC100 specifies maximum 5pF. PC100 specifies maximum 6.5pF. -75, 7.5ns; -7E, 7.5ns, 6ns. HIGH during refresh command period tRFC (MIN) else LOW. IDD6 limit actually nominal value does result fail value. PC133 specifies minimum 2.5pF. PC133 specifies minimum 2.5pF. PC133 specifies minimum 3.0pF.
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Timing Diagrams
Figure Initialize Load Mode Register
tCKS
tCKH
tCMS tCMH
AUTO REFRESH
tCMS tCMH COMMAND
tCMS tCMH
PRECHARGE
AUTO REFRESH
LOAD MODE REGISTER
ACTIVE
DQML, DQMH
A0-A9,
CODE
BANKS SINGLE BANK
CODE
BA0,
BANKS
BANK
100µs Power-up: stable
High-Z
tRFC
tRFC
tMRD
Precharge banks
AUTO REFRESH
AUTO REFRESH
Program Mode Register DON'T CARE
Notes:
HIGH clock HIGH time, commands applied NOP. mode register loaded prior AUTO REFRESH cycles desired. JEDEC PC100 specify clocks. Outputs guaranteed High-Z after command issued.
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Figure Power-Down Mode
tCKS tCKS tCKH
tCKS
tCMS tCMH COMMAND
PRECHARGE
ACTIVE
DQML, DQMH
A0-A9,
BANKS
SINGLE BANK
BA0,
BANK(S)
High-Z
BANK
clock cycles Precharge active banks banks idle, enter power-down mode
Input buffers gated while power-down mode banks idle Exit power-down mode DON'T CARE
Notes:
Violating refresh requirements during power-down result loss data.
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Figure
Clock Suspend Mode
tCKS tCKH
tCKS tCKH
tCMS tCMH COMMAND
READ WRITE
tCMS tCMH DQML, DQMH A0-A9,
COLUMN
COLUMN
BA0,
BANK BANK
DOUT
DOUT
DON'T CARE UNDEFINED
Notes:
this example, auto precharge disabled. x16: "Don't Care." "Don't Care."
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Figure Auto Refresh Mode
tCKS tCMS tCKH tCMH
AUTO REFRESH
COMMAND
PRECHARGE
AUTO REFRESH
ACTIVE
DQML, DQMH
A0-A9,
BANKS
SINGLE BANK
BA0,
BANK(S)
tRFC1 tRFC1
BANK
High-Z
Precharge active banks
DON'T CARE
Notes:
Each AUTO REFRESH command performs refresh cycle. Back-to-back commands required.
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Figure Self Refresh Mode
tCKS
tRAS min1
tCKS tCMS COMMAND tCKH tCMH
AUTO REFRESH
PRECHARGE
COMMAND
INHIBIT
AUTO REFRESH
A0-A9,
BANKS
SINGLE BANK
BA0,
BANK(S)
High-Z Precharge active banks
tXSR Enter self refresh mode Exit self refresh mode (Restart refresh time base) DON'T CARE
stable prior exiting self refresh mode
Notes:
tXSR
maximum time limit self refresh. tRAS applies non-self refresh mode. requires minimum clocks regardless frequency timing. Self refresh mode supported automotive temperature (AT) devices.
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Figure READ Without Auto Precharge
tCKS tCMS tCMH COMMAND ACTIVE READ tCMS tCMH DQML, DQMH A0-A9, BA0, BANK DISABLE AUTO PRECHARGE BANK DOUT DOUT SINGLE BANKS BANK(S) DOUT DOUT BANK
COLUMN
tCKH
PRECHARGE
ACTIVE
BANKS
tRCD tRAS Latency
DON'T CARE UNDEFINED
Notes:
this example, READ burst followed "manual" PRECHARGE. x16: "Don't Care." "Don't Care."
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Figure READ With Auto Precharge
tCKS tCMS tCMH COMMAND
ACTIVE READ ACTIVE
tCKH
tCMS DQML, DQMH A0-A9,
tCMH
COLUMN
ENABLE AUTO PRECHARGE
BA0,
BANK BANK
BANK
tRCD tRAS Latency
DOUT
DOUT
DOUT
DOUT
DON'T CARE UNDEFINED
Notes:
this example, x16: "Don't Care." "Don't Care."
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Figure Single READ Without Auto Precharge
tCKS tCMS tCMH COMMAND ACTIVE READ tCMS tCMH DQML, DQMH A0-A9, BA0, BANK DISABLE AUTO PRECHARGE BANK SINGLE BANKS BANK(S) BANK
COLUMN
tCKH
PRECHARGE
ACTIVE
BANKS
tRCD tRAS Latency
DOUT
DON'T CARE UNDEFINED
Notes:
this example, READ burst followed "manual" PRECHARGE. x16: "Don't Care." "Don't Care." PRECHARGE command allowed tRAS would violated.
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Figure
tCKS tCMS tCMH COMMAND
ACTIVE NOP2 NOP2 READ ACTIVE
Single READ With Auto Precharge
tCKH
tCMS DQML, DQMU A0-A9,
tCMH
COLUMN
ENABLE AUTO PRECHARGE
BA0,
BANK BANK
BANK
tRCD tRAS Latency
DOUT
DON'T CARE UNDEFINED
Notes:
this example, x16: "Don't Care." "Don't Care." READ command allowed tRAS would violated.
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Figure Alternating Bank Read Accesses
tCKS tCMS tCMH COMMAND
ACTIVE READ ACTIVE READ ACTIVE
tCKH
tCMS DQML, DQMH A0-A9,
tCMH
COLUMN
COLUMN
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
BA0,
BANK BANK BANK BANK
BANK
tRCD BANK tRAS BANK BANK tRRD Latency BANK
DOUT
DOUT
DOUT
DOUT
DOUT
BANK
tRCD BANK
tRCD BANK
Latency BANK
DON'T CARE UNDEFINED
Notes:
this example, x16: "Don't Care." "Don't Care."
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Figure
tCKS tCMS COMMAND tCMH
READ
READ Full-Page Burst
tCKH
ACTIVE
BURST TERM
tCMS DQML, DQMH A0-A9,
tCMH
COLUMN
BA0,
BANK
BANK
tRCD Latency
DOUT
DOUT
DOUT
DOUT
DOUT
DOUT
(x16) locations within same 1,024 (x8) locations within same 2,048 (x4) locations within same
Full page completed Full-page burst does self-terminate. BURST TERMINATE command.
DON'T CARE UNDEFINED
Notes:
this example, x16: "Don't Care." "Don't Care." Page left open; tRP.
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Figure READ Operation
tCKS tCMS COMMAND tCMH
READ
tCKH
ACTIVE
tCMS DQML, DQMH A0-A9,
tCMH
COLUMN ENABLE AUTO PRECHARGE
BA0,
BANK
DISABLE AUTO PRECHARGE BANK
tRCD Latency
DOUT
DOUT
DOUT
DON'T CARE UNDEFINED
Notes:
this example, x16: "Don't Care." "Don't Care."
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Figure
tCKS tCMS COMMAND tCMH
WRITE PRECHARGE ACTIVE
WRITE Without Auto Precharge
tCKH
ACTIVE
tCMS tCMH DQML, DQMH A0-A9,
COLUMN BANKS DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK
BA0,
BANK
tRCD tRAS
DON'T CARE
Notes:
this example, WRITE burst followed "manual" PRECHARGE. 15ns required between <DIN PRECHARGE command, regardless frequency. x16: "Don't Care." "Don't Care."
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Figure
tCKS tCMS COMMAND tCMH
WRITE ACTIVE
WRITE With Auto Precharge
tCKH
ACTIVE
tCMS tCMH DQML, DQMH A0-A9,
COLUMN ENABLE AUTO PRECHARGE
BA0,
BANK BANK
BANK
tRCD tRAS
DON'T CARE
Notes:
this example, x16: "Don't Care." "Don't Care."
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Figure Single WRITE Without Auto Precharge
tCKS tCMS COMMAND tCMH
WRITE NOP2 NOP2 PRECHARGE ACTIVE
tCKH
ACTIVE
tCMS tCMH DQML, DQMU A0-A9,
COLUMN BANKS DISABLE AUTO PRECHARGE BANK SINGLE BANK BANK BANK
BA0,
BANK
tRCD tRAS
DON'T CARE
Notes:
this example, WRITE burst followed "manual" PRECHARGE. 15ns required between <DIN PRECHARGE command, regardless frequency. x16: "Don't Care." "Don't Care."
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Figure
tCKS tCMS COMMAND tCMH
NOP3 NOP3 NOP3 WRITE ACTIVE
Single WRITE With Auto Precharge
tCKH
ACTIVE
tCMS DQML, DQMH A0-A9,
tCMH
COLUMN ENABLE AUTO PRECHARGE
BA0,
BANK BANK
BANK
tRCD tRAS
DON'T CARE
Notes:
this example, x16: "Don't Care." "Don't Care." Write command allowed tRAS would violated.
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Figure
tCKS tCMS COMMAND tCMH
WRITE ACTIVE WRITE ACTIVE
Alternating Bank Write Accesses
tCKH
ACTIVE
tCMS DQML, DQMH A0-A9,
tCMH
COLUMN
COLUMN
ENABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
BA0,
BANK BANK BANK BANK
BANK
tRCD BANK tRAS BANK BANK tRRD
tRCD BANK
BANK
BANK
tRCD BANK
BANK
DON'T CARE
Notes:
this example, x16: "Don't Care." "Don't Care."
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Figure WRITE Full-Page Burst
tCKS tCMS COMMAND tCMH
WRITE
tCKH
ACTIVE
BURST TERM
tCMS tCMH DQML, DQMH A0-A9,
COLUMN
BA0,
BANK
BANK
tRCD
Full-page burst does self-terminate. BURST TERMINATE command stop.2,
(x16) locations within same 1,024 (x8) locations within same 2,048 (x4) locations within same
Full page completed
DON'T CARE
Notes:
x16: "Don't Care." "Don't Care." must satisfied prior PRECHARGE command. Page left open; tRP.
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Figure WRITE Operation
tCKS tCMS COMMAND tCMH
WRITE
tCKH
ACTIVE
tCMS tCMH DQML, DQMH A0-A9,
COLUMN ENABLE AUTO PRECHARGE
BA0,
DISABLE AUTO PRECHARGE BANK
BANK
tRCD
DON'T CARE
Notes:
this example, x16: "Don't Care." "Don't Care."
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Package Dimensions
Figure 54-Pin Plastic TSOP (400 mil)
0.10 0.375 ±0.075
22.22 ±.08 0.75 1.00 0.71
0.80 (FOR REFERENCE ONLY)
0.10 2.80 10.16 ±0.08 11.76 ±0.20 DETAIL +0.03 0.15 -0.02
PLATED LEAD FINISH: 100%Sn PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC PACKAGE WIDTH LENGTH INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION 0.25 SIDE. GAGE PLANE 0.25 +0.10 0.10 -0.05
0.50 ±0.10 0.80 DETAIL
Notes:
dimensions millimeters. Package width length include mold protrusion; allowable mold protrusion 0.25mm side. "2X" means notch present locations (both ends device).
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128Mb: SDRAM Package Dimensions
Figure 60-Ball FBGA "FB/BB" Package device), 16mm
0.155 ±0.013 0.850 ±0.05 0.10 SEATING PLANE 2.40 ±0.05 0.45 DIMENSIONS APPLY SOLDER BALLS POST REFLOW. PREREFLOW DIAMETER 0.42 0.33 NSMD BALL PAD. BALL 8.00 ±0.05 16.00 ±0.10 11.20 5.60 SOLDER BALL MATERIAL: 96.5% 0.5% SUBSTRATE: PLASTIC LAMINATE 8.00 ±0.10 5.60 0.80 BALL ENCAPSULATION MATERIAL: EPOXY NOVOLAC BALL BALL
0.80
2.80 4.00 ±0.05 1.20
Notes:
dimensions millimeters. Recommended size 0.33mm ±0.025mm. Topside part marking decoder found http://www.micron.com/decoder.
PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm Rev. 1/09
Micron Technology, Inc., reserves right change products specifications without notice. ©1999 Micron Technology, Inc. rights reserved.
128Mb: SDRAM Package Dimensions
Figure 54-Ball VFBGA "F4/B4" Package (x16 device),
0.65 ±0.05
SEATING PLANE 0.10 ±0.05 SOLDER BALL DIAMETER REFERS POST REFLOW CONDITION. PREREFLOW DIAMETER 0.42. BALL SOLDER BALL MATERIAL: 96.5% 0.5% SOLDER MASK DEFINED BALL PADS: SUBSTRATE MATERIAL: PLASTIC LAMINATE MOLD COMPOUND: EPOXY NOVOLAC BALL BALL
6.40 0.80
BALL 4.00 ±0.05 8.00 ±0.10
6.40
3.20
0.80
3.20 4.00 ±0.05 1.00
8.00 ±0.10
Notes:
dimensions millimeters. Recommended size 0.40mm SMD. Topside part marking decoder found http://www.micron.com/decoder.
8000 Federal Way, P.O. Boise, 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, logo, Micron logo trademarks Micron Technology, Inc. other trademarks property their respective owners. This data sheet contains minimum maximum limits specified over complete power supply temperature range forth herein. Although considered final, these specifications subject change, further product development data characterization sometimes occur.
PDF: 09005aef8091e66d/Source: 09005aef8091e625 128MSDRAM_2.fm Rev. 1/09
Micron Technology, Inc., reserves right change products specifications without notice. ©1999 Micron Technology, Inc. rights reserved.
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