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MSM9405
IrDA Controller
SECOND EDITION
ISSUE DATE: Jul. 2000 FEAL9405-02
NOTICE
information contained herein change without notice owing product and/or technical improvements. Before using product, please make sure that information being referred up-to-date. outline action examples application circuits described herein have been chosen explanation standard action performance product. When planning product, please ensure that external conditions reflected actual circuit, assembly, program designs. When designing your product, please product below specified maximum ratings within specified operating ranges including, limited operating voltage, power dissipation, operating temperature. assumes responsibility liability whatsoever failure unusual unexpected operation resulting from misuse, neglect, improper installation, repair, alteration accident, improper handling, unusual physical electrical stress including, limited exposure parameters beyond specified maximum ratings operation outside specified operating range. Neither indemnity against license third party's industrial intellectual property right, etc. granted connection with product and/or information drawings contained herein. responsibility assumed infringement third party's right which result from thereof. products listed this document intended general electronics equipment commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products authorized system application that requires special enhanced quality reliability characteristics system application where failure such system application result loss damage property, death injury humans. Such applications include, limited traffic automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, life-support systems. Certain products this document need government approval before they exported particular countries. purchaser assumes responsibility determining legality export these products will take appropriate necessary steps their expense these. part contents cotained herein reprinted reproduced without prior permission. MS-DOS registered trademark Microsoft Corporation.
Copyright 2000 Electric Industry Co., Ltd.
Printed Japan
Semiconductor
MSM9405
CONTENTS
General Description Features Configuration Descriptions External Connection Example Transmit/Receive Procedure Examples Initialization Procedure Example. Receive Procedure Example: Transmit Procedure Example: Receive Procedure Example: Ex-SIR Transmit Procedure Example: Ex-SIR (S_EOT used) Transmit Procedure Example: Ex-SIR (TFL/TCC used) Transmit Procedure Example: Media Busy Detection Procedure Example External Interface Settings Setting Infrared Transceiver Module Interface 3.1.1 SD_INV 3.1.2 IRIN_SL 3.1.3 RXINV 3.1.4 MS_EN Selecting Crystal Unit. Setting DMAC Interface 3.3.1 DMA_EN 3.3.2 DMA_SL1, DMA_SL0 3.3.3 DMATH1, DMATH0 3.3.4 TC_INV, DACK_INV, DREQ_INV Setting Interrupt Interface Communication Mode Settings Setting Operating Modes 4.1.1 Power-Down Mode 4.1.2 Idle Mode 4.1.3 Transmit Mode 4.1.4 Receive Mode Setting Transfer Mode Setting Transfer Speed Setting Number BOFs (STAs) Setting Interrupts TXE_EV, TXE_IE TXL_EV, TXL_IE RXH/T_EV, TOUT, RXH/T_IE EOF_EV, EOF_IE MLE_EV, MLE_IE CE_EV, CE_IE OE_EV, OE_IE FE_EV, FE_IE.
MSM9405
Semiconductor
FCS/EOF S_EOT TFL/TCC. FIFO Setting Transmit/Receive Threshold Levels Number Data Bytes FIFO FCLR Other Functions. IR_DET. Send Serial Infrared Interaction Pulses Inverted Appendix-A Block Diagram Appendix-B Electrical Characteristics Appendix-C Timing Diagram Appendix-D Register Table Appendix-E Package Outline Dimensions.
Semiconductor
MSM9405
General Description
MSM9405 communication controller conforming physical specification ver1.1 IrDA, international standard infrared data communication. combining MSM9405 with another microcontroller, protocol stack, infrared transceiver module, equipment provided with IrDA-compliant communication function configured. MSM9405 provided with unique Extended-SIR mode insert remove BOF, EOF, hardware. They were inserted removed only software before. With Extended-SIR mode, possibe down software development cost, speed processing, reduce capacity. Since input pins except composed tolerant buffers, MSM9405 interface with systems. Features Data transfer rates 2400, 9600 bps; 19.2, 38.4, 57.6, 115.2 kbps; 0.576, 1.152, Mbps Extended-SIR mode support some functions protocol
Mode Extended-SIR Transfer rate 115.2 kbps 115.2 kbps 0.576 1.152 Mbps Mbps
Insert remove remove remove remove remove remove Preamble
Insert
Insert
Insert
Insert
Insert
Control Escape Byte Supported software (microcontroller) Supported hardware (MSM9405) Host interface 8-bit data transfer DREQ, DACK, Interrupt INTR Address Control signal Infrared transceiver module control signal Built-in 32-byte transmit-receive FIFOs Power down mode Built-in oscillator circuit Crystal oscillation frequency 18.432 (other than Mbps data rate) Mbps data rate) Operating voltage (VDD) Package: 30-pin plastic SSOP (SSOP30-P-56-0.65-K) (Product name MSM9405MB)
MSM9405 Application Manual Configuration Descriptions Configuration (Top View)
Semiconductor
XOUT TEST IRIN-A IRIN-B IROUT DREQ DACK PWDN RESET INTR
30-Pin Plastic SSOP
Semiconductor Descriptions
Function Infrared Transceiver Module Interface Symbol IRIN-A IRIN-B Type
MSM9405
Description Receive signal input (2.4 kbps Mbps)*1 Receive signal input (0.576 Mbps) When connecting this device infrared transceiver module, this high number receive signal output pins that module only one.*1
IROUT
Transmit signal output. Active high. Infrared transceiver module control signal output. Becomes active when PWDN low.*1 This must left open connecting this device infrared transceiver module having shutdown pins.
Microcontroller Interface
10-13
D7-D0 A3-A0 INTR DREQ DACK PWDN
Data input-output. Register address inputs. Chip select input. Active low. When low, read write signals enabled. Read signal input. Active low. Write signal input. Active low. Interrupt request signal output. Request signal output. acknowledge signal input. transfer signal input. Power down control. Active low. When low, oscillation stops device enters power down (low supply current) mode.
Controller Interface Others
RESET TEST XOUT
System reset input. Active low. When low, internal registers initialized. Test. Must left open. Crystal connect. Crystal connect. Power supply. Ground.
Either active high active selected depending register setting.
MSM9405 Application Manual External Connection Example Microcontroller interface
Semiconductor
MSM9405MB DACK DREQ INTR RESET PWDN XOUT
crystal TEST 0.01
HRM230S IRIN-A IRIN-B IROUT RxD_A RxD_B
Crystal units manufactured MEIDENSHA CORP. recommended. details, refer section 3.2, "Selecting Crystal Unit." value this resistor reference value connection HRM230S device manufactured Stanley Electric Co., Ltd. Consult with individual module manufacturers regarding peripheral components each infrared transceiver module. Since input pins except composed tolerant buffers, MSM9405 interface with systems. pins should pulled supply.
Note:
Semiconductor
MSM9405
Transmit/Receive Procedure Examples
Initialization Procedure Example
Transfer mode: Transfer speed: 9600 Crystal: Infrared transceiver module: HRM230S (manufactured Stanley Electric Co., Ltd.) controller: 8237 type (DMA transfer disabled)
Initialization start
DMA/interrupt interface
interface according 8237 type. (Set DREQ Active High; DACK Active Low; Active High; threshold during transmission during reception transfer mode single; disable transfer) (See section 3.3, "Setting DMAC Interface") INTR Active Low. (See section 3.4, "Setting Interrupt Interface") transfer mode SIR, transfer speed 9600 bps, crystal frequency MHz. (See section 3.2, "Selecting Crystal Unit", section 4.2, "Setting Transfer Mode", section 4.3, "Setting Transfer Speed") shutdown signal polarity receive pulse polarity HRM230S polarity, receive setting pins. (See section 3.1, "Setting Infrared Transceiver Module Interface") threshold level both transmit receive "14". (See section 7.1, "Setting Transmit/Receive Threshold Levels")
transfer mode, transfer speed, crystal frequency
infrared transceiver module
transmit/receive threshold level
Initialization completed
MSM9405 Application Manual Receive Procedure Example:
Semiconductor
Transfer mode: DMA: unused Window size:
Reception start
interrupts
Enable RXH/T, interrupts, disable other interrupts. (See section "Setting Interrupts")
receive mode ICR1
receive mode. (See section 4.1, "Setting Operating Modes")
INTR active? RXH/T_EV error processing
(See section "Setting Interrupts") Read receive data (Repeat read operation times) (See figure Read receive data FIFO. Read number receive data bytes FIFO. (See section 7.2, "Number Data Bytes FIFO")
Reception complete? idle mode ICR1 idle mode. (See section 4.1, "Setting Operating Modes")
Reception complete
Semiconductor Transmit Procedure Example:
MSM9405
Transfer mode: DMA: unused Window size: Transmission start interrupts transmit mode ICR1 INTR active? TXL_EV Write transmit data Write transmit data FIFO. (See figure (See section "Setting Interrupts") Enable interrupt, disable other interrupts. (See section "Setting Interrupts") transmit mode. (See section 4.1, "Setting Operating Modes")
transmit data been written?
(See section 7.2, "Number Data Bytes FIFO")
interrupts
Enable interrupt disable other interrupts. (See section "Setting Interrupts")
INTR active? TXE_EV idle mode ICR1 Transmission complete idle mode. (See section 4.1, "Setting Operating Modes") (See section "Setting Interrupts")
MSM9405 Application Manual Receive Procedure Example: Ex-SIR
Semiconductor
Transfer mode: Ex-SIR DMA: unused Window size:
Reception start Enable RXH/T, EOF, MLE, interrupts, disable other interrupts. (See section "Setting Interrupts") receive mode. (See section 4.1, "Setting Operating Modes")
interrupts
receive mode ICR1
INTR active?
(See section "Setting Interrupts") RXH/T_EV Read
Read number receive data bytes FIFO. (See section 7.2, "Number Data Bytes FIFO")
Read receive data (Repeat read operation number receive data bytes)
(See figure Read receive data FIFO.
Semiconductor Receive Procedure Example: Ex-SIR (continued)
MSM9405
E0F_EV
(See section "Setting Interrupts")
Error processing
(See section 7.2, "Number Data Bytes FIFO")
Read received data
(See figure
idle mode ICR1
idle mode. (See section 4.1, "Setting Operating Modes")
Reception complete
MSM9405 Application Manual Transmit Procedure Example: Ex-SIR (S_EOT used)
Semiconductor
Transfer mode: Ex-SIR unused S_EOT used Window size: N-byte data transmission
Transmission start
interrupts
Enable interrupt, disable other interrupts. (See section "Setting Interrupts")
transmit mode ICR1
transmit mode. (See section 4.1, "Setting Operating Modes")
INTR active? TXL_EV
(See section "Setting Interrupts")
(See section 7.2, "Number Data Bytes FIFO")
Remaining transmit data Byte?
Write transmit data Write transmit data FIFO. (See figure
Semiconductor Transmit Procedure Example: Ex-SIR (S_EOT used) (continued)
MSM9405
S_EOT
(See section 6.1, "How S_EOT")
Write last Byte transmit data
(See figure
interrupts
Enable interrupt disable other interrupts. (See section "Setting Interrupts")
INTR active? TXE_EV idle mode ICR1
(See section "Setting Interrupts")
idle mode. (See section 4.1, "Setting Operating Modes")
Transmission complete
MSM9405 Application Manual Transmit Procedure Example: Ex-SIR (TFL/TCC used)
Transfer mode: Ex-SIR unused TFL/TCC used Window size: N-byte data transmission Transmission start
Semiconductor
interrupts
Enable interrupt, disable other interrupts. (See section "Setting Interrupts")
number transmit data bytes
number transmit bytes register. (See section 6.2, "How TFL/TCC") 2048 transmit mode. (See section 4.1, "Setting Operating Modes") Enable TCC_EN. (See section 6.2, "How TFL/TCC")
transmit mode ICR1
INTR active? TXL_EV
(See section "Setting Interrupts")
Write transmit data
(See section 7.2, "Number Data Bytes FIFO") Write transmit data FIFO. (See figure
data been written TDR?
Semiconductor
MSM9405
Transmit Procedure Example: Ex-SIR (TFL/TCC used) (continued)
interrupts
Enable interrupt disable other interrupts. (See section "Setting Interrupts")
INTR active? TXE_EV idle mode ICR1
(See section "Setting Interrupts")
idle mode. (See section 4.1, "Setting Operating Modes")
Transmission complete
MSM9405 Application Manual Transmit Procedure Example:
Semiconductor
Transfer mode: Transfer speed: 1.152Mbps used controller: 8237 type Single address mode transfer mode: single Window size: N-byte data transmission
Process
Indicates process corresponding controller. (See controller specification details)
Transmission start
interrupts
Enable interrupt, disable other interrupts. (See section "Setting Interrupts")
mode
Enable mode. (See section 3.3, "Setting DMAC Interface")
number transmit data bytes
word count register controller.
controller operating mode
operating mode controller single transfer.
transmit mode ICR1
transmit mode. (See section 4.1, "Setting Operating Modes") Serial Infrared interaction pulse output mode. (See section 8.2, "How Send Serial Infrared Interaction Pulses") Enable inverted output. (See section 8.3, "Inverted CRC")
Enable transfer
Enable transfer controller.
Semiconductor Transmit Procedure Example: (continued)
MSM9405
Process
Indicates process corresponding controller.
INTR active? Read transfer complete flag Read transfer complete flag. (DMA transfer complete flag: transfer complete when Error processing (See section "Setting Interrupts")
Error processing
(See section 7.2, "Number Data Bytes FIFO") idle mode ICR1 idle mode. (See section 4.1, "Setting Operating Modes")
Transmission complete
MSM9405 Application Manual Media Busy Detection Procedure Example
Semiconductor
Media busy detection start
Read IR_DET
Clear IR_DET. (See section 8.1, "How IR_DET")
500ms Wait
(See section 8.1, "How IR_DET") IR_DET Media Busy True Media Busy Faulse
Media busy detection complete
Semiconductor
MSM9405
External Interface Settings
Setting Infrared Transceiver Module Interface MSM9405 contains following pins interfacing infrared transceiver: IRIN-A, IRIN-B, IROUT, Selection receive pins (IRIN-A, IRIN-B) selection polarity IRIN-A, IRIN-B, pins performed (SD_INV), (IRIN_SL), (RXINV) ICR2 register (address 5h). These pins settings allow connection various types infrared transceiver modules. example showing connection HRM230S infrared transceiver module (manufactured Stanley Electric Co., Ltd.) shown figure
IRIN-A IRIN-B IROUT MSM9405
RxD_A RxD_B HRM230S
(reference value) Figure 3.1.1 SD_INV (pin linked input signal PWDN (pin 20). connecting infrared transceiver module that active-low power-down (shuts down when level), SD_INV this state, level input PWDN MSM9405, MSM9405 will output level infrared transceiver module will enter shut down state. (The MSM9405 will enter power-down mode.) connecting transceiver module that active-high power-down (shuts down when high level), SD_INV this state, level input PWDN MSM9405, MSM9405 will output high level infrared transceiver module will enter shut down state. (The MSM9405 will enter power-down mode.) infrared transceiver module connected does contain shut down pin, leave MSM9405 open (unconnected) SD_INV either 3.1.2 IRIN_SL MSM9405 receive signal input pins, IRIN-A IRIN-B. IRIN_SL input signal will received from IRIN-A when transfer speed 115.2 kbps, from IRIN-B when transfer speed 0.576 Mbps. IRIN_SL input signal will received only from IRIN-A, regardless transfer speed. IRIN_SL when connecting infrared transceiver module that contains receive signal output pins. IRIN_SL when connecting infrared transceiver module that contains receive signal output pin.
MSM9405 Application Manual 3.1.3 RXINV
Semiconductor
RXINV setting selects polarity receive signal. RXINV IRIN-A IRIN-B) polarity active low. polarity active high. RXINV when connecting infrared transceiver module that will output high level when there signal level pulse when infrared pulse received. RXINV when connecting infrared transceiver module that will output level when there signal high level pulse when infrared pulse received. 3.1.4 MS_EN MS_EN (bit ICR1 register) utilized when infrared transceiver module (Note) used that requires mode externally. written this bit, MSM9405 will operate follows corresponding transfer mode. After operation complete, MS_EN automatically reset "0." When MSM9405 mode: high level IROUT high level. After approximately level Approximately after step (above), IROUT level When MSM9405 SIR, Ex-SIR, modes: high level IROUT level After approximately level Maintain IROUT level from approximately after step (above) MS_EN cannot used when 18.432 crystal used (XT_SL section 3.2, "Selecting Crystal Unit") Note: methods modes infrared transceiver modules, refer data sheet each module. When active high. When active low, level inverted.
Semiconductor Selecting Crystal Unit
MSM9405
18.432 external crystal Unit connected MSM9405. 18.432 unit used, transfer speed will 1.152 Mbps. Selection crystal unit performed (XT_SL) register (address 6h). XT_SL crystal unit used, XT_SL 18.432 crystal unit used.
XOUT MSM9405 MSM9405 XOUT
18.432
0.01
Figure following crystal units manufactured MEIDENSHA Corp. recommended. Depending upon crystal usage conditions, appropriate values will differ. Please consult with crystal manufacturer. MHz: 49U3H MHz, MS-3H 18.432 MHz: 49U3H 18.432 MHz, MS-3H 18.432
MSM9405 Application Manual Setting DMAC Interface
Semiconductor
register (address performs various settings related transfer. 3.3.1 DMA_EN DMA_EN (bit enables disables transfer. transfer disabled when DMA_EN transfer enabled when DMA_EN "1." 3.3.2 DMA_SL1, DMA_SL0 DMA_SL1 DMA_SL0 (bits select transfer mode. Modes selected follows. (See Figure Figure
DMA_SL1 DMA_SL0 Function Supports single address mode transfer signal asserted while DACK active, read cycle*1 begins. signal asserted while DACK active, write cycle*2 begins. When DACK active, access address (TDR/RDR) independently Supports single address mode transfer signal asserted while DACK active, read cycle*1 begins. signal asserted while DACK active, write cycle*2 begins. When DACK active, access address (TDR/RDR) independently Supports dual address mode transfer Access TDR/RDR Reserved
Read cycle: Write cycle:
Semiconductor
MSM9405
Single address mode (DMA_SL1 DMA_SL0 DACK: active low)
Memory Address
Memory Address
DACK
Read cycle Write cycle
Single address mode (DMA_SL1 DMA_SL0 DACK: active low)
Memory Address
Memory Address
DACK
Read cycle Write cycle
Figure
MSM9405
Semiconductor
Dual address mode (DMA_SL1 DMA_SL0 DACK: active low)
Memory Address
M9405*
M9405*
Memory Address
DACK
Read cycle Write cycle
Specify TDR/RDR (address 0h). Figure
Semiconductor
MSM9405
3.3.3 DMATH1, DMATH0 DMATH1 DMATH0 (bits determine threshold level which DREQ signal deasserted. When enabled during reception, DREQ signal asserted when number receive data bytes FIFO equal greater than receive threshold level register. (See section 7.1, "Setting Transmit/Receive Threshold Levels") when data read from FIFO number data bytes FIFO equal value DMATH, DREQ signal deasserted. When enabled during transmission, DREQ signal asserted when number transmit data bytes FIFO smaller than transmit threshold level register. (See section 7.1, "Setting Transmit/Receive Threshold Levels") when data written FIFO number data bytes FIFO equal value DMATH, DREQ signal deasserted. value greater than TXTH (see section 7.1, "Setting Transmit/Receive Threshold Levels") should DMATH during transmission, value smaller than RXTH should DMATH during reception.
DMATH1 DMATH0 During transmission During reception
3.3.4 TC_INV, DACK_INV, DREQ_INV TC_INV (bit sets polarity signal. When TC_INV "0", signal active when TC_INV "1", signal active high. DACK_INV (bit sets polarity DACK signal. When DACK_INV "0", DACK signal active high when DACK_INV "1", DACK signal active low. DREQ_INV (bit sets polarity DREQ signal. When DREQ _INV "0", DREQ signal active when DREQ _INV "1", DREQ signal active high. When transfer function used, DREQ should open DACK pins should connected GND. DREQ_INV either "1". However, DACK_INV TC_INV should that DACK pins become inactive. Setting Interrupt Interface (address sets interrupt interface. INTR_INV (bit sets polarity INTR signal. When INTR _INV "0", INTR signal active when INTR _INV "1", INTR signal active high. When interrupt function used, INTR should open INTR-INV either "1". through reserved future use.
MSM9405
Semiconductor
Communication Mode Settings
Setting Operating Modes MSM9405 following four operating modes. Operation modes directly controlled externally microcontroller other device. PWDN pulled low-level, MSM9405 enters power-down mode. with high-level applied PWDN pin, bits (RX_EN TX_EN) ICR1 register receive transmit modes.
PWDN Don't care RX_EN TX_EN Operating Mode Power-down Idle Transmit Receive
4.1.1 Power-Down Mode power-down mode, MSM9405 stops oscillation enters supply current state. this state, access TDR/RDR register (address 0h). Other registers accessed (addresses Dh). After power-down mode released, wait least before performing transmission reception. 4.1.2 Idle Mode idle mode, MSM9405 does perform transmission reception. register address operates TDR, transmit data written FIFO. FIFO cannot read. 4.1.3 Transmit Mode transmit mode, register address operates TDR, transmit data written FIFO. FIFO cannot read. Transmission automatically begins when there data FIFO. Data written FIFO differs depending upon transfer mode. Write data shaded sections figure MSM9405 automatically adds sections outside shaded areas. (See section "How FCS/EOF.") Ex-SIR mode, specific code (C0, escape sequence inserted front specific code specific code inverted) automatically performed. mode, inserted there consecutive after, inserted bit). When transmission completed, after transmit data been written FIFO, TXE_EV become "1", after both FIFO (See APPENDIX-A "Block Diagram" Transmitter Shift Register (TSR)) empty, TX_EN (See section "Setting Interrupts.") shift receive mode transmit mode mode, following operations should taken. idle mode. bits (TXTH register (address "0000". Write byte dummy data FIFO.
Semiconductor value TXTH arbitrary value. Write byte dummy data FIFO again. Clear dummy data written FIFO using FCLR. Start transmission. 4.1.4 Receive Mode
MSM9405
receive mode, register address operates RDR, FIFO read. Writing FIFO possible. code (Note) input IRIN-A IRIN-B) pin, reception will begin. Thereafter, serial pulse strings input IRIN-A IRIN-B) transformed into 8-bit parallel data written FIFO. Data written FIFO differs depending upon transfer mode. This data shaded sections figure MSM9405 automatically deletes sections outside shaded areas. However, Ex-SIR mode, mode, mode, MSM9405 cannot detect (STO) errors after reception begins code next frame input, MSM9405 will write code into FIFO data without identifying code begining frame. this case, setting RX_EN then allows MSM9405 detect code that input thereafter begining frame. Ex-SIR mode, contrast transmission, specific code (C0, automatically reconstructed front specific code deleted specific code inverted). mode, deleted there consecutive before, deleted). Note Ex-SIR code (C0h) (C0h) (7Eh) Preamble (1000000010101000)
Address Control section section Information section
Ex-SIR
Address Control section section
Information section
Address Control section section
Information section
Address Control section section
Information section FIR: CRC32
(Frame Check Sequence) Ex-SIR, MIR: CRC16
Figure
MSM9405
Semiconductor
Setting Transfer Mode MSM9405 following different transfer modes using (IRSL1) (IRSL0) register address
IRSL1 IRSL0 Extended-SIR Mode Transfer speed 115.2 kbps 115.2 kbps 0.576 1.152 Mbps Mbps
Setting Transfer Speed MSM9405 select transfer speed using (DRS2 register address 6h). There different transfer speeds selectable each transfer mode shown below.
During mode 2400 9600 19.2 kbps 38.4 kbps 57.6 kbps 115.2 kbps Reserved Reserved During mode 0.576 Mbps 1.152 Mbps Reserved Reserved Reserved Reserved Reserved Reserved During mode Reserved Mbps Reserved Reserved Reserved Reserved Reserved Reserved
Semiconductor
MSM9405
Setting Number BOFs (STAs) MSM9405 number BOFs (STAs), that indicate beginning frame during Ex-SIR mode mode, using (SBF3 MBF3 ICR2 register. number BOFs (STAs) SBF3 through SBF0 MBF3 MBF0) automatically appended front data written FIFO, then transmitted. These bits used modes. During mode, preambles chips chips automatically appended front data written FIFO. (See figure
ICR2 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 During Ex-SIR mode Reserved Reserved Reserved Reserved During mode Reserved Reserved Reserved Reserved Reserved Reserved Reserved
MSM9405
Semiconductor
Setting Interrupts
MSM9405 factors interrupts. (TXE_EV), (TXL_EV), (RXH/T_EV), (EOF_EV), (MLE_EV), (CE_EV), (OE_EV), (FE_EV) register (address 2h), (TOUT) register (address indicate interrupts, change when interrupt occurs. register (address enable disable each interrupt. bits correspond array interrupts indicated register. Enable necessary interrupts setting corresponding bits Setting disables corresponding interrupt. Even corresponding bits register (disabled) each register will still change when interrupt event occurs. TXE_EV, TXE_IE TXE_EV data written FIFO transmitted both FIFO (Transmitter Shift Register: APPENDIX-A "Block Diagram") become empty. register read, reset TXE_EV will FIFO become empty only middle frame, also after normal completion frame transfer. significance TXE_EV differs depending upon transfer mode generated timing. When mode, interrupt occurs before frame data been written FIFO, TXE_EV indicates that transmit data write complete, that data fragmented. this case, data written hereafter FIFO will transmitted. restart transmission, necessary first reset TX_EN then TX_EN modes (SIR, Ex-SIR, FIR), interrupt occurs after frame data been written FIFO, TXE_EV indicates that transmission that frame complete. TXE_IE enables disables interrupt asserted TXE_EV. TXE_IE TXE_EV valid modes (SIR, Ex-SIR, FIR). TXL_EV, TXL_IE During transmit idle mode, number transmit data bytes FIFO less than transmit threshold level bits through (TXTH3 TXTH0) register (address 8h), then TXL_EV (See section 7.1, "Setting Transmit/Receive Threshold Levels"). Transmit data written FIFO number transmit data bytes FIFO equal greater than transmit threshold level, TXL_EV receive mode, TXL_IE always TXL_EV trigger write transmit data. TXL_IE enables disables interrupt asserted TXL_EV. TXL_IE TXL_EV valid modes (SIR, Ex-SIR, FIR).
Semiconductor RXH/T_EV, TOUT, RXH/T_IE
MSM9405
When receive mode, RXH/T_EV number receive data bytes FIFO equal greater than receive threshold level (See section 7.1, "Setting Transmit/Receive Threshold Levels) bits through (RXTH3 RXTH0) register (address timeout generated. When timeout generated, (TOUT) register (address also RXH/T_EV been because received number data bytes equal greater than receive threshold level, received data read. number received data bytes FIFO less than receive threshold level, RXH/T_EV RXH/T_EV been generation timeout, RXH/T_EV will reset when received data read. TOUT will also reset when received data read. transmit idle modes, RXH/T_EV always condition causing timeout Ex-SIR modes: least more bytes data FIFO time Tout elapsed since last data written from receiver shift register (RSR) FIFO. During this interval, FIFO data been read controller. Tout 1/baud rate baud rate: transfer speed (2.4 115.2 kbps) condition causing timeout modes: least more bytes data FIFO 69.5 elapsed since last data written from receiver shift register FIFO. During this interval, FIFO data been read controller. RXH/T_IE enables disables interrupt asserted RXH/T_EV. RXH/T_EV trigger read receive data. RXH/T_EV, RXH/T_IE, TOUT valid modes (SIR, Ex-SIR, FIR). EOF_EV, EOF_IE During receive mode, EOF_EV when last byte information section receive frame reaches bottom FIFO RDR). register read, EOF_EV EOF_EV indicates that next data read last data frame. EOF_IE enables disables interrupt asserted EOF_EV. EOF_IE EOF_EV valid Ex-SIR, modes. mode, EOF_IE EOF_EV.
MSM9405 Application Manual MLE_EV, MLE_IE
Semiconductor
During receive mode, MLE_EV when frame received whose length exceeds maximum receive data size MDS(L) MDS(H) registers (addresses Ch). register read, MLE_EV will reset MLE_IE enables disables interrupt asserted MLE_EV. valid Ex-SIR, modes. mode, MLE_IE MLE_EV. data size register does include FCS, EOF. mode, MLE_IE MLE_EV.) (Control Escape Byte) (Frame Check Sequence) Ex-SIR, MIR: CRC16 FIR:CRC32 CE_EV, CE_IE receive mode, check receive frame performed CE_EV when error occurs. register read, CE_EV will reset CE_EV indicates that there error received frame. enables disables interrupt asserted _EV. valid Ex-SIR, modes. mode, CE_IE CE_EV. OE_EV, OE_IE During receive mode, OE_EV when FIFO already full bytes receive data, next receive data completely received receiver shift register (RSR) (See Appendix-A, "Block Diagram"). register read, OE_EV will reset When OE_EV asserted, data written FIFO. Data receiving shift register will overwritten next receive data. indicates that received data could read portion received data lost. Even OE_EV asserted, CE_EV will asserted. enables disables interrupt asserted _EV. valid modes (SIR, Ex-SIR, modes). FE_EV, FE_IE receive mode, FE_EV there stop received data. register read, FE_EV will reset enables disables interrupt asserted _EV. valid Ex-SIR modes. modes, FE_IE FE_EV.
Semiconductor
MSM9405
FCS/EOF
(Frame Check Sequence) Ex-SIR, MIR: CRC16 S_EOT Disable setting (TCC_EN) ICR1 (address register value greater than number bytes (Note) frame transmitted register (addresses Ah). operating mode MSM9405 transmit setting ICR1 register's (RX_EN) (TX_EN) Write transmit data register. Just prior writing last data frame, write (S_EOF) ICR1 register. MSM9405 will recognize data written register last data that frame, (STO) then added frame transmitted. After transmitted, S_EOF automatically reset TFL/TCC Enable setting (TCC_EN) ICR1 register number bytes (Note) frame transmitted register. operating mode MSM9405 transmit mode setting ICR1 register's (RX_EN) (TX_EN) Write transmit data register. When written TX_EN, value previously frame length loaded into TCC. counter count down number transmit data bytes. value decremented each time when Byte transmitted. When value zero, MSM9405 recognizes that last data byte frame been transmitted automatically transmits together with When next frame transmitted, value loaded into again. CTEST (bit ICR2 register) access CTEST read TCC. signal used when writing data with controller that output. Disable setting (TCC_EN) ICR1 register value greater than number bytes (Note) frame transmitted register. operating mode MSM9405 transmit setting ICR1 register's (RX_EN) (TX_EN) Write transmit data register. When signal received from controller, data written that time will recognized frame, (STO) will added frame transmit. Note Number bytes frame does include FCS, (STA), (STO). FIR: CRC32
MSM9405
Semiconductor
FIFO
Setting Transmit/Receive Threshold Levels MSM9405 receive threshold level with bits (RXTH3 RXTH0) register (address transmit threshold level with bits (TXTH3 TXTH0) register. receive mode, number receive data bytes FIFO equal greater than receive threshold level register, interrupt generated RXH/T_EV register been enabled, DREQ signal will asserted.) this state, FIFO data read, number data bytes FIFO becomes less than receive threshold level, RXH/T_EV (The FIFO data read when number data bytes FIFO becomes same value DMATH (See section 3.3, "Setting DMAC Interface"), DREQ signal will deasserted.) transmit mode, number receive data bytes FIFO less than transmit threshold level register, interrupt generated TXL_EV register been enabled, DREQ signal will asserted.) this state, data written FIFO, number data bytes FIFO becomes equal greater than transmit threshold level, TXL_EV (Data written FIFO when number data bytes FIFO becomes same value DMATH, DREQ signal will deasserted.) When setting transmit receive threshold levels, value smaller than value DMATH should TXTH during transmission, value greater than value DMATH should RXTH during reception.
(bit reception) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Threshold Level Reserved Threshold Level Reserved
Semiconductor Number Data Bytes FIFO
MSM9405
When transmit mode, bits (FLV5 FLV0) register (address indicate number transmit data bytes currently FIFO. When receive mode, these bits indicate number receive data bytes currently FIFO. indicates MSB, indicates LSB. maximum 85ns original oscillation 48MHz) required from time when FIFO data accessed until value register changes. (When original oscillation 18.432MHz, maximum time 130ns.) Data FIFO (including RDR) FLV5 through FLV0 cleared writing (FCLR) ICR1 register (address 4h). After data cleared FIFO, FCLR automatically FCLR MSM9405 clear data FIFO using FCLR (bit ICR1). Setting FCLR clears FIFO (including RDR) sets "0". (Transmitter Shift Register Receive Shift Register: Appendix-A, "Block Diagram") cleared. FCLR automatically "0". transmit mode idle mode, case FCLR cleared FIFO when number data bytes more than transmit threshold level, TXL_EV event does occur INTR DREQ pins become active. When starting transmission after clearing FIFO, following operations should performed. idle mode. Write byte dummy data FIFO. Clear dummy data written FIFO using FCLR. Start transmission.
MSM9405
Semiconductor
Other Functions
IR_DET Infrared pulses detected monitoring (IR_DET) register (address 3h). Ex-SIR modes, 0.9s (minimum value pulse width during reception) longer pulse input IRIN-A pin, IR_DET will IR_DET read, reset IR_DET used modes. IR_DET cleared setting FCLR Send Serial Infrared Interaction Pulses Setting (IR_PLS) ICR1 register (address causes serial infrared interaction pulse output. After interaction pulse output, IR_PLS automatically After IR_PLS serial infrared interaction pulse output immediately after first that output. Serial infrared interaction pulses only output modes. Serial infrared interaction pulses output Ex-SIR modes. mode
Rate 1.74 1.75
Serial infrared interaction pulse (7E) 6.99
Figure Rate: 1/transfer speed Inverted modes, TXE_EV asserted during frame transfer, MSM9405 function transmit inverted (Note) EOF, terminate subsequent data transmission. This function enabled setting (CRC_INV) ICR1 register (address disabled setting that restart data transmission that been stopped assertion TXE_EV, necessary (TX_EN) ICR1 register then TX_EN again. This function invalid Ex-SIR modes. Note Inverted obtained calculating data transmitted before TXE_EV event accurs, then inverting calculated bits.
Semiconductor
MSM9405
register (address register that stacks receive frame lengths. When frame completely received EOF_EV (bit register (address become receive frame length counted internal counter pushed onto register. next frame completely received EOF_EV again register value will overwritten. data from more frames received together, read every 1-frame reception. Even transmission reception MSM9405 switched, value will maintained. read while (CTEST) ICR2 register (address possible write RST. While CTEST will read. valid Ex-SIR, modes. used mode.
MSM9405
Semiconductor
Appendix
Block Diagram
Semiconductor
Appendix Block Diagram
D0-7 A0-3
Control/Status Register
Control Circuit Flag Detection/ Removal Circuit TCC/RCC
Microcontroller
UART
HDLCDEC
Flag Detection/ Removal Circuit IrDA IRIN-A IRIN-B
Receiver Shift Register (RSR)
PPMDEC
Preamble/Flag Detection/ Removal Circuit
Demodulator
INTR RESET PWDN
Transmit-Receive FIFO bit)
Flag Insertion Circuit
UART
HDLCENC
MSM9405 Application Manual Appendix Block Diagram
Flag Insertion Circuit IrDA
DREQ DACK XOUT TEST
Transmitter Shift Register (TSR)
PPMENC
Preamble/Flag/ Insertion Circuit
Modulator
IROUT
Baud Rate Generator
MSM9405 Application Manual Appendix Block Diagram
Semiconductor
Appendix
Electrical Characteristics
Semiconductor
MSM9405 Application Manual Appendix Electrical Characteristics
Appendix Electrical Characteristics Absolute Maximum Ratings
Parameter Supply Voltage Input Voltage Output Current Power Dissipation Storage Temperature Symbol TSTG Condition Rating -0.5 +4.6 -0.5 +6.0 +150 Unit
Recommended Operating Conditions
Parameter Supply Voltage Operating Temperature Crystal Oscillation Frequency Symbol fOSC Condition Range 18.432 ±200 ±100 Unit
Characteristics
(VDD +70°C) Parameter Input Voltage Input Voltage Input Leakage Current Input Voltage Input Voltage Input Leakage Current Output Voltage Output Voltage Output Voltage Output Voltage Supply Current Symbol VIH1 VIL1 ILI1 VIH2 VIL2 ILI2 VOH1 VOL1 VOH2 VOL2 Condition VDD/0 VDD/0 Min. Typ. Max. Unit 2.2*1 2.2*1 IROUT, INTR, DREQ, Applicable IRIN-A, IRIN-B, PWDN RESET, DACK
when
MSM9405 Application Manual Appendix Electrical Characteristics Characteristics
Semiconductor
(VDD +70°C) Parameter Read Pulse Width Read Data Delay Time Read Data Hold Time Data Open Time Read/Write Recovery Time Setup Time Hold Time Write Address Hold Time Write Pulse Width Write Data Setup Time Write Data Hold Time Write Address Setup Time Interrupt Clear Time DACK Setup Time DREQ Clear Time DACK Hold Time (during Read) DACK Hold Time (during Write) Pulse Width Setup Time Hold Time Pulse Width Data Rate Tolerance Pulse width Data Rate Tolerance Single Pulse Width Data Rate Tolerance Double Pulse Width Reset Pulse Width Symbol trpw trdd trdh trcv tcss tcsh twah twpw twds twdh twas tintr tacs tdrqr tachr tachw ttcw ttcs ttch tspw SDRT tmpw MDRT tfpw FDRT tfdpw trstw Condition Transmitter Receiver Transmitter Receiver Transmitter Receiver Transmitter Receiver Transmitter Receiver Transmitter Receiver Transmitter Receiver Min. 120/70 120/70 Typ. 1.63 Max. 135/95 ±0.87 ±1.0 ±0.1 ±0.2 ±0.01 ±0.1 Unit Note
when master oscillation frequency 18.432 MHz, when MHz. when master oscillation frequency 18.432 MHz, when MHz. That which occurs latest following used data delay time (trdd): change from A0-A3 invalid valid, change from high low, change from high mode).
Semiconductor
MSM9405 Application Manual Appendix Electrical Characteristics
That which occurs first following used read data hold time (trdh): change from A0-A3 valid invalid, change from high, change from high. That which occurs latest following used data delay time (trdd): change from DACK inactive active change from high mode). That which occurs first following used read data hold time (trdd): change from DACK active inactive change from high mode). That which occurs first following used write data setup time write data hold time (twds twdh): change from DACK active inactive change from high. That which occurs latest following used DREQ clear time (tdrqr): change from DACK high change from high low.
MSM9405 Application Manual Appendix Electrical Characteristics
Semiconductor
Appendix
Timing Diagram
Semiconductor Appendix Timing Diagram Read Timing
MSM9405 Application Manual Appendix Timing Diagram
trdd trpw trdd trpw trpw trdd trdh trcv trdh trdh
tintr INTR*
When INTR active low.
MSM9405 Application Manual Appendix Timing Diagram Write Timing
Semiconductor
tcss
tcsh
twas twpw
twah
trcv
twds
twdh
tintr INTR*
When INTR active low.
Semiconductor DMAC Access Timing
MSM9405 Application Manual Appendix Timing Diagram
DMA_EN "1", DMA_SL1 "0", DMA_SL0 "0", DREQ: active low, DACK: active high
tdrqr
DREQ tachr trcv
DACK
tacs trpw trcv
twds twdh
tdrqr DREQ trcv tachw trdh
DACK
tacs twpw
trcv
trdd trdh
MSM9405 Application Manual Appendix Timing Diagram DMAC Access Timing
DMA_EN "1", DMA_SL1 "0", DMA_SL0 "1", DREQ: active low, DACK: active high
Semiconductor
DREQ
tdrqr tacs
DACK tachr trpw trcv trdd trdh
DREQ
tdrqr tacs
DACK tachw twpw trcv twds twdh
ttcw ttcs ttch
When active low.
Semiconductor DMAC Access Timing
DMA_EN "1", DMA_SL1 "1", DMA_SL0 "0", DREQ: active high tdrqr DREQ trdd trpw trdd trpw trpw
MSM9405 Application Manual Appendix Timing Diagram
trdh
trdh
trdd trdh
tdrqr DREQ tcss twas twpw twds twdh twah tcsh
MSM9405 Application Manual Appendix Timing Diagram
Semiconductor
Infrared Interface Timing
tspw
tmpw
tfpw
tfdpw
Reset Timing
trstw RESET
Appendix
Register Table
Semiconductor
MSM9405 Application Manual Appendix Register Table
Appendix Register Table Register Table
Register name TDR/RDR Mode Ex-SIR Ex-SIR TXE_EV TXL_EV RXH/T EOF_EV MLE_EV CE_EV OE_EV TXE_IE TXL_IE RXH/T EOF_IE Function each Bit7 TDR7 /RDR7 Bit6 TDR6 /RDR6 Bit5 TDR5 /RDR5 Bit4 TDR4 /RDR4 MLE_IE Bit3 TDR3 /RDR3 Bit2 TDR2 /RDR2 CE_IE OE_IE Bit1 TDR1 /RDR1 Bit0 TDR0 /RDR0 FE_IE FE_EV
FLV5
FLV4
FLV3
FLV2
FLV1
FLV0
IR_DET
TOUT
ICR1 Ex-SIR ICR2 Ex-SIR TEST DRS2 RXTH3 TFL7 TCC7 MDS7 RST7 TEST7 DRS1 RXTH2 TFL6 TCC6 MDS6 RST6 TEST6 CTEST SD_INV MS_EN TCC_EN
CRC_ FCLR
IR_PLS
S_EOT SBF2 MBF2 DMA_ TXTH2 TFL2 TCC2 TFL10 TCC10 MDS2 RST2 MDS10 RST10 TEST2 RX_EN TX_EN
SBF1 MBF1 IRSL1 DMA_ TXTH1 TFL1 TCC1 TFL9 TCC9 MDS1 RST1 MDS9 RST9 TEST1
SBF0 MBF0 IRSL0 DMA_ TXTH0 TFL0 TCC0 TFL8 TCC8 MDS0 RST0 MDS8 RST8 INTR_ TEST0
IRIN DRS0 RXTH1 TFL5 TCC5 MDS5 RST5 TEST5
RXINV
SBF3 MBF3
XT_SL
DREQ_ DACK_
DMATH1 DMATH0 RXTH0 TFL4 TCC4 MDS4 RST4 TEST4 TXTH3 TFL3 TCC3 TFL11 TCC11 MDS3 RST3 MDS11 RST11 TEST3
Reserved
MSM9405 Application Manual Appendix Register Table Registers TDR: Transmitter Data Register (Write Only) RDR: Receiver Data Register (Read Only) (Address
Semiconductor
(Transmitter Data Register) (Receiver Data Register) used read/write data directly upon receiving/transmitting data. share same address. When data written transmit mode during idle mode, works FIFO 1-byte data written FIFO. When data read receive mode, works bottom FIFO 1-byte data FIFO read. Serial-toparallel conversion performed RSR. Parallel-to-serial conversion performed TSR. Reading from writing invalid. contents FIFO TDR/ cleard writing FCLR ICR1 register. cannot cleared. ENR: Enable Register (Address (Enable Register) used control enabling/disabling various interrupts MSM9405. Each eight bits corresponds each eight interrupts provided MSM9405. Each eight interrupts independently controlled each bit. When system reset, bits reset "0". writing corresponding desired interrupt, specified interrupt enabled.
Initial value after reset
FE_IE (Enable "1") OE_IE (Enable "1") CE_IE (Enable "1") MLE_IE (Enable "1") EOF_IE (Enable "1") RXH/T_IE (Enable "1") TXL_IE (Enable "1") TXE_IE (Enable "1")
Semiconductor
MSM9405 Application Manual Appendix Register Table
ENR[0]
Table FE_IE (Framing Error Interrupt Enable): This enables disables interrupt when (Framing Error: Stop detected) occurred. This valid mode Ex-SIR mode. mode mode, this must (disable). OE_IE (Overrun Error Interrupt Enable) This enables disables interrupt when (Overrun
ENR[1]
error Error that occurs when FIFO full upon receiving next character completely received RSR) occurred. CE_IE (CRC Error Interrupt Enable) This enables disables interrupt when (CRC Error)
ENR[2]
occurred. This valid Extended-SIR mode, mode, mode. mode, this must (disable). MLE_IE (Maximum Length Error Interrupt Enable) This enables disables interrupt when (Maximum Length Error: Error that occurs when frame exceeding maximum data size received) occurred. Extended-SIR mode, mode mode, this valid. mode, this must (disable). EOF_IE (End Frame Interrupt Enable) This enables disables interrupt when last byte frame's data field been detected Extended-SIR mode, mode, mode. Extended-SIR mode, mode mode, this valid. mode, this must (disable). RXH/T_IE (Receiver High-Data-Level/Timeout Interrupt Enable) This enables disables
ENR[3]
ENR[4]
ENR[5]
interrupt when received data above receiving threshold level time-out occurred. TXL_IE (Transmitter Low-Data-Level Interrupt Enable) This enables disables interrupt when sent data below sending threshold level. TXE_IE (Transmitter Empty Interrupt Enable) This enables disables interrupt when data written FIFO been transmitted both FIFO have become empty.
ENR[6] ENR[7]
MSM9405 Application Manual Appendix Register Table EIR: Event Identification Register (Read Only) (Address
Semiconductor
(Event Identification Register) indicates factors various interrupts MSM9405. Each eight bits corresponds each interrupt assignment ENR. works status register even interrupt disabled. When event occurs, each corresponding "1". When system reset, each initial value.
Initial value after reset
FE_EV (Framing Error "1") OE_EV (Overrun Error "1") CE_EV (CRC Error "1") MLE_EV (Maximum Length "1") EOF_EV (EOF "1") RXH/T_EV High-Data-Level/Timeout "1") TXL_EV Low-Data-Level "1") TXE_EV Empty "1")
Semiconductor
MSM9405 Application Manual Appendix Register Table
EIR[0]
Description FE_EV (Framing Error Event): This when occurs. When reads EIR, this "0". mode Ex-SIR mode, this valid. This used mode mode. OE_EV (Overrun Error Event): When occurs, this "1". When reads
EIR[1]
contents, OE_EV "0". Data transfered FIFO when OE_EV occurs overwritten next receive data. CE_EV (CRC Error Event): When error occurs, this "1". When reads
EIR[2]
EIR, this "0". Extended-SIR mode, mode mode, this valid. This used mode. MLE_EV (Maximum Length Error Event): When occurs, this "1". When
EIR[3]
reads EIR, this "0". Extended-SIR mode, mode mode, this valid. This used mode. EOF_EV (End Frame Event): This valid either Extended-SIR, MIR, mode. When last byte frame's data field reaches bottom FIFO receiving mode, EOF_EV "1". When reads EIR, this "0". Extended-SIR mode, mode mode, this valid. mode, this used. RXH/T_EV (Receiver High-Data-Level/Timeout Event): When received data FIFO above receiving threshold level time-out occurs, RXH/T_EV "1". condition setting RXH/T_EV depends following cases
EIR[4]
EIR[5]
received data FIFO above receiving threshold level Received data read. When received data FIFO below threshold level, this "0". time-out occurs After received data FIFO read, this "0". TXL_EV (Transmitter Low-Data-Level Event): When sent data FIFO below sending
EIR[6]
threshold level, this "1". When sent data written sent data FIFO above threshold level, this "0". TXE_EV (Transmitter Empty Event): When data written FIFO been transmit
EIR[7]
both FIFO empty, this "1". When reads EIR, this "0".
MSM9405 Application Manual Appendix Register Table LSR: Line Status Register (Read Only) (Address
Semiconductor
(Line Status Register) indicates various statuses MSM9405 that running. When system reset, bits "0". This register read only cannot written.
Initial value after reset
TOUT (Timeout "1") IR_DET (SIR Pulse detect "1") (Byte number FIFO)
LSR[0]
Description TOUT (FIFO Timeout): When time-out occurs, this "1". When received data read from FIFO, TOUT "0". IR_DET (SIR Pulse detect) This when pulse having width tspw (SIR pulse width upon receiving) detected. when reads LSR. This valid mode Ex-SIR mode, used mode mode. (FIFO Level): These bits indicate number data items FIFO with value indicates indicates LSB.
LSR[1]
LSR[2-7]
Semiconductor ICR1: Infrared Control Register (Address
MSM9405 Application Manual Appendix Register Table
ICR1 (Infrared Control Register used various environments that MSM9405 perform IrDA communication under proper conditions. When system reset, bits ICR1 "0".
ICR1 Initial value after reset
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
ICR1
TX_EN ("1": Transmit Enable) RX_EN ("1": Receive Enable) S_EOT ("1": Transmission) IR_PLS ("1": Send Interaction Pulse) FCLR ("1": FIFO Clear) CRC_INV ("1": Send Inverted Enable) TCC_EN ("0": off, "1": MS_EN ("1": Automatic mode Select)
MSM9405 Application Manual Appendix Register Table
Semiconductor
ICR1 ICR1[0] ICR1[1]
Description TX_EN (Transmit Enable): When written this bit, device starts sending data that FIFO. When written this bit, sending terminates. RX_EN (Receive Enable): When written this bit, device starts receiving data. When written this bit, device enters receive mode. S_EOT (Set Transmission): When written this bit, data written FIFO next time recognized frame, immediately after data added with sent frame. After frame sent, this automatically "0". S_EOT, must maximum value must unused with TCC_EN "0". This used mode. Extended-SIR mode, mode mode, this valid. This used mode. IR_PLS (Send Interaction Pulse): When written this bit, approximately 2-ms serial infrared interaction pulse sent. interaction pulse sent immediately after first sent after IR_PLS "1". After frame sent, this automatically "0". mode mode, this valid. This used mode Extended-SIR mode. FCLR (FIFO Clear): When written this bit, FIFO (including RDR) made
ICR1[2]
ICR1[3]
ICR1[4]
empty. FIFO threshold level does change. cleared. When FIFO made empty, this automatically "0". CRC_INV (Invert Transmitter CRC): When written this bit, transmission interrupted (Transmitter Empty) occurs during frame transmit. inverted
ICR1[5]
automatically added frame that caused TXE, then frame sent. Writing this disables this function. mode mode, this valid. This used mode Extended mode. TCC_EN (TCC Enable): When this "1", enabled. When TCC_EN "0", disabled. S_EOT, must maximum value must disabled with TCC_EN "0". Extended-SIR mode, mode mode, this valid. This used mode. MS_EN (Mode Select Enable): When written this bit, MSM9405 performs following operation depending mode. After operation completed, this automatically "0". MSM9405 mode: "H"*, IROUT "H". Approximately later, "L"*. Approximately later, IROUT "L". MSM9405 SIR, Extended-SIR, mode: "H"*, IROUT "L". Approximately later, "L"*. IROUT held level approximately This valid only when crystal used. this when 18.432 crystal used. When active high. level reversed when active low.
ICR1[6]
ICR1[7]
Semiconductor ICR2: Infrared Control Register (Address
MSM9405 Application Manual Appendix Register Table
ICR2 (Infrared Control Register used various environment that MSM9405 perform IrDA communication under proper conditions. When system reset, bits ICR2 "0".
ICR2 Initial value after reset
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
ICR2
(SIR Beginning Flags) (MIR Beginning Flags) RXINV ("1": Signal Invert) IRIN_SL ("0": Single Input "1": Double Input) SD_INV ("0": Active High "1": Active Low) CTEST ("0": TCC/RST "1": TFL/MDS)
MSM9405 Application Manual Appendix Register Table
Semiconductor
ICR2
Description These bits work when Extended-SIR mode selected, when mode selected. This function disabled mode mode. (SIR beginning Flags): These bits determine number BOFs added during sending Extended-SIR mode shown below. (MIR Beginning Flags): These bits determine number BOFs added during sending mode shown below. Encoding 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 BOFs Reserved Reserved Reserved Reserved Reserved BOFs Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
ICR2[0-3]
RXINV (IRIN Signal Invert): This used select active active high receive signal. ICR2[4] RXINV "0": Active RXINV "1": Active high IRIN_SL (IRIN Select): This determines receive signal input used. ICR2[5] IRIN_SL "0": Only input from IRIN-A (2.4 kbps Mbps) accepted. IRIN_SL "1": input from IRIN-A IRIN-B automatically selected depending transfer rate. 115.2 kbps, 0.576 Mbps) SD_INV Signal Invert): This changes polarity (active high/low) output ICR2[6] MSM9405. SD_INV "0": Active high SD_INV "1": Active CTEST (Counter Test): Normally this "0". When TFL/TCC MDS/RST read after ICR2[7] written this bit, values obtained. values obtained reading TFL/TCC MDS/RST when CTEST "0".
D-10
Semiconductor MSR: Mode Select Register (Address
MSM9405 Application Manual Appendix Register Table
used select various modes MSM9405. When system reset, each initial value.
Initial value after reset
IRSL0 (IrDA mode Select IRSL1 (IrDA mode Select Used XT_SL ("0": "1": 18.432 MHz) (Data Rate Select)
IRSL1 MSR[0-1] MSR[2-3] MSR[4] These bits used. IRSL0
Description IRSL (Infrared Mode Select): These bits used select transfer mode shown below. mode Extended-SIR
XT_SL (Crystal Select): This determines crystal used. XT_SL "0": crystal used XT_SL "1": 18.432 crystal used (Data Rate Select): These bits determine transfer rate shown below. Encoding MSR[5-7] Data Rate 2400 9600 19.2 kbps 38.4 kbps 57.6 kbps 115.2 kbps Reserved Reserved Data Rate 0.576 Mbps 1.152 Mbps Reserved Reserved Reserved Reserved Reserved Reserved Data Rate Reserved Mbps Reserved Reserved Reserved Reserved Reserved Reserved
D-11
MSM9405 Application Manual Appendix Register Table DSR: Mode Select Register (Address
Semiconductor
(DMA Mode Select Register) used select mode MSM9405. When system reset, bits "0".
Initial value after reset
DMA_EN ("1": mode) DMA_SL (DMA Select) DMATH (DMA Threshold Select) TC_INV ("0": Active "1": Active High) DACK_INV ("0": Active High "1": Active Low) DREQ_INV ("0": Active "1": Active High)
D-12
Semiconductor
MSM9405 Application Manual Appendix Register Table
Description DMA_EN (DMA Mode Enable): This determines whether used. When written this bit, DSR[1-2] (DMA_SL0, DMA_SL1) setting enabled
DSR[0]
MSM9405 enters transfer standby mode. DMA_EN "0", DSR[1-2] (DMA_SL0, DMA_SL1) setting disabled transfer performed. DMA_SL (DMA Select): These bits used select method interfacing with DMAC. DMA_SL1 DMA_SL0 Function Supports transfer Single Address mode. When signal becomes active while DACK active, read cycle selected. When signal becomes active while DACK active, write cycle selected. While DACK being asserted, address (TDR/RDR) accessed regardless status Supports transfer Single Address mode. When signal becomes active while DACK active, read cycle selected. When signal becomes active while DACK active, write cycle selected. While DACK being asserted, address (TDR/RDR) accessed regardless status Supports transfer Dual Address mode. Access TDR/RDR Reserved
DSR[1-2]
DMATH (DMA Threshold Select): These bits determine threshold level release DREQ. DREQ signal deasserted when number data bytes reaches following values. DMATH1 DSR[3-4] DMATH0 During transmission During reception
TC_INV Signal Invert): This selects polarity signal. DSR[5] TC_INV "0": Active TC_INV "1": Active high DACK_INV (DACK Signal Invert): This selects polarity DACK signal. DSR[6] DACK_INV "0": Active high DACK_INV "1": Active DREQ_INV (DREQ Signal Invert): This selects polarity DREQ signal. DSR[7] DREQ_INV "0": Active DREQ_INV "1": Active high
D-13
MSM9405 Application Manual Appendix Register Table FCR: FIFO Control Register (Address
Semiconductor
(FIFO Control Register) used threshold level FIFO used MSM9405 upon sending/receiving. setting applied both interrupt DMA. When system reset, each
Initial value after reset
TXTH Threshold Select) RXTH Threshold Select)
D-14
Semiconductor
MSM9405 Application Manual Appendix Register Table
(0-3) 0000 0001 0010 0011 0100 0101 FCR[0-3] 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Description TXTH (Transmit Threshold Select): These four bits following sending threshold levels. Threshold Level (Byte) Reserved
RXTH (Receive Threshold Select): These four bits following receiving threshold levels. (4-7) 0000 0001 0010 0011 0100 0101 0110 FCR[4-7] 0111 1000 1001 1010 1011 1100 1101 1110 1111 Threshold Level (Byte) Reserved
D-15
MSM9405 Application Manual Appendix Register Table TFL: Transmitter Frame Length Register TCC: Transmitter Current-Count Register (Address
Semiconductor
(Transmitter Frame Length Register) (Transmitter Current-Count Register) used specify length frame transferred transmitting. shares same address. Bits address bits address (totally bits) used. address LSB. When TFL/TCC value read, CTEST setting reflected. CTEST "0", contents read. CTEST "1", contents read. When TFL/TCC written, value rewritten. cannot written. TFL/TCC, write TCC_EN, frame length TFL. frame length does include FCS, BOF, EOF. When written TX_EN, value that been frame length loaded TCC. When sending started, value decremented each time byte sent. When value becomes "0", frame assumed frame automatically added with sent. After frame sent, value loaded again into when second frame sent. TFL/TCC initial value 800h. MDS: Maximum Data Size Register RST: Receiver Frame Length Stack Register (Address (Maximum Data Size Register) used maximum data size. (Receiver Frame Length Stack Register) used stack received frame length. share same address. Bits address bits address (totally bits) used. address LSB. When MDS/RST value read, CTEST setting reflected. CTEST "0", contents read. CTEST "1", contents read. When MDS/RST written, value rewritten. cannot written. MDS, maximum data size advance. frame length does include FCS, BOF, EOF. When receiving started, (Receiver Current-Counter) value incremented each time byte received. value exceeds value during receiving, occurs. initial value 800h. When frame fully received EOF_EV "1", received frame length counted internal counter stacked RST. This value stored until next frame fully received. value stacked maintained even MSM9405 transmitting/receiving switched. initial value
D-16
Semiconductor
MSM9405 Application Manual Appendix Register Table
ISR: Interrupt Signal Control Register (Address (Interrupt Signal Control Register) used determine polarity INTR signal. When system reset, each
Initial value after reset
INTR_INV ("0": Active "1": Active High) Used
ISR[0] ISR[1-7] INTR_INV "0": Active INTR_INV "1": Active High These bits used.
Description INTR_INV (DMA mode Enable): This selects polarity INTR signal.
TEST: Test Register (Address This register used only testing.
D-17
MSM9405 Application Manual Appendix Register Table
Semiconductor
D-18
Appendix
Package Outline Dimensions
Semiconductor
MSM9405 Application Manual Appendix Package Outline Dimensions
Appendix Package Outline Dimensions
(Unit
Mirror finish
30-Pin Plastic SSOP
MSM9405 Application Manual Appendix Package Outline Dimensions
Semiconductor
MSM9405
Application Manual First Edition: January 1999 Second Edition: July 2000
2000 Electric Industry Co., Ltd. FEAL9405-02
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