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MRF24J40 Data Sheet
IEEE 802.15.42.4 Transceiver
2010 Microchip Technology Inc.
DS39776C
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Trademarks Microchip name logo, Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC UNI/O registered trademarks Microchip Technology Incorporated U.S.A. other countries. FilterLab, Hampshire, HI-TECH Linear Active Thermistor, MXDEV, MXLAB, SEEVAL Embedded Control Solutions Company registered trademarks Microchip Technology Incorporated U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock ZENA trademarks Microchip Technology Incorporated U.S.A. other countries. SQTP service mark Microchip Technology Incorporated U.S.A. other trademarks mentioned herein property their respective companies. 2010, Microchip Technology Incorporated, Printed U.S.A., Rights Reserved. Printed recycled paper. ISBN: 978-1-60932-459-9
Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS39776C-page
2010 Microchip Technology Inc.
MRF24J40
IEEE 802.15.42.4 Transceiver
Features:
IEEE 802.15.4Standard Compliant Transceiver Supports ZigBee®, MiWiTM, MiWi Proprietary Wireless Networking Protocols Simple, 4-Wire Serial Peripheral Interface (SPI) Integrated 32.768 Crystal Oscillator Circuitry Low-Current Consumption: mode: (typical) mode: (typical) Sleep: (typical) Small, 40-Pin Leadless Package
RF/Analog Features:
Band 2.405-2.48 Operation Data Rate: kbps (IEEE 802.15.4); kbps (Turbo mode) Typical Sensitivity with Maximum Input Level Typical Output Power with Power Control Range Differential Input/Output with Integrated TX/RX Switch Integrated Phase Noise VCO, Frequency Synthesizer Loop Filter Digital Filter Calibration Integrated RSSI DACs Integrated High Receiver RSSI Dynamic Range
MAC/Baseband Features:
Hardware CSMA-CA Mechanism, Automatic Acknowledgement Response Check Independent Beacon, Transmit FIFO Supports modes RSSI/ED Automatic Packet Retransmit Capability Hardware Security Engine (AES-128) with CTR, CBC-MAC modes Supports Encryption Decryption Sublayer Upper Layer
Diagram:
LCAP OSC1 OSC2 GPIO0 GPIO1 GPIO5 GPIO4 LPOSC1 LPOSC2
40-Pin
MRF24J40
GPIO2 GPIO3 RESET WAKE
Note: Backside center GND.
2010 Microchip Technology Inc.
DS39776C-page
MRF24J40
Overview Hardware Description. Functional Description. Applications Electrical Characteristics Packaging Information. Appendix Revision History. Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System.
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Most Current Data Sheet
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Errata
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DS39776C-page
2010 Microchip Technology Inc.
MRF24J40
OVERVIEW
MRF24J40 IEEE 802.15.4Standard compliant transceiver. integrates functionality single chip solution. Figure shows simplified block diagram MRF24J40 wireless node. MRF24J40 creates low-cost, low-power, data rate (250 kbps) Wireless Personal Area Network (WPAN) device. MRF24J40 interfaces many popular Microchip PIC® microcontrollers 4-wire serial interface, interrupt, wake Reset pins. MRF24J40 provides hardware support for: Energy Detection Carrier Sense Three Modes CSMA-CA Algorithm Automatic Packet Retransmission Automatic Acknowledgment Independent Transmit, Beacon FIFO Buffers Security Engine supports Encryption Decryption Sublayer Upper Layer These features reduce processing load, allowing low-cost 8-bit microcontrollers. MRF24J40 compatible with Microchip's ZigBee®, MiWiand MiWi software stacks. Each software stack available free download, including source code, from Microchip site:
FIGURE 1-1:
Antenna
WIRELESS NODE BLOCK DIAGRAM
MRF24J40 Matching Circuitry Interface Power Management Memory WAKE RESET PIC® INTx
Crystal
2010 Microchip Technology Inc.
DS39776C-page
MRF24J40
IEEE 802.15.4-2003 Standard
MRF24J40 compliant with IEEE 802.15.4TM-2003 Standard. Standard specifies physical (PHY) Media Access Controller (MAC) functions that form basis wireless network device. Figure shows structure packet frame. highly recommended that design engineer familiar with IEEE 802.15.4-2003 Standard order best understand configuration operation MRF24J40. Standard downloaded from IEEE site: http://www.ieee.org.
FIGURE 1-2:
IEEE 802.15.4PHY PACKET FRAME STRUCTURE
Sequence Number
octets
Sublayer
Acknowledgment Frame
Frame Control
Sublayer Data Frame Frame Control
Sequence Number
Adressing Fields
Data Payload MSDU
Beacon Payload
octets
Sublayer Command Frame Frame Control
Sequence Number
Adressing Fields
Command Type
octets
Command Payload MSDU
Sublayer Beacon Frame Frame Control
Sequence Number
Adressing Fields
Superframe Specification
Fields
Pending Address Fields
octets
Layer
Preamble
MSDU PSDU Payload
Frame Length
octets
packet
PPDU
DS39776C-page
2010 Microchip Technology Inc.
MRF24J40
HARDWARE DESCRIPTION
Overview
General Purpose Input/Output (GPIO) pins configured control monitoring purposes. They also configured control external PA/LNA switches. power management circuitry consists integrated Dropout (LDO) voltage regulator. MRF24J40 placed into very low-current typical) Sleep mode. internal oscillator external crystal oscillator used Sleep mode timing. Media Access Controller (MAC) circuitry verifies reception formats transmission IEEE 802.15.4 Standard compliant packets. Data buffered Transmit Receive FIFOs. Carrier Sense Multiple Access-Collision Avoidance (CSMA-CA), superframe constructor, receive frame filter security engine functionality implemented hardware. security engine provides hardware circuitry AES-128 with CTR, CBC-MAC modes. Control transceiver 4-wire SPI, interrupt, wake Reset pins.
MRF24J40 IEEE 802.15.4 Standard compliant transceiver. integrates functionality single chip solution. Figure block diagram MRF24J40 circuitry. frequency synthesizer clocked external crystal generates frequency. receiver low-IF architecture consisting Noise Amplifier (LNA), down conversion mixers, polyphase channel filters baseband limiting amplifiers with Receiver Signal Strength Indicator (RSSI). transmitter direct conversion architecture with maximum output (typical) power control range. internal Transmit/Receive (TR) switch combines transmitter receiver circuits into differential pins. These pins connected impedance matching circuitry (balun) antenna. external Power Amplifier (PA) and/or controlled GPIO pins.
2010 Microchip Technology Inc.
DS39776C-page
FIGURE 2-1:
DS39776C-page
MRF24J40
Block Diagram
Filter Interrupts MEMORY Frequency Synthesizer RXFIFO TXMAC TXNFIFO Baseband Generator Packet Retriever Superframe State Machine CSMA-CA TXBFIFO TXG1FIFO TXG2FIFO Security FIFO Control Registers RSSI Baseband Checker Frame Checker
RXMAC
Interface WAKE RESET GPIO
MRF24J40 ARCHITECTURE BLOCK DIAGRAM
SLEEP CLOCK Crystal Oscillator Power Management Internal Oscillator Security Engine
20MHz Crystal Oscillator
2010 Microchip Technology Inc.
MRF24J40
Descriptions
MRF24J40 DESCRIPTIONS
Type Power Power Power Ground Ground Power Ground Ground Ground Power Power Power Ground Power Power Differential input/output (+). Differential input/output (-). power supply. Bypass with capacitor close possible. Guard ring power supply. Bypass with capacitor close possible. Guard ring ground. General purpose digital I/O, also used external enable. General purpose digital I/O, also used external TX/RX switch control. General purpose digital I/O. General purpose digital I/O. General purpose digital I/O, also used external TX/RX switch control. General purpose digital I/O. Global hardware Reset active-low. Ground digital circuit. External wake-up trigger (must enabled software). Interrupt microcontroller. Serial interface data output from MRF24J40. Serial interface data input MRF24J40. Serial interface clock. Serial interface enable. Digital circuit power supply. Bypass with capacitor close possible. Ground digital circuit. Connection. Ground digital circuit. Ground digital circuit. Connection. (Allow float; connect signal.) crystal input. crystal input. Connection. (Allow float; connect signal.) Connection. (Allow float; connect signal.) Power supply band reference circuit. Bypass with capacitor close possible. Power supply analog circuit. Bypass with capacitor close possible. crystal input. crystal input. power supply. Bypass with capacitor close possible. Ground PLL. Charge pump power supply. Bypass with capacitor close possible. Connection. supply. Bypass with capacitor close possible. loop filter external capacitor. Connected external capacitor. Description power supply. Bypass with capacitor close possible.
TABLE 2-1:
Symbol
GPIO0 GPIO1 GPIO5 GPIO4 GPIO2 GPIO3 RESET WAKE LPOSC2 LPOSC1 OSC2 OSC1 LCAP
Legend: Analog, Digital, Input, Output
2010 Microchip Technology Inc.
DS39776C-page
MRF24J40
Power Ground Pins
FIGURE 2-2:
Recommended bypass capacitors listed Table 2-2. pins require bypass capacitors ensure sufficient bypass decoupling. Minimize trace length from bypass capacitors make them short possible.
MAIN OSCILLATOR CRYSTAL CIRCUIT
OSC2
TABLE 2-2:
RECOMMENDED BYPASS CAPACITOR VALUES
Bypass Capacitor 0.01 0.01 0.01 0.01
Main Oscillator
OSC1
Phase-Locked Loop
Phase-Locked Loop (PLL) circuitry requires external capacitor connected (LCAP). recommended value layout around capacitor should designed carefully such minimize interference PLL.
Main Oscillator
External Crystal Oscillator
main oscillator provides main frequency (MAINCLK) signal internal baseband circuitry. external quartz crystal connected OSC1 OSC2 pins shown Figure 2-2. crystal parameters listed Table 2-3.
external crystal oscillator provides Sleep clock (SLPCLK) frequencies Sleep mode counters. Sleep mode counters time Beacon Interval (BI) inactive period beacon-enabled device Sleep interval nonbeacon-enabled device. Refer Section 3.15 "Sleep" more information. SLPCLK frequency selectable between external crystal oscillator internal oscillator. external crystal oscillator provides better frequency accuracy stability than internal oscillator. external tuning fork crystal connected LPOSC1 LPOSC2 pins, shown Figure 2-3. crystal parameters listed Table 2-4.
TABLE 2-3:
CRYSTAL PARAMETERS(1)
Parameter Value ppm(2) ppm(2) Fundamental 10-15 max.
Frequency Frequency Tolerance 25°C Frequency Stability over Operating Temperature Range Mode Load Capacitance Note
TABLE 2-4:
CRYSTAL PARAMETERS(1)
Value 32.768 12.5 max.
Parameter Frequency Frequency Tolerance Load Capacitance Note
These values design guidance only. IEEE 802.15.4Standard specifies transmitted center frequency tolerance shall maximum.
These values design guidance only.
DS39776C-page
2010 Microchip Technology Inc.
MRF24J40
FIGURE 2-3: EXTERNAL OSCILLATOR CRYSTAL CIRCUIT
LPOSC2
Note:
will remain high low, depending INTEDGE polarity setting, until INSTAT register read.
CL22
2.11
Wake (WAKE)
External Crystal Oscillator
CL11
LPOSC1
Wake (WAKE) provides external wake-up signal MRF24J40 from host microcontroller. used conjunction with Sleep modes MRF24J40. WAKE disabled default. Refer Section 3.15.2 "Immediate Sleep Wake-up Mode" functional description Immediate Sleep Wake-up modes.
Internal Oscillator
2.12
internal oscillator requires external components provides Sleep clock (SLPCLK) frequencies Sleep mode counters. Sleep mode counters time Beacon Interval (BI) inactive period beacon-enabled device Sleep interval nonbeacon-enabled device. Refer Section 3.15 "Sleep" more information. SLPCLK frequency selectable between external crystal oscillator internal oscillator. external crystal oscillator provides better frequency accuracy stability than internal oscillator. recommended that internal oscillator calibrated before use. calibration procedure given Section 3.15.1.2 "Sleep Clock Calibration".
General Purpose Input/Output (GPIO) Pins
GPIO pins configured individually control monitoring purposes. Input output selection configured TRISGPIO (0x34) register. GPIO data read/written GPIO (0x33) register. GPIO pins have limited output drive capability. Table lists individual GPIO source current limits.
TABLE 2-5:
GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5
GPIO SOURCE CURRENT LIMITS
Maximum Current Sourced
Reset (RESET)
external hardware Reset performed asserting RESET low. MRF24J40 will released from Reset approximately after RESET released. RESET internal weak pull-up resistor.
2.10
Interrupt (INT)
Interrupt (INT) provides interrupt signal host microcontroller from MRF24J40. polarity configured INTEDGE SLPCON0 (0x211<1>) register. Interrupts have enabled unmasked before active. Refer Section "Interrupts" functional description interrupts. Note: INTEDGE polarity defaults Falling Edge. Ensure that interrupt polarity matches interrupt polarity host microcontroller.
GPIO0, GPIO1 GPIO2 configured control external switches internal state machine. This allows external controlled MRF24J40 without host microcontroller intervention. Refer Section "External PA/LNA Control" control register configuration, timing diagrams application information.
2010 Microchip Technology Inc.
DS39776C-page
MRF24J40
2.13 Serial Peripheral Interface (SPI) Port Pins
Note: defaults state when high (the MRF24J40 selected). MRF24J40 share bus, tri-state buffer should placed signal provide high-impedance signal bus. Section "MRF24J40 Schematic Bill Materials" example application circuit.
MRF24J40 communicates with host microcontroller 4-wire port slave device. MRF24J40 supports (mode 0,0) which requires that idles state. must held while communicating with MRF24J40. Figure shows timing write operation. Data received MRF24J40 clocked rising edge SCK. Figure shows timing read operation. Data sent MRF24J40 clocked falling edge SCK.
FIGURE 2-4:
PORT WRITE (INPUT) TIMING
FIGURE 2-5:
PORT READ (OUTPUT) TIMING
DS39776C-page
2010 Microchip Technology Inc.
MRF24J40
2.14 Memory Organization
Memory MRF24J40 implemented static accessible port. Memory functionally divided into control registers data buffers (FIFOs), shown Figure 2-6. Control registers provide control, status device addressing MRF24J40 operations. FIFOs serve temporary buffers data transmission, reception security keys. Memory accessed addressing methods: Short Long.
FIGURE 2-6:
MEMORY MRF24J40
Short Address Memory Space
0x00 0x3F Control Registers bytes 0x000
Long Address Memory Space
Normal FIFO 0x07F 0x080 Beacon FIFO 0x0FF 0x100 GTS1 FIFO 0x17F 0x180 GTS2 FIFO 0x1FF 0x200 Control Registers 0x27F 0x280 Security FIFO 0x2BF 0x2C0 Reserved 0x2FF 0x300 FIFO 0x38F bytes bytes bytes bytes bytes bytes
bytes
2010 Microchip Technology Inc.
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MRF24J40
2.14.1 SHORT ADDRESS REGISTER INTERFACE
short address memory space contains control registers with 6-bit address range 0x00 0x3F. Figure shows short address read Figure shows short address write. 8-bit transfer begins with indicate short address transaction. followed 6-bit register address, Most Significant (MSb) first. indicates read (`0') write (`1') transaction.
FIGURE 2-7:
SHORT ADDRESS READ
FIGURE 2-8:
SHORT ADDRESS WRITE
DS39776C-page
2010 Microchip Technology Inc.
MRF24J40
2.14.2 LONG ADDRESS REGISTER INTERFACE
long address memory space contains control registers FIFOs with 10-bit address range 0x000 0x38F. Figure shows long address read Figure 2-10 shows long address write. 12-bit transfer begins with indicate long address transaction. followed 10-bit register address, Most Significant (MSb) first. 12th indicates read (`0') write (`1') transaction.
FIGURE 2-9:
LONG ADDRESS READ
FIGURE 2-10:
LONG ADDRESS WRITE
2010 Microchip Technology Inc.
DS39776C-page
MRF24J40
2.15 Control Register Description
Control registers provide control, status device addressing MRF24J40 operations. following figures, tables register definitions describe control register operation.
2.15.1
CONTROL REGISTER SHORT ADDRESS CONTROL REGISTER MRF24J40
RXMCR PANIDL PANIDH SADRL SADRH EADR0 EADR1 EADR2 EADR3 EADR4 EADR5 EADR6 EADR7 RXFLUSH Reserved Reserved 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F ORDER TXMCR ACKTMOUT ESLOTG1 SYMTICKL SYMTICKH PACON0 PACON1 PACON2 Reserved TXBCON0 TXNCON TXG1CON TXG2CON ESLOTG23 ESLOTG45 0x20 0x21 0x22 ESLOTG67 TXPEND WAKECON 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F RXSR INTSTAT INTCON GPIO TRISGPIO SLPACK RFCTL SECCR2 BBREG0 BBREG1 BBREG2 BBREG3 BBREG4 Reserved BBREG6 CCAEDTH
FIGURE 2-11:
0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
0x23 FRMOFFSET 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F TXSTAT TXBCON1 GATECLK TXTIME HSYMTMRL HSYMTMRH SOFTRST Reserved SECCON0 SECCON1 TXSTBL Reserved
FIGURE 2-12:
0x200 0x201 0x202 0x203 0x204 0x205 0x206 0x207 0x208 0x209 0x20A 0x20B 0x20C 0x20D 0x20E 0x20F RFCON0 RFCON1 RFCON2 RFCON3 Reserved RFCON5 RFCON6 RFCON7 RFCON8 SLPCAL0 SLPCAL1 SLPCAL2 Reserved Reserved Reserved RFSTATE
LONG ADDRESS CONTROL REGISTER MRF24J40
0x210 0x211 0x212 0x213 0x214 0x215 0x216 0x217 0x218 0x219 0x21A 0x21B 0x21C 0x21D 0x21E 0x21F RSSI SLPCON0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 0x220 0x221 0x222 0x223 0x224 0x225 0x226 0x227 0x228 0x229 0x22A 0x22B 0x22C 0x22D 0x22E 0x22F SLPCON1 Reserved WAKETIMEL WAKETIMEH REMCNTL REMCNTH MAINCNT0 MAINCNT1 MAINCNT2 MAINCNT3 Reserved Reserved Reserved Reserved Reserved TESTMODE ox230 0x231 0x232 0x233 0x234 0x235 0x236 0x237 0x238 0x239 0x23A 0x23B 0x23C 0x23D 0x23E 0x23F ASSOEADR0 ASSOEADR1 ASSOEADR2 ASSOEADR3 ASSOEADR4 ASSOEADR5 ASSOEADR6 ASSOEADR7 ASSOSADR0 ASSOSADR1 Reserved Reserved Unimplemented Unimplemented Unimplemented Unimplemented 0x240 0x241 0x242 0x243 0x244 0x245 0x246 0x247 0x248 0x249 0x24A 0x24B 0x24C UPNONCE0 UPNONCE1 UPNONCE2 UPNONCE3 UPNONCE4 UPNONCE5 UPNONCE6 UPNONCE7 UPNONCE8 UPNONCE9 UPNONCE10 UPNONCE11 UPNONCE12
DS39776C-page
2010 Microchip Technology Inc.
MRF24J40
2.15.2 CONTROL REGISTER SUMMARY SHORT ADDRESS CONTROL REGISTER SUMMARY MRF24J40
NOACKRSP PANCOORD COORD ERRPKT PROMI Value 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 BCNONLY CSMABF1 MAWD1 CAP1 TICKP1 TXONT0 PAONT1 PAONTS0 TXONT8 TXBSECEN TXNSECEN TXG1SECEN TXG2SECEN RXFLUSH CSMABF0 MAWD0 CAP0 TICKP0 TICKP8 PAONT0 PAONT8 TXONT7 TXBTRIG TXNTRIG TXG1TRIG TXG2TRIG 0000 0000 0000 0000 0000 0000 1111 1111 0001 1100 0011 1001 0000 0000 0100 0000 0101 0001 0010 1001 0000 0010 1000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Details Page:
TABLE 2-6:
Addr. File Name
0x00 RXMCR 0x01 PANIDL 0x02 PANIDH 0x03 SADRL 0x04 SADRH 0x05 EADR0 0x06 EADR1 0x07 EADR2 0x08 EADR3 0x09 EADR4 0x0A EADR5 0x0B EADR6 0x0C EADR7 0x0D RXFLUSH 0x0E Reserved 0x0F Reserved 0x10 ORDER 0x11 TXMCR 0x12 ACKTMOUT 0x13 ESLOTG1 0x14 SYMTICKL 0x15 SYMTICKH 0x16 PACON0 0x17 PACON1 0x18 PACON2 0x19 Reserved 0x1A TXBCON0 0x1B TXNCON 0x1C TXG1CON 0x1D TXG2CON Legend:
Byte (PANIDL<7:0>) High Byte (PANIDH<15:8>) Short Address Byte (SADRL<7:0>) Short Address High Byte (SADRH<15:8>) 64-Bit Extended Address bits (EADR0<7:0>) 64-Bit Extended Address bits (EADR1<15:8>) 64-Bit Extended Address bits (EADR2<23:16>) 64-Bit Extended Address bits (EADR3<31:24>) 64-Bit Extended Address bits (EADR4<39:32>) 64-Bit Extended Address bits (EADR5<47:40>) 64-Bit Extended Address bits (EADR6<55:48>) 64-Bit Extended Address bits (EADR7<63:56>) NOCSMA DRPACK GTS1-3 TICKP7 TXONT6 PAONT7 FIFOEN TXG1RETRY1 TXG2RETRY1 WAKEPOL BATLIFEXT MAWD6 GTS1-2 TICKP6 TXONT5 PAONT6 TXG1RETRY0 TXG2RETRY0 WAKEPAD SLOTTED MAWD5 GTS1-1 TICKP5 TXONT4 PAONT5 TXONTS3 TXG1SLOT2 TXG2SLOT2 MACMINBE1 MAWD4 GTS1-0 TICKP4 TXONT3 PAONT4 PAONTS3 TXONTS2 FPSTAT TXG1SLOT1 TXG2SLOT1 CMDONLY MACMINBE0 MAWD3 CAP3 TICKP3 TXONT2 PAONT3 PAONTS2 TXONTS1 INDIRECT TXG1SLOT0 TXG2SLOT0 DATAONLY CSMABF2 MAWD2 CAP2 TICKP2 TXONT1 PAONT2 PAONTS1 TXONTS0 TXNACKREQ TXG1ACKREQ TXG2ACKREQ
reserved
2010 Microchip Technology Inc.
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MRF24J40
TABLE 2-6:
Addr. File Name
SHORT ADDRESS CONTROL REGISTER SUMMARY MRF24J40 (CONTINUED)
GTS3-3 GTS5-3 MLIFS5 IMMWAKE OFFSET7 TXNRETRY1 TXBMSK TURNTIME3 HSYMTMR7 HSYMTMR15 SECIGNORE RFSTBL3 GTS3-2 GTS5-2 MLIFS4 REGWAKE OFFSET6 TXNRETRY0 WU/BCN TURNTIME2 HSYMTMR6 HSYMTMR14 SECSTART TXBCIPHER2 RFSTBL2 GTS3-1 GTS5-1 MLIFS3 INTL OFFSET5 CCAFAIL RSSINUM1 TURNTIME1 HSYMTMR5 HSYMTMR13 RXCIPHER2 TXBCIPHER1 RFSTBL1 GTS3-0 GTS5-0 MLIFS2 INTL OFFSET4 TXG2FNT RSSINUM0 TURNTIME0 HSYMTMR4 HSYMTMR12 RXCIPHER1 TXBCIPHER0 RFSTBL0 GTS2-3 GTS4-3 GTS6-3 MLIFS1 INTL OFFSET3 TXG1FNT GTSON HSYMTMR3 HSYMTMR11 RXCIPHER0 MSIFS3 GTS2-2 GTS4-2 GTS6-2 MLIFS0 INTL OFFSET2 TXG2STAT HSYMTMR2 HSYMTMR10 RSTPWR TXNCIPHER2 MSIFS2 GTS2-1 GTS4-1 GTS6-1 GTSSWITCH INTL OFFSET1 TXG1STAT HSYMTMR1 HSYMTMR09 RSTBB TXNCIPHER1 DISDEC MSIFS1 GTS2-0 GTS4-0 GTS6-0 FPACK INTL OFFSET0 TXNSTAT HSYMTMR0 HSYMTMR08 RSTMAC TXNCIPHER0 DISENC MSIFS0 Value 0000 0000 0000 0000 0000 0000 1000 0100 0000 0000 0000 0000 0000 0000 0011 0000 0000 0000 0100 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0111 0101 0000 0000 Details Page:
0x1E ESLOTG23 0x1F ESLOTG45 0x20 ESLOTG67 0x21 TXPEND 0x22 WAKECON 0x23 FRMOFFSET 0x24 TXSTAT 0x25 TXBCON1 0x26 GATECLK 0x27 TXTIME 0x28 HSYMTMRL 0x29 HSYMTMRH 0x2A SOFTRST 0x2B Reserved 0x2C SECCON0 0x2D SECCON1 0x2E TXSTBL 0x2F Reserved Legend:
reserved
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2010 Microchip Technology Inc.
MRF24J40
TABLE 2-6:
Addr. File Name
SHORT ADDRESS CONTROL REGISTER SUMMARY MRF24J40 (CONTINUED)
SLPIF SLPIE SLPACK UPDEC CCAMODE1 PREVALIDTH3 CSTH2 RSSIMODE1 CCAEDTH7 UPSECERR WAKEIF WAKEIE WAKECNT6 UPENC CCAMODE0 PREVALIDTH2 CSTH1 RSSIMODE2 CCAEDTH6 BATIND HSYMTMRIF HSYMTMRIE GPIO5 TRISGP5 WAKECNT5 TXG2CIPHER2 CCACSTH3 PREVALIDTH1 CSTH0 CCAEDTH5 SECIF SECIE GPIO4 TRISGP4 WAKECNT4 WAKECNT8 TXG2CIPHER1 CCACSTH2 PREVALIDTH0 PRECNT2 CCAEDTH4 RXIF RXIE GPIO3 TRISGP3 WAKECNT3 WAKECNT7 TXG2CIPHER0 CCACSTH1 PREDETTH2 PRECNT1 CCAEDTH3 SECDECERR TXG2IF TXG2IE GPIO2 TRISGP2 WAKECNT2 RFRST TXG1CIPHER2 RXDECINV CCACSTH0 PREDETTH1 PRECNT0 CCAEDTH2 TXG1IF TXG1IE GPIO1 TRISGP1 WAKECNT1 RFTXMODE TXG1CIPHER1 PREDETTH0 CCAEDTH1 TXNIF TXNIE GPIO0 TRISGP0 WAKECNT0 RFRXMODE TXG1CIPHER0 TURBO RSSIRDY CCAEDTH0 Value 0000 0000 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0100 1000 1101 1000 1001 1100 0000 0000 0000 0001 0000 0000 Details Page:
0x30 RXSR 0x31 INTSTAT 0x32 INTCON 0x33 GPIO 0x34 TRISGPIO 0x35 SLPACK 0x36 RFCTL 0x37 SECCR2 0x38 BBREG0 0x39 BBREG1 0x3A BBREG2 0x3B BBREG3 0x3C BBREG4 0x3D Reserved 0x3E BBREG6 0x3F CCAEDTH Legend:
reserved
TABLE 2-7:
Addr. File Name
LONG ADDRESS CONTROL REGISTER SUMMARY MRF24J40
CHANNEL3 VCOOPT7 PLLEN TXPWRL1 BATTH3 TXFIL SLPCLKSEL1 SLPCAL7 SLPCAL15 SLPCALRDY RFSTATE2 RSSI7 CHANNEL2 VCOOPT6 TXPWRL0 BATTH2 SLPCLKSEL0 SLPCAL6 SLPCAL14 RFSTATE1 RSSI6 CHANNEL1 VCOOPT5 TXPWRS2 BATTH1 SLPCAL5 SLPCAL13 RFSTATE0 RSSI5 CHANNEL0 VCOOPT4 TXPWRS1 BATTH0 20MRECVR RFVCO SLPCAL4 SLPCAL12 SLPCALEN RSSI4 RFOPT3 VCOOPT3 TXPWRS0 BATEN SLPCAL3 SLPCAL11 SLPCAL19 RSSI3 RFOPT2 VCOOPT2 SLPCAL2 SLPCAL10 SLPCAL18 RSSI2 RFOPT1 VCOOPT1 CLKOUTMODE1 SLPCAL1 SLPCAL9 SLPCAL17 RSSI1 INTEDGE RFOPT0 VCOOPT0 Value 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Details Page:
0x200 RFCON0 0x201 RFCON1 0x202 RFCON2 0x203 RFCON3 0x204 Reserved 0x205 RFCON5 0x206 RFCON6 0x207 RFCON7 0x208 RFCON8 0x209 SLPCAL0 0x20A SLPCAL1 0x20B SLPCAL2 0x20C Reserved 0x20D Reserved 0x20E Reserved 0x20F RFSTATE 0x210 RSSI 0x211 SLPCON0 0x212 Reserved Legend:
CLKOUTMODE0 0000 0000 SLPCAL0 SLPCAL8 SLPCAL16 RSSI0 SLPCLKEN 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
reserved
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TABLE 2-7:
Addr. File Name
LONG ADDRESS CONTROL REGISTER SUMMARY MRF24J40 (CONTINUED)
WAKETIME7 REMCNT7 REMCNT15 MAINCNT7 MAINCNT15 MAINCNT23 STARTCNT WAKETIME6 REMCNT6 REMCNT14 MAINCNT6 MAINCNT14 MAINCNT22 CLKOUTEN WAKETIME5 REMCNT5 REMCNT13 MAINCNT5 MAINCNT13 MAINCNT21 SLPCLKDIV4 WAKETIME4 REMCNT4 REMCNT12 MAINCNT4 MAINCNT12 MAINCNT20 RSSIWAIT1 SLPCLKDIV3 WAKETIME3 REMCNT3 REMCNT11 MAINCNT3 MAINCNT11 MAINCNT19 RSSIWAIT0 SLPCLKDIV2 WAKETIME2 WAKETIME10 REMCNT2 REMCNT10 MAINCNT2 MAINCNT10 MAINCNT18 TESTMODE2 SLPCLKDIV1 WAKETIME1 WAKETIME9 REMCNT1 REMCNT9 MAINCNT1 MAINCNT9 MAINCNT17 MAINCNT25 TESTMODE1 SLPCLKDIV0 WAKETIME0 WAKETIME8 REMCNT0 REMCNT8 MAINCNT0 MAINCNT8 MAINCNT16 MAINCNT24 TESTMODE0 Value 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 -0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Details Page:
0x213 Reserved 0x214 Reserved 0x215 Reserved 0x216 Reserved 0x217 Reserved 0x218 Reserved 0x219 Reserved 0x21A Reserved 0x21B Reserved 0x21C Reserved 0x21D Reserved 0x21E Reserved 0x21F Reserved 0x220 SLPCON1 0x221 Reserved 0x222 WAKETIMEL 0x223 WAKETIMEH 0x224 REMCNTL 0x225 REMCNTH 0x226 MAINCNT0 0x227 MAINCNT1 0x228 MAINCNT2 0x229 MAINCNT3 0x22A Reserved 0x22B Reserved 0x22C Reserved 0x22D Reserved 0x22E Reserved 0x22F TESTMODE 0x230 ASSOEADR0 0x231 ASSOEADR1 0x232 ASSOEADR2 0x233 ASSOEADR3 0x234 ASSOEADR4 0x235 ASSOEADR5 0x236 ASSOEADR6 0x237 ASSOEADR7 0x238 ASSOSADR0 0x239 ASSOSADR1 0x23A Reserved 0x23B Reserved 0x23C Unimplemented 0x23D Unimplemented 0x23E Unimplemented 0x23F Unimplemented 0x240 UPNONCE0 0x241 UPNONCE1 0x242 UPNONCE2 0x243 UPNONCE3 0x244 UPNONCE4 0x245 UPNONCE5 Legend: reserved
ASSOEADR0<7:0> ASSOEADR1<15:8> ASSOEADR2<23:16> ASSOEADR3<31:24> ASSOEADR4<39:32> ASSOEADR5<47:40> ASSOEADR6<55:48> ASSOEADR7<63:56> ASSOSADR0<7:0> ASSOSADR1<15:8> UPNONCE<7:0> UPNONCE<15:8> UPNONCE<23:16> UPNONCE<31:24> UPNONCE<39:32> UPNONCE<47:40>
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TABLE 2-7:
Addr. File Name
LONG ADDRESS CONTROL REGISTER SUMMARY MRF24J40 (CONTINUED)
Value 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Details Page:
0x246 UPNONCE6 0x247 UPNONCE7 0x248 UPNONCE8 0x249 UPNONCE9 0x24A UPNONCE10 0x24B UPNONCE11 0x24C UPNONCE12 Legend: reserved
UPNONCE<55:48> UPNONCE<63:56> UPNONCE<71:64> UPNONCE<79:72> UPNONCE<87:80> UPNONCE<95:88> UPNONCE<103:96>
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2.15.3 SHORT ADDRESS CONTROL REGISTERS DETAIL RXMCR: RECEIVE CONTROL REGISTER (ADDRESS: 0x00)
R/W-0 R/W-0 NOACKRSP R/W-0 R/W-0 PANCOORD R/W-0 COORD R/W-0 ERRPKT R/W-0 PROMI reserved Writable Unimplemented bit, read cleared unknown
REGISTER 2-1:
R/W-0 Legend: Readable Value
Reserved: Maintain NOACKRSP: Automatic Acknowledgement Response Disables automatic Acknowledgement response Enables automatic Acknowledgement response. Acknowledgements returned when they requested (default). Reserved: Maintain PANCOORD: Coordinator device coordinator Device coordinator (default) COORD: Coordinator device coordinator Device coordinator (default) ERRPKT: Packet Error Mode Accept packets including those with error Accept only packets with good (default) PROMI: Promiscuous Mode Receive packet types with good Discard packet when there address mismatch, illegal frame type, dPAN/sPAN short address mismatch (default)
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REGISTER 2-2:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
PANIDL: BYTE REGISTER (ADDRESS: 0x01)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Byte (PANIDL<7:0>)
PANIDL<7:0>: Byte bits
REGISTER 2-3:
R/W-0 Legend: Readable Value
PANIDH: HIGH BYTE REGISTER (ADDRESS: 0x02)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 High Byte (PANIDH<15:8>)
Writable
Unimplemented bit, read cleared unknown
PANIDH<15:8>: High Byte bits
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REGISTER 2-4:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
SADRL: SHORT ADDRESS BYTE REGISTER (ADDRESS: 0x03)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Short Address Byte (SADRL<7:0>)
SADRL<7:0>: Short Address Byte bits
REGISTER 2-5:
R/W-0 Legend: Readable Value
SADRH: SHORT ADDRESS HIGH BYTE REGISTER (ADDRESS: 0x04)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Short Address High Byte (SADRH<15:8>)
Writable
Unimplemented bit, read cleared unknown
SADRH<15:8>: Short Address High Byte bits
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REGISTER 2-6:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
EADR0: EXTENDED ADDRESS REGISTER (ADDRESS: 0x05)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<7:0>)
EADR<7:0>: 64-Bit Extended Address bits
REGISTER 2-7:
R/W-0 Legend: Readable Value
EADR1: EXTENDED ADDRESS REGISTER (ADDRESS: 0x06)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<15:8>)
Writable
Unimplemented bit, read cleared unknown
EADR<15:8>: 64-Bit Extended Address bits
REGISTER 2-8:
R/W-0 Legend: Readable Value
EADR2: EXTENDED ADDRESS REGISTER (ADDRESS: 0x07)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<23:16>)
Writable
Unimplemented bit, read cleared unknown
EADR<23:16>: 64-Bit Extended Address bits
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REGISTER 2-9:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
EADR3: EXTENDED ADDRESS REGISTER (ADDRESS: 0x08)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<31:24>)
EADR<31:24>: 64-Bit Extended Address bits
REGISTER 2-10:
R/W-0 Legend: Readable Value
EADR4: EXTENDED ADDRESS REGISTER (ADDRESS: 0x09)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<39:32>)
Writable
Unimplemented bit, read cleared unknown
EADR<39:32>: 64-Bit Extended Address bits
REGISTER 2-11:
R/W-0 Legend: Readable Value
EADR5: EXTENDED ADDRESS REGISTER (ADDRESS: 0x0A)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<47:40>)
Writable
Unimplemented bit, read cleared unknown
EADR<47:40>: 64-Bit Extended Address bits
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REGISTER 2-12:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
EADR6: EXTENDED ADDRESS REGISTER (ADDRESS: 0x0B)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<55:48>)
EADR<55:48>: 64-Bit Extended Address bits
REGISTER 2-13:
R/W-0 Legend: Readable Value
EADR7: EXTENDED ADDRESS REGISTER (ADDRESS: 0x0C)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 64-Bit Extended Address bits (EADR<63:56>)
Writable
Unimplemented bit, read cleared unknown
EADR<63:56>: 64-Bit Extended Address bits
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REGISTER 2-14:
R/W-0 Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
RXFLUSH: RECEIVE FIFO FLUSH REGISTER (ADDRESS: 0x0D)
R/W-0 R/W-0 WAKEPAD R/W-0 R/W-0 CMDONLY R/W-0 DATAONLY R/W-0 BCNONLY RXFLUSH
WAKEPOL
Reserved: Maintain WAKEPOL: Wake Signal Polarity Wake signal polarity active-high Wake signal polarity active-low (default) WAKEPAD: Wake Enable Enable wake Disable wake (default) Reserved: Maintain CMDONLY: Command Frame Receive Only command frames received, other frames filtered valid frames received (default) DATAONLY: Data Frame Receive Only data frames received, other frames filtered valid frames received (default) BCNONLY: Beacon Frame Receive Only beacon frames received, other frames filtered valid frames received (default) RXFLUSH: Reset Receive FIFO Address Pointer Resets RXFIFO Address Pointer zero. RXFIFO data modified. automatically cleared hardware.
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REGISTER 2-15:
R/W-1 BO3(1) Legend: Readable Value Writable Unimplemented bit, read cleared unknown
ORDER: BEACON SUPERFRAME ORDER REGISTER (ADDRESS: 0x10)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1 SO0(1)
BO<3:0>: Beacon Order bits (macBeaconOrder)(1) Specifies often coordinator will transmit beacon.(2) 1111 coordinator will transmit beacon Superframe Order (SO) parameter value ignored (default) 1110 0000 SO<3:0>: Superframe Order bits (macSuperframeOrder)(1) Specifies length active portion superframe, including beacon frame.(2) 1111 superframe will active following beacon (i.e., active portion superframe (default)) 1110 0000 Refer IEEE 802.15.4TM-2003 Standard, Section 7.5.1.1 "Superframe Structure". PANs that wish superframe structure shall macBeaconOrder value between macSuperframeOrder value between value macBeaconOrder (i.e., 14).
Note
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REGISTER 2-16:
R/W-0 NOCSMA Legend: Readable Value Writable Unimplemented bit, read cleared unknown
TXMCR: CSMA-CA MODE CONTROL REGISTER (ADDRESS: 0x11)
R/W-0 SLOTTED R/W-1 MACMINBE1 R/W-1 MACMINBE0 R/W-1 CSMABF2 R/W-0 CSMABF1 R/W-0 CSMABF0
R/W-0 BATLIFEXT
NOCSMA: Carrier Sense Multiple Access (CSMA) Algorithm bits Disable CSMA-CA algorithm when transmitting Unslotted mode with GTSSWITCH (TXPEND 0x21<1>) Enable CSMA-CA algorithm when transmitting Unslotted mode with GTSSWITCH (TXPEND 0x21<1>) (default) BATLIFEXT: Battery Life Extension Mode (macBattLifeExt) Enable Disable (default) SLOTTED: Slotted CSMA-CA Mode Enable Slotted CSMA-CA mode Disable Slotted CSMA-CA mode (default) MACMINBE<1:0>: Minimum Backoff Exponent bits (macMinBE) minimum value backoff exponent CSMA-CA algorithm. Note that this value `0', collision avoidance disabled.(1) Default: 0x3. CSMABF<2:0>: CSMA Backoff bits (macMaxCSMABackoff) maximum number backoffs CSMA-CA algorithm will attempt before declaring channel access failure.(1) Undefined Undefined (default) Refer IEEE 802.15.4TM-2003 Standard, Table attributes.
Note
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REGISTER 2-17:
R/W-0 DRPACK Legend: Readable Value Writable Unimplemented bit, read cleared unknown
ACKTMOUT: TIME-OUT DURATION REGISTER (ADDRESS: 0x12)
R/W-0 R/W-1 MAWD5
R/W-1 MAWD4
R/W-1 MAWD3
R/W-0 MAWD2
R/W-0 MAWD1
R/W-1 MAWD0(1)
MAWD6(1)
DRPACK: Data Request Pending Acknowledgement bit(1) Sets clears frame pending Acknowledgement frame received data request command. Sets frame pending Clears frame pending MAWD<6:0>: macAckWaitDuration bits(2) maximum number symbols wait Acknowledgment frame arrive following transmitted data command frame. Units: Symbol period Default value: 0x39. Refer IEEE 802.15.4TM-2003 Standard, Section 5.4.2.2 "Data Transfer from Coordinator" Section "MAC Command Frames". Refer IEEE 802.15.4TM-2003 Standard, Table Attributes.
Note
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REGISTER 2-18:
R/W-0 GTS1-3 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
ESLOTG1: GTS1 SLOT REGISTER (ADDRESS: 0x13)
R/W-0 R/W-0 GTS1-1 R/W-0 GTS1-0 R/W-0 CAP3 R/W-0 CAP2 R/W-0 CAP1 R/W-0 CAP0
GTS1-2
GTS1-<3:0>: Slot bits 1111 0000 (default) CAP<3:0>: Contention Access Period (CAP) Slot bits 1111 0000 (default)
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REGISTER 2-19:
R/W-0 TICKP7 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
SYMTICKL: SYMBOL PERIOD TICK BYTE REGISTER (ADDRESS: 0x14)
R/W-1 R/W-0 TICKP5 R/W-0 TICKP4 R/W-0 TICKP3 R/W-0 TICKP2 R/W-0 TICKP1 R/W-0 TICKP0
TICKP6
TICKP<7:0>: Symbol Period Tick bits Number ticks define symbol period. Tick period based system clock frequency MHz. TICKP 9-bit value. TICKP8 located SYMTICKH<0>. Units: tick ns). Default value 0x140 (320
REGISTER 2-20:
R/W-0 TXONT6(1) Legend: Readable Value
SYMTICKH: SYMBOL PERIOD TICK HIGH BYTE REGISTER (ADDRESS: 0x15)
R/W-0 TXONT4(1) R/W-1 TXONT3(1) R/W-0 TXONT2(1) R/W-0 TXONT1(1) R/W-0 TXONT0(1) R/W-1 TICKP8
R/W-1 TXONT5(1)
Writable
Unimplemented bit, read cleared unknown
TXONT<6:0>: Transmitter Enable Time Tick bits(1) Transmitter time before beginning packet. TXONT 9-bit value. TXONT<8:7> bits located PACON2<1:0>. Units: tick ns). Default value 0x028 TICKP8: Symbol Period Tick Number ticks define symbol period. Tick period based system clock frequency MHz. TICKP 9-bit value. TICKP<7:0> bits located SYMTICKL<7:0>. Units: tick ns). Default value 0x140 (320 Refer Figure timing diagram.
Note
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REGISTER 2-21:
R/W-0 PAONT7(1) Legend: Readable Value Writable Unimplemented bit, read cleared unknown
PACON0: POWER AMPLIFIER CONTROL REGISTER (ADDRESS: 0x16)
R/W-1
R/W-0 PAONT6
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
PAONT5
PAONT4
PAONT3
PAONT2
PAONT1
PAONT0(1)
PAONT<7:0>: Power Amplifier Enable Time Tick bits(1) Power amplifier time before beginning packet. PAONT 9-bit value. PAONT8 located PACON1<0>. Units: tick ns). Default value 0x029 2.05 Refer Figure timing diagram.
Note
REGISTER 2-22:
R/W-0 Legend: Readable Value
PACON1: POWER AMPLIFIER CONTROL REGISTER (ADDRESS: 0x17)
R/W-0 R/W-0 PAONTS3(1) R/W-0 PAONTS2(1) R/W-0 PAONTS1(1) R/W-1 PAONTS0(1) R/W-0 PAONT8(1) reserved Writable Unimplemented bit, read cleared unknown
R/W-0
Reserved: Maintain PAONTS<3:0>: Power Amplifier Enable Time Symbol bits(1) Power amplifier time before beginning packet. Units: symbol period Minimum value: (default) PAONT8: Power Amplifier Enable Time Tick bit(1) Power amplifier time before beginning packet. PAONT 9-bit value. PAONT<7:0> bits located PACON0<7:0>. Units: tick ns). Default value 0x029 2.05 Refer Figure timing diagram.
Note
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REGISTER 2-23:
R/W-1 FIFOEN Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
PACON2: POWER AMPLIFIER CONTROL REGISTER (ADDRESS: 0x18)
R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 TXONT8(1) R/W-0 TXONT7(1) TXONTS3(1) TXONTS2(1) TXONTS1(1) TXONTS0(1)
R/W-0
FIFOEN: FIFO Enable Enabled (default). Always maintain this `1'. Reserved: Maintain TXONTS<3:0>: Transmitter Enable Time Symbol bits(1) Transmitter time before beginning packet. Units: symbol period Minimum value: 0x1. Default value: Recommended value: TXONT<8:7>: Transmitter Enable Time Tick bits(1) Transmitter time before beginning packet. TXONT 9-bit value. TXONT<6:0> bits located SYMTICKH<7:1>. Units: tick ns). Default value 0x028 Refer Figure timing diagram.
Note
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REGISTER 2-24:
Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
TXBCON0: TRANSMIT BEACON FIFO CONTROL REGISTER (ADDRESS: 0x1A)
R/W-0 TXBSECEN TXBTRIG
Reserved: Maintain TXBSECEN: Beacon FIFO Security Enabled Security enabled Security disabled (default) TXBTRIG: Transmit Frame Beacon FIFO Transmit frame Beacon FIFO; automatically cleared hardware
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REGISTER 2-25:
R/W-0 Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
TXNCON: TRANSMIT NORMAL FIFO CONTROL REGISTER (ADDRESS: 0x1B)
R/W-0 FPSTAT
R/W-0
R/W-0 INDIRECT
R/W-0 TXNACKREQ
(2,4)
R/W-0 TXNSECEN
(3,4)
TXNTRIG
Reserved: Maintain FPSTAT: Frame Pending Status bit(1) Status frame pending received Acknowledgement frame. Sets frame pending Clears frame pending INDIRECT: Activate Indirect Transmission (coordinator only)(4) Indirect transmission enabled Indirect transmission disabled (default) TXNACKREQ: Normal FIFO Acknowledgement Request bit(2,4) Transmit frame with Acknowledgement frame expected. Acknowledgement received, retransmit. Acknowledgement requested Acknowledgement requested (default) TXNSECEN: Normal FIFO Security Enabled bit(3,4) Security enabled Security disabled (default) TXNTRIG: Transmit Frame Normal FIFO Transmit frame Normal FIFO; automatically cleared hardware Refer IEEE 802.15.4TM-2003 Standard, Section 7.2.1.1.3 "Frame Pending Subfield". Refer IEEE 802.15.4-2003 Standard, Section 7.2.1.1.4 "Acknowledgement Request Subfield". Refer IEEE 802.15.4-2003 Standard, Section 7.2.1.1.2 "Security Enabled Subfield". cleared next triggering FIFO.
Note
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REGISTER 2-26:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
TXG1CON: GTS1 FIFO CONTROL REGISTER (ADDRESS: 0x1C)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TXG1TRIG
TXG1RETRY1 TXG1RETRY0 TXG1SLOT2 TXG1SLOT1 TXG1SLOT0 TXG1ACKREQ TXG1SECEN
TXG1RETRY<1:0>: GTS1 FIFO Retry Times bits Write: retry times packet Read: number retry times successfully transmitted packet TXG1SLOT<2:0>: Slot that GTS1 FIFO Occupies bits TXG1ACKREQ: GTS1 FIFO Acknowledgement Request Transmit frame with Acknowledgement frame expected. Acknowledgement received, retransmit. Acknowledgement requested Acknowledgement requested (default) TXG1SECEN: GTS1 FIFO Security Enabled Security enabled Security disabled (default) TXG1TRIG: Transmit Frame GTS1 FIFO Transmit frame GTS1 FIFO; automatically cleared hardware
REGISTER 2-27:
R/W-0 Legend: Readable Value
TXG2CON: GTS2 FIFO CONTROL REGISTER (ADDRESS: 0x1D)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
TXG2RETRY1 TXG2RETRY0 TXG2SLOT2 TXG2SLOT1 TXG2SLOT0 TXG2ACKREQ TXG2SECEN TXG2TRIG
Writable
Unimplemented bit, read cleared unknown
TXG2RETRY<1:0>: GTS2 FIFO Retry Times bits Write: retry times packet Read: number retry times successfully transmitted packet TXG2SLOT<2:0>: Slot that GTS2 FIFO Occupies bits TXG2ACKREQ: GTS2 FIFO Acknowledgement Request Transmit frame with Acknowledgement frame expected. Acknowledgement received, retransmit. Acknowledgement requested Acknowledgement requested (default) TXG2SECEN: GTS2 FIFO Security Enabled Security enabled Security disabled (default) TXG2TRIG: Transmit Frame GTS2 FIFO Transmit frame GTS2 FIFO; automatically cleared hardware
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REGISTER 2-28:
R/W-0 GTS3-3 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
ESLOTG23: SLOT GTS3 GTS2 REGISTER (ADDRESS: 0x1E)
R/W-0 R/W-0 GTS3-1 R/W-0 GTS3-0 R/W-0 GTS2-3 R/W-0 GTS2-2 R/W-0 GTS2-1 R/W-0 GTS2-0
GTS3-2
GTS3-<3:0>: Slot bits GTS2-<3:0>: Slot bits
REGISTER 2-29:
R/W-0 GTS5-3 Legend: Readable Value
ESLOTG45: SLOT GTS5 GTS4 REGISTER (ADDRESS: 0x1F)
R/W-0 R/W-0 GTS5-1 R/W-0 GTS5-0 R/W-0 GTS4-3 R/W-0 GTS4-2 R/W-0 GTS4-1 R/W-0 GTS4-0
GTS5-2
Writable
Unimplemented bit, read cleared unknown
GTS5-<3:0>: Slot bits GTS4-<3:0>: Slot bits
REGISTER 2-30:
Legend: Readable Value
ESLOTG67: SLOT GTS6 REGISTER (ADDRESS: 0x20)
R/W-0 GTS6-3 R/W-0 GTS6-2 R/W-0 GTS6-1 R/W-0 GTS6-0 reserved Writable Unimplemented bit, read cleared unknown
Reserved: Maintain GTS6-<3:0>: Slot bits exists, slot must
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REGISTER 2-31:
R/W-1 MLIFS5 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
TXPEND: DATA PENDING REGISTER (ADDRESS: 0x21)
R/W-0 MLIFS3 R/W-0 MLIFS2 R/W-0 MLIFS1 R/W-1 MLIFS0 R/W-0 GTSSWITCH R/W-0 FPACK(1)
R/W-0 MLIFS4
MLIFS<5:0>: Minimum Long Interframe Spacing bits minimum number symbols forming Long Interframe Spacing (LIFS) period. Refer IEEE 802.15.4TM-2003 Standard, Section 7.5.1.2 "IFS" Table Sublayer Constants. MLIFS RFSTBL aMinLIFSPeriod symbols. Units: symbol period Default value: 0x21. Recommended values: MLIFS 0x1F RFSTBL 0x9. GTSSWITCH: Continue FIFO Switch GTS1 GTS2 FIFO will toggle with each other during GTS1 GTS2 FIFO will stop toggling with each other transmission fails (default) FPACK: Frame Pending Acknowledgement Frame bit(1) Sets clears frame pending Acknowledgement frame. Sets frame pending Clears frame pending Refer IEEE 802.15.4TM-2003 Standard, Section 7.2.1.1.3 "Frame Pending Subfield" Section 7.2.2.3.1 "Acknowledgement Frame Fields".
Note
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REGISTER 2-32:
R/W-0 IMMWAKE Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
WAKECON: WAKE CONTROL REGISTER (ADDRESS: 0x22)
R/W-0 R/W-0 INTL R/W-0 INTL R/W-0 INTL R/W-0 INTL R/W-0 INTL R/W-0 INTL
REGWAKE
IMMWAKE: Immediate Wake-up Mode Enable Enable Immediate Wake-up mode Disable Immediate Wake-up mode (default) REGWAKE: Register Wake-up Signal Host processor should `1', then clear `0', perform wake-up. INTL<5:0>: Interval Start Beacon(1) Beacon-Enabled mode timing interval between triggering slotted mode first time transmit beacon. Default Value: 0x00. Refer Section 3.8.1.4 "Configuring Beacon-Enabled Coordinator" more information.
Note
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REGISTER 2-33:
R/W-0 OFFSET7(1) Legend: Readable Value Writable Unimplemented bit, read cleared unknown
FRMOFFSET: SUPERFRAME COUNTER OFFSET ALIGN BEACON REGISTER (ADDRESS: 0x23)
R/W-0 R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OFFSET6
OFFSET5
OFFSET4
OFFSET3
OFFSET2
OFFSET1
OFFSET0(1)
OFFSET<7:0>: Superframe Counter Offset Align Slot Boundary bits(1) Beacon-Enabled mode device. Default value: 0x00. Recommended value: 0x15. Refer Section 3.8.1.6 "Configuring Beacon-Enabled Device" more information.
Note
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REGISTER 2-34:
Legend: Readable Value Writable Unimplemented bit, read cleared unknown
TXSTAT: STATUS REGISTER (ADDRESS: 0x24)
CCAFAIL TXG2FNT TXG1FNT TXG2STAT TXG1STAT TXNSTAT
TXNRETRY1 TXNRETRY0
TXNRETRY<1:0>: Normal FIFO Retry Times bits Number retries most recent Normal FIFO transmission. CCAFAIL: Clear Channel Assessment (CCA) Status Last Transmission Channel busy Channel Idle TXG2FNT: GTS2 FIFO Transmission failed enough time before Failed Succeeded TXG1FNT: GTS1 FIFO Transmission failed enough time before Failed Succeeded TXG2STAT: GTS2 FIFO Release Status Failed, retry count exceeded Succeeded TXG1STAT: GTS2 FIFO Release Status Failed, retry count exceeded Succeeded TXNSTAT: Normal FIFO Release Status Failed, retry count exceeded Succeeded
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REGISTER 2-35:
R/W-0 TXBMSK Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
TXBCON1: TRANSMIT BEACON CONTROL REGISTER (ADDRESS: 0x25)
R/W-1 RSSINUM1 R/W-1 RSSINUM0
WU/BCN
TXBMSK: Beacon FIFO Interrupt Mask Beacon FIFO interrupt masked Beacon FIFO interrupt masked (default) WU/BCN: Wake-up/Beacon Interrupt Status Indicates WAKEIF interrupt beacon start wake-up. Beacon start interrupt Wake-up interrupt RSSINUM<1:0>: RSSI Average Symbols bits symbols (default) symbols symbols symbol Reserved: Maintain
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REGISTER 2-36:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
GATECLK: GATED CLOCK CONTROL REGISTER (ADDRESS: 0x26)
R/W-0 R/W-0 R/W-0 R/W-0 GTSON R/W-0 R/W-0 R/W-0
Reserved: Maintain GTSON: FIFO Clock Enable Enabled Disabled (default) Reserved: Maintain
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REGISTER 2-37:
R/W-0 Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
TXTIME: TURNAROUND TIME REGISTER (ADDRESS: 0x27)
R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-0
R/W-1
TURNTIME3 TURNTIME2 TURNTIME1 TURNTIME0
TURNTIME<3:0>: Turnaround Time bits Transmission reception reception transmission turnaround time. Refer IEEE 802.15.4TM-2003 Standard, Table Constants Section 7.5.6.4.2 "Acknowledgment". TURNTIME RFSTBL aTurnaroundTime symbols. Units: symbol period Default value: 0x4. Minimum value: 0x2. Recommended values: TURNTIME RFSTBL 0x9. Reserved: Maintain
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REGISTER 2-38:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
HSYMTMRL: HALF SYMBOL TIMER BYTE REGISTER (ADDRESS: 0x28)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 HSYMTMR5 HSYMTMR4 HSYMTMR3 HSYMTMR2 HSYMTMR1 HSYMTMR0
R/W-0
HSYMTMR7 HSYMTMR6
HSYMTMR<7:0>: Half Symbol Timer Byte bits Units:
REGISTER 2-39:
R/W-0 Legend: Readable Value
HSYMTMRH: HALF SYMBOL TIMER HIGH BYTE REGISTER (ADDRESS: 0x29)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
HSYMTMR15 HSYMTMR14 HSYMTMR13 HSYMTMR12 HSYMTMR11 HSYMTMR10 HSYMTMR09 HSYMTMR08
Writable
Unimplemented bit, read cleared unknown
HSYMTMR<15:8>: Half Symbol Timer High Byte bits Units:
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REGISTER 2-40:
R/W-0 Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
SOFTRST: SOFTWARE RESET REGISTER (ADDRESS: 0x2A)
R/W-0 R/W-0 R/W-0 R/W-0 RSTPWR RSTBB RSTMAC
Reserved: Maintain RSTPWR: Power Management Reset Reset power management circuitry (bit automatically cleared hardware) RSTBB: Baseband Reset Reset baseband circuitry (bit automatically cleared hardware) RSTMAC: Reset Reset circuitry (bit automatically cleared hardware)
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REGISTER 2-41:
SECIGNORE Legend: Readable Value Writable Unimplemented bit, read cleared unknown
SECCON0: SECURITY CONTROL REGISTER (ADDRESS: 0x2C)
R/W-0 R/W-0 R/W-0 R/W-0 TXNCIPHER2 R/W-0 TXNCIPHER1 R/W-0 TXNCIPHER0 RXCIPHER1 RXCIPHER0
SECSTART RXCIPHER2
SECIGNORE: Security Decryption Ignore Ignore decryption process SECSTART: Security Decryption Start Start decryption process
RXCIPHER<2:0>: FIFO Security Suite Select bits AES-CBC-MAC-32 AES-CBC-MAC-64 AES-CBC-MAC-128 AES-CCM-32 AES-CCM-64 AES-CCM-128 AES-CTR None (default) TXNCIPHER<2:0>: Normal FIFO Security Suite Select bits AES-CBC-MAC-32 AES-CBC-MAC-64 AES-CBC-MAC-128 AES-CCM-32 AES-CCM-64 AES-CCM-128 AES-CTR None (default)
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REGISTER 2-42:
R/W-0 Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
SECCON1: SECURITY CONTROL REGISTER (ADDRESS: 0x2D)
R/W-0 TXBCIPHER1 R/W-0 TXBCIPHER0 R/W-0 R/W-0 R/W-0 DISDEC R/W-0 DISENC
R/W-0 TXBCIPHER2
Reserved: Read TXBCIPHER<2:0>: Beacon FIFO Security Suite Select bits AES-CBC-MAC-32 AES-CBC-MAC-64 AES-CBC-MAC-128 AES-CCM-32 AES-CCM-64 AES-CCM-128 AES-CTR None (default) Reserved: Read DISDEC: Disable Decryption Function Will generate security interrupt security enabled header DISENC: Disable Encryption Function
Will encrypt packet transmit security enabled
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REGISTER 2-43:
R/W-0 RFSTBL3 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
TXSTBL: STABILIZATION REGISTER (ADDRESS: 0x2E)
R/W-1 RFSTBL1 R/W-1 RFSTBL0 R/W-0 MSIFS3 R/W-1 MSIFS2 R/W-0 MSIFS1 R/W-1 MSIFS0
R/W-1 RFSTBL2
RFSTBL<3:0>: Stabilization Period bits Units: symbol period Default value: 0x7. Recommended value: 0x9. MSIFS<3:0>: Minimum Short Interframe Spacing bits minimum number symbols forming Short Interframe Spacing (SIFS) period. Refer IEEE 802.15.4TM-2003 Standard, Section 7.5.1.2 "IFS" Table Sublayer Constants. MSIFS RFSTBL aMinSIFSPeriod symbols. Units: symbol period Default value: 0x5.
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REGISTER 2-44:
Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
RXSR: STATUS REGISTER (ADDRESS: 0x30)
BATIND(1) SECDECERR R/W-0
R/W-0 UPSECERR
Reserved: Read UPSECERR: Error Upper Layer Security Mode error occurred. Write clear error occur BATIND: Battery Low-Voltage Indicator bit(1) Supply voltage lower than battery low-voltage threshold Supply voltage greater than battery low-voltage threshold Reserved: Maintain SECDECERR: Security Decryption Error Security decryption error occurred Security decryption error occur Reserved: Maintain Battery low-voltage threshold (BATTH) value RFCON5 (0X205<7:4>) register Battery Monitor Enable (BATEN) located RFCON6 (0x206<3>) register.
Note
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REGISTER 2-45:
RC-0 SLPIF(1) Legend: Readable Value Read clear Writable SLPIF: Sleep Alert Interrupt bit(1) Sleep alert interrupt occurred Sleep alert interrupt occurred WAKEIF: Wake-up Alert Interrupt bit(1) wake-up alert interrupt occurred wake-up alert interrupt occurred HSYMTMRIF: Half Symbol Timer Interrupt bit(1) half symbol timer interrupt occurred half symbol timer interrupt occurred SECIF: Security Request Interrupt bit(1) security request interrupt occurred security request interrupt occurred RXIF: FIFO Reception Interrupt bit(1) FIFO reception interrupt occurred FIFO reception interrupt occurred TXG2IF: GTS2 FIFO Transmission Interrupt bit(1) GTS2 FIFO transmission interrupt occurred GTS2 FIFO transmission interrupt occurred TXG1IF: GTS1 FIFO Transmission Interrupt bit(1) GTS1 FIFO transmission interrupt occurred GTS1 FIFO transmission interrupt occurred TXNIF: Normal FIFO Release Interrupt bit(1) Normal FIFO transmission interrupt occurred Normal FIFO transmission interrupt occurred Interrupt bits cleared when INTSTAT register read. Unimplemented bit, read cleared unknown
INTSTAT: INTERRUPT STATUS REGISTER (ADDRESS: 0x31)
RC-0 WAKEIF
RC-0 HSYMTMRIF
RC-0 SECIF
RC-0 RXIF
RC-0 TXG2IF
RC-0 TXG1IF
RC-0 TXNIF(1)
Note
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REGISTER 2-46:
R/W-1 SLPIE Legend: Readable Value Writable Unimplemented bit, read cleared unknown
INTCON: INTERRUPT CONTROL REGISTER (ADDRESS: 0x32)
R/W-1 HSYMTMRIE R/W-1 SECIE R/W-1 RXIE R/W-1 TXG2IE R/W-1 TXG1IE R/W-1 TXNIE
R/W-1 WAKEIE
SLPIE: Sleep Alert Interrupt Enable Disables Sleep alert interrupt (default) Enables Sleep alert interrupt WAKEIE: Wake-up Alert Interrupt Enable Disables wake-up alert interrupt (default) Enables wake-up alert interrupt HSYMTMRIE: Half Symbol Timer Interrupt Enable Disables half symbol timer interrupt (default) Enables half symbol timer interrupt SECIE: Security Request Interrupt Enable Disables security request interrupt (default) Enable security request interrupt RXIE: FIFO Reception Interrupt Enable Disables FIFO reception interrupt (default) Enables FIFO reception interrupt TXG2IE: GTS2 FIFO Transmission Interrupt Enable Disables GTS2 FIFO transmission interrupt (default) Enables GTS2 FIFO transmission interrupt TXG1IE: GTS1 FIFO Transmission Interrupt Enable Disables GTS1 FIFO transmission interrupt (default) Enables GTS1 FIFO transmission interrupt TXNIE: Normal FIFO Transmission Interrupt Enable Disables Normal FIFO transmission interrupt (default) Enables Normal FIFO transmission interrupt
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REGISTER 2-47:
R/W-0 Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
GPIO: GPIO PORT REGISTER (ADDRESS: 0x33)
R/W-0 R/W-0 GPIO5 R/W-0 GPIO4 R/W-0 GPIO3 R/W-0 GPIO2 R/W-0 GPIO1 R/W-0 GPIO0
Reserved: Maintain GPIO5: General Purpose GPIO5 GPIO4: General Purpose GPIO4 GPIO3: General Purpose GPIO3 GPIO2: General Purpose GPIO2 GPIO1: General Purpose GPIO1 GPIO0: General Purpose GPIO0
REGISTER 2-48:
R/W-0 Legend: Readable Value
TRISGPIO: GPIO DIRECTION REGISTER (ADDRESS: 0x34)
R/W-0 R/W-0 TRISGP5 R/W-0 TRISGP4 R/W-0 TRISGP3 R/W-0 TRISGP2 R/W-0 TRISGP1 R/W-0 TRISGP0 reserved Writable Unimplemented bit, read cleared unknown
Reserved: Maintain TRISGP5: General Purpose GPIO5 Direction Output Input (default) TRISGP4: General Purpose GPIO4 Direction Output Input (default) TRISGP3: General Purpose GPIO3 Direction Output Input (default) TRISGP2: General Purpose GPIO2 Direction Output Input (default) TRISGP1: General Purpose GPIO1 Direction Output Input (default) TRISGP0: General Purpose GPIO0 Direction Output Input (default)
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REGISTER 2-49:
SLPACK Legend: Readable Value Writable Unimplemented bit, read cleared unknown
SLPACK: SLEEP ACKNOWLEDGEMENT WAKE-UP COUNTER REGISTER (ADDRESS: 0x35)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKECNT2 R/W-0 WAKECNT1 R/W-0 WAKECNT0 WAKECNT5 WAKECNT4 WAKECNT3
WAKECNT6
SLPACK: Sleep Acknowledge Places MRF24J40 Sleep (automatically cleared hardware) WAKECNT<6:0>: Wake Count bits Main oscillator MHz) start-up timer counter bits. WAKECNT 9-bit value. WAKECNT<8:7> bits located RFCTL<4:3>. Units: Sleep clock (SLPCLK) period.(1) Default value: 0x00. Recommended value: 0x05F. Sleep Clock (SLPCLK) period depends Sleep Clock Selection (SLPCLKSEL) RFCON7<7:6> Sleep Clock Divisor (SLPCLKDIV) SLPCON1<4:0>.
Note
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REGISTER 2-50:
Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
RFCTL: MODE CONTROL REGISTER (ADDRESS: 0x36)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RFRST(2) R/W-0 R/W-0 WAKECNT8 WAKECNT7 RFTXMODE RFRXMODE
Reserved: Maintain WAKECNT<8:7>: Wake Count bits Main oscillator MHz) start-up timer counter bits. WAKECNT 9-bit value. WAKECNT<6:0> bits located SLPACK<6:0>. Units: Sleep clock (SLPCLK) period.(1) Default value: 0x00. Recommended value: 0x05F RFRST: State Machine Reset bit(2) Hold state machine Reset Normal operation state machine RFTXMODE: Forces Control State Machine transmit State(3) RFRXMODE: Forces Control State Machine receive State Sleep clock (SLPCLK) period depends Sleep clock selection (SLPCLKSEL) RFCON7<7:6> Sleep clock divisor (SLPCLKDIV) SLPCON1<4:0>. Perform Reset setting RFRST then RFRST Delay least after performing allow circuitry calibrate. Recommended sequence RFCTL 0x06 (reset mode) then RFCTL 0x02 (transmit mode).
Note
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REGISTER 2-51:
UPDEC Legend: Readable Value Writable Unimplemented bit, read cleared unknown
SECCR2: SECURITY CONTROL REGISTER (ADDRESS: 0x37)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
UPENC TXG2CIPHER2 TXG2CIPHER1 TXG2CIPHER0 TXG1CIPHER2 TXG1CIPHER1 TXG1CIPHER0
UPDEC: Upper Layer Security Decryption Mode Perform upper layer decryption using Normal FIFO. Automatically cleared when finished. UPENC: Upper Layer Security Encryption Mode Perform upper layer encryption using Normal FIFO. Automatically cleared when finished. TXG2CIPHER-<2:0>: GTS2 FIFO Security Suite Select bits AES-CBC-MAC-32 AES-CBC-MAC-64 AES-CBC-MAC-128 AES-CCM-32 AES-CCM-64 AES-CCM-128 AES-CTR None (default) TXG1CIPHER-<2:0>: GTS1 FIFO Security Suite Select bits AES-CBC-MAC-32 AES-CBC-MAC-64 AES-CBC-MAC-128 AES-CCM-32 AES-CCM-64 AES-CCM-128 AES-CTR None (default)
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REGISTER 2-52:
R/W-0 Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
BBREG0: BASEBAND REGISTER (ADDRESS: 0x38)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TURBO
Reserved: Maintain TURBO: Turbo Mode Enable Turbo mode (625 kbps) IEEE 802.15.4mode (250 kbps)
REGISTER 2-53:
R/W-0 Legend: Readable Value
BBREG1: BASEBAND REGISTER (ADDRESS: 0x39)
R/W-0 R/W-0 R/W-0 R/W-0 RXDECINV R/W-0 R/W-0 reserved Writable Unimplemented bit, read cleared unknown
R/W-0
Reserved: Maintain RXDECINV: Decode Inversion decode symbol sign inverted decode symbol sign inverted (default) Reserved: Maintain
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REGISTER 2-54:
R/W-0 Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
BBREG2: BASEBAND REGISTER (ADDRESS: 0x3A)
R/W-0 R/W-0 CCACSTH2 R/W-1 CCATCSH1 R/W-0 CCACSTH0 R/W-0 R/W-0
R/W-1
CCAMODE1 CCAMODE0 CCACSTH3
CCAMODE<1:0>: Clear Channel Assessment (CCA) Mode bits Mode Carrier sense with energy above threshold. shall report busy medium only upon detection signal with modulation spreading characteristics IEEE 802.15.4with energy above Energy Detection (ED) threshold. Mode Energy above threshold. shall report busy medium upon detecting energy above Energy Detection (ED) threshold. Mode Carrier sense only. shall report busy medium only upon detection signal with modulation spreading characteristics IEEE 802.15.4. This signal above below Energy Detection (ED) threshold (default). Reserved CCACSTH<3:0>: Clear Channel Assessment (CCA) Carrier Sense (CS) Threshold bits 1111 1110 Recommended value 1101 0010 (default) 0001 0000 Reserved: Maintain
REGISTER 2-55:
R/W-1
BBREG3: BASEBAND REGISTER (ADDRESS: 0x3B)
R/W-1 R/W-0 R/W-1 R/W-1 R/W-0 PREDETTH1 R/W-0 PREDETTH0 R/W-0
PREVALIDTH3 PREVALIDTH2 PREVALIDTH1 PREVALIDTH0 PREDETTH2
Legend: Readable Value
reserved Writable Unimplemented bit, read cleared unknown
PREVALIDTH<3:0>: Preamble Search Energy Valid Threshold bits 1101 IEEE 802.15.4(250 kbps) optimized value (default) 0011 Turbo mode (625 kbps) optimized value PREDETTH<2:0>: Preamble Search Energy Detection Threshold bits Default value: 0x4.
Reserved: Maintain
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REGISTER 2-56:
R/W-1 CSTH2 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
BBREG4: BASEBAND REGISTER (ADDRESS: 0x3C)
R/W-0 CSTH0 R/W-1 PRECNT2 R/W-1 PRECNT1 R/W-1 PRECNT0 R/W-0 R/W-0
R/W-0 CSTH1
CSTH<2:0>: Carrier Sense Threshold bits IEEE 802.15.4(250 kbps) optimized value (default) Turbo mode (625 kbps) optimized value PRECNT<2:0>: Preamble Counter Threshold bits Optimized value (default)
Reserved: Maintain
REGISTER 2-57:
Legend: Readable Value
BBREG6: BASEBAND REGISTER (ADDRESS: 0x3E)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RSSIRDY reserved Writable Unimplemented bit, read cleared unknown
RSSIMODE1 RSSIMODE2
RSSIMODE1: RSSI Mode Initiate RSSI calculation (bit automatically cleared hardware) RSSIMODE2: RSSI Mode Calculate RSSI each received packet. RSSI value stored RXFIFO RSSI calculation performed each received packet (default) Reserved: Maintain RSSIRDY: RSSI Ready Signal RSSIMODE1 RSSIMODE1 then RSSI calculation finished RSSI value ready RSSI calculation progress
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REGISTER 2-58:
R/W-0 CCAEDTH7 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
CCAEDTH: ENERGY DETECTION THRESHOLD REGISTER (ADDRESS: 0x3F)
R/W-0 CCAEDTH5 R/W-0 CCAEDTH4 R/W-0 CCAEDTH3 R/W-0 CCAEDTH2 R/W-0 CCAEDTH1 R/W-0 CCAEDTH0
R/W-0 CCAEDTH6
CCAEDTH<7:0>: Clear Channel Assessment (CCA) Energy Detection (ED) Mode bits in-band signal strength greater than threshold, channel busy. 8-bit value mapped power level according RSSI. Refer Section "Received Signal Strength Indicator (RSSI)/Energy Detection (ED)". Default value: 0x00. Recommended value: 0x60 (approximately dBm).
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2.15.4 LONG ADDRESS CONTROL REGISTERS DETAIL RFCON0: CONTROL REGISTER (ADDRESS: 0x200)
R/W-0 CHANNEL2 R/W-0 R/W-0 R/W-0 RFOPT3 R/W-0 RFOPT2 R/W-0 RFOPT1 R/W-0 RFOPT0 CHANNEL1 CHANNEL0
REGISTER 2-59:
R/W-0 CHANNEL3 Legend: Readable Value
Writable
Unimplemented bit, read cleared unknown
CHANNEL<3:0>: Channel Number bits 0000 Channel (2405 MHz) (default) 0001 Channel (2410 MHz) 0010 Channel (2415 MHz) 1111 Channel (2480 MHz) RFOPT<3:0>: Optimize Control bits Default value: 0x0. Recommended value: 0x3.
REGISTER 2-60:
R/W-0 VCOOPT7 Legend: Readable Value
RFCON1: CONTROL REGISTER (ADDRESS: 0x201)
R/W-0 R/W-0 VCOOPT5 R/W-0 VCOOPT4 R/W-0 VCOOPT3 R/W-0 VCOOPT2 R/W-0 VCOOPT1 R/W-0 VCOOPT0
VCOOPT6
Writable
Unimplemented bit, read cleared unknown
VCOOPT<7:0>: Optimize Control bits Default value: 0x0. Recommended value: 0x2.
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REGISTER 2-61:
R/W-0 PLLEN Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
RFCON2: CONTROL REGISTER (ADDRESS: 0x202)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PLLEN: Enable bit(1) Enabled Disabled (default) Reserved: Maintain must enabled reception transmission.
Note
REGISTER 2-62:
R/W-0 TXPWRL1 Legend: Readable Value
RFCON3: CONTROL REGISTER (ADDRESS: 0x203)
R/W-0 R/W-0 TXPWRS2 R/W-0 TXPWRS1 R/W-0 TXPWRS0 R/W-0 R/W-0 R/W-0
TXPWRL0
Writable
Unimplemented bit, read cleared unknown
TXPWRL<1:0>: Large Scale Control Power bits TXPWRS<2:0>: Small Scale Control Power bits -6.3 -4.9 -3.7 -2.8 -1.9 -1.2 -0.5 Reserved: Maintain
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REGISTER 2-63:
R/W-0 BATTH3(1) Legend: Readable Value reserved Writable Unimplemented bit, read cleared unknown
RFCON5: CONTROL REGISTER (ADDRESS: 0x205)
R/W-0 R/W-0 BATTH1
R/W-0 BATTH0
R/W-0
R/W-0
R/W-0
R/W-0
BATTH2
BATTH<3:0>: Battery Low-Voltage Threshold bits(1) 1110 3.5V 1101 3.3V 1100 3.2V 1011 3.1V 1010 2.8V 1001 2.7V 1000 2.6V 0111 2.5V 0110 Undefined 0000 Undefined Reserved: Maintain Battery Low-Voltage Indicator (BATIND) located RXSR (0x30<5>) register Battery Monitor Enable (BATEN) located RFCON6 (0x206<3>) register.
Note
REGISTER 2-64:
R/W-0 TXFIL Legend: Readable Value
RFCON6: CONTROL REGISTER (ADDRESS: 0x206)
R/W-0 R/W-0 20MRECVR R/W-0 BATEN(1) R/W-0 R/W-0 R/W-0 reserved Writable Unimplemented bit, read cleared unknown
R/W-0
TXFIL: Filter Control Default value: `0'. Recommended value: `1'. Reserved: Maintain 20MRECVR: Clock Recovery Control bits Recovery from Sleep control. Less than (recommended) Less than (default) BATEN: Battery Monitor Enable bit(1) Enabled Disabled (default) Reserved: Maintain Battery Low-Voltage Threshold (BATTH) bits located RFCON5 (0x205<7:4>) register Battery Low-Voltage Indicator (BATIND) located RXSR (0x30<5>) register.
Note
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REGISTER 2-65:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
RFCON7: CONTROL REGISTER (ADDRESS: 0x207)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
SLPCLKSEL1 SLPCLKSEL0
SLPCLKSEL<1:0>: Sleep Clock Selection bits internal oscillator external crystal oscillator Reserved: Maintain
REGISTER 2-66:
R/W-0 Legend: Readable Value
RFCON8: CONTROL REGISTER (ADDRESS: 0x208)
R/W-0 R/W-0 RFVCO R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
Writable
Unimplemented bit, read cleared unknown
Reserved: Maintain RFVCO: Control Default value: `0'. Recommended value: `1'. Reserved: Maintain
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REGISTER 2-67:
SLPCAL7 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
SLPCAL0: SLEEP CALIBRATION REGISTER (ADDRESS: 0x209)
SLPCAL5 SLPCAL4 SLPCAL3 SLPCAL2 SLPCAL1 SLPCAL0
SLPCAL6
SLPCAL<7:0>: Sleep Calibration Counter bits 20-bit counter calibrate Sleep Clock (SLPCLK) period. counter contains count SLPCLK periods. SLPCLK period depends Sleep Clock Selection (SLPCLKSEL), RFCON7<7:6> Sleep Clock Divisor (SLPCLKDIV) SLPCON1<4:0> bits. Units: tick ns).
REGISTER 2-68:
SLPCAL15 Legend: Readable Value
SLPCAL1: SLEEP CALIBRATION REGISTER (ADDRESS: 0x20A)
SLPCAL13 SLPCAL12 SLPCAL11 SLPCAL10 SLPCAL9 SLPCAL8
SLPCAL14
Writable
Unimplemented bit, read cleared unknown
SLPCAL<15:8>: Sleep Calibration Counter bits 20-bit counter calibrate Sleep Clock (SLPCLK) period. counter contains count SLPCLK periods. SLPCLK period depends Sleep Clock Selection (SLPCLKSEL), RFCON7<7:6> Sleep Clock Divisor (SLPCLKDIV) SLPCON1<4:0> bits. Units: tick ns).
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REGISTER 2-69:
SLPCALRDY Legend: Readable Value Writable Unimplemented bit, read cleared unknown
SLPCAL2: SLEEP CALIBRATION REGISTER (ADDRESS: 0x20B)
R/W-0 R/W-0 SLPCALEN SLPCAL19 SLPCAL18 SLPCAL17 SLPCAL16
SLPCALRDY: Sleep Calibration Ready Sleep calibration count complete Reserved: Maintain SLPCALEN: Sleep Calibration Enable Starts Sleep calibration counter. Automatically cleared hardware SLPCAL<19:16>: Sleep Calibration Counter bits 20-bit counter calibrate Sleep Clock (SLPCLK) period. counter contains count SLPCLK periods. SLPCLK period depends Sleep Clock Selection (SLPCLKSEL), RFCON7<7:6> Sleep Clock Divisor (SLPCLKDIV) SLPCON1<4:0> bits. Units: tick ns).
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MRF24J40
REGISTER 2-70:
RFSTATE2 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
RFSTATE: STATE REGISTER (ADDRESS: 0x20F)
RFSTATE0
RFSTATE1
RFSTATE<2:0>: State Machine bits RTSEL2 RTSEL1 CALVCO SLEEP CALFIL RESET Reserved: Maintain
REGISTER 2-71:
RSSI7(1) Legend: Readable Value Note
RSSI: AVERAGED RSSI VALUE REGISTER (ADDRESS: 0x210)
RSSI5(1) RSSI4(1) RSSI3(1) RSSI2(1) RSSI1(1) RSSI0(1)
RSSI6(1)
Writable
Unimplemented bit, read cleared unknown
RSSI<7:0>: Averaged RSSI Value bits(1) number RSSI samples averaged, RSSINUMx (0x25<5:4>) bits.
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MRF24J40
REGISTER 2-72:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
SLPCON0: SLEEP CLOCK CONTROL REGISTER (ADDRESS: 0x211)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 INTEDGE
R/W-0 SLPCLKEN
Reserved: Maintain INTEDGE: Interrupt Edge Polarity bit(1) Rising edge Falling edge (default) SLPCLKEN: Sleep Clock Enable Disabled Enabled (default) Ensure that interrupt polarity matches interrupt polarity host microcontroller.
Note
REGISTER 2-73:
R/W-0 Legend: Readable Value
SLPCON1: SLEEP CLOCK CONTROL REGISTER (ADDRESS: 0x220)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 reserved Writable Unimplemented bit, read cleared unknown CLKOUTEN SLPCLKDIV4 SLPCLKDIV3 SLPCLKDIV2 SLPCLKDIV1 SLPCLKDIV0
R/W-0
Reserved: Maintain CLKOUTEN: CLKOUT Enable CLKOUT feature been discontinued. recommended that disabled. Disable (recommended) Enable (default) SLPCLKDIV<4:0>: Sleep Clock Divisor bits Sleep clock divided where SLPCLKDIV.(1) Default value: 0x00. Sleep Clock Selection, SLPCLKSEL (0x207<7:6), internal oscillator (100 kHz), SLPCLKDIV minimum value 0x01.
Note
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MRF24J40
REGISTER 2-74:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
WAKETIMEL: WAKE-UP TIME MATCH VALUE REGISTER (ADDRESS: 0x222)
R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 R/W-0
WAKETIME7(1) WAKETIME6(1) WAKETIME5(1) WAKETIME4(1) WAKETIME3(1) WAKETIME2(1) WAKETIME1(1) WAKETIME0(1)
WAKETIME<7:0>: Wake Time Match Value bits(1) WAKETIME 11-bit value that compared with Main Counter (MAINCNT) signal time enable (wake-up) main oscillator when MRF24J40 using Sleep mode timers. Default value: 0x00A. Minimum value: 0x001. Rule: WAKETIME WAKECNT.
Note
REGISTER 2-75:
R/W-0 Legend: Readable Value
WAKETIMEH: WAKE-UP TIME MATCH VALUE HIGH REGISTER (ADDRESS: 0x223)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 reserved Writable Unimplemented bit, read cleared unknown WAKETIME10(1) WAKETIME9(1) WAKETIME8(1)
R/W-0
Reserved: Maintain WAKETIME<10:8>: Wake-up Time Counted SLPCLK bits(1) WAKETIME 11-bit value that compared with Main Counter (MAINCNT) signal time enable (wake-up) main oscillator when MRF24J40 using Sleep mode timers. Default value: 0x00A. Minimum value: 0x001. Rule: WAKETIME WAKECNT.
Note
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MRF24J40
REGISTER 2-76:
R/W-0 REMCNT7 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
REMCNTL: REMAIN COUNTER REGISTER (ADDRESS: 0x224)
R/W-0 R/W-0 REMCNT5 R/W-0 REMCNT4 R/W-0 REMCNT3 R/W-0 REMCNT2 R/W-0 REMCNT1 R/W-0 REMCNT0
REMCNT6
REMCNT<7:0>: Remain Counter bits Remain counter 16-bit counter. Together with main counter times events: Beacon Interval (BI) inactive period beacon-enabled devices Sleep interval nonbeacon-enabled devices. Units: tick ns).
REGISTER 2-77:
R/W-0 REMCNT15 Legend: Readable Value
REMCNTH: REMAIN COUNTER HIGH REGISTER (ADDRESS: 0x225)
R/W-0 REMCNT13 R/W-0 REMCNT12 R/W-0 REMCNT11 R/W-0 REMCNT10 R/W-0 REMCNT9 R/W-0 REMCNT8
R/W-0 REMCNT14
Writable
Unimplemented bit, read cleared unknown
REMCNT<15:8>: Remain Counter bits Remain counter 16-bit counter. Together with main counter times events: Beacon Interval (BI) inactive period beacon-enabled devices Sleep interval nonbeacon-enabled devices. Units: tick ns).
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MRF24J40
REGISTER 2-78:
R/W-0 MAINCNT7 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
MAINCNT0: MAIN COUNTER REGISTER (ADDRESS: 0x226)
R/W-0 MAINCNT5 R/W-0 MAINCNT4 R/W-0 MAINCNT3 R/W-0 MAINCNT2 R/W-0 MAINCNT1 R/W-0 MAINCNT0
R/W-0 MAINCNT6
MAINCNT<7:0>: Main Counter bits Main counter 26-bit counter. Together with remain counter times events: Beacon Interval (BI) inactive period beacon-enabled devices Sleep interval nonbeacon-enabled devices. Units: SLPCLK.(1) Sleep Clock (SLPCLK) period depends Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits.
Note
REGISTER 2-79:
R/W-0 Legend: Readable Value
MAINCNT1: MAIN COUNTER REGISTER (ADDRESS: 0x227)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MAINCNT9 R/W-0 MAINCNT8
R/W-0
MAINCNT15 MAINCNT14 MAINCNT13 MAINCNT12 MAINCNT11 MAINCNT10
Writable
Unimplemented bit, read cleared unknown
MAINCNT<15:8>: Main Counter bits Main counter 26-bit counter. Together with remain counter times events: Beacon Interval (BI) inactive period beacon-enabled devices Sleep interval nonbeacon-enabled devices. Units: SLPCLK.(1) Sleep Clock (SLPCLK) period depends Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits.
Note
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MRF24J40
REGISTER 2-80:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
MAINCNT2: MAIN COUNTER REGISTER (ADDRESS: 0x228)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
MAINCNT23 MAINCNT22 MAINCNT21 MAINCNT20 MAINCNT19 MAINCNT18 MAINCNT17 MAINCNT16
MAINCNT<23:16>: Main Counter bits Main counter 26-bit counter. Together with remain counter times events: Beacon Interval (BI) inactive period beacon-enabled devices Sleep interval nonbeacon-enabled devices. Units: SLPCLK.(1) Sleep Clock (SLPCLK) period depends Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits.
Note
REGISTER 2-81:
STARTCNT Legend: Readable Value
MAINCNT3: MAIN COUNTER REGISTER (ADDRESS: 0x229)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MAINCNT25 R/W-0 MAINCNT24
R/W-0
Writable
Unimplemented bit, read cleared unknown
STARTCNT: Start Sleep Mode Counters bits Trigger Sleep mode Nonbeacon Enable mode Slotted automatically clears `0'. Reserved: Maintain MAINCNT<25:24>: Main Counter bits Main counter 26-bit counter. Together with remain counter times events: Beacon Interval (BI) inactive period beacon-enabled devices Sleep interval nonbeacon-enabled devices. Units: SLPCLK.(1) Sleep Clock (SLPCLK) period depends Sleep Clock Selection (SLPCLKSEL) RFCON<7:6> Sleep Clock Divisor (SLPCLKDIV) CLKCON<4:0> bits.
Note
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MRF24J40
REGISTER 2-82:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
TESTMODE: TEST MODE REGISTER (ADDRESS: 0x22F)
R/W-0 R/W-0 RSSIWAIT1 R/W-1 R/W-0 R/W-0 R/W-0 RSSIWAIT0 TESTMODE2 TESTMODE1 TESTMODE0
R/W-0
Reserved: Maintain RSSIWAIT<1:0>: RSSI State Machine Parameter bits Optimized value (default) TESTMODE<2:0>: Test Mode bits GPIO0, GPIO1 GPIO2 configured control external and/or LNA(1) Single Tone Test mode Normal operation (default) Refer Section "External PA/LNA Control" more information.
Note
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MRF24J40
REGISTER 2-83:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
ASSOEADR0: ASSOCIATED COORDINATOR EXTENDED ADDRESS REGISTER (ADDRESS: 0x230)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
ASSOEADR7 ASSOEADR6 ASSOEADR5 ASSOEADR4 ASSOEADR3 ASSOEADR2 ASSOEADR1 ASSOEADR0
ASSOEADR<7:0>: 64-Bit Extended Address Associated Coordinator bits
REGISTER 2-84:
R/W-0 Legend: Readable Value
ASSOEADR1: ASSOCIATED COORDINATOR EXTENDED ADDRESS REGISTER (ADDRESS: 0x231)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
ASSOEADR15 ASSOEADR14 ASSOEADR13 ASSOEADR12 ASSOEADR11 ASSOEADR10 ASSOEADR9 ASSOEADR8
Writable
Unimplemented bit, read cleared unknown
ASSOEADR<15:8>: 64-Bit Extended Address Associated Coordinator bits
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MRF24J40
REGISTER 2-85:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
ASSOEADR2: ASSOCIATED COORDINATOR EXTENDED ADDRESS REGISTER (ADDRESS: 0x232)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ASSOEADR23 ASSOEADR22 ASSOEADR21 ASSOEADR20 ASSOEADR19 ASSOEADR18 ASSOEADR17 ASSOEADR16
ASSOEADR<23:16>: 64-Bit Extended Address Associated Coordinator bits
REGISTER 2-86:
R/W-0 Legend: Readable Value
ASSOEADR3: ASSOCIATED COORDINATOR EXTENDED ADDRESS REGISTER (ADDRESS: 0x233)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
ASSOEADR31 ASSOEADR30 ASSOEADR29 ASSOEADR28 ASSOEADR27 ASSOEADR26 ASSOEADR25 ASSOEADR24
Writable
Unimplemented bit, read cleared unknown
ASSOEADR<31:24>: 64-Bit Extended Address Associated Coordinator bits
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REGISTER 2-87:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
ASSOEADR4: ASSOCIATED COORDINATOR EXTENDED ADDRESS REGISTER (ADDRESS: 0x234)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
ASSOEADR39 ASSOEADR38 ASSOEADR37 ASSOEADR36 ASSOEADR35 ASSOEADR34 ASSOEADR33 ASSOEADR32
ASSOEADR<39:32>: 64-Bit Extended Address Associated Coordinator bits
REGISTER 2-88:
R/W-0 Legend: Readable Value
ASSOEADR5: ASSOCIATED COORDINATOR EXTENDED ADDRESS REGISTER (ADDRESS: 0x235)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
ASSOEADR47 ASSOEADR46 ASSOEADR45 ASSOEADR44 ASSOEADR43 ASSOEADR42 ASSOEADR41 ASSOEADR40
Writable
Unimplemented bit, read cleared unknown
ASSOEADR<47:40>: 64-Bit Extended Address Associated Coordinator bits
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REGISTER 2-89:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
ASSOEADR6: ASSOCIATED COORDINATOR EXTENDED ADDRESS REGISTER (ADDRESS: 0x236)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
ASSOEADR55 ASSOEADR54 ASSOEADR53 ASSOEADR52 ASSOEADR51 ASSOEADR50 ASSOEADR49 ASSOEADR48
ASSOEADR<55:48>: 64-Bit Extended Address Associated Coordinator bits
REGISTER 2-90:
R/W-0 Legend: Readable Value
ASSOEADR7: ASSOCIATED COORDINATOR EXTENDED ADDRESS REGISTER (ADDRESS: 0x237)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
ASSOEADR63 ASSOEADR62 ASSOEADR61 ASSOEADR60 ASSOEADR59 ASSOEADR58 ASSOEADR57 ASSOEADR56
Writable
Unimplemented bit, read cleared unknown
ASSOEADR<63:56>: 64-Bit Extended Address Associated Coordinator bits
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MRF24J40
REGISTER 2-91:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
ASSOSADR0: ASSOCIATED COORDINATOR SHORT ADDRESS REGISTER (ADDRESS: 0x238)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
ASSOSADR7 ASSOSADR6 ASSOSADR5 ASSOSADR4 ASSOSADR3 ASSOSADR2 ASSOSADR1 ASSOSADR0
ASSOSADR<7:0>: 16-Bit Short Address Associated Coordinator bits
REGISTER 2-92:
R/W-0 Legend: Readable Value
ASSOSADR1: ASSOCIATED COORDINATOR SHORT ADDRESS REGISTER (ADDRESS: 0x239)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
ASSOSADR15 ASSOSADR14 ASSOSADR13 ASSOSADR12 ASSOSADR11 ASSOSADR10 ASSOSADR9 ASSOSADR8
Writable
Unimplemented bit, read cleared unknown
ASSOSADR<15:8>: 16-Bit Short Address Associated Coordinator bits
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REGISTER 2-93:
R/W-0 UPNONCE7 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
UPNONCE0: UPPER NONCE SECURITY REGISTER (ADDRESS: 0x240)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE2 R/W-0 R/W-0 UPNONCE1 UPNONCE0
UPNONCE6 UPNONCE5 UPNONCE4 UPNONCE3
UPNONCE<7:0>: Upper Nonce bits 13-byte nonce value used security.
REGISTER 2-94:
R/W-0 Legend: Readable Value
UPNONCE1: UPPER NONCE SECURITY REGISTER (ADDRESS: 0x241)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE9 R/W-0 UPNONCE8
R/W-0
UPNONCE15 UPNONCE14 UPNONCE13 UPNONCE12 UPNONCE11 UPNONCE10
Writable
Unimplemented bit, read cleared unknown
UPNONCE<15:8>: Upper Nonce bits 13-byte nonce value used security.
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REGISTER 2-95:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
UPNONCE2: UPPER NONCE SECURITY REGISTER (ADDRESS: 0x242)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
UPNONCE23 UPNONCE22 UPNONCE21 UPNONCE20 UPNONCE19 UPNONCE18 UPNONCE17 UPNONCE16
UPNONCE<23:16>: Upper Nonce bits 13-byte nonce value used security.
REGISTER 2-96:
R/W-0 Legend: Readable Value
UPNONCE3: UPPER NONCE SECURITY REGISTER (ADDRESS: 0x243)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
UPNONCE31 UPNONCE30 UPNONCE29 UPNONCE28 UPNONCE27 UPNONCE26 UPNONCE25 UPNONCE24
Writable
Unimplemented bit, read cleared unknown
UPNONCE<31:24>: Upper Nonce bits 13-byte nonce value used security.
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REGISTER 2-97:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
UPNONCE4: UPPER NONCE SECURITY REGISTER (ADDRESS: 0x244)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
UPNONCE39 UPNONCE38 UPNONCE37 UPNONCE36 UPNONCE35 UPNONCE34 UPNONCE33 UPNONCE32
UPNONCE<39:32>: Upper Nonce bits 13-byte nonce value used security.
REGISTER 2-98:
R/W-0 Legend: Readable Value
UPNONCE5: UPPER NONCE SECURITY REGISTER (ADDRESS: 0x245)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
UPNONCE47 UPNONCE46 UPNONCE45 UPNONCE44 UPNONCE43 UPNONCE42 UPNONCE41 UPNONCE40
Writable
Unimplemented bit, read cleared unknown
UPNONCE<47:40>: Upper Nonce bits 13-byte nonce value used security.
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REGISTER 2-99:
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown
UPNONCE6: UPPER NONCE SECURITY REGISTER (ADDRESS: 0x246)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
R/W-0
UPNONCE55 UPNONCE54 UPNONCE53 UPNONCE52 UPNONCE51 UPNONCE50 UPNONCE49 UPNONCE48
UPNONCE<55:48>: Upper Nonce bits 13-byte nonce value used security.
REGISTER 2-100: UPNONCE7: UPPER NONCE SECURITY REGISTER (ADDRESS: 0x247)
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE63 UPNONCE62 UPNONCE61 UPNONCE60 UPNONCE59 UPNONCE58 UPNONCE57 UPNONCE56
UPNONCE<63:56>: Upper Nonce bits 13-byte nonce value used security.
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REGISTER 2-101: UPNONCE8: UPPER NONCE SECURITY REGISTER (ADDRESS: 0x248)
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE71 UPNONCE70 UPNONCE69 UPNONCE68 UPNONCE67 UPNONCE66 UPNONCE65 UPNONCE64
UPNONCE<71:64>: Upper Nonce bits 13-byte nonce value used security.
REGISTER 2-102: UPNONCE9: UPPER NONCE SECURITY REGISTER (ADDRESS: 0x249)
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE79 UPNONCE78 UPNONCE77 UPNONCE76 UPNONCE75 UPNONCE74 UPNONCE73 UPNONCE72
UPNONCE<79:72>: Upper Nonce bits 13-byte nonce value used security.
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REGISTER 2-103: UPNONCE10: UPPER NONCE SECURITY REGISTER (ADDRESS: 0x24A)
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE87 UPNONCE86 UPNONCE85 UPNONCE84 UPNONCE83 UPNONCE82 UPNONCE81 UPNONCE80
UPNONCE<87:80>: Upper Nonce bits 13-byte nonce value used security.
REGISTER 2-104: UPNONCE11: UPPER NONCE SECURITY REGISTER (ADDRESS: 0x24B)
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE95 UPNONCE94 UPNONCE93 UPNONCE92 UPNONCE91 UPNONCE90 UPNONCE89 UPNONCE88
UPNONCE<95:88>: Upper Nonce bits 13-byte nonce value used security.
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REGISTER 2-105: UPNONCE12: UPPER NONCE SECURITY REGISTER (ADDRESS: 0x24C)
R/W-0 Legend: Readable Value Writable Unimplemented bit, read cleared unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 UPNONCE103 UPNONCE102 UPNONCE101 UPNONCE100 UPNONCE99 UPNONCE98 UPNONCE97 UPNONCE96
UPNONCE<103:96>: Upper Nonce bits 13-byte nonce value used security.
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NOTES:
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MRF24J40
FUNCTIONAL DESCRIPTION
Reset
MRF24J40 four Reset types: Power-on Reset MRF24J40 built-in Power-on Reset circuitry that will automatically reset control registers when power applied. recommended delay after Reset before accessing MRF24J40 allow circuitry start stabilize. RESET MRF24J40 reset host microcontroller asserting RESET low. control registers will reset. MRF24J40 will released from Reset approximately after RESET released. RESET internal weak pull-up resistor. recommended delay after Reset before accessing MRF24J40 allow circuitry start stabilize.
Software Reset Software Reset performed host microcontroller. power management circuitry reset setting RSTPWR (0x2A<2>) `1'. control registers retain their values. baseband circuitry reset setting RSTBB (0x2A<1>) `1'. control registers retain their values. circuitry reset setting RSTMAC (0x2A<0>) `1'. control registers will reset. Resets performed individually together. bit(s) will automatically cleared hardware. delay necessary after Software Reset. State Machine Reset Perform State Machine Reset setting RFRST (RFCTL 0x36<2>) then clearing `0'. Delay least after performing allow circuitry calibrate. control registers retain their values. Note: state machine should Reset after frequency channel been changed (RFCON0 0x200).
TABLE 3-1:
Addr. 0x36 Name RFCTL
REGISTERS ASSOCIATED WITH RESET
WAKECNT8 WAKECNT7 RSTPWR RFRST RSTBB RFTXMODE RSTMAC RFRXMODE
0x2A SOFTRST
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Initialization
Certain control register values must initialized basic operations. These values differ from Power-on Reset values provide improved operational parameters. These settings normally made once after Reset. After initialization, MRF24J40 features configured application. steps initialization shown Example 3-1.
EXAMPLE 3-1:
INITIALIZING MRF24J40
Example steps initialize MRF24J40: SOFTRST (0x2A) 0x07 Perform software Reset. bits will automatically cleared hardware. PACON2 (0x18) 0x98 Initialize FIFOEN TXONTS 0x6. TXSTBL (0x2E) 0x95 Initialize RFSTBL 0x9. RFCON0 (0x200) 0x03 Initialize RFOPT 0x03. RFCON1 (0x201) 0x01 Initialize VCOOPT 0x02. RFCON2 (0x202) 0x80 Enable (PLLEN RFCON6 (0x206) 0x90 Initialize TXFIL 20MRECVR RFCON7 (0x207) 0x80 Initialize SLPCLKSEL (100 Internal oscillator). RFCON8 (0x208) 0x10 Initialize RFVCO SLPCON1 (0x220) 0x21 Initialize CLKOUTEN SLPCLKDIV 0x01.
Configuration nonbeacon-enabled devices (see Section "Beacon-Enabled Nonbeacon-Enabled Networks"): BBREG2 (0x3A) 0x80 mode CCAEDTH 0x60 threshold. BBREG6 (0x3E) 0x40 appended RSSI value RXFIFO. Enable interrupts Section "Interrupts". channel Section "Channel Selection". Maintain 0x200<3:0> 0x03 transmitter power "REGISTER 2-62: CONTROL REGISTER (ADDRESS: 0x203)". RFCTL (0x36) 0x04 Reset state machine. RFCTL (0x36) 0x00. Delay least
Note:
TABLE 3-2:
Addr. Name 0x18 PACON2 0x2A SOFTRST 0x2E TXSTBL 0x201 RFCON1 0x202 RFCON2 0x206 RFCON6 0x207 RFCON7 0x208 RFCON8 0x220 SLPCON1
REGISTERS ASSOCIATED WITH INITIALIZATION
FIFOEN RFSTBL3 VCOOPT7 PLLEN TXFIL RFSTBL2 VCOOPT6 TXONTS3 RFSTBL1 VCOOPT5 TXONTS2 RFSTBL0 VCOOPT4 20MRECVR RFVCO TXONTS1 MSIFS3 VCOOPT3 BATEN TXONTS0 RSTPWR MSIFS2 VCOOPT2 TXONT8 RSTBB MSIFS1 VCOOPT1 TXONT7 RSTMAC MSIFS0 VCOOPT0
SLPCLKSEL1 SLPSCKSEL0
CLKOUTEN SLPCLKDIV4 SLPCLKDIV3 SLPCLKDIV2 SLPCLKDIV1 SLPCLKDIV0
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MRF24J40
Interrupts
MRF24J40 interrupt (INT) that signals eight interrupt events host microcontroller. interrupt structure shown Figure 3-1. Interrupts enabled INTCON (0x32) register. Interrupt flags located INTSTAT (0x31) register. INTSTAT register clears-to-zero upon read. Therefore, host microcontroller should read store INTSTAT register check bits determine which interrupt occurred. will continue signal interrupt until INTSTAT register read. edge polarity configured INTEDGE SLPCON0 (0x211<1>) register. Note INTEDGE polarity defaults Falling Edge. Ensure that interrupt polarity matches interrupt polarity host microcontroller. will remain high low, depending INTEDGE polarity setting, until INTSTAT register read.
FIGURE 3-1:
MRF24J40 INTERRUPT LOGIC
INTSTAT.SLPIF INTCON.SLPIE
INTSTAT.WAKEIF INTCON.WAKEIE
INTSTAT.HSYMTMRIF INTCON.HSYMTMRIE SLPCON0.INTEDGE INTSTAT.SECIF INTCON.SECIE INTSTAT.RXIF INTCON.RXIE
INTSTAT.TXG2IF INTCON.TXG2IE
INTSTAT.TXG1IF INTCON.TXG1IE
INTSTAT.TXNIF INTCON.TXNIE
TABLE 3-3:
Addr. 0x31 0x32 Name INTSTAT INTCON
REGISTERS ASSOCIATED WITH INTERRUPTS
SLPIF SLPIE SECIF SECIE RXIF RXIE TXG2IF TXG2IE TXG1IF TXG1IE INTEDGE TXNIF TXNIE SLPCKEN WAKEIF HSYMTMRIF WAKEIE HSYMTMRIE
0x211 SLPCON0
2010 Microchip Technology Inc.
DS39776C-page
MRF24J40
Channel Selection
TABLE 3-4:
MRF24J40 capable selecting sixteen channel frequencies band. desired channel selected configuring CHANNEL bits RFCON0 (0x200<7:4>) register. Table RFCON0 register setting channel number frequency. Note: Perform State Machine Reset (see Section "Reset") after channel frequency change. Then, delay least after State Machine Reset, allow circuitry calibrate.
CHANNEL SELECTION RFCON0 (0x200) REGISTER SETTING
Frequency 2.405 2.410 2.415 2.420 2.425 2.430 2.435 2.440 2.445 2.450 2.455 2.460 2.465 2.470 2.475 2.480 Value 0x03 0x13 0x23 0x33 0x43 0x53 0x63 0x73 0x83 0x93 0xA3 0xB3 0xC3 0xD3 0xE3 0xF3
Channel Number
TABLE 3-5:
Addr. Name 0x36 RFCTL 0x200 RFCON0
REGISTERS ASSOCIATED WITH CHANNEL SELECTION
RFRST RFTXMODE RFRXMODE WAKECNT8 WAKECNT7 RFOPT3
CHANNEL3 CHANNEL2 CHANNEL1 CHANNEL0
RFOPT2 RFOPT1 RFOPT0
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2010 Microchip Technology Inc.
MRF24J40
Clear Channel Assessment (CCA)
3.5.3
signal indication layer from layer whether medium busy idle. MRF24J40 provides three methods performing CCA. Refer IEEE 802.15.4-2003 Standard, Section 6.7.9 "CCA".
MODE CARRIER SENSE WITH ENERGY ABOVE THRESHOLD
reports busy medium only upon detection signal with modulation spreading characteristics IEEE 802.15.4 with energy above threshold. Program CCAMODE 0x3A<7:6> value, `11'. Program CCACSTH 0x3A<5:2> with carrier sense threshold. Program CCAEDTH 0x3F<7:0> with threshold (RSSI value). 8-bit CCAEDTH threshold mapped power level according RSSI. Refer Section "Received Signal Strength Indicator (RSSI)/Energy Detection (ED)".
3.5.1
MODE ENERGY ABOVE THRESHOLD
reports busy medium upon detecting energy above Energy Detection (ED) threshold. Program CCAMODE 0x3A<7:6> value, `10'. Program CCAEDTH 0x3F<7:0> with threshold value (RSSI value). 8-bit CCAEDTH threshold mapped power level according RSSI. Refer Section "Received Signal Strength Indicator (RSSI)/Energy Detection (ED)".
3.5.2
MODE CARRIER SENSE ONLY
reports busy medium only upon detection signal with modulation spreading characteristics IEEE 802.15.4. This signal above threshold. Program CCAMODE 0x3A<7:6> value, `01'. Program CCACSTH 0x3A<5:2> with carrier sense threshold (units).
TABLE 3-6:
Addr. Name 0x3A BBREG2
REGISTERS ASSOCIATED WITH
CCAMODE1 CCAMODE0 CCACSTH3 CCACSTH2 CCACSTH1 CCACSTH0
0x3F CCAEDTH CCAEDTH7 CCAEDTH6 CCAEDTH5 CCAEDTH4 CCAEDTH3 CCAEDTH2 CCAEDTH1 CCAEDTH0
2010 Microchip Technology Inc.
DS39776C-page
MRF24J40
Received Signal Strength Indicator (RSSI)/Energy Detection (ED)
3.6.1 RSSI FIRMWARE REQUEST (RSSI MODE1)
this mode, host microcontroller sends request calculate RSSI, then waits until done then reads RSSI value. steps are: RSSIMODE1 0x3E<7> Initiate RSSI calculation. Wait until RSSIRDY 0x3E<0> RSSI calculation complete. Read RSSI 0x210<7:0> RSSI register contains averaged RSSI received power level symbol periods.
RSSI/ED estimate received signal power within bandwidth IEEE 802.15.4 channel. RSSI value 8-bit value ranging from 0-255. mapping between RSSI values with received power level shown Figure shown tabular form Table 3-8. number symbols average changed programming RSSINUM (TXBCON1 0x25<5:4>) bits. programmer obtain RSSI/ED value methods.
3.6.2
APPENDED RSSI RECEIVED PACKET (RSSI MODE
RSSI value appended each successfully received packet. enable RSSI Mode RSSIMODE2 (0x3E<6>). RSSI value will appended RXFIFO shown Figure 3-2.
FIGURE 3-2:
Octet Frame Length
PACKET FORMAT FIFO
Octets Header Octets Payload Octets Octet Octet RSSI
TABLE 3-7:
Addr. Name 0x25 TXBCON1 0x3E BBREG6 0x210 RSSI
REGISTERS ASSOCIATED WITH RSSI/ED
TXBMSK RSSI7 WU/BCN RSSI6 RSSI3 RSSI2 RSSI1 RSSIRDY RSSI0 RSSINUM1 RSSINUM0 RSSI5 RSSI4
RSSIMODE1 RSSIMODE2
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MRF24J40
FIGURE 3-3: RSSI RECEIVED POWER (dBm)
RSSI
-120 -100 Received Power (dBm)
2010 Microchip Technology Inc.
DS39776C-page
MRF24J40
RSSI versus received power (dB) shown tabular form Table 3-8.
TABLE 3-8:
RSSI RECEIVED POWER (dB) (CONTINUED)
RSSI Value (hex) 0x8F 0x94 0x99 0x9F 0xA5 0xAA 0xB0 0xB7 0xBC 0xC1 0xC6 0xCB 0xCF 0xD4 0xD8 0xDD 0xE1 0xE4 0xE9 0xEF 0xF5 0xFA 0xFD 0xFE 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF RSSI Value (dec)
TABLE 3-8:
RSSI RECEIVED POWER (dB)
RSSI Value (hex) 0x0D 0x12 0x17 0x1B 0x20 0x25 0x2B 0x30 0x35 0x3A 0x3F 0x44 0x49 0x4E 0x53 0x59 0x5F 0x64 0x6B 0x6F 0x75 0x79 0x7D 0x81 0x85 0x8A RSSI Value (dec)
Received Power (dBm)
Received Power (dBm) -100
DS39776C-page
2010 Microchip Technology Inc.
MRF24J40
Link Quality Indication (LQI)
Link Quality Indication (LQI) characterization strength quality received packet. Several metrics, example, RSSI, Signal Noise Ratio (SNR), RSSI combined with SNR, etc., used measuring link quality. Using RSSI alone best estimate quality link. received RSSI value will very high value packet received with greater signal strength even interferer present channel. Hence, better approximation link quality, MRF24J40 reports correlation degree between spreading sequences incoming chips during reception packet. This correlation value directly mapped range 0-255 (256 values), where value indicates that quality link very low, value indicates quality link very high. correlation degree between spreading sequences incoming chips computed over period symbol periods during reception preamble packet. reported along with each received packet FIFO shown Figure 3-2.
Beacon-Enabled Nonbeacon-Enabled Networks
IEEE 802.15.4 Standard defines modes operation: Beacon-enabled network Nonbeacon-enabled network
3.8.1
BEACON-ENABLED NETWORK
beacon-enabled network, beacons will transmitted periodically coordinator. These beacons mainly used provide synchronization services between devices also support other extended features, like Guaranteed Time Slots (GTS), Quality Service (QoS) mechanism IEEE 802.15.4 Standard. coordinator defines structure superframe using beacons.
2010 Microchip Technology Inc.
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MRF24J40
3.8.1.1 Superframe Structure
superframe structure shown Figure 3-4. superframe bounded transmission beacon frame have active inactive portion. coordinator will interact with only during active portion superframe, during inactive portion superframe, coordinator low-power mode. active portion superframe divided into equally spaced slots composed three parts: beacon, Contention Access Period (CAP) optional Contention Free Period (CFP). structure superframe depends values Beacon Order (BO) Superframe Order (SO). CFP, present, follows immediately after extends active portion superframe. allocated GTSs shall located active portion superframe. frames transmitted CAP, except Acknowledgement frames data frames that immediately follow data request command, must slotted CSMA-CA. Refer Section "Carrier Sense Multiple Access-Collision Avoidance (CSMA-CA) Algorithm" more information.
FIGURE 3-4:
SUPERFRAME STRUCTURE
Backoff Period (aUnitBackoffPeriod symbols)
Slot ESLOTG1 (0x13<3:0>) Beacon Slots ESLOTG23 (0x1E), ESLOTG45 (0x1F), ESLOT67 (0x20) Slot
Beacon
GTS1
GTS3
Inactive Portion
Active Portion
Inactive Portion
Superframe Duration (SD) aBaseSuperframeDuration symbols ORDER 0x10<3:0>)
Beacon Interval (BI) aBaseSuperframeDuration symbols ORDER 0x10<7:4>)
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2010 Microchip Technology Inc.
MRF24J40
3.8.1.2 3.8.1.3
Values Beacon Order (BO) Superframe Order (SO) determine Beacon Interval (BI) Superframe Duration (SD). Beacon Interval (BI) terms expressed
aBaseSuperframeduration
device wants transmit receive during CFP, sends "GTS request" coordinator. coordinator broadcasts address device number that device beacon frame resources available. support operation, MRF24J40 uses TXGTS1FIFO TXGTS2FIFO. TXGTS1FIFO TXGTS2FIFO ping-pong FIFOs assigned different slots same slots. both assigned same slot, they take turns transmission within that slot. TXGTS1FIFO TXGTS2FIFO triggered ahead their slot time, transmission from FIFO will take place exactly assigned slot time. Refer Section 3.12 "Transmission" information transmit data frame using TXGTSxFIFOs.
Similarly, Superframe Duration (SD) terms expressed
aBaseSuperframeduration
where aBaseSuperframeduration symbols. configured programming (0x10<7:4>) bits (0x10<3:0>) bits ORDER register. beacon-enabled networks, values should range, values equal, then superframe does have inactive portion. Beacon Interval short long seconds based values
FIGURE 3-5:
GTSFIFO STATE DIAGRAM
GTSSWITCH Switch TXGTSxFIFO Transmit Error GTSSWITCH Hold wait TXGTSxFIFO Transmit Error
Wait Slot TXGTS1FIFO TXGTS1FIFO Transmit Error (clear TXG1TRIG TXG2TRIG)
Wait Slot
Transmit Complete Transmit Error (clear TXG1TRIG)
Transmit Complete Transmit Error (clear TXG2TRIG)
Transmit Complete
Transmit Complete
Hold Wait until Next
TXGTS2FIFO Wait Slot Wait Slot
TXGTS2FIFO Transmit Error (clear TXG1TRIG TXG2TRIG)
2010 Microchip Technology Inc.
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MRF24J40
3.8.1.4 Configuring Beacon-Enabled Coordinator 3.8.1.5 Configuring Beacon-Enabled Settings Coordinator
following steps configure MRF24J40 coordinator beacon-enabled network: PANCOORD (RXMCR 0x00<3>) configure coordinator. SLOTTED (TXMCR 0x11<5>) Slotted CSMA-CA mode. Load beacon frame into TXBFIFO (0x080-0x0FF). TXBMSK (TXBCON1 0x25<7>) mask beacon interrupt mask. INTL (WAKECON 0x22<5:0>) value 0x03. Program slot (ESLOTG1 0x13<3:0>) value. coordinator supports Guaranteed Time Slot operation, refer Section 3.8.1.5 "Configuring Beacon-Enabled Settings Coordinator" below. Calibrate Sleep Clock (SLPCLK) frequency. Refer Section 3.15.1.2 "Sleep Clock Calibration" WAKECNT (SLPACK 0x35<6:0>) value 0x5F main oscillator MHz) start-up timer value. Program Beacon Interval into Main Counter, MAINCNT (0x229<1:0>, 0x228, 0x227, 0x226), Remain Counter, REMCNT (0x225, 0x224), according values. Refer Section 3.15.1.3 "Sleep Mode Counters". Configure (ORDER 0x10<7:4>) (ORDER 0x10<3:0>) values. After configuring beacon frame will sent immediately. following steps configure MRF24J40 coordinator beacon-enabled network with Guaranteed Time Slots: GTSON (GATECLK 0x26 <3>) enable FIFO clock. Based number GTSs that active current superframe, program slot value each into ESLOT registers shown Table 3-9.
TABLE 3-9:
Number
GTS1 GTS2 GTS3 GTS4 GTS5 GTS6 GTS7
PROGRAMMING SLOT VALUES
Register
ESLOTG1 0x13<3:0> ESLOTG1 0x13<7:4> ESLOTG23 0x1E<3:0> ESLOTG23 0x1E<7:4> ESLOTG45 0x1F<3:0> ESLOTG45 0x1F<7:4> ESLOTG67 0x20<3:0> exists, slot must
GTSSWITCH (TXPEND 0x21<1>) that TXGTS1FIFO TXGTS2FIFO transmission error occurs, will switch another TXGTSxFIFO.
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2010 Microchip Technology Inc.
MRF24J40
3.8.1.6 Configuring Beacon-Enabled Device 3.8.2 NONBEACON-ENABLED NETWORK
following steps configure MRF24J40 device beacon-enabled network: SLOTTED (TXMCR 0x11<5>) Slotted CSMA-CA mode. OFFSET (FRMOFFSET 0x23<7:0>) value 0x15 optimum timing alignment. Calibrate Sleep Clock (SLPCLK) frequency. Refer Section 3.15.1.2 "Sleep Clock Calibration". Program associated coordinator's 64-bit extended address ASSOEADR registers (0x230-0x237). Program associated coordinator's 16-bit short address ASSOSADR registers (0x238-0x239). nonbeacon-enabled network does transmit beacon unless receives beacon request, hence, does have superframe structure. nonbeacon-enabled network uses unslotted CSMA-CA access medium. unslotted CSMA-CA explained Section "Carrier Sense Multiple Access-Collision Avoidance (CSMA-CA) Algorithm". nonbeacon-enabled networks, both Guaranteed Time Slots (GTS) supported, generally, devices require less computing power there strict timing requirements that need met.
3.8.2.1
Configuri
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