MPC89E58A
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MPC89E58A 8-bit micro-controller
Features General Description Description. Definition. Configuration. Block Diagram Special Function Register Memory. Organization. Nonvolatile Registers:. Embedded Flash. Functional Description. TIMERS/COUNTERS. TIMER0 (T0) TIMER1 (T2) TIMER2 Interrupt. Watchdog Timer. Serial Port (UART) Reset. Power Saving Mode POF. System Programming (ISP) In-Application Program Note Other Absolute Maximum Rating. Characteristics Package Dimension.
This document contains information product under development Megawin. Megawin reserves right change discontinue this product without notice. Megawin Technology Co., Ltd. 2004 right reserved. 2005/06 version
MEGAWIN
Features
80C51 Central Processing Unit Operation voltage range: 4.5V 5.5V Optional mode operation frequency 48MHz@12T 24MHz@6T 32KB on-chip program memory capability; optional 1KB/2KB/4KB memory shared with data flash memory. capability; byte programmable data flash available shared with memory. On-chip byte scratch-pad 1024 byte auxiliary RAM; capable addressing bytes external memory MOVC-disabling, encrypting, locking flash memory realize security mechanism. Three 16-bit timer/counter, Timer2 up/down counter with programmable clock output P1.0 Eight sources, four-level-priority interrupt capability Enhanced UART, provides frame-error detection hardware address-recognition Dual DPTR fast-accessing data memory bits Watch-Dog-Timer with 8-bit pre-scalar, one-time enabled Power control: idle mode power-down mode; Power-down woken-up P3.2/P3.3/P4.2/P4.3 EMI: inhibit emission Four 8-bit bi-directional ports; extra four-bit additional available PLCC-44 PQPF-44 Three package types: PDIP MPC89E58AE PLCC MPC89E58AP PQFP MPC89E58AF
MPC89E58A Technical Summary
MEGAWIN
General Description
MPC89E58A single-chip 8-bit microcontroller with instruction sets. fully compatible with industrial-standard 80C51 series microcontroller. There bytes flash memory embedded application program. bytes data flash shared both In-System Programming code In-Application-Programming code. In-System-Programming In-Application-Programming allows users download code data while microcontroller sits running state. There 1280 bytes on-chip embedded that provides requirement from wide field application. user configure device clocks machine cycle, same performance just uses another standard 80C51 device that provided other vendor, clocks machine cycle achieve twice performance. MPC89E58A four 8-bit ports, 4-bit ports, three 16-bit timer/counters, eight-source, four-priority-level interrupt structure, enhanced UART, on-chip crystal oscillator. fabricated advanced embedded flash CMOS technology. Excellent flash-endurance, flash-retention, code-protecting security make most excellent microcontroller.
MEGAWIN
MPC89E58A Technical Summary
Description
Definition
Name
DIP-40
Number
PLCC-44 PQFP-44
Type
Description
P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) P1.0 (T2) P1.1 (T2EX) P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
Port0 open-drain, bi-directional port. When written Port0, they become high-impedance inputs. Port0 also multiplexed with low-order address data during accesses external program data memory.
General-purposed with weak pull-up resistance inside. When written into Port1, strong output driving PMOS only turn-on clock periods then weak pull-up resistance keep port high. P1.0 also used event sources timer2, output carrier timer2, alias P1.1 also used interrupt-controlling sources time2, alias T2EX.
P2.0 (A8) P2.1 (A9) P2.2 (A10) P2.3 (A11) P2.4 (A12) P2.5 (A13) P2.6 (A14) P2.7 (A15) P3.0 (RXD) P3.1 (TXD) P3.2 (INT0) P3.3 (INT1) P3.4 (T0)
Port2 8-bit bi-directional port with pull-up resistance. Except being GPIO, address Port2 byte emits during high-order accessing
external program data memory.
General-purposed with weak pull-up resistance inside. When written into Port1, strong output driving PMOS only turn-on clock periods then weak pull-up resistance keep port high Port3 also serves MEGAWIN
MPC89E58A Technical Summary
P3.5 (T1) P3.6 (/WR) P3.7 (/RD)
keep port high.
Port3 also serves
other special functions this device. P3.0 P3.1 receiver transceiver data UART function block, Alias TXD. P3.2 P3.3 also external interrupt sources, alias INT0 INT1. P3.4 P3.5 also event sources timer0 timer1 individually, alias P3.6 also acts write signal while access external memory, alias /WR. P3.7 also acts read signal while access external memory, alias /RD.
P4.0 P4.1 P4.2 (/INT3) P4.3 (/INT2) RESET
Port4 extended ports such like Port1. available only 44L-PLCC 44L-PQFP package.
high this least machine cycles will reset device. Output pulse latching byte address during accesses external memory.
/PSEN
read strobe external program memory, active. must kept enable device fetch program code from external flash memory. internal pull-up resistance been embedded this pin.
XTAL1 XTAL2
Input inverting oscillator amplifier. Output from inverting amplifier. Power Supply Ground
MEGAWIN
MPC89E58A Technical Summary
Configuration
(AD3) P0.3 (AD2) P0.2 (AD1) P0.1 (AD0) P0.0 (INT3) P4.2 (T2) P1.0 (T2EX) P1.1 P1.2 P1.3 P1.4
(T2) P1.0 (T2EX) P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (/WR) P3.6 (/RD) P3.7 XTAL2 XTAL1
P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) /PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.2 (A8)
P1.5 P1.6 P1.7 RESET (RXD) P3.0 (/INT2) P4.3 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5
2021 2223242526 2728
MPC89E58AP (PLCC-44)
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7)
MPC89E58AE (PDIP-40)
(Timer
/PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) P4.0 XTAL1 XTAL2 P3.7 (/RD) P3.6 (/WR)
P1.5 P1.6 P1.7 RESET (RXD) P3.0 (/INT2) P4.3 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5
1415 16171819202122
(AD3) P0.3 (AD2) P0.2 (AD1) P0.1 (AD0) P0.0 (INT3) P4.2 (T2) P1.0 (T2EX) P1.1 P1.2 P1.3 P1.4
MPC89E58AF (PQFP-44)
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) P4.1 /PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8) P4.0 XTAL1 XTAL2 P3.7 (/RD) P3.6 (/WR)
MPC89E58A Technical Summary
MEGAWIN
Block Diagram
P2.0 P2.7 P0.0 P0.7
Port2 Driver
Port0 Driver
ADDR Register
RAM256
Port2 Latch
Port0 Latch
Register
Stack Pointer
Flash
TMP2
TMP1 Timer
Timer
Address Generator
UART Program Counter
DPTR PSEN RESET Port1 Latch Port3 Latch Port4 Latch
Control Unit
Port1 Driver Port3 Driver Port4 Driver
ERAM
XTAL
XTAL P1.0 P1.7 P3.0 P3.7 P4.0 P4.3
MC89E58A Block Diagram
MEGAWIN
MPC89E58A Technical Summary
Special Function Register
T2CON XICON SCON TCON
WDTCR
IFADRH
IFADRL
IFMT
SCMD
ISPCR
T2MOD SADEN
RCAP2L
RCAP2H
SADDR AUXR1 SBUF TMOD Reserved AUXR PCON INITIAL VALUE 11111111B 00000111B 00000000B 00000000B 01110000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B ERAM xxxxx00B T2EX 11111111B 00000000B xxxxxxxxB 11111111B xxxx0xx0B 00000000B 00000000B 11111111B PT0H PX0H x0000000B x0000000B 00000000B C/T2 CP/RL 00000000B T2OE DCEN xxxxxx00B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B xx000000B 11111111B 00000000B 00000000B xxxxx000B xxxxxxxxB 000xx000B xxxx1111B 00000000B
SYMBOL PCON TCON TMOD AUXR SCON SBUF AUXR1 SADDR SADEN XICON T2CON T2MOD RCAP2L RCAP2H WDTCR IFADRH IFADRL IFMT SCMD ISPCR
DESCRIPTION Port Stack Pointer Data Pointer Data Pointer High Power Control SMOD SMOD0 Timer Control Timer Mode GATE C//T GATE C//T Timer Timer Timer High Timer High Auxiliary Port Serial Control Serial Buffer Port Auxiliary Interrupt Enable Slave Address Port INT1 INT0 Interrupt Priority High PX3H PX2H PT2H PT1H PX1H Interrupt Priority Slave Address Mask External Interrupt Control Timer Control EXF2 RCLK TCLK EXEN2 Timer2 mode Timer2 Capture Timer2 Capture High Timer Timer High Program Status Word Accumulator Watch-dog-timer Control WIDL register Flash data Flash Address High Flash Address Mode Table Serial Command Control Register ISPEN SRST ICK2 Port Register
ICK1
ICK0
MPC89E58A Technical Summary
MEGAWIN
Memory
Organization
00-7F 80-FF 80-FF RAM, Access direct addressing SFR, Access direct addressing indirect on-chip RAM, Access indirect addressing on-chip expanded (1024B), Access MOVX instruction off-chip memory, enabled setting ERAM
0000-03FF 0000-
03FF
FZWDTCR
MEGAWIN
0000
Bit-7
Address Space MPC89E58A embedded Flash memory
Address Space MPC89E58A
0000-7FFF Program Memory (32KB) 8000-FBFF NonVolatile data memory shared with program memory. program could take 1KB, depending OR0[5:4]
FBFF
8000 7FFF Bit-6 Bit-5 Bit-4 Bit-3 ISPAS1 ISPAS0 Non-volatile register OSCDN Non-volatile register
Bit-2 MOVCL
Bit-1
Bit-0 LOCK
HWBS
EN6T
MPC89E58A Technical Summary
Nonvolatile Registers:
There Nonvolatile Registers named individually. They designed configure MPC89E58A options. Generally these nonvolatile registers will written popular writer, Hi-Lo System All-11, Leaper-48 Megawin-Provided writer. Furthermore, user change register program manner same does writing data flash, written only off-line popular writer. register: (Option Register
Bit-7 Bit-6 Bit-5 ISPAS1 Bit-4 ISPAS0 Bit-3 Bit-2 MOVCL Bit-1 Bit-0 LOCK
{ISPAS1, ISPAS0}: Used identify start address program space from 0xEC00 0xFBFF size). space from 0xF400 0xFBFF size). space from 0xF800 0xFBFF size) space. These bits decide where program locates, program data flash shares embedded flash. MOVCL: Used decide MOVC instruction will disabled. MOVC conditionally disabled. MOVC always available. Used decide program code will scrambled while dumped. Code dump from Writer scrambled. Code dump from Writer transparent.
LOCK: Used decide program code will locked against popular writer. lock code. does lock code code locked, data dumped from popular will always show FFh.
default value FFh.
MPC89E58A Technical Summary
MEGAWIN
register: (Option Register
Bit-7 FZWDTCR Bit-6 Bit-5 Bit-4 OSCDN Bit-3 Bit-2 Bit-1 HWBS Bit-0 EN6T
FZWDTCR: Used freeze WDT-controlling register. Configure WDTCR reset only power-up action, while software style reset reset from Watch Timer. (default) Permit reset events from power-up, software style Watch Timer could reset WDTCR. OSCDN: Used adjust behavior crystal oscillator. gain crystal oscillator amplifier doubled bandwidth reduced. will bring help reducing improve power consumption. Dealing with application does need high frequency clock (under 20MHz). recommended gain crystal oscillator enough oscillator start oscillating 48MHz. HWBS: Used configure MPC89E58A boot from program normal application program after power-on sequence. MPC89E58A will boot from start address after power-on. operation. MPC89E58A will boot from normal application program. EN6T: Used configure MPC89E58A mode mode. MPC89E58A will mode MPC89E58A will mode
default value FFh.
There 1280 bytes built MPC89E58A. user visit leading 128-byte direct addressing instructions, name those direct that occupies address space 7Fh. Followed 128-byte visited indirect addressing instructions, name those indirect that occupied address space FFh. other 1024-byte named expanded that still occupied address space 0000h 03FFh. user access general register data pointers DPTR associated with MOVX instructions, MOVX
MOVX
@DPTR.
reserve natural
character instruction MOVX that designed access external memory, user ERAM AUXR hide expanded visit external memory.
MEGAWIN
MPC89E58A Technical Summary
Embedded Flash
There totally byte flash embedded MPC89E58A. leading byte flash memory designed storage user program, followed byte flash memory shared with nonvolatile data flash program. While program counter MPC89E58A spanning over 7FFFh, device will fetch program code from external memory once ignoring status. that case, will never fetch program code from following embedded flash.
user develop program into embedded flash that addressed from EC00h, F400h, F800h configuring [5:4]. Excluding program, remained flash taken data flash which read, even written application program program from user.
MPC89E58A Technical Summary
MEGAWIN
Functional Description
TIMERS/COUNTERS
MPC89E58A three 16-bit timers, they named Each them also used general event counter, which counts transition from
While T0/T1/T2 used "timer" function, time unit that used trig timer machine cycle. machine cycle equals oscillator periods, depends mode mode that user configured this device. While T0/T1/T2 used "1-0 event counter" function, counting event "high-to-low transition" primitive T0/T1/T2. this mode, device periodically samples status T0/T1/T2 once each machine cycle. Whenever sampled result turns from device will count once counter. carefully, kind implementation counter
requires that high-duty low-duty from T0/T1/T2 must short compared machine cycle. There designed configure timers They TMOD, TCON. There extra designed configure timer They T2MOD, T2CON. SFR: TMOD
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
(for timer1 use) GATE C//T GATE
(for timer0 use) C//T
GATE: Gating control when set. GATE=1, Timer/Counter enabled only while "/INTx" high "TRx" control set. When cleared Timer enabled whenever "TRx" control set.
C//T:
Timer Counter function selector. =timer, =counter
{M1, M0}: mode select 13-bit timer/counter Timer0 Timer1 16-bit timer/counter Timer0 Timer1 8-bit timer/counter with automatic reload Timer0 Timer1 Timer0: 8-bit timer/counter, locked into 8-bit timer Timer1 Timer/Counter1 Stopped
MEGAWIN
MPC89E58A Technical Summary
SFR: TCON
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
TF1: Timer1 overflow flag. hardware Timer/Counter overflow. Cleared hardware when processor vectors interrupt routine, clearing software. TR1: Timer1 control bit. Set/Cleared software. TF0: Timer0 overflow flag. hardware Timer/Counter overflow. Cleared hardware when processor vectors interrupt routine, clearing software. TR0: Timer1 control bit. Set/Cleared software. IE1: Interrupt Edge flag. hardware when external interrupt edge detected. Cleared when interrupt processed. IT1: Interrupt type control bit. Set/Cleared software specified falling edge/low level triggered interrupt. IE0: Interrupt Edge flag. hardware when external interrupt edge detected. Cleared when interrupt processed. IT0: Interrupt type control bit. Set/Cleared software specified falling edge/low level triggered interrupt.
SFR: T2MOD
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 T2OE Bit-0 DCEN
T2OE: Timer Output Enable bit. enables Timer2 overflow rate toggle P1.0. DCEN: Down Count Enable bit. When set, this allows Timer2 configured down counter.
SFR: T2CON
Bit-7 Bit-6 EXF2 Bit-5 RCLK Bit-4 TCLK Bit-3 EXEN2 Bit-2 Bit-1 C//T2 Bit-0 CP/RL2
TF2: Timer2 overflow flag. will Timer2 overflow must cleared software. will when either TCLK RCLK EXF2: Timer2 external flag. will when either capture reload caused negative transition T2EX EXEN2=1. When Timer2 interrupt enabled, EXF2=1 will cause vector timer2 interrupt routine. EXF2 must cleared software. EXF2 does cause interrupt Auto-Reload Up-Down mode (ARUD). RCLK: When causes serial port Timer2 overflow pulse receive clock mode mode RCLK=0 causes Timer1 overflow pulse used. TCLK: When causes serial port Timer2 overflow pulse transmit clock mode mode RCLK=0 causes Timer1 overflow pulse used. EXEN2: Timer-2 external enable flag. When set, allows capture reload occur. result negative transition T2EX Timer2 being used clock serial port. EXEN2=0 causes Timer2 ignore events T2EX. TR2: Start/Stop control Timer2.
MPC89E58A Technical Summary
MEGAWIN
C/T2: Timer counter select. timer external event counter. CP/RL2: Capture/Reload flag. When set, captures will occurs negative transition T2EX EXEN2=1. When cleared, auto-reloads will occur either with Timer2 overflows negative transition T2EX when EXEN2=1. When wither TCLK RCLK this ignored timer forced auto-reload Timer2 overflow.
TIMER0 (T0) TIMER1 (T2)
Mode timer register configured 13-bit register. count rolls over from sets timer interrupt flag TFx. counted input enabled timer when either GATE=0 INTx Mode operation same Timer0 Timer1.
OSC/12 (sampled) C//T
TLx[4:0] THx[7:0]
Interrupt
GATE /INTx
Mode Mode1 same Mode0, except that timer register being with bits.
OSC/12 (sampled) C//T GATE /INTx TLx[7:0] THx[7:0] Interrupt
Mode Mode configures timer register 8-bit counter (TLx) with automatic reload. Overflow from does only TFx, also reloads with content THx, which determined user's program. reload leaves unchanged. Mode operation same Timer0 Timer1.
MEGAWIN
MPC89E58A Technical Summary
OSC/12 (Sampled) C//T GATE /INTx
[7:0]
Interrupt
Reload [7:0]
Mode Timer1 Mode3 simply holds count, effect same setting Timer0 Mode enables separate 8-bit counters. uses Timer0 control bits such like C/T, GATE, TR0, INT0 TF0. locked into timer function (can external event counter) take over TR1, from Timer1. controls Timer1 interrupt.
[7:0] Interrupt
OSC/12 Sampled C//T
GATE /INT0
XTAL2
[7:0]
Interrupt
TIMER2
Timer2 16-bit timer/counter which operate either event timer event counter selected C//T2 special function register T2CON. Timer2 four operation modes: Capture Mode (CP), Auto-Reload Up/Down Mode (ARUD), Auto-Reload
Up-Only mode (ARUO) Baud-Rate Generator Mode (BRG).
LogicalOR (RCLK, TCLK) CP/RL2 Timer2 Mode Table DCEN Mode Baud-Rate Generation Capture Auto-Reload Up-only Auto-Reload Up/Down
MPC89E58A Technical Summary
MEGAWIN
Timer2 also configured periodical signal generator. MPC89E58A able generate programmable clock output P1.0. When T2OE C//T2 cleared, Timer2 overflow pulse will generate duty clock output that P1.0. frequency clock-out calculated according following formula.
Oscillator frequency (65536 RCAP2H, RCAP2L)
clock-out mode, Timer2 rollovers will generate interrupt.
Capture Mode (CP) Capture mode, Timer2 incremented either OSC/12 external (T2) 1-to-0 transition. controls event timer2 1-to-0 transition T2EX will trigger RCAP2H RCAP2L registers capture Timer2 contents onto them EXEN2 set. overflow Timer2 flag 1-to-0 transition T2EX sets EXF2 flag EXEN2=1. EXF2 ORed request interrupt service.
[7:0] TH2[7:0]
OSC/12 C//T2
RCAP2L [7:0]
RCAP2H [7:0]
Interrupt
T2EX EXEN2
EXF2
MEGAWIN
MPC89E58A Technical Summary
Auto-Reload Up-Only Mode (ARUO) ARUO mode, Timer2 configured count with software-defined value reloaded. When reset applied DCEN CP/RL2=0, Timer2 ARUO mode. overflow Timer2 1-to-0 transition T2EX will load RCAP2H RCAP2L contents onto Timer2, also EXF2, respectively.
OSC/12 C//T2
[7:0]
TH2[7:0]
RCAP2L [7:0] RCAP2H [7:0]
Interrupt EXF2
T2EX
EXEN2
Auto-Reload Up-Down Mode (ARUD) ARUD mode, Timer2 configured count down. When DCEN CP/RL2=0, Timer2 ARUD mode. counting direction determined T2EX pin. T2EX=1, counting otherwise counting down. overflow Timer2 will toggle EXF2. EXF2 cannot generate interrupt request this mode. counting direction DOWN, overflow loads 0xFFFF onto Timer2 loads RCAP2H, RCAP2L contents onto Timer2 counting direction
EXF2
OSC/12 C//T2
[7:0]
TH2[7:0]
Interrupt
RCAP2L [7:0]
RCAP2H [7:0]
T2EX
MPC89E58A Technical Summary
MEGAWIN
Baud-Rate Generator Mode (BRG) Timer2 configured generate various baud-rate. TCLK and/or RCLK T2CON allow serial port transmit receive baud rates derived from either Timer1 Timer2. When TCLK=0, Timer1 used serial port transmit baud rate generator. When TCLK=1, Timer2 used serial port transmit baud rate generator. RCLK same effect serial port baud rate. With these bits, serial port have different receive transmit baud rates generated from Timer1 other from Timer2. mode, Timers operated very like auto-reload up-only mode except that T2EX cannot control reload. overflow Timer2 will load RCAP2H, RCAP2L contents onto
Timer2, will set. 1-to-0 transition P2EX EXF2 request interrupt service EXEN2=1. baud rate UART Mode1 Mode3 determined Timer2's overflow rate given below:
Timer2 overflow rate
Baud Rate
(counting T2EX)
Baud Rate
Oscillator Frequency [65536 (RCAP2H, RCAP2L)
timer)
Timer1 overflow
SMOD OSC/12 C//T2
RCAP2L[7:0] RCAP2H[7:0]
TL2[7:0]
TH2[7:0]
RCLK TCLK Clock Clock
T2EX
EXF2
Timer2 interrupt
EXEN2
MEGAWIN
MPC89E58A Technical Summary
Interrupt
There eight interrupt sources available MPC89E58A. Each interrupt source individually enabled disabled setting clearing named This register also contains global disable (EA), which cleared disable interrupts once. Each interrupt source corresponding bits represent priority. located named other IP/XICON register. Higher-priority interrupt will interrupted lower-priority interrupt request. interrupt requests different priority levels received simultaneously, request higher priority serviced. interrupt requests same priority level received simultaneously, internal polling sequence determine which request serviced. following table shows internal polling sequence same priority level interrupt vector address. Source External interrupt Timer External interrupt Timer1 Serial Port Timer2 External interrupt External interrupt Vector address Priority within level (highest)
external interrupt /INT0, /INT1, /INT2 /INT3 each either level-activated transition-activated, depending bits TCON, XICON. flags that actually generate these interrupts bits TCON, XICON. When external interrupt generated, flag that generated cleared hardware when service routine vectored only interrupt transition -activated, then external requesting source what controls request flag, rather than on-chip hardware. Timer0 Timer1 interrupts generated TF1, which rollover their respective Timer/Counter registers most cases. When timer interrupt generated, flag that generated cleared on-chip hardware when service routine vectored serial port interrupt generated logical Neither these flags cleared hardware when service routine vectored service routine should poll determine which request service will cleared software. timer2 interrupt generated logical EXF2. Just same serial port, neither these flags cleared hardware when service routine vectored MPC89E58A Technical Summary MEGAWIN
bits that generate interrupts cleared software, with same result though been cleared hardware. other words, interrupts generated pending interrupts canceled software.
following content describes several related interrupt mechanism.
SFR: (Interrupt Enabling):
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Global disables interrupts when cleared.
ET2: When set, enables Timer2 interrupt. When set, enables serial port interrupt.
ET1: When set, enables Timer1 interrupt. EX1: When set, enables external interrupt ET0: When set, enables Timer interrupt. EX0: When set, enables external interrupt
SFR: (Interrupt Priority Low):
Bit-7 PT2: PT1: PX1: PT0: PX0: Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
set, priority timer2 interrupt higher set, priority serial port interrupt higher set, priority timer1 interrupt higher set, priority external interrupt higher set, priority timer0 interrupt higher set, priority external interrupt higher
SFR: (Interrupt Priority High):
Bit-7 PX3H PX3H: PX2H: PT2H: PSH: PT1H: PX1H: PT0H: PX0H: Bit-6 PX2H Bit-5 PT2H Bit-4 Bit-3 PT1H Bit-2 PX1H Bit-1 PT0H Bit-0 PX0H
set, priority external interrupt highest set, priority external interrupt highest set, priority timer2 interrupt highest set, priority serial port interrupt highest set, priority timer1 interrupt highest set, priority external interrupt highest set, priority timer0 interrupt highest set, priority external interrupt highest
MEGAWIN
MPC89E58A Technical Summary
XICON) combined form 4-level priority interrupt following table. {IPH.x IP.x} Priority Level (highest)
SFR: XICON (External Interrupt Control):
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
PX3: set, priority external interrupt higher EX3: set, Enables external interrupt IE3: Interrupt Edge flag. Sets hardware when external interrupt edge interrupt processed. IT3: Interrupt type control bit. Set/Cleared software specified falling interrupt. PX2: set, priority external interrupt higher EX2: set, enables external interrupt IE2: Interrupt Edge flag. Sets hardware when external interrupt edge interrupt processed. IT2: Interrupt types control bit. Set/Cleared software specify falling interrupt.
detected. Cleared when edge/low level triggered
detected. Cleared when edge/low level triggered
Watchdog Timer
CLK/12
8-bit pre-scalar timer 15-bit RESET
IDLE WIDL
CLRW
MPC89E58A Technical Summary
MEGAWIN
SFR: WDTCR (Watchdog Timer Control):
Bit-7 ENW: Bit-6 Bit-5 Bit-4 CLRW Bit-3 WIDL Bit-2 Bit-1 Bit-0
Enable while set. cannot cleared firmware. enable watchdog timer, does watchdog timer
CLRW: Clear recount while set. Hardware will automatically clear this bit. WIDL: this disable generating reset even though idle mode.
{PS2, PS1, PS0}: select pre-scalar output. pre-scaling value pre-scaling value pre-scaling value pre-scaling value pre-scaling value pre-scaling value pre-scaling value pre-scaling value
Serial Port (UART)
serial port MPC89E58A duplex. transmit receive simultaneously. receiving transmitting serial port share same SBUF, actually there SBUF registers implemented chip, transmitting other receiving. serial port operated different modes. Mode Generally, this mode purely used extend features this device. Operating under this mode, device receives serial data transmits serial data RXD, while there clock stream shifted which makes convenient external synchronization. 8-bit data serially transmitted/received with first. baud rate fixed 1/12 oscillator frequency.
Mode1 10-bits data serially transmitted through received through RXD. frame data includes start (0), data bits stop (1). After finishing receiving, device will keep stop which from SCON.
Baud Rate (for Mode
SMOD
(Timer-1 overflow rate)
(Timer-2 overflow rate)
MEGAWIN MPC89E58A Technical Summary
Mode2 11-bit data serially transmitted through received through RXD. frame data includes start (0), data bits, programmable stop (1). transmit, data comes from SCON. receive, data goes into SCON. baud rate programmable, permitted either 1/32 1/64 oscillator frequency.
Baud Rate (for Mode
SMOD
Fosc
Mode3 Mode same mode except baud rate variable.
Baud Rate (for Mode
SMOD
(Timer-1 overflow rate)
(Timer-2 overflow rate)
four modes, transmission initiated instruction that uses SBUF destination register. Reception initiated mode condition Reception initiated other modes incoming start with 1-to-0 transition REN=1.
There several related serial port configuration described following. SFR: SCON (Serial Port Control):
Bit-7 SM0/FE Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
Frame Error bit. This receiver when invalid stop detected. cleared valid frames, should cleared software. SMOD0 (PCON.6) must enable access bit. SM0, Used operating mode serial port. enabled access clearing SMOD0. serial port operate under Mode serial port operate under Mode serial port operate under Mode serial port operate under Mode
MPC89E58A Technical Summary
MEGAWIN
SM2: Enable automatic address recognition feature mode SM2=1, will unless received data indicating address, received byte Given Broadcast address. mode1, SM2=1 then will unless valid stop received, received byte Given Broadcast address. REN: TB8: RB8: Enable serial port reception. enable disable
data bit, which will transmitted Mode Mode mode received data will into this bit. Transmit interrupt flag. After transmit been finished, hardware will this bit. Receive interrupt flag. After reception been finished, hardware will this bit.
SFR: SBUF (Serial port Buffer register):
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 (data transmitted received data)
Automatic Address Recognition There extra feature makes device convenient master, which communicates multiple slaves simultaneously. really Automatic Address Recognition. There SADDR SADEN implemented device. user read write both them. Finally, hardware will make these "generate" "compared byte". formula specifies following.
Bit[ Compared Byte (SADEN[ SADDR[
example: SADDR 11000000b SADEN 11111101b achieved "Compared Byte" will "110000x0" another example: SADDR 11100000b SADEN 11111010b achieved "Compared Byte" will "11100x0x"
means don't care)
After generic "Compared Byte" been worked out, MPC89E58A will make this byte determine SCON.
Normally, UART will whenever done byte reception; UART MPC89E58A, set, will according following formula.
(SM2 (SBUF Compared Byte) (RB8
MEGAWIN
MPC89E58A Technical Summary
other words, data reception will respond while specific data does. setting SADDR SADEN, user filter those data byte that doesn't like care. This feature brings great help reduce software overhead.
above feature adapts serial port when operated Mode1, Mode2, Mode3. Dealing with Mode user ignore
Frame Error Detection missing stop will SCON register. shares SCON with actual function SCON.7 determined SMOD0 (PCON.6). SMOD0 set, SCON.7 functions otherwise functions SM0. When used bit, only cleared software.
Reset
RESET used reset this device. connected into device Schmitt Trigger buffer, excellent noise immunity. positive pulse from RESET must kept least two-machine cycle, device cannot reset.
Power Saving Mode
There power saving modes, which selectable drive MPC89E58A enter power-saving mode. IDLE mode user PCON.0, drive this chip enter IDLE mode. IDLE mode, internal clock gated CPU, interrupt, timer serial port functions. There ways terminate idle. Activation enabled interrupt will cause PCON.0 cleared hardware, terminating idle mode. interrupt will serviced, following RETI, next instruction executed will following instruction that device into idle. Another wake-up from idle pull RESET high generate internal hardware reset.
MPC89E58A Technical Summary
MEGAWIN
POWER-DOWN mode user PCON.1, drive this chip enter POWER-DOWN mode. POWER-DOWN mode, on-chip oscillator stopped. contents on-chip SFRs maintained. only wake-up from power-down mode hardware reset. carefully keep RESET active least 10ms order stable clock while wakeup this chip from POWER-DOWN mode. power-down mode woken-up either hardware reset /INT0, /INT1, /INT2 /INT3 external interrupts. When woken-up RESET pin, program will execute from address 0x0000, carefully keep RESET active least 10ms order stable clock while wakeup this chip from POWER-DOWN mode. woken-up from I/O, program will jump related interrupt service routine. wake-up, interrupt-related registers have programmed accurately before power-down entered. attention least "NOP" instruction subsequent power-down instruction waken-up used. Mode Idle Idle Power-Down Power-Down Program Memory Internal External Internal External PSEN Port0 Data Float Data Float Port1 Data Data Data Data Port2 Data Address Data Data Port3 Data Data Data Data
Status IDLE Mode POWER-DOWN Mode
POWER-ON FLAG (POF) register PCON.4 only power-on action. System RESET from watch-dog-timer, software RESET RESET this bit. cleared firmware.
System Programming (ISP)
develop good program function, user understand architecture embedded flash. embedded flash consists pages. Each page contains bytes. Dealing with flash, user must erase page unit before writing (programming) data into Erasing flash means setting content that flash FFh. erase modes available this chip. mass mode other page mode. mass mode gets more performance, erases entire flash. page mode something performance less,
flexible since erases flash page unit.
MEGAWIN
MPC89E58A Technical Summary
Unlike RAM's real-time operation, erase flash write (program) flash often takes long time wait finish. Furthermore, quite complex timing procedure erase/program flash. Fortunately, MPC89E58A carried with convenient mechanism help user read/change flash content. Just filling target address data into several SFR, triggering built-in automation, user easily erase, read, program embedded flash option registers OR1. There several designed help user implement functionality.
SFR: (ISP Flash Data register):
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 (Data written into flash, data from flash) data port register operation. data will written into desired address operating write data window readout operating read.
SFR: IFADRH (ISP Flash Address High):
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 (High byte address pointing flash memory) IFADRH high-byte address port modes.
SFR: IFADRL (ISP Flash Address Low):
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 (Low byte address pointing flash memory) IFADRL low-byte address port modes.
SFR: IFMT (ISP Flash Mode Table):
Bit-7 Bit-6 Bit-5 reserved Bit-4 Bit-3 Bit-2 Bit-1 Mode Selection Bit-0
Mode Selection
Operate Standby AP-memory read AP-memory/Data-flash program AP-memory/Data-flash page erase memory erase (IFADRL[0]=1). memory read IFADRL[0] memory program IFADRL[0]
Note: cannot changed operation. accessed only Writer. Only changed program.
MPC89E58A Technical Summary
MEGAWIN
SFR: SCMD (Sequential Command Data register ISP)
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0 ISP-Command (Device SCMD command port triggering activity. SCMD filled with sequential 46h, ISPCR.7 activity will triggered. When this register read, device MPC89E58A will returned bytes). byte byte 08h. IFADRL[0] used select HIGH/LOW byte DID.
SFR: ISPCR (ISP Control register):
Bit-7 ISPEN Bit-6 SWBS Bit-5 SWRST Bit-4 Bit-3 Bit-2 Bit-1 WAIT Bit-0
ISPEN: function enabling Disable program change flash Enable program change flash SWBS: Secondary Booting program selecting Boot from main-memory. Boot from memory. SWRST: software reset trigger operation Generate software system reset.
will cleared hardware automatically.
Notice: Software reset actions could reset other SFR, never influences bits ISPEN SWBS. ISPEN SWBS only will reset power-up action, while software reset. WAIT: Waiting time selection while flash busy. Wait time (Machine Cycle) Program Read Recommended System clock
ISPCR[2:0]
Page Erase 43769 21885 10942 5471
Procedures demonstrating function
IFMT xxxxx011 ISPCR 100xx010b IFADRH (page address high byte) IFADRL (page address byte) SCMD SCMD (CPU progressing will hold here (CPU continues) choice page-erasing command ISPEN=1 enable flash change. WAIT=010, 10942 assumed X's*/ specify address page erased trig activity
Erase specific flash page
MEGAWIN
MPC89E58A Technical Summary
IFMT xxxxx010 ISPCR 100xx010b IFADRH (Address high byte) IFADRL (Address byte) (byte date written into flash) SCMD SCMD (CPU progressing will hold here) (CPU continues)
choice byte-programming command ISPEN=1 enable flash change. WAIT=010, assumed X's*/ specify address programmed prepare data source trig activity
Program byte into flash IFMT xxxxx001 ISPCR 100xx010b choice byte-read command ISPEN=1 enable flash change. WAIT=010, assumed X's*/ specify address read
IFADRH (Address high byte) IFADRL (Address byte) SCMD trig activity SCMD (CPU progressing will hold here) (CPU continues currently contain desired data byte
Read byte from flash
Booting Program Entrance MPC89E58A boots according following rule.
HWBS
ISPAS1, ISPAS0}
System will boot from program else System will boot from normal program
Above rule adaptive only power-up procedure, while software reset.
Switching from program program device permits user normally start running program soon program finished updating flash content. Just program instruction tail program
ISPCR
001xxxxxb
MPC89E58A Technical Summary
MEGAWIN
which disables flash-writing authority, SWBS trigger software reset. After that, system will reset (not powered-up), system will refer SWBS startup from program entrance. power-up procedure, HWBS will referred decide program entrance, software reset, SWBS will referred
Switch program from program device also permits user program switches directly program. Just program instruction program
ISPCR
x11xxxxxb
which sets SWBS direct device boot from program, trigger software reset. After that, system will reset (not powered-up), system will refer SWBS startup from program entrance.
In-Application Program
In-Application Program feature designed user Read/Write nonvolatile data flash. bring great help store parameters those should independent power-up power-done action. other words, user store data data flash memory, after shutting down rebooting MCU, original value, which stored user program data flash according same program, should deeper understanding related IFD, IFADRL, IFADRH, IFMT, SCMD, ISPCR. data flash programmed program well program. program program memory data flash, while program program data flash memory. program desires change memory associated with specific address space, hardware will ignore
Note Even users need space, OR0[5:4] still needs programmed with {10} data flash desired. other words, maximum available size data flash operation 30Kbytes.
MEGAWIN
MPC89E58A Technical Summary
Note Other
SFR: AUXR
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 ERAM Bit-0
ERAM: Define hide expanded RAM, access external internal auxiliary access enabled internal auxiliary access disabled. MOVX instructions always direct external RAM.
emitted constant rate oscillator frequency mode, constant rate
oscillator frequency mode active only during access external memory both MOVC MOVX
SFR: AUXR1
Bit-7 Bit-6 Bit-5 Bit-4 Bit-3 Bit-2 Bit-1 Bit-0
GF2: General purpose flag DPS: Data pointer switch Make data pointer-0 active Make data pointer-1 active
MPC89E58A Technical Summary
MEGAWIN
Absolute Maximum Rating
Parameter Operating temperature under bias Storage temperature Voltage Operating Frequency Rating -0.5 5.5V 45MHz
Characteristics
clocks machine cycle ,unless otherwise specified
Symbol VIL1 VIL2 VIH1
Parameter Input voltage (P0, 1,2,3,4) Input voltage (RESET) Input high voltage (P0, 4,EA)
Test Condition
Vcc=5.0V Vcc=5.0V =5.0V
Min.
Specification Typ. Max.
Unit
VIH2 IOL1
Input high voltage (RESET) Sinking Current output (P1,
Vcc=5.0V Vcc=5.0V
IOL2
Sinking Current output (P0, ALE, PSEN)
Vcc=5.0V
IOH1
Sourcing Current output High (P1,
5.0V
IOH2
Sourcing Current output High (ALE, PSEN)
5.0V
Logic input current (P1,2,3,4) Logic transition current (P1,2,3,4)
Vpin=0V Vpin=2.0V
IIDLE Rrst
Operating current @20MHz Idle mode current 20MHz Power down current
Internal pull-down resistance RESET
Vcc=5.0V Vcc=5.0V Vcc=5.0V
45K~116K
MEGAWIN
MPC89E58A Technical Summary
Package Dimension
40-pin PDIP (MPC89E58AE)
44-pin PLCC (MPC89E58AP)
MPC89E58A Technical Summary
MEGAWIN
44-pin PQFP (MPC89E58AF)
MEGAWIN
MPC89E58A Technical Summary
Version History Version Date 2004/10 2004/11 2005/01 Page reorganized Added Procedures demonstrating function Re-Format Mark reset resistance Remove read-only limitation AUXR Document option register OR1.7 Baud-Rate-Computing formula Timer-1 start address incorrect Update PQFP-44 package shape Modify location PDIP PLCC package Modify bits definition PCON Absolute Maximum Rating Description
2005/01 2005/3/30 2005/6/14
MPC89E58A Technical Summary
MEGAWIN
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