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MPC750/D (Motorola Order Number)
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MPC750 RISC Microprocessor Technical Summary This document gives overview MPC750 MPC740 microprocessor features, major functional components. summarizes including block diagram showing MPC750 MPC740 processors implement PowerPC® architecture specification describes processor-specific features defined PowerPC architecture.
Advance Information
This document parts: Part "MPC750 Microprocessor Overview," provides overview MPC750 features, including block diagram showing major functional components. Part "MPC750 Microprocessor: Implementation," describes PowerPC architecture general provides specific details about MPC750 lowpower, 32-bit implementation PowerPC architecture.
MPC750 Technical Summary
Unless otherwise noted, references this document MPC750 apply MPC740. MPC750 differs from MPC740 primarily extensive cache support. locate published errata updates this document, refer website http://www.mot.com/powerpc/.
PowerPC name registered trademark PowerPC logotype trademark International Business Machines Corporation used Motorola under license from International Business Machines Corporation. This document contains information product under development Motorola. Motorola reserves right change discontinue this product without notice. Motorola Inc. 1997. rights reserved.
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Part MPC750 Microprocessor Overview
This section describes features general operation MPC750 provides block diagram showing major functional units. MPC750 implementation PowerPC microprocessor family reduced instruction computer (RISC) microprocessors. MPC750 implements 32-bit portion PowerPC architecture, which provides 32-bit effective addresses, integer data types bits, floating-point data types bits. MPC750 superscalar processor that complete instructions simultaneously. incorporates following execution units: Floating-point unit (FPU) Branch processing unit (BPU) System register unit (SRU) Load/store unit (LSU) integer units (IUs): executes integer instructions. executes integer instructions except multiply divide instructions.
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ability execute several instructions parallel ICsimple instructions with rapid execution times yield high efficiency throughput MPC750-basedM systems. Most integer instructions execute broken into subtasks, implemented three clock cycle. pipelined, tasks performs successive stages. Typically, floating-point instruction occupy only three stages time, freeing previous stage work nextC floating-point instruction. Thus, three single-precision floating-point instructions FPUEE execute stage time. Double-precision instructions have three-cycle latency; double-precision multiply multiply-add instructions have four-cycle latency. Figure shows parallel organization execution units (shaded diagram). instruction unit fetches, dispatches, predicts branch instructions. Note that this conceptual model that shows basic features rather than attempting show features implemented physically.
MPC750 independent on-chip, 32-Kbyte, eight-way set-associative, physically addressed caches instructions data independent instruction data memory management units (MMUs). Each 128-entry, two-way set-associative translation lookaside buffer (DTLB ITLB) that saves recently used page address translations. Block address translation done through four-entry instruction data block address translation (IBAT DBAT) arrays, defined PowerPC architecture. During block translation, effective addresses compared simultaneously with four entries. cache implemented with on-chip, two-way, set-associative memory, with external, synchronous SRAMs data storage. external SRAMs accessed through dedicated cache port that supports single bank Mbyte synchronous SRAMs. cache interface implemented MPC740. MPC750 32-bit address 64-bit data bus. Multiple devices compete system resources through central external arbiter. MPC750's three-state cache-coherency protocol (MEI) supports exclusive, modified, invalid states, compatible subset MESI four-state protocol, operates coherently systems with four-state caches. MPC750 supports single-beat burst data transfers memory accesses memory-mapped operations. MPC750 four software-controllable power-saving modes. Three static modes, doze, nap, sleep, progressively reduce power dissipation. When functional units idle, dynamic power management mode causes those units enter low-power mode automatically without affecting operational performance, software execution, external hardware. MPC750 also provides thermal assist unit (TAU) reduce instruction fetch rate limiting power dissipation. MPC750 uses advanced CMOS process technology fully compatible with devices.
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Instruction Unit Fetcher BTIC Instruction Queue Word) Entry ITLB IBAT Array (Shadow) Instruction Branch Processing Unit
128-Bit Instructions)
Additional Features Time Base Counter/Decrementer Clock Multiplier JTAG/COP Interface Thermal/Power Management Performance Monitor
Tags
32-Kbyte Cache
Instructions Dispatch Unit 64-Bit Instructions)
Reservation Station Reservation Station File Rename Buffers Integer Unit System Register Unit 32-Bit Load/Store Unit Reservation Station
Reservation Station Entry)
File Rename Buffers 64-Bit 64-Bit
Reservation Station
Integer Unit
Floating-Point Unit
32-Bit 32-Bit
Calculation)
Store Queue
FPSCR FPSCR
Data (Original) DBAT Array DTLB
64-Bit
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Interface Unit Instruction Fetch Queue
Figure MPC750 Microprocessor Block Diagram
Completion Unit
Reorder Buffer Entry)
Castout Queue Tags 32-Kbyte Cache
Interface Unit Castout Queue
Data Load Queue
Controller
L2CR 32-Bit Address 32-/64-Bit Data 17-Bit Address 64-Bit Data Tags MPC740
MPC750 Microprocessor Features
This section lists features MPC750. interrelationship these features shown Figure
1.1.1 Overview MPC750 Microprocessor Features
Major features MPC750 follows: High-performance, superscalar microprocessor many four instructions fetched from instruction cache clock cycle
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many instructions execute clock (including integer instructions) Single-clock-cycle execution most instructions independent execution units register files featuring both static dynamic branch prediction 64-entry (16-set, four-way set-associative) branch target instruction cache (BTIC), cache branch instructions that have been encountered branch/loop code sequences. target instruction BTIC, fetched into instruction queue cycle sooner than ALcache. Typically, fetch access hits BTIC, made available from instruction provides first instructions target stream. 512-entry branch history table (BHT) with bits entry four levels prediction- not-taken, strongly not-taken, taken, strongly taken that update count register (CTR) link register (LR) Branch instructions removed instruction stream. from integer units (IUs) that share thirty-two GPRs integer operands
many instructions dispatched clock execute integer instruction. execute integer instructions except multiply divide instructions (multiply, divide, shift, rotate, arithmetic, logical instructions). Most instructions that execute take cycle execute. single-entry reservation station. Three-stage Fully IEEE 754-1985-compliant both single- double-precision operations Supports non-IEEE mode time-critical operations Hardware support denormalized numbers Single-entry reservation station Thirty-two 64-bit FPRs single- double-precision operands Two-stage Two-entry reservation station Single-cycle, pipelined cache access Dedicated adder performs calculations Performs alignment precision conversion floating-point data Performs alignment sign extension integer data Three-entry store queue Supports both big- little-endian modes
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handles miscellaneous instructions Executes logical Move to/Move from instructions (mtspr mfspr) Single-entry reservation station Rename buffers rename buffers rename buffers Condition register buffering supports writes clock Completion unit completion unit retires instruction from six-entry reorder buffer (completion queue) Ifinished execution, when instructions ahead have been completed, instruction exceptions pending. Guarantees sequential programming model (precise exception model) Monitors dispatched instructions retires them order Retires many instructions clock
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Tracks unresolved branches flushes instructions from mispredicted branch Separate on-chip instruction data caches (Harvard architecture) Pseudo least-recently-used (PLRU) replacement algorithm 32-byte (eight-word) cache block
32-Kbyte, eight-way set-associative instruction data caches
Physically indexed/physical tags. (Note that PowerPC architecture refers physical real address space.) address space
Cache write-back write-through operation programmable per-page per-block basis Instruction cache provide four instructions clock; data cache provide words clock Caches disabled software Caches locked software Data cache coherency (MEI) maintained hardware critical double word made available requesting unit when burst into linefill buffer. cache nonblocking, accessed during this operation. Level (L2) cache interface (The cache interface supported MPC740.) On-chip two-way set-associative cache controller tags External data SRAMs Support 256-Kbyte, 512-Kbyte, 1-Mbyte caches 64-byte (256-Kbyte/512-Kbyte) 128-byte Mbyte) sectored line size Supports flow-through (register-buffer), pipelined (register-register), pipelined late-write (register-register) synchronous burst SRAMs
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Separate memory management units (MMUs) instructions data 52-bit virtual address; 32-bit physical address Address translation 4-Kbyte pages, variable-sized blocks, 256-Mbyte segments Memory programmable write-back/write-through, cacheable/noncacheable, coherency enforced/coherency enforced page block basis Separate IBATs DBATs (four each) also defined SPRs Separate instruction data translation lookaside buffers (TLBs) Both TLBs 128-entry, two-way associative, replacement algorithm Separate interface units system memory cache
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interface features include following: Selectable bus-to-core clock frequency ratios 2.5x, 3.5x, 4.5x half-clock multipliers in-between) 64-bit, split-transaction external data with burst transfers Support address pipelining limited out-of-order transactions Single-entry load queue Single-entry instruction fetch queue Two-entry cache castout queue No-DRTRY mode eliminates DRTRY signal from qualified grant. This allows forwarding data during load operations internal core cycle sooner than useH DRTRY enabled. cache interface features (which implemented MPC740) include following:
Core-to-L2 frequency divisors 1.5, 2.5, Four-entry cache castout queue cache 17-bit address 64-bit data
TLBs hardware reloadable (that page table search performedC. hardware)
Multiprocessing support features include following: Hardware-enforced, three-state cache coherency protocol (MEI) data cache. Load/store with reservation instruction pair atomic memory references, semaphores, other multiprocessor operations
Power thermal management Three static modes, doze, nap, sleep, progressively reduce power dissipation: Doze-All functional units disabled except time base/decrementer registers snooping logic. Nap-The mode further reduces power consumption disabling snooping, leaving only time base register powered state. Sleep-All internal functional units disabled, after which external system logic disable SYSCLK.
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Thermal management facility provides software-controllable thermal management. Thermal management performed through three supervisor-level registers MPC750specific thermal management exception. Instruction cache throttling provides control instruction fetching limit power consumption. Performance monitor used help debug system designs improve software efficiency. In-system testability debugging features through JTAG boundary-scan capability
1.1.2 Instruction Flow
shown Figure MPC750 instruction unit provides centralized control instruction flow execution units. instruction unit contains sequential fetcher, six-entry instruction queue (IQ), dispatch unit, BPU. determines address next instruction fetched based information from sequential fetcher from BPU.
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sequential fetcher loads instructions from instruction cache into instruction queue. extracts branch instructions from sequential fetcher. Branch instructions that cannot resolved immediately predicted using either MPC750-specific dynamic branch prediction architectureIC defined static branch prediction.
Branch instructions that affect removed from instruction stream. folds branch instructions when branch takenC predicted taken); branch instructions that taken, predicted taken, removed from instruction stream through dispatch mechanism. 1.1.2.1 Instruction Queue Dispatch Unit
Instructions issued beyond predictedFbranch complete execution until branch resolved, preserving programming model sequential execution. branch prediction incorrect, instruction unit flushes predicted path instructions, instructions fetched from correct path.
instruction queue (IQ), shown Figure holds many instructions loads four instructions from instruction cache during single processor clock cycle. instruction fetcher continuously attempts load many instructions there were vacancies previous clock cycle. instructions except branch instructions dispatched their respective execution units from bottom positions instruction queue (IQ0 IQ1) maximum rate instructions cycle. Reservation stations provided IU1, IU2, FPU, LSU, SRU. dispatch unit checks source destination register dependencies, determines whether position available completion queue, inhibits subsequent instruction dispatching required. Branch instructions detected, decoded, predicted from anywhere instruction queue. more detailed discussion instruction dispatch, Section 2.6, "Instruction Timing."
1.1.2.2 Branch Processing Unit (BPU)
receives branch instructions from sequential fetcher performs lookahead operations conditional branches resolve them early, achieving effect zero-cycle branch many cases. Unconditional branch instructions conditional branch instructions which condition known resolved immediately. unresolved conditional branch instructions, branch path predicted using either architecture-defined static branch prediction MPC750-specific dynamic branch prediction. Dynamic branch prediction enabled HID0[BHT] When prediction made, instruction fetching, dispatching, execution continue from predicted path, instructions cannot complete write back results architected registers until prediction determined correct (resolved). When prediction incorrect, instructions from incorrect path flushed from processor processing begins from correct path. MPC750 allows second
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branch instruction predicted; instructions from second predicted instruction stream fetched cannot dispatched. Dynamic prediction implemented using 512-entry branch history table (BHT), cache that provides bits entry that together indicate four levels prediction branch instruction-not-taken, strongly not-taken, taken, strongly taken. When dynamic branch prediction disabled, uses instruction encoding predict direction conditional branch. Therefore, when unresolved conditional branch instruction encountered, MPC750 executes instructions from predicted target stream although results committed architected registers until conditional branch resolved. This execution continue until second unresolved branch instruction encountered. When branch taken predicted taken), instructions from untaken path must. flushed target instruction stream must fetched into BTIC 64-entry cache that contains most recently used branch target instructions, typically pairs. When instruction fetch hits BTIC, instructions arrive instruction queue next clock cycle, clock cycle sooner than they would arrive from instruction cache. Additional instructions arrive from theD instruction cache next clock cycle. BTIC reduces number missed opportunities dispatch instructions gives processor one-cycle head start processing target stream.
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three user-control registers-the link contains adder compute branch target addresses register (LR), count register (CTR), calculates return pointer subroutine AThe calls saves into certain types ofSC branch instructions. also contains branch target (bclrx) instruction. contains branch target address Branch Conditional Link Register address Branch Conditional Count Register (bcctrx) instruction. Because SPRs, their contents copied from GPR. Because uses dedicated registers rather branch instructions largely independent from execution integer than GPRs FPRs, execution floating-point instructions. 1.1.2.3 Completion Unit
completion unit operates closely with instruction unit. Instructions fetched dispatched program order. point dispatch, program order maintained assigning each dispatched instruction successive entry six-entry completion queue. completion unit tracks instructions from dispatch through execution retires them program order from bottom entries completion queue (CQ0 CQ1). Instructions cannot dispatched execution unit unless there vacancy completion queue. Branch instructions that update removed from instruction stream take entry completion queue. Instructions that update follow same dispatch completion procedures nonbranch instructions, except that they issued execution unit. Completing instruction commits execution results architected registers (GPRs, FPRs, CTR). In-order completion ensures correct architectural state when MPC750 must recover from mispredicted branch exception. Retiring instruction removes from completion queue.
1.1.2.4 Independent Execution Units
addition BPU, MPC750 provides five execution units described following sections.
1.1.2.4.1 Integer Units (IUs)
integer units, IU2, shown Figure execute integer instruction; execute integer instruction except multiplication division instructions. Each singleentry reservation station that receive instructions from dispatch unit operands from GPRs rename buffers.
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Each consists three single-cycle subunits-a fast adder/comparator, subunit logical operations, subunit performing rotates, shifts, count-leading-zero operations. These subunits handle one-cycle arithmetic instructions; only subunit execute instruction time. 32-bit integer multiplier/divider well adder, shift, logical units IU2. multiplier supports early exit operations that require full 32-bit multiplication. Each dedicated result (not shown Figure that connects rename buffers.
1.1.2.4.2 Floating-Point Unit (FPU)
FPU, shown Figure designed such that single-precision operations require only single pass, with latency three cycles. instructions dispatched FPU's reservation station,.source operand data accessed from FPRs from rename buffers. Results turn written rename buffers made available subsequent instructions. Instructions pass through reservation station dispatch order.
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contains single-precision multiply-add array floating-point status control register (FPSCR). multiply-add array allows MPC750 efficiently implement multiply multiply-add operations. pipelined that single- double-precision instruction issued clock cycle. Thirty-two 64-bit floating-point registers provided support floating-point operations. Stalls floating-point rename registers. contention FPRs minimized automatic allocation appropriate when floating-point instructions MPC750 writes contents rename registers retired completion unit. Unit (LSU) 1.1.2.4.3 Load/Store executes load store instructions provides data transfer interface between GPRs,
FPRs, cache/memory subsystem. calculates effective addresses, performs data alignment, provides sequencing load/store string multiple instructions.
MPC750 supports IEEE 754Y floating-point data types (normalized, denormalized, NaN, zero, infinity) hardware, eliminating latency incurred software exception routines. (Note that exception also referred interrupt architecture specification.)
Load store instructions issued translated program order; however, some memory accesses occur order. Synchronizing instructions used enforce strict ordering. When there data dependencies guarded page block cleared, maximum out-of-order cacheable load operation execute cycle, with two-cycle total latency cache hit. Data returned from cache held rename register until completion logic commits value FPR. Stores cannot executed order held store queue until completion logic signals that store operation completed memory. MPC750 executes store instructions with maximum throughput cycle three-cycle total latency data cache. time required perform actual load store operation depends processor/bus clock ratio whether operation involves on-chip cache, cache, system memory, device.
1.1.2.4.4 System Register Unit (SRU)
executes various system-level instructions, well condition register logical operations move to/from special-purpose register instructions. maintain system state, most instructions executed execution-serialized; that instruction held execution until previously issued instructions have executed. Results from execution-serialized instructions executed available forwarded subsequent instructions until instruction completes.
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MPC750's MMUs support Petabytes (252) virtual memory Gigabytes (232) physical memory instructions data. MMUs also control access privileges these spaces block page granularities. Referenced changed status maintained processor each page support demand-paged virtual memory systems. calculates effective addresses data loads stores; instruction unit calculates effective addresses instruction fetching. translates effective address determine correct physical address memory access.
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machine state Real addressing mode-In this mode, translation disabled clearing bits register (MSR): MSR[IR] instruction fetching MSR[DR] data accesses. When address translation disabled, physical address identical effective address. Page address translation-translates page frame address forD 4-Kbyte page size Block address translation-translates base address blocks (128 Kbytes Mbytes) translation enabled, appropriate translates higher-order bits effective address into physical address bits. lower-order address bits (that untranslated therefore, considered both where they form index into eight-way setlogical physical) directed on-chip caches passes higher-order physical address bits associative array. After translating address, cache cache lookup completes. caching-inhibited accesses accesses that miss cache, untranslated lower-order address bits concatenated with translated higher-order address bits; resulting 32-bit physical address used memory unit system interface, which accesses external memory. TLBs store pageR address translations recent memory accesses. each access, effective address
MPC750 supports following types memory translation: presented page block translation simultaneously. translation found both array, block address translation array used. Usually translation physical address readily available on-chip cache. When page address translation TLB, hardware searches page table following model defined PowerPC architecture. Instruction data TLBs provide address translation parallel with on-chip cache access, incurring additional time penalty event hit. MPC750's TLBs 128-entry, two-way setassociative caches that contain instruction data address translations. MPC750 automatically generates search miss.
1.1.4 On-Chip Instruction Data Caches
MPC750 implements separate instruction data caches. Each cache 32-Kbyte eight-way associative. defined PowerPC architecture, they physically indexed. Each cache block contains eight contiguous words from memory that loaded from 8-word boundary (that bits EA[27-31] zeros); thus, cache block never crosses page boundary. entire cache block updated fourbeat burst load. Misaligned accesses across page boundary incur performance penalty. Caches nonblocking, write-back caches with hardware support reloading cache misses. critical double word transferred first beat simultaneously written cache forwarded requesting unit, minimizing stalls load delays. cache being loaded blocked internal accesses while load completes. MPC750 cache organization shown Figure
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Sets
Block Block Block Block Block
Address Address Address Address Address Address Address Address
State State State State State State State State
Words [0-7] Words [0-7] Words [0-7]
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Block Block Block
Within cycle, data cache provides double-word access LSU. Like instruction cache, data cache invalidated once per-cache-block basis. data cache disabled invalidated clearing HID0[DCE] setting HID0[DCFI]. data cache locked setting HID0[DLOCK]. ensure cache coherency, data cache supports three-state protocol. data cache tags single-ported, simultaneous load store snoop access represent resource collision. snoop occurs, blocked internally cycle allow eight-word block data copied write-back buffer.
Within cycle, instruction cache provides four instructions instruction queue. instruction cache invalidated entirely cache-block basis. instruction cache disabled invalidated clearing HID0[ICE] setting HID0[ICFI]. instruction cache locked setting HID0[ILOCK]. instruction cache supports only valid/invalid states. MPC750 also implements 64-entry (16-set, four-way set-associative) branch target instruction cache (BTIC). BTIC cache branch instructions that have been encountered branch/loop code sequences. target instruction BTIC, fetched into instruction queue cycle sooner than made available from instruction cache. Typically BTIC contains first instructions target stream. BTIC disabled invalidated through software. more information, Section 1.1.2.2, "Branch Processing Unit (BPU)."
Figure Cache Organization
Words [0-7] Words [0-7] MWords [0-7]
Words [0-7] Words [0-7] Words/Block
1.1.5 Cache Implementation (Not Supported MPC740)
cache unified cache that receives memory requests from both instruction data caches independently. cache implemented with on-chip, two-way, set-associative memory, with external, synchronous SRAMs data storage. external SRAMs accessed through dedicated cache port that supports single bank Mbyte synchronous SRAMs. cache normally operates write-back mode supports system cache coherency through snooping.
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Depending size, cache organized into 128-byte lines, which turn subdivided into 32-byte sectors (blocks), unit which cache coherency maintained. cache controller contains cache control register (L2CR), which includes bits enabling parity checking, setting L2-to-processor clock ratio, identifying type used cache implementation. cache controller also manages cache array, two-way setassociative with tags way. Each sector (32-byte cache block) valid modified status bits. Requests from cache generally result from instruction misses, data load store misses, writethrough operations, cache management instructions. Requests from cache looked tags serviced cache they hit; they forwarded interface they.miss.
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1.1.6 System Interface/Bus Interface Unit (BIU) ALaddress data tenures memory access address data buses operate independently; Ememory traffic. primary activity system interface decoupled provide more flexible control transferring data instructions between processor system memory. There types memory accesses: memory accesses allow transfer sizes bits Single-beat transfers-These clock cycle. Single-beat transactions caused uncacheable read write operations that access memory directly (that when caching disabled), cache-inhibited accesses, stores write-through mode.
Four-beat burst bytes) data transfers-Burst transactions, which always transfer entire cache block bytes), initiated when entire cache block transferred. Because first-level caches MPC750 write-back caches, burst-read memory, burst operations most common memory accesses, followed burst-write memory operations, single-beat (noncacheable write-through) memory read write operations.
cache accept multiple, simultaneous accesses. instruction cache request operations. instruction same time that data cache requesting load store cache also services snoop requests from bus. there multiple pending requests cache, snoop requests have highest priority. next priority consists load store requests from data instruction cache. cache. next priority consists instruction fetch requests from
MPC750 also supports address-only operations, variants burst single-beat operations, (for example, atomic memory operations global memory operations that snooped), address retry activity (for example, when snooped read access hits modified block cache). broadcast some address-only operations controlled through HID0[ABE]. accesses same protocol memory accesses. Access system interface granted through external arbitration mechanism that allows devices compete mastership. This arbitration mechanism flexible, allowing MPC750 integrated into systems that implement various fairness parking procedures avoid arbitration overhead. Typically, memory accesses weakly ordered-sequences operations, including load/store string multiple instructions, necessarily complete order they begin-maximizing efficiency without sacrificing data coherency. MPC750 allows read operations ahead store operations (except when dependency exists, cases where noncacheable access performed), provides support write operation ahead previously-queued read data tenure (for example, letting snoop push enveloped between address data tenures read operation). Because MPC750 dynamically optimize run-time ordering load/store traffic, overall performance improved.
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system interface specific each PowerPC microprocessor implementation. MPC750 signals grouped shown Figure Signals provided clocking control caches, well separate address data buses. Test control signals provide diagnostics selected internal circuits.
Address Arbitration Address Start Address Transfer Transfer Attribute
Data Arbitration Data Transfer Data Termination
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Clocks Processor Status/Control UControl Test System Status (I/O) supported MPC740 Interface Figure System system interface supports address pipelining, which allows address tenure transaction pipelining depends external arbitration control overlap data tenure another. extent circuitry. Similarly, MPC750 supports split-bus transactions systems with multiple potential masters-one device have mastership address while another mastership data bus. Allowing multiple transactions occur simultaneously increases available bandwidth other activity. MPC750's clocking structure supports wide range processor-to-bus clock ratios.
Address Termination Cache Address/Data
MPC750
Cache Clock/Control
1.1.7 Signals
MPC750's signals grouped follows: Address arbitration signals-The MPC750 uses these signals arbitrate address mastership. Address start signals-These signals indicate that master begun transaction address bus. Address transfer signals-These signals include address address parity signals. They used transfer address ensure integrity transfer. Transfer attribute signals-These signals provide information about type transfer, such transfer size whether transaction bursted, write-through, caching-inhibited. Address termination signals-These signals used acknowledge address phase transaction. They also indicate whether condition exists that requires address phase repeated. Data arbitration signals-The MPC750 uses these signals arbitrate data mastership. Data transfer signals-These signals, which consist data data parity signals, used transfer data ensure integrity transfer.
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Data termination signals-Data termination signals required after each data beat data transfer. single-beat transaction, data termination signal also indicates tenure; burst accesses, data termination signals apply individual beats indicate tenure only after final data beat. They also indicate whether condition exists that requires data phase repeated. cache clock/control signals-These signals provide clocking control cache. (The cache feature supported MPC740.) cache address/data-The MPC750 separate address data buses accessing cache. (The cache feature supported MPC740.) Interrupt signals-These signals include interrupt signal, checkstop signals, and.both soft reset hard reset signals. These signals used generate interrupt exceptions and, under various conditions, reset processor.
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Processor status/control signals-These signals used reservation coherency bit, enable time base, other functions.
Miscellaneous signals-These signals used conjunction with such resources secondary caches time base facility.
JTAG/COP interface signals-The common on-chip processor (COP) unit provides serial interface system performing board-level boundary-scan interconnect tests.
Clock signals-These signals determine system clock frequency. These signals also used synchronize multiprocessor systems.
over aEsignal name indicates that signal active low-for example, ARTRY (address retry) (transfer start). Active-low Care referred asserted (active) when they negated signals when they high. Signals that active low, such AP[0-3]
(address parity signals) TT[0-4] (transfer type signals) referred asserted when they high negated when they low.
NOTE
1.1.8 Signal Configuration
Figure shows MPC750's logical configuration. signals grouped function.
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L2AV supported MPC740 Address Arbitration L2ADDR[16-0] L2DATA[0-63] L2DP[0-7] Cache Address/ Data
Address Start
L2CE L2WE L2CLK_OUT[A-B] L2SYNC_OUT L2SYNC_IN L2ZZ
A[0-31] Address AP[0-3]
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TT[0-4] TBST Transfer Attributes TSIZ[0-2]
Address Termination
Data ArbitrationA
Data Transfer
MPC750 AACK ARTRY
SRESET
Cache Clock/ Control
HRESET CKSTP_IN CKSTP_OUT
Interrupts/ Resets
RSRV TBEN TLBISYNC QREQ QACK Processor Status/ Control
D[0-63] DP[0-7] DBDIS
SYSCLK PLL_CFG[0-3] CLK_OUT Clock Control
Data Termination DRTRY
JTAG/COP Factory Test
Test Interface
(I/O)
Figure MPC750 Microprocessor Signal Groups
1.1.9 Clocking
MPC750 requires single system clock input, SYSCLK, that represents interface frequency. Internally, processor uses phase-locked loop (PLL) circuit generate master core clock that frequency-multiplied phase-locked SYSCLK input. This core frequency used operate internal circuitry.
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configured PLL_CFG[0-3] signals, which select multiplier that uses multiply SYSCLK frequency internal core frequency. feedback guarantees that processor clock phase locked clock, regardless process variations, temperature changes, parasitic capacitances. also ensures duty cycle processor clock. MPC750 supports various processor-to-bus clock frequency ratios, although ratios available frequencies. Configuration processor/bus clock ratios displayed through MPC750-specific register, HID1. information about supported clock frequencies, MPC750 hardware specifications.
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PowerPC architecture derived from POWER architecture (Performance Optimized with Enhanced RISC architecture). PowerPC architecture shares benefits POWER architecture optimized single-chip implementations. PowerPC architecture design facilitates parallel instruction execution scalable take advantage future technological gains.
This section describes PowerPC architecture general, andIC specific details about implementation MPC750 low-power, 32-bit member PowerPC processor family. Registers programming model-Section "PowerPC Registers Programming Model," 2.1, describes registers operatingSC environment architecture common among PowerPC processors describes programming model. also describes registers that unique MPC750.
Part MPC750 Microprocessor: Implementation
Instruction addressing modes-Section 2.2, "Instruction Set," describes PowerPC instruction addressing modes PowerPC operating environment architecture, defines describes PowerPC instructions implemented MPC750.
Cache implementation-Section 2.3, "On-Chip Cache Implementation," describes cache model that defined generally PowerPC processors virtual environment architecture. also provides specific details about MPC750 cache implementation. Exception model-Section 2.4, "Exception Model," describes exception model PowerPC operating environment architecture differences MPC750 exception model. Memory management-Section 2.5, "Memory Management," describes generally conventions memory management among PowerPC processors. This section also describes MPC750's implementation 32-bit PowerPC memory management specification. Instruction timing-Section 2.6, "Instruction Timing," provides general description instruction timing provided superscalar, parallel execution supported PowerPC architecture MPC750. Power management-Section 2.7, "Power Management," describes power management used reduce power consumption when processor, portions idle. Thermal management-Section 2.8, "Thermal Management," describes thermal management unit associated registers (THRM1-THRM3) exception used manage system activity that prevents exceeding system junction temperature thresholds. This particularly useful high-performance portable systems, which cannot same cooling mechanisms (such fans) that control overheating desktop systems. Performance monitor-Section 2.9, "Performance Monitor," describes performance monitor facility, which system designers help bring debug, optimize software performance.
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following sections summarize features MPC750, distinguishing those that defined architecture from those that unique MPC750 implementation. PowerPC architecture consists following layers, adherence PowerPC architecture described terms which following levels architecture implemented: PowerPC user instruction architecture (UISA)-Defines base user-level instruction set, userlevel registers, data types, floating-point exception model, memory models uniprocessor environment, programming model uniprocessor environment. PowerPC virtual environment architecture (VEA)-Describes memory model multiprocessor environment, defines cache control instructions, describes other aspects virtual environments. Implementations that conform also adhere UISA, necessarily adhere OEA. PowerPC operating environment architecture (OEA)-Defines memory management model, supervisor-level registers, synchronization requirements, exception model. Implementations that conform also adhere UISA VEA.
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PowerPC architecture allows wide range designs such features cache system interface Mthree levels architecture described implementations. MPC750 implementations support Sthe above. more information about PowerPC architecture, PowerPC Microprocessor Family: Programming Environments. Specific features MPC750 listed Section 1.1, "MPC750 Microprocessor Features." PowerPC Registers Programming Model PowerPC architecture defines register-to-register operations most computational instructions. Source operands instructions accessed from registers provided immediate values these embedded instruction opcode. three-register instruction format allows specification target
register distinct from source operands. Load store instructions transfer data between registers memory. PowerPC processors have levels privilege-supervisor mode operation (typically used operating system) user mode operation (used application software). programming models incorporate GPRs, FPRs, special-purpose registers (SPRs), several miscellaneous registers. Each PowerPC microprocessor also unique hardware implementation (HID) registers. Having access privileged instructions, registers, other resources allows operating system control application environment (providing virtual memory protecting operating-system critical machine resources). Instructions that control state processor, address translation mechanism, supervisor registers executed only when processor operating supervisor mode. Figure shows MPC750 registers available user supervisor level. numbers right SPRs indicate number that used syntax instruction operands access register.
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SUPERVISOR MODEL-OEA Configuration Registers USER MODEL-VEA
Time Base Facility (For Reading) Hardware Implementation Registers HID0 HID1 1008 1009 Processor Version Register Machine State Register
USER MODEL-UISA
Count Register General-Purpose Registers GPR0 GPR1 Link Register Floating-Point Registers FPR0 FPR1 GPR31 Instruction Registers IBAT0U IBAT0L
Memory Management Registers
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Performance Monitor Registers (For Reading)
Performance Counters UPMC1 UPMC2 UPMC3 UPMC4
Sampled InstructionA
Address USIA Monitor Control UMMCR0 UMMCR1
FPR31 Condition Register
SPRGs
IBAT1U DBAT1UUC IBAT1L DBAT1L IBAT2U DBAT2U DBAT2L IBAT2L IBAT3U DBAT3U IBAT3L DBAT3L
DBAT0U DBAT0L
Data Registers
Segment Registers
SR15 SDR1 SDR1
Exception Handling Registers
Data Address Register DSISR DSISR
SPRG0 SPRG1 SPRG2 SPRG3
Save Restore Registers SRR0 SRR1
Miscellaneous Registers
Floating-Point Status Control Register FPSCR External Access Register Time Base (For Writing) Data Address Breakpoint Register DABR 1013 Control Register L2CR 1017 Instruction Address Breakpoint Register IABR 1010 Decrementer
Performance Monitor Registers
Performance Counters PMC1 PMC2 PMC3 PMC4 Sampled Instruction Address
Power/Thermal Management Registers
Thermal Assist Unit Registers THRM1 THRM2 THRM3 1020 1021 1022 Instruction Cache Throttling Control Register ICTC 1019
Monitor Control MMCR0 MMCR1
These registers MPC750-specific registers. They supported other PowerPC processors. supported MPC740.
Figure MPC750 Microprocessor Programming Model-Registers
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following tables summarize PowerPC registers implemented MPC750; Table describes registers (excluding SPRs) defined architecture.
Table Architecture-Defined Registers MPC750 (Excluding SPRs)
Register Level User Function condition register (CR) consists eight 4-bit fields that reflect results certain operations, such move, integer floating-point compare, arithmetic, logical instructions, provide mechanism testing branching. floating-point registers (FPRs) serve data source destination floating. point instructions. These 64-bit registers hold either single- double-precision floatingpoint values.
FPRs
User
FPSCR
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GPRs
SR0- SR15
defines numerous special-purpose registers that serve variety functions, such providing controls, indicating status, configuring processor, performing special operations. During normal execution, program access registers, shown Figure depending program's access privilege (supervisor user, determined privilege-level (PR) MSR). GPRs FPRs accessed through operands that part instructions. Access registers explicit (that through specific instructions that purpose such Move Special-Purpose Register (mtspr) Move from Special-Purpose Register (mfspr) instructions) implicit, part execution instruction. Some registers accessed both explicitly implicitly. MPC750, SPRs bits wide. Table describes architecture-defined SPRs implemented MPC750. more information about these registers, PowerPC Microprocessor Family: Programming Environments.
Table Architecture-Defined SPRs Implemented MPC750
Register BATs Level User Supervisor Function link register (LR) used provide branch target address hold return address after branch link instructions. architecture defines block address translation registers (BATs), which operate pairs. There four pairs data BATs (DBATs) four pairs instruction BATs (IBATs). BATs used define configure blocks memory. count register (CTR) decremented tested branch-and-count instructions.
User floating-point status control register (FPSCR) contains floating-point exception signal bits, exception summary bits, exception enable bits, rounding control bits needed compliance with IEEE-754 standard. User GPRs serve data source destination integer instructions. Supervisor machine state register (MSR) definesEMprocessor state. contents saved when exception taken restored when exception handling completes. MPC750 implements MSR[POW], (defined architecture optional), which used enable power management feature. MPC750-specific MSR[PM] used mark process performance monitor. Supervisor sixteen 32-bit segment registers (SRs) define 4-Gbyte space sixteen 256-Mbyte segments. MPC750 implements segment registers arrays-a main array data accesses shadow array instruction accesses; Figure Loading segment entry with Move Segment Register (mtsr) instruction loads both arrays. mfsr reads master register, shown part data Figure instruction
User
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Table Architecture-Defined SPRs Implemented MPC750 (Continued)
Register DABR DSISR Level Supervisor User Supervisor User Supervisor Function optional data address breakpoint register (DABR) supports data address breakpoint facility. data address register (DAR) holds address access after alignment exception. decrementer register (DEC) 32-bit decrementing counter that provides schedule decrementer exceptions.
external access register (EAR) controls access external access facility through External Control Word Indexed (eciwx) External Control Word Indexed (ecowx) instructions.
processor version register (PVR) read-only register that identifies processor.
DSISR defines cause data access alignment exceptions.
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SDR1 SRR0 SRR1 SPRG0- SPRG3
Supervisor Supervisor
(SRR0) saves address used restarting Supervisor machine status save/restore register interrupted program when Return from Interrupt (rfi) instruction executes. Supervisor machine status save/restore register (SRR1) used save machine status exceptions restore machine status when instruction executed. Supervisor SPRG0-SPRG3 provided operating system use. User: read time base register (TB) 64-bit register that maintains time operates Supervisor: interval timers. consists 32-bit fields-time base upper (TBU) time base read/write lower (TBL).
User contains summary overflow bit, integer carry bit, overflow bit, field specifying number bytes transferred Load String Word Indexed (lswx) Store String Word Indexed (stswx) instruction.
SDR1 specifies page table format used virtual-to-physical page address translation.
Table describes SPRs MPC750 that defined PowerPC architecture.
Table MPC750-Specific Registers
Register HID0 HID1 IABR Level Function
Supervisor hardware implementation register (HID0) provides checkstop enables other functions. Supervisor hardware implementation register (HID1) allows software read configuration configuration signals. Supervisor instruction address breakpoint register (IABR) supports instruction address breakpoint exceptions. hold address compare with instruction addresses address match causes instruction address breakpoint exception. Supervisor instruction cache-throttling control register (ICTC) bits controlling interval which instructions fetched into instruction buffer instruction unit. This helps control MPC750's overall junction temperature. Supervisor cache control register (L2CR) used configure operate cache. bits enabling parity checking, setting L2-to-processor clock ratio, identifying type used cache implementation. (The cache feature supported MPC740.)
ICTC
L2CR
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Table MPC750-Specific Registers (Continued)
Register MMCR0- MMCR1 PMC1- PMC4 Level Function
Supervisor monitor mode control registers (MMCR0-MMCR1) used enable various performance monitoring interrupt functions. UMMCR0-UMMCR1 provide user-level read access MMCR0-MMCR1. Supervisor performance monitor counter registers (PMC1-PMC4) used count specified events. UPMC1-UPMC4 provide user-level read access these registers. Supervisor sampled instruction address register (SIA) holds instruction executing around time processor signals performance monitor interrupt condition. USIA register provides user-level read access SIA.
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NDoutput sample time. THRM3 Supervisor THRM3 used enable control UMMCR0- User user monitor mode control registers (UMMCR0-UMMCR1) provide user-level read UMMCR1 access MMCR0-MMCR1. UPMC1- User user performance monitorL counter registers (UPMC1-UPMC4) provide user-level UPMC4 read access PMC1-PMC4. USIA User user sampled instruction address register (USIA) provides user-level read access register. InstructionESet PowerPC instructions encoded single-word (32-bit) opcodes. Instruction formats consistent ARtypes, permitting efficient decoding occur parallel with operand accesses. This among instruction
fixed instruction length consistent format greatly simplifies instruction pipelining.
THRM1- THRM2
Supervisor THRM1 THRM2 provide compare junction temperature against user-provided thresholds. thermal assist unit (TAU) operated that thermal sensor output compared only threshold, selected THRM1 THRM2.
2.2.1 PowerPC Instruction
PowerPC instructions divided into following categories: Integer instructions-These include computational logical instructions. Integer arithmetic instructions Integer compare instructions Integer logical instructions Integer rotate shift instructions Floating-point instructions-These include floating-point computational instructions, well instructions that affect FPSCR. Floating-point arithmetic instructions Floating-point multiply/add instructions Floating-point rounding conversion instructions Floating-point compare instructions Floating-point status control instructions
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Load/store instructions-These include integer floating-point load store instructions. Integer load store instructions Integer load store multiple instructions Floating-point load store Primitives used construct atomic memory operations (lwarx stwcx. instructions) Flow control instructions-These include branching instructions, condition register logical instructions, trap instructions, other instructions that affect instruction flow. Branch trap instructions Condition register logical instructions Processor control instructions-These instructions used synchronizingImemory accesses management caches, TLBs, segment registers.
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Move to/from instructions Move to/from Synchronize Instruction synchronize Order loads stores Memory control instructions-These instructions provide control caches, TLBs, SRs.
Supervisor-level cache management instructions User-level cache instructions Segment register manipulation instructions Translation lookaside buffer management instructions does indicate
This grouping instructions.
execution unit that executes particular instruction group
Integer instructions operate byte, half-word, word operands. Floating-point instructions operate single-precision (one word) double-precision (one double word) floating-point operands. PowerPC architecture uses instructions that four bytes long word-aligned. provides byte, half-word, word operand loads stores between memory GPRs. also provides word doubleword operand loads stores between memory floating-point registers (FPRs). Computational instructions modify memory. memory operand computation then modify same another memory location, memory contents must loaded into register, modified, then written back target location with distinct instructions. PowerPC processors follow program flow when they normal execution state. However, flow instructions interrupted directly execution instruction asynchronous event. Either kind exception cause several components system software invoked. Effective address computations both data instruction accesses 32-bit unsigned binary arithmetic. carry from ignored 32-bit implementations.
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MPC750 instruction defined follows: MPC750 provides hardware support 32-bit PowerPC instructions. MPC750 implements following instructions optional PowerPC architecture: External Control Word Indexed (eciwx) External Control Word Indexed (ecowx) Floating Select (fsel) Floating Reciprocal Estimate Single-Precision (fres) Floating Reciprocal Square Root Estimate (frsqrte) Store Floating-Point Integer Word (stfiwx)
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On-Chip Cache ImplementationD following subsections describe PowerPC architecture'sC treatment cache general, MPC750-specific implementation, respectively. 2.3.1 PowerPC Cache Model PowerPC architecture does define hardware aspects cache implementations. example, PowerPC processors have unified caches, separate instruction data caches (Harvard architecture), cache all. PowerPC microprocessors control following memory access modes page block basis: mode Write-back/write-through mode Caching-inhibited
Memory coherency caches physically addressed, data cache operate either write-back write-through mode specified PowerPC architecture. PowerPC architecture defines term `cache block' cacheable unit. define cache management instructions programmer affect cache contents.
2.3.2 MPC750 Cache Implementation
MPC750 cache implementation described Section 1.1.4, "On-Chip Instruction Data Caches," Section 1.1.5, Cache Implementation (Not Supported MPC740)." also contains 64-entry BTIC that provides immediate access cached target instructions. more information, Section 1.1.2.2, "Branch Processing Unit (BPU)."
Exception Model
following sections describe PowerPC exception model MPC750 implementation.
2.4.1 PowerPC Exception Model
PowerPC exception mechanism allows processor interrupt instruction flow handle certain situations caused external signals, errors, unusual conditions arising from instruction execution. When exceptions occur, information about state processor saved certain registers processor begins execution address (exception vector) predetermined each exception. Exception processing occurs supervisor mode.
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Although multiple exception conditions single exception vector, more specific condition determined examining register associated with exception-for example, DSISR FPSCR. Additionally, some exception conditions enabled disabled explicitly software. PowerPC architecture requires that exceptions handled program order; therefore, although particular implementation recognize exception conditions order, they handled order. When instruction-caused exception recognized, unexecuted instructions that appear earlier instruction stream, including that undispatched, required complete before exception taken, exceptions those instructions cause must also handled first. Likewise, asynchronous, precise exceptions recognized when they occur, handled until instructions currently completion queue successfully retire generate exception, completion queue is.emptied.
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Unless catastrophic condition causes system reset machine check exception,,only exception handled time. example, instruction encounters multiple exception conditions, those conditions instruction processing handled sequentially. After exception handler handles exception, continues until next exception condition encountered. RecognizingDU handling exception conditions sequentially guarantees that exceptions recoverable.
When exception taken, information about processor before exception taken saved Estate SRR0 SRR1. Exception handlers should save information stored SRR0 SRR1 early prevent program state from being lost system reset machine check exception instruction-caused exception exception handler, before enabling external interrupts.
exceptions: PowerPC architecture supports four types Synchronous, precise-These caused instructions. instruction-caused exceptions handled precisely; that machine state time exception occurs known means that (excluding trap system call exceptions) address completely restored. This provided exception handler that neither faulting instruction faulting instruction subsequent instructions code stream will complete execution before exception
taken. Once exception processed, execution resumes address faulting instruction alternate address provided exception handler). When exception taken trap system call instruction, execution resumes address provided handler. Synchronous, imprecise-The PowerPC architecture defines imprecise floating-point exception modes, recoverable nonrecoverable. Even though MPC750 provides means enable imprecise modes, implements these modes identically precise mode (that enabled floating-point exceptions always precise). Asynchronous, maskable-The PowerPC architecture defines external decrementer interrupts maskable, asynchronous exceptions. When these exceptions occur, their handling postponed until next instruction, exceptions associated with that instruction, completes execution. instructions execution units, exception taken immediately upon determination correct restart address (for loading SRR0). shown Table MPC750 implements additional asynchronous, maskable exceptions. Asynchronous, nonmaskable-There nonmaskable asynchronous exceptions: system reset machine check exception. These exceptions recoverable, provide limited degree recoverability. Exceptions report recoverability through MSR[RI] bit.
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MPC750 exception classes described above shown Table
Table MPC750 Microprocessor Exception Classifications
Synchronous/Asynchronous Precise/Imprecise Asynchronous, nonmaskable Asynchronous, maskable Imprecise Precise Exception Type Machine check, system reset External, decrementer, system management, performance monitor, thermal management interrupts Instruction-caused exceptions
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Table describes Although exceptions have other characteristics, such priority recoverability, synchronous imprecise categories exceptions MPC750 handles uniquely. Table includes exceptions; although PowerPC architecture supports impreciseON handling floating-point exceptions, MPC750 implements these exception modes precisely. TableI5 lists MPC750 exceptions conditions that cause them. Exceptions specific MPC750 indicated. Table Exceptions Conditions Vector Offset Exception Type Causing Conditions (hex) Reserved 00000 System reset 00100V Assertion either HRESET SRESET power-on reset Machine check Assertion during data transaction, assertion MCP, AR00200
address, data, parity error. MSR[ME] must set. 00300 specified PowerPC architecture. misses load, store, cache operations, exception occurs page fault occurs. defined PowerPC architecture. MSR[EE] asserted. floating-point load/store, stmw, stwcx., lmw, lwarx, eciwx ecowx instruction operand word-aligned. multiple/string load/store operation attempted little-endian mode. operand dcbz memory that write-through-required caching-inhibited cache disabled
Synchronous
Precise
External interrupt Alignment
00400 00500 00600
Program Floating-point unavailable Decrementer
00700 00800
defined PowerPC architecture. defined PowerPC architecture.
00900
defined PowerPC architecture, when most-significant register changes from MSR[EE]
Reserved System call
00A00-00BFF 00C00 Execution System Call (sc) instruction.
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Table Exceptions Conditions (Continued)
Exception Type Trace Vector Offset (hex) 00D00 Causing Conditions MSR[SE] branch instruction completes MSR[BE] Unlike architecture definition, isync does cause trace exception. MPC750 does generate exception this vector. Other PowerPC processors this vector floating-point assist exceptions.
Reserved
00E00
Reserved
00E10-00EFF
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complete, IABR[TE] Instruction address 01300 IABR[0-29] matches EA[0-29] next instruction breakpoint matches MSR[IR], IABR[BE] System management 01400 MSR[EE] asserted. interrupt Reserved 01500-016FF Thermal management enabled, junction temperature exceeds Thermal management 01700 threshold specified THRM1 THRM2, MSR[EE] interrupt Reserved 01800-02FFF 1MPC750-specific Management Memory
Performance monitor 00F00
limit specified register reached MMCR0[ENINT]
following subsections describe memory management features PowerPC architecture, MPC750 implementation, respectively.
2.5.1 PowerPC Memory Management Model
primary functions translate logical (effective) addresses physical addresses memory accesses provide access protection blocks pages memory. There types accesses generated MPC750 that require address translation-instruction accesses, data accesses memory generated load, store, cache control instructions. PowerPC architecture defines different resources 64-bit processors; MPC750 implements 32-bit memory management model. memory-management model provides Gbytes logical address space accessible supervisor user programs with 4-Kbyte page size 256-Mbyte segment size. block sizes range from Kbyte Mbyte software selectable. addition, defines interim 52-bit virtual address hashed page tables generating 32-bit physical addresses. architecture also provides independent four-entry arrays instructions data that maintain address translations blocks memory. These entries define blocks that vary from Kbytes Mbytes. arrays maintained system software. PowerPC exception model support demand-paged virtual memory. Virtual memory management permits execution programs larger than size physical memory; demand-paged implies that individual pages loaded into physical memory from system memory only when they first accessed executing program.
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hashed page table variable-sized data structure that defines mapping between virtual page numbers physical page numbers. page table size power starting address multiple size. page table contains number page table entry groups (PTEGs). PTEG contains eight page table entries (PTEs) eight bytes each; therefore, each PTEG bytes long. PTEG addresses entry points table search operations. Setting MSR[IR] enables instruction address translations MSR[DR] enables data address translations. cleared, respective effective address same physical address.
2.5.2 MPC750 Memory Management Implementation
MPC750 implements separate MMUs instructions data. implements copy.of segment registers instruction MMU, however, read write accesses (mfsr mtsr) IareC handled through segment registers implemented part data MMU. MPC750R, described Section 1.1.3, "Memory Management Units (MMUs)."
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(referenced) updated memory necessary) during table search miss. Updates (changed) treated like misses. complete table search performed entire entry rewritten update bit.
Instruction Timing
MPC750 pipelined, superscalar processor. pipelined processor which instruction processing divided into discrete stages, allowing work done different instructions each stage. example, after instruction completes stage, pass next stage leaving previous stage available subsequent instruction. This improves overall instruction throughput.
superscalar processor that issues multiple independent instructions into separate execution units, allowing instructions execute parallel. MPC750 independent execution units, integer instructions, each floating-point instructions, branch instructions, load/store instructions, system register instructions. Having separate GPRs FPRs allows integer, floating-point calculations, load store operations occur simultaneously without interference. Additionally, rename buffers provided allow operations post execution results subsequent instructions without committing them architected FPRs GPRs. shown Figure common pipeline MPC750 four stages through which instructions must pass-fetch, decode/dispatch, execute, complete/write back. Some instructions occupy multiple stages simultaneously some individual execution units have additional stages. example, floatingpoint pipeline consists three stages through which floating-point instructions must pass.
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Fetch Dispatch Maximum three-instruction dispatch clock cycle (includes branch instruction) Execute Stage Maximum four-instruction fetch clock cycle
FPU1 FPU2 FPU3
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Complete (Write Back)
Note that Figure does show features, such reservation stations rename buffers that reduce stalls improve instruction throughput. instruction pipeline MPC750 four major pipeline stages, described follows:
Figure Pipeline Diagram
LSU2
LSU1
Maximum two-instruction completion clock cycle
fetch pipeline stage primarily involves retrieving instructions from memory system determining location next instruction fetch. decodes branches during fetch stage removes those that update from instruction stream.
dispatch stage responsible decoding instructions supplied instruction fetch stage determining which instructions dispatched current cycle. source operands instruction available, they read from appropriate register file rename register execute pipeline stage. source operand available, dispatch provides that indicates which rename register will supply operand when becomes available. dispatch stage, dispatched instructions their operands latched appropriate execution unit. Instructions executed IUs, FPU, SRU, dispatched from bottom positions instruction queue. single clock cycle, maximum instructions dispatched these execution units combination. When instruction dispatched, assigned position six-entry completion queue. branch instruction issued same clock cycle maximum three-instruction dispatch.
During execute pipeline stage, each execution unit that executable instruction executes selected instruction (perhaps over multiple cycles), writes instruction's result into appropriate rename register, notifies completion stage that instruction finished execution. case internal exception, execution unit reports exception completion pipeline stage (except FPU) discontinues instruction execution until exception handled. exception signaled until that instruction next completed. Execution most floating-point instructions pipelined within allowing three instructions executing concurrently. stages multiply, add, round-
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convert. Execution most load/store instructions also pipelined. load/store unit pipeline stages. first stage effective address calculation translation second stage accessing data cache. complete pipeline stage maintains correct architectural machine state transfers execution results from rename registers GPRs FPRs (and some instructions) instructions retired. with dispatching instructions from instruction queue, instructions retired from bottom positions completion queue. completion logic detects instruction causing exception, following instructions cancelled, their execution results rename registers discarded, instructions fetched from appropriate exception vector.
Because PowerPC architecture applied such wide variety implementations, instruction timing varies among PowerPC processors.
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Power Management
MPC750 provides four power modes, selectable setting appropriate control bits HID0 registers. four power modes follows: Full-power-This default power state MPC750. MPC750 fully powered Afull processor clock speed. dynamic power internal functional units operating management mode enabled, functional units that idle will automatically enter low-power state without affecting performance, software execution, external hardware.
Doze-All functional units MPC750 disabled except time base/decrementer registers snooping logic. When processor doze mode, external asynchronous interrupt, system management interrupt, decrementer exception, hard soft reset, machine check brings theH MPC750 into full-power state. MPC750 doze mode maintains fully powered state locked system external clock input (SYSCLK) transition full-power state takes only processor clock cycles. Nap-The mode further reduces power consumption disabling snooping, leaving only time base register powered state. MPC750 returns full-power state upon receipt external asynchronous interrupt, system management interrupt, decrementer exception, hard soft reset, machine check input (MCP). return full-power state from state takes only processor clock cycles. When processor mode, QACK negated, processor doze mode support snooping. Sleep-Sleep mode minimizes power consumption disabling internal functional units, after which external system logic disable SYSCLK. Returning MPC750 fullpower state requires enabling SYSCLK, followed assertion external asynchronous interrupt, system management interrupt, hard soft reset, machine check input (MCP) signal after time required relock PLL.
Thermal Management
MPC750's thermal assist unit (TAU) provides control heat dissipation. This ability particularly useful portable computers, which, power consumption size limitations, cannot desktop cooling solutions such fans. Therefore, better heat sink designs coupled with intelligent thermal management critical importance high performance portable systems. Primarily, thermal management system monitors regulates system's operating temperature. example, temperature about exceed limit, system made slow down even suspend operations temporarily order lower temperature.
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thermal management facility also ensures that processor's junction temperature does exceed operating specification. avoid inaccuracies that arise from measuring junction temperature with external thermal sensor, MPC750's on-chip thermal sensor logic tightly couples thermal management implementation. consists thermal sensor, digital-to-analog convertor, comparator, control logic, dedicated SPRs described Section 2.1, "PowerPC Registers Programming Model." does following: Compares junction temperature against user-programmable thresholds Generates thermal management interrupt temperature crosses threshold
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temperature against userC THRM1 THRM2 provide ability compare theIjunction provided thresholds. Having dual thresholds gives theM thermal management software finer control junction temperature. single threshold mode, thermal sensor output compared only threshold either THRM1 THRM2. THRM3 used enable control comparator output sample time. thermal management logic manages thermal management interrupt generation time multiplexed comparisons dual threshold mode well other control functions. Instruction cache throttling provides control MPC750's overall junction temperature determining fetched. This feature accessed through ICTC register. interval which instructions
controlled through privileged mtspr/mfspr instructions three SPRs provided configuring controlling sensor control logic, which function follows:
Enables user estimate junction temperature software successive approximation routine
Performance Monitor
MPC750 incorporates performance monitor facility that system designers help bring debug, optimize software performance. performance monitor counts events during execution code, relating dispatch, execution, completion, memory accesses. performance monitor incorporates several registers that read written supervisor-level software. User-level versions these registers provide read-only access user-level applications. These registers described Section 2.1, "PowerPC Registers Programming Model." Performance monitor control registers, MMCR0 MMCR1 used specify which events counted conditions which performance monitoring interrupt taken. Additionally, sampled instruction address register, (USIA), holds address first instruction complete after counter overflowed. Attempting write user-read-only performance monitor register causes program exception, regardless MSR[PR] setting. When performance monitoring interrupt occurs, program execution continues from vector offset 0x00F00.
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