ML145053 MC145053
|
|
|
Top Searches for this datasheet
MC145053* - MC145053*
ML145053 - ML145053
MC145053 - MC145053
ML145053
10-Bit Converter With Serial Interface
Legacy Device: Motorola MC145053
This ratiometric 10-bit serial interface port provide communication with MCUs MPUs. Either 16-bit format used. The16-bit format continuous 16-bit stream intermittent 8bit streams. converter operates from single power supply with external trimming required. Reference voltages down accommodated. ML145053 internal clock oscillator operate dynamic conversion sequence end-of-conversion (EOC) output. Analog Input Channels with Internal Sample-and-Hold Operating Temperature Range: 125°C Successive Approximation Conversion Time: Maximum Maximum Sample Rate: 20.4 ks/s Analog Input Range with 5-Volt Supply: Monotonic with Missing Codes Direct Interface Motorola National MICROWIRESerial DataPorts Digital Inputs/Outputs TTL, NMOS, CMOS Compatible Power Consumption: Chip Complexity: 1630 Elements (FETs, Capacitors, etc.) Application Note AN1062 Operation with QSPI
BLOCK DIAGRAM
Vref PLASTIC CASE
CASE 751A
CROSS REFERENCE/ORDERING INFORMATION MOTOROLA PACKAGE LANSDALE MC145053P ML145053CP MC145053D ML145053-5P
Note: Lansdale lead free (Pb) product, becomes available, will identified part number prefix change from MLE.
ASSIGNMENT
SCLK Dout Vref
10-BIT WITH SAMPLE HOLD
INTERNAL TEST VOLTAGES
ANALOG Dout SCLK
SUCCESSIVE APPROXIMATION REGISTER ADDRESS REGISTER
DATA REGISTER AUTO-ZEROED COMPARATOR DIGITAL CONTROL LOGIC
MICROWIRE trademark National Semiconductor Corp.
Page
www.lansdale.com
Issue
ML145053
LANSDALE Semiconductor, Inc.
MAXIMUM RATINGS*
Symbol Vref Vout Iout IDD, Tstg Parameter Supply Voltage (Referenced VSS) Reference Voltage Analog Ground Input Voltage, Analog Digital Input Output Voltage Input Current, Output Current, Supply Current, Pins Storage Temperature Lead Temperature, from Case Seconds Value Vref Unit This device contains protection circuitry guard against damage high static voltages electric fields. However, precautions must taken avoid applications voltage higher than maximum rated voltages this high-impedance circuit. proper operation, Vout should constrained range (Vin Vout) VDD. Unused inputs must always tied appropriate logic voltage level (e.g., either VDD). Unused outputs must left open.
Maximum Ratings those values beyond which damage device occur. Functional operation should restricted Operation Ranges below.
OPERATION RANGES (Applicable Guaranteed Limits)
Symbol Vref Vin, Vout Parameter Supply Voltage, Referenced Reference Voltage Analog Ground Analog Input Voltage (See Note) Digital Input Voltage, Output Voltage Ambient Operating Temperature Value Vref Vref Unit
NOTE: Analog input voltages greater than Vref convert full scale. Input voltages less than convert zero. Vref descriptions.
ELECTRICAL CHARACTERISTICS
(Voltages Referenced VSS, Full Temperature Voltage Ranges Operation Ranges Table, unless otherwise indicated) Symbol Iref Parameter Minimum High-Level Input Voltage (Din, SCLK, Maximum Low-Level Input Voltage (Din, SCLK, Minimum High-Level Output Voltage (Dout, EOC) Minimum Low-Level Output Voltage (Dout, EOC) Maximum Input Leakage Current (Din, SCLK, Maximum Three-State Leakage Current (Dout) Maximum Power Supply Current Maximum Static Analog Reference Current (Vref) Maximum Analog Input Leakage Current between deselected inputs selected input (AN0-AN4) Iout Iout Iout Iout Vout VDD, Outputs Open Vref VDD, Test Condition Guaranteed Limit Unit
Page
www.lansdale.com
Issue
ML145053
LANSDALE Semiconductor, Inc.
CONVERTER ELECTRICAL CHARACTERISTICS
(Full Temperature Voltage Ranges Operation Ranges Table) Characteristic Resolution Maximum Nonlinearity Maximum Zero Error Maximum Full-Scale Error Maximum Total Unadjusted Error Maximum Quantization Error Absolute Accuracy Maximum Conversion Time Data Transfer Time Sample Acquisition Time Minimum Total Cycle Time Maximum Sample Rate Definition Test Conditions Number bits resolved converter Maximum difference between ideal actual transfer function Difference between maximum input voltage ideal actual zero output code Difference between minimum input voltage ideal actual full-scale output code Maximum nonlinearity, zero error, full-scale error Uncertainty converter resolution Difference between actual input voltage full-scale weighted equivalent binary output code, error sources included Total time perform single analog-to-digital conversion Total time transfer digital serial data into device Analog input acquisition time window Total time transfer serial data, sample analog input, perform conversion; SCLK Rate which analog inputs sampled; SCLK Guaranteed Limit 1-1/2 20.4 Unit Bits SCLK cycles SCLK cycles ks/s
Page
www.lansdale.com
Issue
ML145053
LANSDALE Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS
(Full Temperature Voltage Ranges Operation Ranges Table) Figure Symbol Clock Frequency, SCLK Note: Refer twH, below tPLH, tPHL tPLZ, tPHZ tPZL, tPZH tCSd tCAs tPHL tTLH, tTHL Cout Minimum Clock High Time, SCLK Minimum Clock Time, SCLK Maximum Propagation Delay, SCLK Dout Minimum Hold Time, SCLK Dout Maximum Propagation Delay, Dout High-Z Maximum Propagation Delay, Dout Driven Minimum Setup Time, SCLK Minimum Hold Time, SCLK Maximum Delay Time, Dout (MSB) Minimum Setup Time, SCLK Minimum Time Required Between 10th SCLK Falling Edge Allow Conversion Maximum Delay Between 10th SCLK Falling Edge Abort Conversion Minimum Hold Time, Last SCLK Maximum Propagation Delay, 10th SCLK Maximum Input Rise Fall Times Maximum Output Transition Time, Output Maximum Input Capacitance Maximum Three-State Output Capacitance SCLK, Dout SCLK Din, Parameter (10-bit xfer) (11- 16-bit xfer) (10- 16-bit xfer) Max) Guaranteed Limit Note 2.425 Note 2.35 Unit
NOTES: After 10th SCLK falling edge least SCLK rising edge must occur within 18.5 edge received immediately after active transition pin.
Page
www.lansdale.com
Issue
ML145053
LANSDALE Semiconductor, Inc.
SWITCHING WAVEFORMS
SCLK tPLH, tPHL Dout tTLH, tTHL Dout tPZH, tPZL tPHZ, tPLZ
Figure
Figure
tTLH VALID SCLK Dout VALID
NOTE: driven only when active (low).
Figure
Figure
FIRST CLOCK LAST CLOCK
SCLK
10TH CLOCK
tPHL
tTHL
SCLK
Figure
Figure
TEST POINT Dout DEVICE UNDER TEST TEST POINT
DEVICE UNDER TEST
Figure Test Circuit
Figure Test Circuit
Page
www.lansdale.com
Issue
ML145053
LANSDALE Semiconductor, Inc.
DESCRIPTIONS DIGITAL INPUTS OUTPUT various serial bit-stream formats ML145053 illustrated timing diagrams Figures through Table assists selection appropriate diagram. Note that accepts clocks which makes (Serial Peripheral Interface) compatible.
Table Timing Diagram Selection
Clocks Serial Transfer Using Serial Transfer Interval Don't Care Don't Care Shorter than Conversion Shorter than Conversion Longer than Conversion Longer than Conversion Figure
Active-Low Chip Select Input (Pin Chip select initializes chip perform conversions provides 3-state control data output (Dout). While inactive high, forces Dout high-impedance state disables data input (Din) serial clock (SCLK) pins. high-to-low transition resets serial dataport synchronizes data stream. remain active during conversion cycle stay active state multiple serial transfers inactive high after each transfer. kept active between transfers, length each transfer limited either SCLK cycles. inactive high state between transfers, each transfer anywhere from to16 SCLK cycles long. SCLK description more detailed discussion these requirements. Spurious chip selects caused system noise minimized internal circuitry. transitions recognized valid only level maintained about after transition. NOTE inactive high after 10th SCLK cycle then goes active before conversion complete, conversion aborted chip enters initial state, ready another serial transfer/conversion sequence. this point, output data register contains result from conversion before aborted conversion. Note that last step conversion sequence update output data register with result. Therefore, goes active attempt abort conversion close conversion sequence, result register corrupted chip could thrown sync with processor until toggled again (refer Electrical Characteristics spec tables).
Dout Serial Data Output Conversion Result (Pin This output high-impedance state when inactive high. When chip recognizes valid active Dout taken high-impedance state driven with previous conversion result. (For first transfer after power-up, data Dout undefined entire transfer.) value Dout changes second most significant result upon first falling edge SCLK.The remaining result bits shifted order, with appearing Dout upon ninth falling edge SCLK. Note that order transfer LSB. Upon the10th falling edge SCLK, Dout immediately driven allowed that transfers more than SCLKs read zeroes unused LSBs. When held active between transfers, Dout driven from level conversion result three cases: Case upon 16th SCLK falling edge transfer longer than conversion time (Figure 14); Case upon completion conversion 16-bit transfer interval shorter than conversion (Figure 12); Case upon completion conversion 10-bit transfer (Figure 10). Serial Data Input (Pin four-bit serial input stream begins with analog address user test mode) that converted next. address shifted first four rising edges SCLK. After four address bits have been received, data ignored remainder present serial transfer. Table Applications Information. SCLK Serial Data Clock (Pin This clock input drives internal state machine perform three major functions: drives data shift registers simultaneously shift next address from shift previous conversion result Dout pin, begins sampling analog voltage onto RCDAC soon address available, transfers control conversion state machine after last previous conversion result been shifted Dout pin. serial data shift registers completely static, allowing SCLK rates down There some cases, however, that require minimum SCLK frequency discussed later this section. least SCLK cycles required each simultaneous data transfer. 16-bit format used, SCLK continuous 16-bit stream intermittent 8-bit streams. After serial port been initiated perform serial transfer*, address shifted
*The serial port initiated three ways: recognized falling edge, conversion port performing either 10-bit 16-bit "shorter-than-conversion" transfer with active between transfers, 16th falling edge SCLK port performing 16-bit "longer-than-conversion" transfers with active between transfers.
Page
www.lansdale.com
Issue
ML145053
LANSDALE Semiconductor, Inc.
first four rising edges SCLK, previous 10-bit conversion result shifted first nine falling edges SCLK. After fourth rising edge SCLK, address available; therefore, next edge SCLK (the fourth falling edge), analog input voltage selected input begins charging continues until tenth falling edge SCLK. After this tenth SCLK edge, analog input voltage disabled from begins "hold" portion conversion sequence. Also upon this tenth SCLK edge, control internal circuitry transferred internal clock oscillator which drives successive approximation logic complete conversion. SCLK cycles used during each transfer, then there constraint minimum SCLK frequency. Specifically, there must least rising edge SCLK before conversion complete. SCLK frequency rising edge does occur during conversion, chip thrown sync with processor needs toggled order restore proper operation. SCLKs used transfer, then there lower frequency limit SCLK. Also note that operated such that inactive high between transfers, then number SCLK cycles transfer anything between cycles, "rising edge" constraint still effect more than SCLKs used. stays active multiple transfers, number SCLK cycles must either 16.) End-of-Conversion Output (Pin goes tenth falling edge SCLK. low-tohigh transition occurs when conversion complete data ready transfer. ANALOG INPUTS TEST MODES through Analog Multiplexer Inputs (Pins input addressed loading into address register. addressed Table shows input format 16-bit stream. features break-before-make switching structure minimize noise injection into analog inputs. source resistance driving these inputs must During normal operation, leakage currents through analog
from unselected channels selected channel leakage currents through protection diodes selected channel occur. These leakage currents cause offset voltage appear across series source resistance selected channel. Therefore, source resistance greater than (Lansdale test condition) induce errors excess guaranteed specifications.There three tests available that verify functionality control logic well successive approximation comparator. These tests performed addressing they convert voltage (Vref VAG)/2, VAG, Vref, respectively. voltages obtained internally sampling Vref onto appropriate elements during sample phase. Addressing produces output $200 (half scale), $000, $3FF (full scale), respectively, converter functioning properly. However, deviation from these values occurs presence sufficient system noise (external chip) onVDD, VSS, Vref, VAG. POWER REFERENCE PINS Device Supply Pins (Pins normally connected digital ground; connected positive digital supply voltage. frequency (VDD VSS) variations over range volts affect accuracy. (See Operations Ranges Table restrictions Vref relative VSS.) Excessive inductance lines, automatic test equipment, cause offsets LSB. bypass capacitor across these pins recommended. Vref Analog Reference Voltage Pins (Pins Analog reference voltage pins which determine lower upper boundary conversion. Analog input voltages Vref produce full scale output input voltages produce output zero. CAUTION: analog input voltage must VDD. conversion result ratiometric Vref VAG. Vref must noisefree possible avoid degradation conversion. Ideally, Vref should single-point connected voltage supply driving system's transducers. 0.22 bypass capacitor across these pins strongly urged.
Page
www.lansdale.com
Issue
ML145053
LANSDALE Semiconductor, Inc.
Dout
D9-MSB
HIGH IMPEDANCE
SCLK
SHIFT ADDRESS, SIMULTANEOUSLY SHIFT PREVIOUS CONVERSION VALUE INITIALIZE CONVERSION INITERVAL
RE-INITIALIZE
Figure Timing 10-Clock Transfer Using
MUST HIGH POWER
Dout
D9-MSB
LEVEL
SCLK
CONVERSION INITERVAL
INITIALIZE
SHIFT ADDRESS, SIMULTANEOUSLY SHIFT PREVIOUS CONVERSION VALUE
Figure Timing 10-Clock Transfer Using
NOTES: result previous conversion. address next conversion.
Page
www.lansdale.com
Issue
ML145053
Page
D9-MSB LEVEL HIGH IMPEDANCE SHIFT ADDRESS SIMUTANEOUSLY SHIFT PREVIOUS CONVERSION VALUE CONVERSION INTERVAL RE-INITIALIZE LEVEL SAMPLE ANALOG OUTPUT CONVERSION INTERVAL
Dout
SCLK
INITIALIZE
Figure Timing 16-Clock Transfer Using (Serial Transfer Interval Shorter than Conversion)
www.lansdale.com
Dout
D9-MSB
SCLK
INITIALIZE
SHIFT ADDRESS SIMUTANEOUSLY SHIFT PREVIOUS CONVERSION VALUE
Figure Timing 16-Clock Transfer Using (Serial Transfer Interval Shorter Than Conversion)
NOTES: result previous conversion. address next conversion.
LANSDALE Semiconductor, Inc.
Issue
ML145053
Page
HIGH IMPEDANCE D9-MSB LEVEL SAMPLE ANALOG INPUT NOTE SHIFT ADDRESS SIMULTANEOUSLY SHIFT PREVIOUS CONVERSION VALUE CONVERSION INTERVAL RE-INITIALIZE
Dout
SCLK
INITIALIZE
Figure Timing 16-Clock Transfer Using (Serial Transfer Interval Longer Than Conversion)
www.lansdale.com
SAMPLE ANALOG INPUT CONVERSION INTERVAL
D9-MSB
LEVEL
NOTE
SHIFT ADDRESS SIMULTANEOUSLY SHIFT PREVIOUS CONVERSION VALUE
INITIALIZE
Figure Timing 16-Clock Transfer Using (Serial Transfer Interval Longer Than Conversion)
NOTES: result previous conversion. address next conversion. *NOTES: 11th SCLK rising edge must occur before conversion complete. Otherwise serial port thrown sync with microprocessor remainder transfer.
LANSDALE Semiconductor, Inc.
Issue
ML145053
LANSDALE Semiconductor, Inc.
Legacy Applications Information
DESCRIPTION This example application ML145053 interfaces four analog signals microprocessor. Figure illustrates ML145053 used cost effective means simplify this type circuit design. Utilizing ADC, four analog inputs interfaced CMOS NMOS microprocessor with serial peripheral interface (SPI) port. Processors with National Semiconductor's MICROWIRE serial port also used. Full duplex operation optimizes throughput this system. DIGITAL DESIGN CONSIDERATIONS Motorola's MC68HC05C4 CMOS chosen reduce power supply size cost. NMOS MCUs used power consumption critical. bypass capacitor should closely mounted ADC. ML145053 end-of-conversion (EOC) signal output define when data ready. ANALOG DESIGN CONSIDERATIONS Analog signal sources with output impedances less than directly interfaced ADC, eliminating need buffer amplifiers. Separate lines connect Vref pins with controllers provide isolation from system noise. Although indicated Figure Vref sensor output lines need shielded, depending their length electrical environment. This should verified during prototyping with oscilloscope. shielding required, twisted pair foil-shielded wire (not coax) appropriate this frequency application. wire pair shield must VAG. reference circuit voltage volts used application shown Figure However, reference circuitry simplified tying system ground Vref system's positive supply. (See Figure 16.) bypass capacitor approximately 0.22 across theVref pins recommended. These pins adjacent package which facilitates mounting capacitor very close ADC. SOFTWARE CONSIDERATIONS software flow acquisition straight forward. four analog inputs, through AN3, scanned reading analog value previously addressed channel into sending address next channel read ADC, simultaneously. designer utilizing ML145053 end-of-conversion signal define conversion interval. used generate interrupt, which serviced reading serial data from ADC. software flow should then process format data. When this used with 16-bit (2-byte) transfer, there types offsets involved. first type offset, channel information sent ADCs offset bits. That 16-bit stream, only first bits MSBs) contain channel information. balance bits don't cares. This results don't-care nibbles, shown Table second type offset conversion result returned from ADC; this offset bits. 16-bitstream, first bits MSBs) contain conversion result. last bits zeroes. hexadecimal result shown first column Table second column shows result after offset removed micro-processor routine. 16bit format used, transfer continuous 16-bit stream intermittent 8-bitstreams.
Page
www.lansdale.com
Issue
ML145053
LANSDALE Semiconductor, Inc.
Legacy Applications Information
Table Programmer Guide 16-Bit Transfers: Input Code
Input Address $0XXX $1XXX $2XXX $3XXX $4XXX $5XXX $6XXX $7XXX $8XXX $9XXX $AXXX $BXXX $CXXX $DXXX $EXXX $FXXX Channel Converted Next None None None None None None None None
Table Programmer Guide 16-Bit Transfers: Output Code
Conversion Result Without Offset Removed $0000 $0040 $0080 $00C0 $0100 $0140 $0180 $01C0 $0200 $0240 $0280 $02C0 $FF40 $FF80 $FFC0 Conversion Result With Offset Removed $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $03FD $03FE $03FF
Comment Allowed Allowed Allowed Allowed Allowed Allowed Half Scale Test: Output $8000 Zero Test: Output $0000 Full Scale Test: Output $FFC0 Allowed Allowed
Value Zero Zero Zero LSBs Zero LSBs Zero LSBs Zero LSBs Zero LSBs Zero LSBs Zero LSBs Zero LSBs Zero LSBs Zero LSBs Full Scale LSBs Full Scale Full Scale
0.22µF Vref ANALOG SENSORS, ETC. ML145053 SCLK Dout PORT
VOLT REFERENCE CIRCUIT
Figure Example Application
Page
www.lansdale.com
Issue
ML145053
LANSDALE Semiconductor, Inc.
Legacy Applications Information
DIGIGAL ANALOG Vref CONNECT
SUPPLY
SENSORS, ETC.
0.22
ML145053
ANALOG DIGITAL
CONNECT
Figure Alternate Configuration Using Digital Supply Reference Voltage
Compatible Motorola MCUs/MPUs
This complete listing Motorola's MCUs/MPUs. Contact your Motorola representative need additional information. Instruction M6805 Memory (Bytes) 2096 2096 4160 4160 4160 7700 EEPROM 4160 Motorla Part Number MC68HC05C2 MC68HC05C3 MC68HC05C4 MC68HSC05C4 MC68HSC05C8 MC68HCL05C4 MC68HCL05C8 MC68HC05C8 MC68HC805C4 MC68HC000
M68000
Serial Peripheral Interface. Serial Communication Interface. High Speed. Power
Page
www.lansdale.com
Issue
ML145053
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
PLASTIC (ML145053CP) CASE 646-06
NOTES: LEADS WITHIN 0.13 (0.005) RADIUS TRUE POSITION SEATING PLANE MAXIMUM MATERIAL CONDITION DIMENSION CENTER LEADS WHEN FORMED PARALLEL DIMENSION DOES INCLUDE MOLD FLASH. ROUNDED CORNERS OPTIONAL
INCHES 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 0.052 0.095 0.008 0.015 0.115 0.135 0.300 0.015 0.039 MILLIMETERS 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 1.32 2.41 0.20 0.38 2.92 3.43 7.62 0.39 1.01
SEATING PLANE
Page
www.lansdale.com
Issue
ML145053
LANSDALE Semiconductor, Inc.
OUTLINE DIMENSIONS
PACKAGE (ML145053-5P) CASE 751A-03
NOTES: DIMENSIONING TOLERANCING ANSI Y14.5M, 1982 CONTROLLING DIMENSION: MILLIMETER DIMENSIONS INCLUDE MOLD PROTRUSION MAXIMUM HOLD PROTRUSION 0.15 (0.006) SIDE DIMENSION DOES INCLUDE DAMBAR PROTRUSION ALLOWABLE DAMBAR PROTRUSION SHALL 0.127 (0.005) TOTAL EXCESS DIMENSION MAXIMUM MATERIAL CONDITION
-A14
0.25 (0.010)
SEATING PLANE
0.25 (0.010)
INCHES 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 0.19 0.25 0.10 0.25 5.80 6.20 0.25 0.50
MILLIMETERS 0.337 0.334 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 0.008 0.009 0.004 0.009 0.228 0.244 0.010 0.019
Lansdale Semiconductor reserves right make changes without further notice products herein improve reliability, function design. Lansdale does assume liability arising application product circuit described herein; neither does convey license under patent rights rights others. "Typical" parameters which provided Lansdale data sheets and/or specifications vary different applications, actual performance vary over time. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Lansdale Semiconductor registered trademark Lansdale Semiconductor, Inc.
Page
www.lansdale.com
Issue
Other recent searches
SF2092E - SF2092E SF2092E Datasheet
SAA2521 - SAA2521 SAA2521 Datasheet
MX29GL256F - MX29GL256F MX29GL256F Datasheet
CNY17 - CNY17 CNY17 Datasheet
AN3032 - AN3032 AN3032 Datasheet
AM2520PBC09 - AM2520PBC09 AM2520PBC09 Datasheet
1SS82 - 1SS82 1SS82 Datasheet
Privacy Policy | Disclaimer
© 2013 Datasheets.org.uk