MC68HC05K1
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HCMOS Microcontroller Unit
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List Sections
Section General Description Section Memory
Section Central Processor Unit (CPU) Section Interrupts Section Resets Section Low-Power Modes. Section Parallel Input/Output (I/O). Section Multifunction Timer Section Personality EPROM (MC68HC05K1 Only) Section Instruction Section Electrical Specifications Section Mechanical Specifications Section Ordering Information Appendix MC68HCL05K0. Appendix MC68HSC05K0 Index.
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Table Contents
Section General Description
Contents Introduction Features Mask Options Structure
Assignments 1.6.1 1.6.2 OSC1, OSC2, PB1/OSC3 1.6.2.1 Crystal 1.6.2.2 Ceramic Resonator 1.6.2.3 2-Pin Resistor-Capacitor (RC) Combination 1.6.2.4 3-Pin Oscillator. 1.6.2.5 External Clock Signal 1.6.3 RESET 1.6.4 IRQ/VPP 1.6.5 PA7-PA0 1.6.6 PB1/OSC3
Section Memory
Contents Introduction Input/Output Section
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Freescale Semiconductor, Inc. Technical Data
Personality EPROM (MC68HC05K1 Only).
Section Central Processor Unit (CPU)
Contents Introduction
Registers 3.3.1 Accumulator 3.3.2 Index Register 3.3.3 Stack Pointer 3.3.4 Program Counter 3.3.5 Condition Code Register Arithmetic/Logic Unit (ALU)
Section Interrupts
Contents Introduction
Interrupt Types 4.3.1 Software Interrupt. 4.3.2 External Interrupts 4.3.2.1 IRQ/VPP 4.3.2.2 PA3-PA0 Pins 4.3.2.3 Status Control Register 4.3.3 Timer Interrupts 4.3.3.1 Timer Overflow Interrupt 4.3.3.2 Real-Time Interrupt Interrupt Processing
Section Resets
Contents Introduction Reset Types
Technical Data
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Table Contents
5.3.1 5.3.2 5.3.3 5.3.4 5.3.5
Power-On Reset. External Reset Computer Operating Properly (COP) Reset Illegal Address Reset Low-Voltage Reset
Reset States 5.4.1 5.4.2 Port Registers. 5.4.3 Timer 5.4.4 Watchdog
Section Low-Power Modes
Contents Introduction Stop Mode Wait Mode. Halt Mode Data-Retention Mode
Section Parallel Input/Output (I/O)
Contents Introduction
Port 7.3.1 Port Data Register 7.3.2 Data Direction Register 7.3.3 Pulldown Register 7.3.4 Port External Interrupts 7.3.5 Port Logic
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Technical Data
Freescale Semiconductor, Inc. Technical Data
Port 7.4.1 Port Data Register 7.4.2 Data Direction Register 7.4.3 Pulldown Register 7.4.4 Port Logic
Section Multifunction Timer
Contents Introduction Timer Status Control Register Timer Counter Register Watchdog.
Section Personality EPROM (MC68HC05K1 Only)
Contents Introduction
PEPROM Registers 9.3.1 PEPROM Select Register 9.3.2 PEPROM Status Control Register PEPROM Programming PEPROM Reading
Section Instruction
10.1 10.2 Contents Introduction
10.3 Addressing Modes 10.3.1 Inherent 10.3.2 Immediate. 10.3.3 Direct 10.3.4 Extended 10.3.5 Indexed, Offset 10.3.6 Indexed, 8-Bit Offset.
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Table Contents
10.3.7 10.3.8
Indexed, 16-Bit Offset. Relative
10.4 Instruction Types 10.4.1 Register/Memory Instructions. 10.4.2 Read-Modify-Write Instructions 10.4.3 Jump/Branch Instructions. .100 10.4.4 Manipulation Instructions .102 10.4.5 Control Instructions .103 10.5 Instruction Summary .104 Opcode .109
10.6
Section Electrical Specifications
11.1 11.2 11.3 11.4 11.5 11.6 11.7 11.8 11.9 Contents .111 Introduction .111 Maximum Ratings .112 Equivalent Loading .112 Operating Temperature Range. .113 Thermal Characteristics .113 Power Considerations. .114 5.0-Volt Electrical Characteristics .115 3.3-Volt Electrical Specifications .116
11.10 5.0-Volt Control Timing .120 11.11 3.3-Volt Control Timing .121 11.12 Typical Oscillator Characteristics .124
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Technical Data
Freescale Semiconductor, Inc. Technical Data Section Mechanical Specifications
12.1 12.2 12.3 12.4 Contents .127 Introduction .127 MC68HC05K0/MC68HC05K1P (PDIP) .128 MC68HC05K0/MC68HC05K1DW (SOIC) .128
Section Ordering Information
13.1 13.2 13.3
Contents .129 Introduction .129 Ordering Forms .130
13.4 Application Program Media. .130 13.4.1 Diskettes. .131 13.4.2 EPROMs .132 13.5 13.6 13.7 Program Verification .132 Verification Units (RVUs). .133 Order Numbers .134
Appendix MC68HCL05K0
Contents .135 Introduction .135 1.8-2.4-Volt Electrical Characteristics .136 2.5-3.6-Volt Electrical Characteristics .136 Low-Power Supply Current. .137 Low-Power Pulldown Current .138 Ordering Information. .139
Technical Data
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Table Contents
Appendix MC68HSC05K0
Contents .141 Introduction .141 High-Speed Supply Current .142 5.0-Volt Control Timing .143 3.3-Volt Control Timing .144 Ordering Information. .144
Index
Index .145
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List Figures
Figure
Title
Page
MC68HC05K0 MC68HC05K1 Block Diagram. Assignments. Bypassing Layout Recommendation Crystal Connections 2-Pin Ceramic Resonator Connections 3-Pin Ceramic Resonator Connections 2-Pin Oscillator Connections 3-Pin Oscillator Connections External Clock Connections Memory Control, Status, Data Registers. Programming Model Accumulator Index Register Stack Pointer (SP) Program Counter Condition Code Register (CCR) External Interrupt Logic Status Control Register (ISCR) Interrupt Stacking Order Interrupt Flowchart Reset Sources Register (COPR) Stop/Wait/Halt Flowchart Port Data Register (PORTA).
Technical Data
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Freescale Semiconductor, Inc. Technical Data
Figure Title Page
Data Direction Register (DDRA) Pulldown Register (PDRA) Port Circuit Port Data Register (PORTB). Data Direction Register (DDRB) Pulldown Register (PDRB) Port Circuit Multifunction Timer Block Diagram. Timer Status Control Register (TSCR) Timer Counter Register (TCNTR) Register (COPR) PEPROM Block Diagram PEPROM Select Register (PEBSR) PEPROM Status Control Register (PESCR) Programming Circuit. Equivalent Test Load .112 Typical High-Side Driver Characteristics .117 Typical Low-Side Driver Characteristics. .117 Typical versus Internal Clock Frequency .118 Typical Wait versus Internal Clock Frequency .118 Typical Stop versus Temperature .119 External Interrupt Timing .122 Stop Mode Recovery Timing .122 Power-On Reset Timing .123 External Reset Timing .123 2-Pin Oscillator versus Frequency (VDD .125 3-Pin Oscillator versus Frequency (VDD .125 2-Pin Oscillator versus Frequency (VDD .126 3-Pin Oscillator versus Frequency (VDD .126 Maximum Mode versus Frequency. .138 Maximum Wait Mode versus Frequency .139
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11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 11-10 11-11 11-12 11-13 11-14 13-1 13-2
Technical Data
Technical Data MC68HC05K0 MC68HC05K1
List Tables
Table
Title
Page
Mask Options Reset/Interrupt Vector Addresses Port Functions. Functions PB1/OSC3 Functions Real-Time Interrupt Rate Selection Watchdog Recommendations PEPROM Selection Register/Memory Instructions. Read-Modify-Write Instructions Jump Branch Instructions .101 Manipulation Instructions. .102 Control Instructions. .103 Instruction Summary .104 Opcode .110 Order Numbers .134 MC68HCL05K0 Order Numbers. .139 MC68HSC05K0 Order Numbers .144
10-1 10-2 10-3 10-4 10-5 10-6 10-7 13-1
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Section General Description
Contents
Introduction Features Mask Options Structure
Assignments 1.6.1 1.6.2 OSC1, OSC2, PB1/OSC3 1.6.2.1 Crystal 1.6.2.2 Ceramic Resonator 1.6.2.3 2-Pin Resistor-Capacitor (RC) Combination 1.6.2.4 3-Pin Oscillator. 1.6.2.5 External Clock Signal 1.6.3 RESET 1.6.4 IRQ/VPP 1.6.5 PA7-PA0 1.6.6 PB1/OSC3
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Technical Data
Freescale Semiconductor, Inc. Technical Data Introduction
MC68HC05K1 MC68HC05K0 members Motorola's low-cost, high-performance M68HC05 Family 8-bit microcontroller units (MCU). M68HC05 Family based customer-specified integrated circuit (CSIC) design strategy. MCUs family popular M68HC05 central processor unit (CPU) available with variety subsystems, memory sizes types, package types. On-chip memory includes bytes user read-only memory (ROM) bytes user random-access memory (RAM). MC68HC05K1 additional 64-bit personality, erasable, programmable, read-only memory (PEPROM). MC68HC05K1 MCU, PEPROM cannot erased serves 64-bit array one-time programmable (OTPROM). Appendix MC68HCL05K0 introduces MC68HCL05K0, low-power version MC68HC05K0. Appendix MC68HSC05K0 introduces MC68HSC05K0, high-speed version MC68HC05K0.
Features
Features MC68HC05K0 MC68HC05K1 include: M68HC05 Memory-mapped input/output (I/O) registers bytes including eight user vector locations bytes user 64-bit PEPROM/OTPROM (MC68HC05K1 only) bidirectional input/output (I/O) pins with these features: Software programmable pulldown devices Four pins with 8-mA current sinking capability Four pins with maskable external interrupt capability
Technical Data
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General Description Mask Options
Hardware mask flag external interrupts Fully static operation with minimum clock speed On-chip oscillator with connections crystal/ceramic resonator mask-optional 2-pin 3-pin resistor-capacitor (RC) oscillator Computer operating properly (COP) watchdog 15-bit multifunction timer with real-time interrupt circuit Power-saving stop, wait/halt, data-retention modes unsigned multiply instruction Illegal address reset Low-voltage reset 16-pin plastic dual in-line package (PDIP) 16-pin small outline integrated circuit package (SOIC)
Mask Options
Table shows available mask options. Table 1-1. Mask Options
Feature watchdog External interrupt triggering Port external interrupt function Low-voltage reset function STOP instruction Oscillator type Port port pulldown devices Mask Options Enabled Edge triggered only Enabled Enabled Enabled Crystal/ceramic resonator Software control Disabled Edge level triggered Disabled Disabled Convert halt Resistor-capacitor 2-pin 3-pin
Disabled
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Technical Data
Freescale Semiconductor, Inc. Technical Data Structure
Figure shows structure MC68HC05K0 MC68HC05K1.
USER BYTES
DATA DIRECTION REGISTER
PERSONALITY EPROM/OTPROM- BITS (MC68HC05K1 ONLY)
PA7* PA6* PA5* PORT PA4* PA3** PA2** PA1** PA0**
USER BYTES
CONTROL
ARITHMETIC/LOGIC UNIT ACCUMULATOR
*8-mA sink capability **External interrupt capability
IRQ/VPP
M68HC05 REGISTER RESET STACK POINTER PROGRAM COUNTER CONDITION CODE REGISTER DATA DIRECTION REGISTER
RESET
PORT
PB1/OSC3
WATCHDOG ILLEGAL ADDRESS DETECT
MULTIFUNCTION TIMER
CLOCK
OSC1 OSC2
LOW-VOLTAGE DETECT
INTERNAL OSCILLATOR OSC3
fosc
DIVIDE
Figure 1-1. MC68HC05K0 MC68HC05K1 Block Diagram
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TIMER CLOCK
General Description Assignments
Assignments
Figure shows MC68HC05K0 MC68HC05K1 assignments.
RESET PB1/OSC3
OSC1 OSC2
IRQ/VPP
Figure 1-2. Assignments
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Technical Data
Freescale Semiconductor, Inc. Technical Data
1.6.1 power supply ground pins. operates from single 3.0-V 6.0-V power supply. Very fast signal transitions occur pins, placing high short-duration current demands power supply. prevent noise problems, take special care provide good power supply bypassing MCU. Place bypass capacitors close possible, Figure shows.
OSC1 OSC2
Note: Actual layout varies according component dimensions.
Figure 1-3. Bypassing Layout Recommendation
1.6.2 OSC1, OSC2, PB1/OSC3 OSC1, OSC2, PB1/OSC3 pins control connections 2-pin 3-pin on-chip oscillator. oscillator driven these: Crystal Ceramic resonator Resistor-capacitor (RC) combination External clock signal
frequency internal oscillator fosc. divides internal oscillator output produce internal clock with frequency fop.
Technical Data
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General Description Assignments
1.6.2.1 Crystal circuit Figure shows typical crystal oscillator circuit AT-cut, parallel resonant crystal. Follow crystal supplier's recommendations, crystal parameters determine external component values required provide reliable startup maximum stability. load capacitance values used oscillator circuit design should account stray layout capacitances. minimize output distortion, mount crystal capacitors close possible pins.
(MASK OPTION) OSC1 OSC1 OSC2 OSC2
XTAL
XTAL
Figure 1-4. Crystal Connections
NOTE:
AT-cut crystal strip tuning fork crystal. overdrive have incorrect characteristic impedance strip tuning fork crystal. crystal-driven oscillator, select crystal/ceramic resonator mask option when ordering MCU. crystal/ceramic resonator mask option connects internal startup resistor between OSC1 OSC2.
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1.6.2.2 Ceramic Resonator reduce cost, ceramic resonator place crystal. circuit Figure 2-pin ceramic resonator Figure 3-pin ceramic resonator follow resonator manufacturer's recommendations.
OSC1 CER. RES. OSC2 CERAMIC RESONATOR
(MASK OPTION)
OSC1
Figure 1-5. 2-Pin Ceramic Resonator Connections
(MASK OPTION) OSC1 OSC1 OSC2 CER. RES. OSC2
OSC2
CERAMIC RESONATOR
Figure 1-6. 3-Pin Ceramic Resonator Connections external component values required maximum stability reliable starting depend upon resonator parameters. load capacitance values used oscillator circuit design should account stray layout capacitances. minimize output distortion, mount resonator capacitors close possible pins.
Technical Data
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General Description Assignments
resonator-driven oscillator, select crystal/ceramic resonator mask option when ordering MCU. crystal/ceramic resonator mask option connects internal startup resistor between OSC1 OSC2. 1.6.2.3 2-Pin Resistor-Capacitor (RC) Combination maximum cost reduction, 2-pin oscillator configuration shown Figure 1-7. OSC2 signal square-type wave, signal OSC1 triangular-type wave. optimum frequency 2-pin oscillator configuration MHz.
OSC1 OSC1 OSC2 OSC2
Figure 1-7. 2-Pin Oscillator Connections 2-pin oscillator configuration, select 2-pin oscillator mask option when ordering MCU.
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1.6.2.4 3-Pin Oscillator Another low-cost option 3-pin oscillator configuration shown Figure 1-8. 3-pin oscillator more stable than 2-pin oscillator. OSC2 PB1/OSC3 signals square-type waves, signal OSC1 triangular-type wave. Short OSC1 side resistor which connected capacitor 3-pin oscillator configuration recommended frequencies down kHz.
OSC1 OSC1 OSC2 PB1/OSC3 PB1/OSC3 OSC2
Figure 1-8. 3-Pin Oscillator Connections 3-pin oscillator configuration, select 3-pin oscillator mask option when ordering MCU.
NOTE:
3-pin oscillator configuration PEPROM MC68HC05K1 cannot programmed user software. voltage IRQ/VPP raised above VDD, oscillator will revert 2-pin oscillator configuration device operation will disrupted.
Technical Data
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General Description Assignments
1.6.2.5 External Clock Signal external clock from another complementary metal oxide semiconductor (CMOS)-compatible device drive OSC1 input, with OSC2 unconnected, Figure shows.
OSC1
EXTERNAL CMOS CLOCK
Figure 1-9. External Clock Connections
1.6.3 RESET logic RESET forces known startup state. Reset Types.
1.6.4 IRQ/VPP IRQ/VPP these functions: Applying asynchronous external interrupt signals. Interrupt Types. Applying personality EPROM programming voltage (MC68HC05K1 only). PEPROM Registers.
1.6.5 PA7-PA0 PA7-PA0 pins port general-purpose, bidirectional port. Port port pins have mask-optional pulldown devices that sink approximately 7.3.3 Pulldown Register mask
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OSC2
Technical Data
Freescale Semiconductor, Inc. Technical Data
option port external interrupts selected, PA3-PA0 serve external interrupt pins. 7.3.4 Port External Interrupts.
1.6.6 PB1/OSC3 PB1/OSC3 pins port general-purpose, bidirectional port. Port oscillator output 3-pin resistor/capacitor (RC) oscillator mask option. 1.6.2 OSC1, OSC2, PB1/OSC3. have mask-optional pulldown devices that sink approximately 7.4.3 Pulldown Register
Technical Data
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Section Memory
Contents
Introduction Input/Output Section Personality EPROM (MC68HC05K1 Only).
Introduction
central processor unit (CPU) address Kbyte memory space. program counter typically advances address time through memory, reading program instructions data. read-only memory (ROM) portion memory holds program instructions, fixed data, user-defined vectors, interrupt service routines. random-access memory (RAM) portion memory holds variable data. Input/output (I/O) registers memory-mapped that access their locations same that accesses other memory locations. Figure memory microcontroller unit (MCU).
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Technical Data
Freescale Semiconductor, Inc. Technical Data Input/Output Section
first addresses memory space, $0000-$001F, section. These addresses control registers, status registers, data registers. Figure register section.
addresses from $00E0 $00FF serve both user stack RAM. uses five bytes save register contents before processing interrupt. During subroutine call, uses bytes store return address. stack pointer decrements during pushes increments during pulls.
NOTE:
careful when using nested subroutines multiple interrupt levels. overwrite data during subroutine during interrupt stacking operation.
Technical Data
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Memory
$0000 $001F $0020
BYTES
USER BYTES $00DF $00E0 STACK BYTES
$00FF $0100
UNUSED BYTES
$01FF $0200
USER BYTES
PORT DATA REGISTER PORT DATA REGISTER UNUSED UNUSED PORT DATA DIRECTION REGISTER PORT DATA DIRECTION REGISTER UNUSED UNUSED TIMER STATUS CONTROL REGISTER TIMER COUNTER REGISTER STATUS CONTROL REGISTER UNUSED UNUSED UNUSED PEPROM SELECT REGISTER(1) PEPROM STATUS CONTROL REGISTER(1) PULLDOWN REGISTER PULLDOWN REGISTER UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED UNUSED RESERVED REGISTER(2) RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED TIMER VECTOR (HIGH) TIMER VECTOR (LOW) VECTOR (HIGH) VECTOR (LOW) VECTOR (HIGH) VECTOR (LOW) RESET VECTOR (HIGH BYTE) RESET VECTOR (LOW BYTE)
$0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0000 $0011 $0012 $0013 $0014 $0015 $0016 $0017 $0018 $0019 $001A $001B $001C $001D $001E $001F $03F0 $03F1 $03F2 $03F3 $03F4 $03F5 $03F6 $03F7 $03F8 $03F9 $03FA $03FB $03FC $03FD $03FE $03FF
$03EF $03F0 INTERNAL TEST REGISTER BYTES $03F7 $03F8 $03FF
USER VECTORS BYTES
MC68HC05K1 only Writing $03F0 clears watchdog. Reading $03F0 returns data.
Figure 2-1. Memory
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Freescale Semiconductor, Inc. Technical Data
Addr.
Register Name Read: Port Data Register (PORTA) Write: page Reset: Read: Port Data Register (PORTB) Write: page Reset: Unimplemented Unimplemented
$0000
Unaffected reset Unaffected reset
$0001
$0002 $0003
$0004
Read: Data Direction Register DDRA7 (DDRA) Write: page Reset: Read: Data Direction Register (DDRB) Write: page Reset: Unimplemented Unimplemented Read: Timer Status Control Register (TSCR) Write: page Reset:
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1 DDRB1
DDRA0 DDRB0
$0005
$0006 $0007
RTIF TOIE RTIE
TOFR
RTIFR TCR2 TCR1 TCR0
$0008
TCR6
TCR5
TCR4
TCR3
$0009
Read: TCR7 Timer Counter Register (TCNTR) Write: page Reset: Read: Status Control Register (ISCR) Write: page Reset: IRQE
IRQF
IRQR
$000A
Reserved
Unimplemented
Unaffected
Figure 2-2. Control, Status, Data Registers (Sheet
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Memory
Addr. $000B $000D
Register Name Unimplemented
Unimplemented Read: PEPROM Select Register (PEBSR) Write: page Reset:
PEB7
PEB6
PEB5 PEPGM
PEB4
PEB3
PEB2
PEB1
PEB0 PEPRZF
$000E
$000F
Read: PEDATA PEPROM Status Control Register (PESCR) Write: page Reset: Read: Pulldown Register (PDRA) Write: PDIA7 page Reset: Read: Pulldown Register (PDRB) Write: page Reset: Unimplemented
$0010
PDIA6
PDIA5
PDIA4
PDIA3
PDIA2
PDIA1
PDIA0
$0011
PDIB1
PDIB0
$0012 $001E
Unimplemented Read:
$001F
Reserved
Write: Reset:
Unaffected reset
$03F0
Register Read: (COPR) Write: page Reset:
COPC
Reserved
Unimplemented
Unaffected
Figure 2-2. Control, Status, Data Registers (Sheet
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Technical Data
Freescale Semiconductor, Inc. Technical Data
Addresses $0200-$03EF contain bytes user ROM. eight addresses from $03F8 $03FF user locations reserved interrupt vectors reset vectors.
Personality EPROM (MC68HC05K1 Only)
MC68HC05K1 MCU, personality EPROM cannot erased serves 64-bit array one-time programmable (OTPROM).
Technical Data
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Technical Data MC68HC05K0 MC68HC05K1
Section Central Processor Unit (CPU)
Contents
Introduction
Registers 3.3.1 Accumulator 3.3.2 Index Register 3.3.3 Stack Pointer 3.3.4 Program Counter 3.3.5 Condition Code Register Arithmetic/Logic Unit (ALU)
Introduction
central processor unit (CPU) contains five registers arithmetic/logic unit (ALU).
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Technical Data
Freescale Semiconductor, Inc. Technical Data Registers
Figure shows five registers. registers part memory map.
ACCUMULATOR INDEX REGISTER CONDITION CODE REGISTER (CCR) PROGRAM COUNTER (PC) STACK POINTER (SP)
HALF-CARRY FLAG INTERRUPT MASK NEGATIVE FLAG ZERO FLAG CARRY/BORROW FLAG
Figure 3-1. Programming Model
Technical Data
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Central Processor Unit (CPU) Registers
3.3.1 Accumulator accumulator shown Figure general-purpose 8-bit register. accumulator holds operands results arithmetic non-arithmetic operations.
Read: Write:
Reset:
Unaffected reset
Figure 3-2. Accumulator
3.3.2 Index Register indexed addressing modes, uses byte index register determine effective address operand. (See 10.3.5 Indexed, Offset, 10.3.6 Indexed, 8-Bit Offset, 10.3.7 Indexed, 16-Bit Offset.) 8-bit index register shown Figure also serve temporary data storage location.
Read: Write: Reset: Unaffected reset
Figure 3-3. Index Register
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Technical Data
Freescale Semiconductor, Inc. Technical Data
3.3.3 Stack Pointer stack pointer (SP) shown Figure 16-bit register that contains address next location stack. During reset after reset stack pointer (RSP) instruction, stack pointer initializes $00FF. address stack pointer decrements data pushed onto stack increments data pulled from stack. most significant bits stack pointer permanently fixed 00000000111, stack pointer produces addresses from $00FF $00E0. subroutines interrupts more than stack locations, stack pointer wraps around address $00FF begins writing over previously stored data. subroutine call uses stack locations; interrupt uses five locations.
Read: Write: Reset:
Figure 3-4. Stack Pointer (SP)
Technical Data
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Central Processor Unit (CPU) Registers
3.3.4 Program Counter program counter (PC) shown Figure 16-bit register that contains address next instruction operand fetched. most significant bits program counter ignored internally appear 000000 when stacked. Normally, address program counter automatically increments next sequential memory location every time instruction operand fetched. Jump, branch, interrupt operations load program counter with address other than that next sequential location.
Read: Write: Reset: Loaded with vector from $03FE $03FF
Figure 3-5. Program Counter
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Technical Data
Freescale Semiconductor, Inc. Technical Data
3.3.5 Condition Code Register condition code register (CCR) shown Figure 8-bit register whose three most significant bits permanently fixed 111. condition code register contains interrupt mask four flags that indicate results prior instructions.
Read:
Write: Reset: Unaffected
Figure 3-6. Condition Code Register (CCR) Bits Bits always read logic Half-Carry Flag sets half-carry flag when carry occurs between bits accumulator during without carry (ADD) with carry (ADC) operation. half-carry required binary-coded decimal (BCD) arithmetic operations. Reset effect half-carry flag. Interrupt Mask Setting interrupt mask disables interrupts. interrupt request occurs while interrupt mask logic saves registers stack, sets interrupt mask, then fetches interrupt vector. interrupt request occurs while interrupt mask set, interrupt request latched. processes latched interrupt soon interrupt mask cleared again. return-from-interrupt (RTI) instruction pulls registers from stack, restoring interrupt mask cleared state. After reset, interrupt mask cleared only clear interrupt mask (CLI), STOP, WAIT instruction.
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Central Processor Unit (CPU) Arithmetic/Logic Unit (ALU)
Negative Flag sets negative flag when arithmetic operation, logical operation, data manipulation produces negative result. Reset effect negative flag. Zero Flag sets zero flag when arithmetic operation, logical operation, data manipulation produces result $00. Reset effect zero flag.
Carry/Borrow Flag sets carry/borrow flag when addition operation produces carry accumulator when subtraction operation requires borrow. Some logical operations data manipulation instructions also clear carry/borrow flag. Reset effect carry/borrow flag.
Arithmetic/Logic Unit (ALU)
performs arithmetic logical operations defined instruction set. binary arithmetic circuits decode instructions selected operation.
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Technical Data
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Technical Data MC68HC05K0 MC68HC05K1
Section Interrupts
Contents
Introduction
Interrupt Types 4.3.1 Software Interrupt. 4.3.2 External Interrupts 4.3.2.1 IRQ/VPP 4.3.2.2 PA3-PA0 Pins 4.3.2.3 Status Control Register 4.3.3 Timer Interrupts 4.3.3.1 Timer Overflow Interrupt 4.3.3.2 Real-Time Interrupt Interrupt Processing
Introduction
This section describes interrupts temporarily change processing sequence.
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Freescale Semiconductor, Inc. Technical Data Interrupt Types
These conditions generate interrupts: instruction (software interrupt) logic applied IRQ/VPP (external interrupt) logic applied PA3-PA0 pins port external interrupt mask option selected (external interrupt) timer overflow (timer interrupt) Expiration real-time interrupt period (timer interrupt)
interrupt temporarily suspends normal program execution process particular event. interrupt does stop execution instruction progress, takes effect when current instruction completes execution. Interrupt processing automatically saves central processor unit (CPU) registers stack loads program counter with user-defined vector address.
4.3.1 Software Interrupt software interrupt (SWI) instruction causes non-maskable interrupt.
4.3.2 External Interrupts These sources generate external interrupts: IRQ/VPP PA3-PA0 pins port external interrupts mask option selected
Setting condition code register clearing IRQE interrupt status control register disables external interrupts. Figure 4-2.
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Interrupts Interrupt Types
4.3.2.1 IRQ/VPP interrupt signal IRQ/VPP latches external interrupt request. IRQ/VPP contains internal Schmitt trigger part input improve noise immunity. After completing current instruction, tests these bits: IRQF interrupt status control register IRQE interrupt status control register condition code register
both IRQF IRQE set, clear, then begins interrupt sequence. clears IRQF while fetches interrupt vector, that another external interrupt request latched during interrupt service routine. soon cleared during return from interrupt, recognize interrupt request. Figure shows logic external interrupts. IRQ/VPP negative-edge triggered only negative-edge low-level triggered, depending mask option selected. When edge- level-sensitive trigger mask option selected: falling edge level IRQ/VPP latches external interrupt request. long IRQ/VPP low, external interrupt request present, continues execute interrupt service routine. edge- level-sensitive trigger option allows connection IRQ/VPP multiple wired-OR interrupt sources.
When edge-sensitive only trigger mask option selected: falling edge IRQ/VPP latches external interrupt request. subsequent interrupt request latched only after voltage level IRQ/VPP returns logic then falls again logic
NOTE:
IRQ/VPP use, connect pin.
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INSTRUCTION PROCESSING LEVEL-SENSITIVE TRIGGER
(MASK OPTION)
LATCH EXTERNAL INTERRUPT REQUEST
VECTOR FETCH IRQR IRQE IRQF
PORT EXTERNAL INTERRUPTS ENABLED (MASK OPTION) INTERNAL DATA
STATUS CONTROL REGISTER
Figure 4-1. External Interrupt Logic 4.3.2.2 PA3-PA0 Pins mask option port external interrupts enables pins PA3-PA0 serve additional external interrupt sources. PA3-PA0 pins contain internal Schmitt triggers. interrupt signal PA3-PA0 pins latches external interrupt request. After completing current instruction, tests these bits: IRQF (IRQ latch) IRQE interrupt status control register condition code register
both latch IRQE clear, then begins interrupt sequence. clears latch while fetches interrupt vector, that another external interrupt request latched during interrupt service routine. soon
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Interrupts Interrupt Types
cleared during return from interrupt, recognize interrupt request. PA3-PA0 pins positive edge triggered only positive-edge high- level triggered, depending mask option selected. When positive edge high level-sensitive trigger mask option selected: rising edge high level PA3-PA0 latches external interrupt request only other PA3-PA0 pins IRQ/VPP high. falling edge level IRQ/VPP latches external interrupt request only PA3-PA0 pins low. long PA3-PA0 high IRQ/VPP low, external interrupt request present, continues execute interrupt service routine.
Edge- level-sensitive triggering allows multiple external interrupt sources wire-ORed PA3-PA0 pins. long source holding PA3-PA0 high, external interrupt request latched, continues execute interrupt service routine. When positive edge-sensitive-only trigger mask option selected: rising edge PA3-PA0 pins latches external interrupt request other PA3-PA0 pins IRQ/VPP high. falling edge IRQ/VPP latches external interrupt request only PA3-PA0 pins low. subsequent PA3-PA0 interrupt request latched only after voltage level previous PA3-PA0 interrupt signal returns logic then rises again logic subsequent IRQ/VPP interrupt request latched only after voltage level previous IRQ/VPP interrupt signal returns logic then falls again logic
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4.3.2.3 Status Control Register status control register (ISCR), shown Figure 4-2, contains external interrupt mask, external interrupt flag, flag reset bit. Unused bits read logic
Address: $000A Read: IRQE IRQF IRQR
Write: Reset:
Unimplemented
Unaffected
Figure 4-2. Status Control Register (ISCR) IRQE External Interrupt Request Enable This read/write enables external interrupts. Reset sets IRQE bit. External interrupt processing enabled External interrupt processing disabled IRQF External Interrupt Request Flag IRQF (IRQ latch) clearable, read-only that when external interrupt request pending. Reset clears IRQF bit. Interrupt request pending interrupt request pending These conditions IRQF bit: external interrupt signal IRQ/VPP external interrupt signal PA3, PA2, PA1, PA3-PA0 enabled mask option serve external interrupt sources clears IRQF when fetching interrupt vector. Writing IRQF effect. Writing logic IRQR clears IRQF bit.
Technical Data
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Interrupts Interrupt Types
IRQR Interrupt Request Reset Writing logic this write-only clears IRQF bit. Writing logic IRQR effect. Reset effect IRQR. IRQF cleared effect
4.3.3 Timer Interrupts multifunction timer generate these interrupts:
Timer overflow interrupt Real-time interrupt
Setting condition code register disables timer interrupts. 4.3.3.1 Timer Overflow Interrupt timer overflow interrupt request occurs timer overflow flag (TOF) becomes while timer overflow interrupt enable (TOIE) also set. Timer Status Control Register. 4.3.3.2 Real-Time Interrupt real-time interrupt request occurs real-time interrupt flag, RTIF, becomes while real-time interrupt enable bit, RTIE, also set. Timer Status Control Register.
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Freescale Semiconductor, Inc. Technical Data Interrupt Processing
begin servicing interrupt, CPU: Stores registers stack order shown Figure Sets condition code register prevent further interrupts Loads program counter with contents appropriate interrupt vector locations: $03FC $03FD (software interrupt vector) $03FA $03FB (external interrupt vector) $03F8 $03F9 (timer interrupt vector) return-from-interrupt (RTI) instruction causes recover registers from stack shown Figure 4-3.
$00E0 (BOTTOM STACK) $00E1 $00E2 UNSTACKING ORDER
CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PROGRAM COUNTER (HIGH BYTE) PROGRAM COUNTER (LOW BYTE)
STACKING ORDER
$00FD $00FE $00FF (TOP STACK)
Figure 4-3. Interrupt Stacking Order
Technical Data
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Interrupts Interrupt Processing
Table summarizes reset interrupt sources vector assignments. Table 4-1. Reset/Interrupt Vector Addresses
Function Source Power-on logic RESET Local Mask Global Mask Priority Highest) Vector Address
Reset
watchdog(1) Low-voltage detect(2) Illegal address logic
None
None
$03FE-$03FF
Software interrupt (SWI)
User code IRQ/VPP pin(3)
None
None
Same priority instruction
$03FC-$03FD
External interrupts
pin(3) pin(3) pin(3)
IRQE
$03FA-$03FB
Timer interrupts
RTIF
TOIE RTIE $03F8-$03F9
computer operating properly (COP) watchdog mask option. low-voltage reset function mask option. Port interrupt capability mask option.
NOTE:
more than interrupt request pending, fetches vector higher priority interrupt first. higher priority interrupt does interrupt lower priority interrupt service routine unless lower priority interrupt service routine clears bit.
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Figure shows sequence events caused interrupt.
FROM RESET
SET?
EXTERNAL INTERRUPT?
CLEAR IRQF
TIMER INTERRUPT?
STACK LOAD WITH INTERRUPT VECTOR
FETCH NEXT INSTRUCTION
INSTRUCTION?
INSTRUCTION?
UNSTACK CCR,
EXECUTE INSTRUCTION
Figure 4-4. Interrupt Flowchart
Technical Data
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Section Resets
Contents
Introduction
Reset Types 5.3.1 Power-On Reset. 5.3.2 External Reset 5.3.3 Computer Operating Properly (COP) Reset 5.3.4 Illegal Address Reset 5.3.5 Low-Voltage Reset Reset States 5.4.1 5.4.2 Port Registers. 5.4.3 Timer 5.4.4 Watchdog
Introduction
This section describes five reset sources they initialize microcontroller unit (MCU).
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Freescale Semiconductor, Inc. Technical Data Reset Types
reset immediately stops operation instruction being executed, initializes certain control bits, loads program counter with user-defined reset vector address. These conditions produce reset: Initial power-up (power-on reset) logic applied RESET (external reset) Timeout mask-optional computer operating properly (COP) watchdog (COP reset) opcode fetch from address read-only memory (ROM) random-access memory (RAM) (illegal address reset) voltage below trip point (mask-optional low-voltage reset)
Figure block diagram reset sources.
5.3.1 Power-On Reset positive transition generates power-on reset. power-on reset strictly power-up conditions cannot used detect drops power supply voltage. 4064 tcyc (internal clock cycle) delay after oscillator becomes active allows clock generator stabilize. RESET logic 4064 tcyc, remains reset condition until signal RESET goes logic
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Resets Reset Types
5.3.2 External Reset external reset generated applying logic tcyc RESET pin. Schmitt trigger senses logic level RESET pin. reset illegal address reset pulls RESET internal clock cycle. low-voltage reset pulls RESET long low-voltage condition exists.
NOTE:
avoid overloading some power supply designs, connect RESET directly VDD. pullup resistor more.
WATCHDOG (MASK OPTION)
LOW-VOLTAGE RESET (MASK OPTION) POWER-ON RESET
ILLEGAL ADDRESS RESET
INTERNAL ADDRESS RESET LATCH
RESET INTERNAL CLOCK
SUBSYSTEMS
Figure 5-1. Reset Sources
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5.3.3 Computer Operating Properly (COP) Reset timeout computer operating properly (COP) watchdog generates reset. watchdog part software error detection system must cleared periodically start timeout period. clear watchdog prevent reset, write logic (COPC) register location $03F0. Watchdog. register, shown Figure 5-2, write-only register that returns contents location when read. watchdog function mask option.
Address: $03F0 Read: Write: Reset: Unaffected COPC
Unimplemented
Figure 5-2. Register (COPR) COPC Clear COPC write-only bit. Periodically writing logic COPC prevents watchdog from resetting MCU. Writing logic effect. Reset clears COPC bit.
5.3.4 Illegal Address Reset opcode fetch from address that (locations $0200-$03FF) (locations $00E0-$00FF) generates illegal address reset. illegal address reset pulls RESET cycle internal clock.
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Resets Reset States
5.3.5 Low-Voltage Reset low-voltage reset circuit mask option that generates reset signal voltage falls below trip point. must ±10% mask option enabling low-voltage reset circuit selected. low-voltage reset pulls RESET long low-voltage condition exists.
NOTE:
When low-voltage reset enabled, pullup resistor RESET because low-voltage reset shorts RESET ground when detects VDD. there pullup limit current, low-voltage reset will short ground, causing chip possibly remain reset being pulled down short. also pull current permanently damage chip.
Reset States
This subsection describes resets initialize MCU.
5.4.1 reset these effects CPU: Loads stack pointer with Sets condition code register, inhibiting interrupts Sets IRQE interrupt status control register Loads program counter with user-defined reset vector from locations $03FE $03FF Clears IRQF (IRQ latch) Clears stop latch, enabling clock, exiting halt mode Clears wait latch, waking from wait mode
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5.4.2 Port Registers reset these effects input/output (I/O) port registers: Clears bits DDRA7-DDRA0 data direction register that port pins inputs Clears bits PDIA7-PDIA0 pulldown register turning port pulldown devices pulldown devices enabled mask option) Clears bits DDRB1 DDRB0 data direction register that port pins inputs Clears bits PDIB1 PDIB0 pulldown register turning port pulldown devices pulldown devices enabled mask option) effect port port data registers
5.4.3 Timer reset these effects multifunction timer: Clears timer status control register Clears timer counter register
5.4.4 Watchdog reset clears watchdog timeout counter.
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Section Low-Power Modes
Contents
Introduction Stop Mode Wait Mode. Halt Mode Data-Retention Mode
Introduction
This section describes four low-power modes: Stop mode Wait mode Halt mode Data-retention mode
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Freescale Semiconductor, Inc. Technical Data Stop Mode
STOP instruction puts microcontroller unit (MCU) lowest power-consumption mode these effects MCU: Clears RTIF, timer interrupt flags timer status control register, removing pending timer interrupts Clears TOIE RTIE, timer interrupt enable bits timer status control register, disabling further timer interrupts Clears multifunction timer counter register Sets IRQE status control register enable external interrupts Clears condition code register, enabling interrupts Stops internal oscillator, turning central processor unit (CPU) clock timer clock, including computer operating properly (COP) watchdog, holds OSC2 logic
STOP instruction does affect other registers input/output (I/O) lines. These conditions bring stop mode: external interrupt signal IRQ/VPP high-to-low transition IRQ/VPP loads program counter with contents locations $03FA $03FB. external interrupt signal port external interrupt mask option port external interrupt function selected, low-to-high transition PA3-PA0 loads program counter with contents locations $03FA $03FB. Low-voltage reset low-voltage detect resets loads program counter with contents locations $03FE $03FF this mask option selected). External reset logic RESET resets loads program counter with contents locations $03FE $03FF.
When exits stop mode, processing resumes after stabilization delay 4064 oscillator cycles.
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Low-Power Modes Wait Mode
Wait Mode
WAIT instruction puts intermediate power-consumption mode these effects MCU: Clears condition code register, enabling interrupts Sets IRQE status control register, enabling external interrupts Stops clock, allows internal oscillator timer clock continue
WAIT instruction does affect other registers lines. These conditions restart clock bring wait mode: external interrupt signal IRQ/VPP high-to-low transition IRQ/VPP loads program counter with contents locations $03FA $03FB. external interrupt signal port external interrupt mask option port external interrupt function selected, low-to-high transition PA3-PA0 loads program counter with contents locations $03FA $03FB. timer interrupt timer overflow real-time interrupt request loads program counter with contents locations $03F8 $03F9. watchdog reset timeout mask-optional watchdog resets loads program counter with contents locations $03FE $03FF. Software enable real-time interrupts that periodically exit wait mode reset watchdog. Low-voltage reset low-voltage detect resets loads program counter with contents locations $03FE $03FF this mask option selected). External reset logic RESET resets loads program counter with contents locations $03FE $03FF.
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Freescale Semiconductor, Inc. Technical Data Halt Mode
mask option disable STOP instruction selected, STOP instruction puts halt mode. Halt mode identical wait mode, except that recovery delay from 4064 internal clock cycles occurs when exits halt mode. mask option disable STOP instruction selected, watchdog cannot turned inadvertently STOP instruction. Figure shows sequence events stop, wait, halt modes.
Data-Retention Mode
data-retention mode, retains random-access memory (RAM) contents register contents voltages Vdc. data-retention feature allows remain power-consumption state during which retains data, cannot execute instructions. data-retention mode: Drive RESET logic Lower voltage. RESET must remain continuously during data-retention mode. take data-retention mode: Return normal operating voltage. Return RESET logic
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Low-Power Modes Data-Retention Mode
STOP
STOP DISABLED?
HALT WAIT
CLEAR IRQE ISCR CLEAR TOF, RTIF, TOIE, RTIE BITS TSCR TURN INTERNAL OSCILLATOR
CLEAR IRQE ISCR TURN CLOCK TIMER CLOCK ACTIVE
CLEAR IRQE ISCR TURN CLOCK TIMER CLOCK ACTIVE
EXTERNAL RESET?
EXTERNAL RESET?
EXTERNAL RESET?
ENABLED? ENABLED? EXTERNAL INTERRUPT? ENABLED?
LVR?
LVR?
LVR?
EXTERNAL INTERRUPT?
EXTERNAL INTERRUPT?
TURN INTERNAL OSCILLATOR START STABILIZATION DELAY
TIMER INTERRUPT?
TIMER INTERRUPT?
STABILIZATION DELAY?
RESET?
RESET?
TURN CLOCK
LOAD WITH RESET VECTOR SERVICE INTERRUPT SAVE REGISTERS STACK LOAD WITH INTERRUPT VECTOR
Figure 6-1. Stop/Wait/Halt Flowchart
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Section Parallel Input/Output (I/O)
Contents
Introduction
Port 7.3.1 Port Data Register 7.3.2 Data Direction Register 7.3.3 Pulldown Register 7.3.4 Port External Interrupts 7.3.5 Port Logic Port 7.4.1 Port Data Register 7.4.2 Data Direction Register 7.4.3 Pulldown Register 7.4.4 Port Logic
Introduction
bidirectional input/output (I/O) pins form parallel ports. Each programmable input output. contents data direction registers determine data direction each pin. pins have mask-optional pulldown devices.
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Freescale Semiconductor, Inc. Technical Data Port
Port 8-bit, general-purpose, bidirectional port with these features: Programmable pulldown devices (mask option) 8-mA current sinking capability (pins PA7-PA4) External interrupt capability (pins PA3-PA0) (mask option)
7.3.1 Port Data Register port data register (PORTA), shown Figure 7-1, contains each port pins. When port programmed output, state data register determines state output pin. When port programmed input, reading port data register returns logic state pin. port data register written while port either input output.
Address: $0000 Read: Write: Reset: Unaffected reset
Figure 7-1. Port Data Register (PORTA) PA7-PA0 Port Data Bits These read/write bits software-programmable. Data direction each under control corresponding data direction register Reset effect port data.
Technical Data
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Parallel Input/Output (I/O) Port
7.3.2 Data Direction Register contents data direction register (DDRA), shown Figure 7-2, determine whether each port input output. Writing logic DDRA enables output buffer associated port pin; logic disables output buffer. reset initializes DDRA bits logic configuring port pins inputs. pulldown devices enabled mask option, setting DDRA logic turns pulldown device that pin.
Address:
$0004 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
Read: DDRA7 Write: Reset:
Figure 7-2. Data Direction Register (DDRA) DDRA7-DDRA0 Port Data Direction Bits These read/write bits control port data direction. Reset clears bits DDRA7-DDRA0. Corresponding port configured output Corresponding port configured input
NOTE:
Avoid glitches port pins writing port data register before changing DDRA bits from logic logic
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7.3.3 Pulldown Register Port pins have mask-optional pulldown devices that sink approximately Clearing PDIA7-PDIA0 bits pulldown register turns port pulldown devices. Pulldown register shown Figure 7-3, turn port pulldown device only when port input. pulldown mask option selected, reset initializes port port pins inputs with pulldown devices turned
Address:
$0010
Read: Write: Reset: PDIA7 PDIA6 PDIA5 PDIA4 PDIA3 PDIA2 PDIA1 PDIA0
Unimplemented
Figure 7-3. Pulldown Register (PDRA) PDIA7-PDIA0 Port Pulldown Inhibit Bits Writing logic these write-only bits turns port pulldown devices. Reading pulldown register returns undefined data. Reset clears bits PDIA7-PDIA0. Corresponding port pulldown device turned Corresponding port pulldown device turned
NOTE:
avoid excessive current draw, connect unused input pins VSS. change pins outputs writing DDRA user initialization code. Avoid floating port input clearing pulldown register before changing DDRA from logic logic Because pulldown register write-only register, using read-modify-write instruction result inadvertently turning bits off.
Technical Data
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Parallel Input/Output (I/O) Port
7.3.4 Port External Interrupts mask option port external interrupts selected, PA3-PA0 pins serve external interrupt pins addition IRQ/VPP pin. External interrupts positive edge-triggered positive edge- high level-triggered.
NOTE:
When testing external interrupts, instructions test voltage IRQ/VPP pin, state internal signal. Therefore, test port external interrupt pins. Port interrupts sensitive direction port pins. Driving logic PA0-PA3 while port interrupts enabled will cause interrupt, even PA0-PA3 outputs.
7.3.5 Port Logic Figure shows port logic.
READ $0004 WRITE $0004 EXTERNAL INTERRUPT REQUEST (PINS PA3-PA0)
DATA DIRECTION REGISTER DDRAx
INTERNAL DATA
WRITE $0000
PORT DATA REGISTER
8-mA SINK CAPABILITY (PINS PA7-PA4)
READ $0000
WRITE $0010
PULLDOWN REGISTER PDIAx PULLDOWNS ENABLED (ACTIVE LOW) (MASK OPTION)
RESET
100-mA PULLDOWN DEVICE
Figure 7-4. Port Circuit
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When port programmed output, reading port actually reads value data latch voltage itself. When port programmed input, reading port reads voltage level pin. data latch always written, regardless state bit. Table summarizes operations port pins. Table 7-1. Port Functions
Pulldown Mask Option
Control Bits Mode PDIAx DDRAx Input, hi-z Output Input, pulldown Output Input, hi-z Output Read
Accesses PDRA Write PDIA7-PDIA0 PDIA7-PDIA0 PDIA7-PDIA0 PDIA7-PDIA0 PDIA7-PDIA0 PDIA7-PDIA0
Accesses DDRA Read/Write DDRA7-DDRA0 DDRA7-DDRA0 DDRA7-DDRA0 DDRA7-DDRA0 DDRA7-DDRA0 DDRA7-DDRA0
Accesses PORTA Read PA0-PA7 PA0-PA7 PA0-PA7 Write PA0-PA7 PA0-PA7 PA0-PA7 PA0-PA7 PA0-PA7 PA0-PA7
Don't care Undefined
Port
Port 2-bit, general-purpose, bidirectional port with these features: Programmable pulldown devices (mask option) Oscillator output 3-pin resistor-capacitor (RC) oscillator mask option
7.4.1 Port Data Register port data register (PORTB), shown Figure 7-5, contains each port pins. When port programmed output, state data register determines state output pin. When port programmed input, reading port
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Parallel Input/Output (I/O) Port
data register returns logic state pin. Reset effect port data.
Address: $0001 Read: Write: Reset: Unaffected reset OSC3 Unimplemented
Alternate Function:
Figure 7-5. Port Data Register (PORTB) PB1/OSC3 Port Data This read/write software programmable. Data direction under control DDRB1 data direction register When 3-pin oscillator mask option selected, PB1/OSC3 used oscillator output. Using 3-pin oscillator configuration affects port these ways: used read/write storage location without affecting oscillator. Reset effect PB1. DDRB1 data direction register used read/write storage location without affecting oscillator. Reset clears DDRB1. PB1/OSC3 pulldown device disabled.
Port Data This read/write software-programmable. Data direction under control DDRB0 data direction register Bits used Bits always read logic
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7.4.2 Data Direction Register contents data direction register (DDRB) determine whether each port input output (see Figure 7-6). Writing logic DDRB enables output buffer associated port pin; logic disables output buffer. reset initializes DDRB bits logic configuring port pins inputs. Setting DDRB logic turns pulldown device that pin.
Address: $0005 Read: Write: Reset: DDRB1 DDRB0
Unimplemented
Figure 7-6. Data Direction Register (DDRB) DDRB1 DDRB0 Data Direction Bits These read/write bits control port data direction. Corresponding port configured output Corresponding port configured input used Bits always read logic Writes these bits have effect.
NOTE:
Avoid glitches port pins writing port data register before changing DDRB bits from logic logic
Technical Data
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Parallel Input/Output (I/O) Port
7.4.3 Pulldown Register Port pins have mask-optional pulldown devices that sink approximately Clearing PDIB1 PDIB0 bits pulldown register turns port pulldown devices. Pulldown register turn port pulldown device only when port input. Figure 7-7. pulldown mask option selected, reset initializes port port pins inputs with pulldown devices turned
Address:
$0011
Read: Write: Reset:
PDIB1
PDIB0
Unimplemented
Unaffected
Figure 7-7. Pulldown Register (PDRB) PDIB1 PDIB0 Port Pulldown Inhibit Bits Writing logic these write-only bits turns port pulldown devices. Reading pulldown register returns undefined data. Reset clears PDIB1 PDIB0. Corresponding port pulldown device turned Corresponding port pulldown device turned Bits used Bits always read logic
NOTE:
avoid excessive current draw, connect unused input pins VSS. change pins outputs writing DDRB user initialization code. Avoid floating port input clearing pulldown register before changing DDRB from logic logic Because pulldown register write-only register, using read-modify-write instruction result inadvertently turning bits off.
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7.4.4 Port Logic Figure shows port logic.
READ $0005 WRITE $0005 3-PIN OSCILLATOR DATA DIRECTION REGISTER (DDRB1)
WRITE $0001
PORT DATA REGISTER (PB1)
PB1/ OSC3
READ $0001 WRITE $0011 PULLDOWN REGISTER (PDIB1) PULLDOWNS ENABLED (MASK OPTION) INTERNAL DATA 3-PIN OSCILLATOR (MASK OPTION) OSCILLATOR (MASK OPTION) (ACTIVE LOW) 100-mA PULLDOWN DEVICE
READ $0005 WRITE $0005
DATA DIRECTION REGISTER (DDRB0)
WRITE $0001
PORT DATA REGISTER (PB0)
READ $0001
WRITE $0011
PULLDOWN REGISTER (PDIB0)
100-mA PULLDOWN DEVICE
RESET
Figure 7-8. Port Circuit
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Parallel Input/Output (I/O) Port
When port programmed output, reading port reads value data latch voltage itself. When port programmed input, reading port reads voltage level pin. data latch always written, regardless state bit. Table Table summarize operation port pins.
Table 7-2. Functions
Pulldown Mask Option Don't care Undefined
Control Bits
Mode Input, hi-z Output Input, pulldown Output Input, hi-z Output
Accesses PDRB
Accesses DDRB
Accesses PORTB
PDIB0
DDRB0
Read
Write
PDIB0 PDIB0 PDIB0 PDIB0 PDIB0 PDIB0
Read/Write
DDRB0 DDRB0 DDRB0 DDRB0 DDRB0 DDRB0
Read
Write
Table 7-3. PB1/OSC3 Functions
Mask Options Control Bits PB1/OSC3 Mode Input, hi-z Output Input, pulldown Output Input, hi-z Output Accesses PDRB Accesses DDRB Accesses PORTB
3-Pin Osc.
Don't care Undefined
Pulldowns
PDIB1
DDRB1
Read
Write
PDIB1 PDIB1 PDIB1 PDIB1 PDIB1 PDIB1
Read/Write
DDRB1 DDRB1 DDRB1 DDRB1 DDRB1 DDRB1
Read
Write
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Technical Data MC68HC05K0 MC68HC05K1
Section Multifunction Timer
Contents
Introduction Timer Status Control Register Timer Counter Register Watchdog.
Introduction
This section describes operation multifunction timer computer operating properly (COP) watchdog. Figure shows organization timer subsystem.
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Freescale Semiconductor, Inc. Technical Data
TIMER CLOCK (fOP) (fOSC
TIMER COUNTER REGISTER
7-BIT COUNTER
RATE SELECT
RTIF
RTIE INTERRUPT REQUEST TOIE
RESET
CLEAR RESET
Figure 8-1. Multifunction Timer Block Diagram
Timer Status Control Register
timer status control register (TSCR), shown Figure 8-2, contains these bits: Timer interrupt enable bits Timer interrupt flags Timer interrupt flag reset bits Timer interrupt rate select bits
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Multifunction Timer Timer Status Control Register
Address:
$0008 RTIF TOIE RTIE TOFR RTIFR
Read: Write: Reset:
Unimplemented
Figure 8-2. Timer Status Control Register (TSCR)
Timer Overflow Flag This read-only flag becomes when first eight stages counter roll over from $00. generates timer overflow interrupt request TOIE also set. Clear writing logic TOFR bit. Writing effect. Reset clears TOF. RTIF Real-Time Interrupt Flag This read-only flag becomes when selected real-time interrupt (RTI) output becomes active. RTIF generates real-time interrupt request RTIE also set. Clear RTIF writing logic RTIFR bit. Writing RTIF effect. Reset clears RTIF. TOIE Timer Overflow Interrupt Enable This read/write enables timer overflow interrupts. Reset clears TOIE. Timer overflow interrupts enabled Timer overflow interrupts disabled RTIE Real-Time Interrupt Enable This read/write enables real-time interrupts. Reset clears RTIE. Real-time interrupts enabled Real-time interrupts disabled TOFR Timer Overflow Flag Reset Writing logic this write-only clears bit. TOFR always reads logic Reset does affect TOFR.
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Freescale Semiconductor, Inc. Technical Data
RTIFR Real-Time Interrupt Flag Reset Writing logic this write-only clears RTIF bit. RTIFR always reads logic Reset does affect RTIFR. Real-Time Interrupt Select Bits These read/write bits select four real-time interrupt rates, shown Table 8-1. Because selected output drives watchdog, changing real-time interrupt rate also changes counting rate watchdog. Reset sets RT0, selecting longest timeout period real-time interrupt period. Table 8-1. Real-Time Interrupt Rate Selection
RT1:RT0 Number Cycles 16,384 32,768 65,536 131,072 Period(1) 16.4 32.8 65.5 Number Cycles Reset 131,072 262,144 524,288 1,048,576 Timeout Period(1) 65.5 131.1 262.1 524.3
2-MHz bus, 4-MHz XTAL, cycle
NOTE:
careful when altering when timeout imminent uncertain. selected modified during cycle when counter switching, RTIF missed additional RTIF generated. avoid this problem, clear just before changing RT0. timer timer divided eight. However, clearing clears only last three dividers. does clear section divider chain. Therefore, timeout period range seven eight times period.
Technical Data
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Multifunction Timer Timer Counter Register
Timer Counter Register
15-stage ripple counter core timer. value first eight stages readable time from read-only timer counter register shown Figure 8-3.
Address: $0009 Read: TCR7 TCR6 TCR5 TCR4 TCR3 TCR2 TCR1 TCR0
Write: Reset:
Unimplemented
Figure 8-3. Timer Counter Register (TCNTR) Power-on clears entire counter chain begins clocking counter. After 4064 cycles, power-on reset circuit released, clearing counter again allowing come reset. timer overflow function eighth counter stage allows timer interrupt every 1024 internal clock cycles. Each count timer counter register takes eight oscillator cycles four cycles internal clock.
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Technical Data
Freescale Semiconductor, Inc. Technical Data Watchdog
Three counter stages timer make mask optional computer operating properly (COP) watchdog (see Figure 8-1). watchdog software error detection system that automatically times resets cleared periodically program sequence. Writing logic register, shown Figure 8-4, clears watchdog prevents reset.
Address: $03F0 Read: Write: Reset: COPC
Unimplemented
Unaffected
Figure 8-4. Register (COPR) COPC Clear This write-only resets watchdog. Reading address $03F0 returns data that address. watchdog active run, wait, halt modes operation. STOP instruction disables watchdog clearing counter turning clock source. applications that depend watchdog, STOP instruction disabled (converted halt) mask option. applications that have wait cycles longer than timeout period, watchdog disabled mask option.
NOTE:
voltage IRQ/VPP exceeds nominal VDD, watchdog turns remains until IRQ/VPP voltage falls below VDD.
Technical Data
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Multifunction Timer Watchdog
Table summarizes recommended conditions enabling disabling watchdog. Table 8-2. Watchdog Recommendations
STOP Instruction (Mask Option) Disabled Disabled Wait/Halt Time Less than timeout period Greater than timeout period Recommended Watchdog Condition Enabled(1) Disabled
Reset watchdog immediately before executing WAIT/HALT instruction.
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Technical Data
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Technical Data MC68HC05K0 MC68HC05K1
Section Personality EPROM (MC68HC05K1 Only)
Contents
Introduction
PEPROM Registers 9.3.1 PEPROM Select Register (PEBSR) 9.3.2 PEPROM Status Control Register (PESCR) PEPROM Programming PEPROM Reading
Introduction
This section describes program 64-bit personality erasable, programmable read-only memory (PEPROM) MC68HC05K1 only. Figure shows structure PEPROM subsystem.
NOTE:
PEPROM cannot erased parts offered without windowed package.
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Technical Data
Freescale Semiconductor, Inc. Technical Data
INTERNAL DATA PEPROM STATUS/CONTROL REGISTER RESET
PEPGM
SINGLE SENSE AMPLIFIER
SWITCH
8-TO-1 COLUMN DECODER MULTIPLEXER
PEPRZF
PEDATA
8-TO-1 DECODER MULTIPLEXER
SWITCH
ZERO DECODER PEB5 PEB4 PEB3 PEB2 PEB1 PEB0
PEPROM STATUS/CONTROL REGISTER INTERNAL DATA
RESET
Figure 9-1. PEPROM Block Diagram
Technical Data
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Personality EPROM (MC68HC05K1 Only) PEPROM Registers
PEPROM Registers
input/output (I/O) registers control programming reading PEPROM: PEPROM select register (PEBSR) PEPROM status control register (PESCR)
9.3.1 PEPROM Select Register
PEPROM select register (PEBSR), shown Figure 9-2, selects bits PEPROM array. Reset clears bits PEPROM select register.
Address: $000E Read: PEB7 Write: Reset: PEB6 PEB5 PEB4 PEB3 PEB2 PEB1 PEB0
Figure 9-2. PEPROM Select Register (PEBSR) PEB7 PEB6 Connected PEPROM Array These read/write bits available storage locations. Reset clears PEB7 PEB6. PEB5-PEB0 PEPROM Select Bits These read/write bits select bits PEPROM shown Table 9-1. Bits PEB2-PEB0 select PEPROM row, bits PEB5-PEB3 select PEPROM column. Reset clears PEB5-PEB0, selecting PEPROM zero, column zero.
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Freescale Semiconductor, Inc. Technical Data
Table 9-1. PEPROM Selection
PEBSR PEPROM Selected Column Column Column
Column Column Column Column
Column Column Column Column
Column Column Column Column Column Column Column Column Column
Technical Data
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Personality EPROM (MC68HC05K1 Only) PEPROM Registers
9.3.2 PEPROM Status Control Register PEPROM status control register (PESCR), shown Figure 9-3, controls PEPROM programming voltage. This register also transfers PEPROM bits internal data contains zero flag.
Address: $000F PEPGM Write: Reset: Unaffected PEPRZF
Read: PEDATA
Unimplemented
Figure 9-3. PEPROM Status Control Register (PESCR) PEDATA PEPROM Data This read-only state PEPROM sense amplifier shows state currently selected bit. Reset does affect PEDATA bit. PEPROM data logic PEPROM data logic PEPGM PEPROM Program Control This read/write controls switches that apply programming voltage, VPP, selected PEPROM cell. Reset clears PEPGM. Programming voltage applied Programming voltage applied PEPRZF PEPROM Zero Flag This read-only when PEPROM select register selects first (row zero) PEPROM array. Selecting other clears PEPRZF. Monitoring PEPRZF reduce code needed access byte PEPROM. Reset sets PEPRZF. zero selected zero selected
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Technical Data
Freescale Semiconductor, Inc. Technical Data PEPROM Programming
Factory-provided software programming PEPROM available through Motorola site htt://mcu.motsps.com circuit shown Figure used program PEPROM with factory-provided programming software.
NOTE:
personality EPROM cannot erased parts offered without windowed package. program PEPROM, must greater than Vdc. PEPROM also programmed user software with applied IRQ/VPP pin. This sequence shows program each PEPROM bit: Select PEPROM writing PEBSR. PEPGM PESCR. Wait Clear PEPGM bit.
NOTE:
While PEPGM applied IRQ/VPP pin, access bits that left unprogrammed (erased). 3-pin oscillator configuration, PEPROM cannot programmed user software. voltage IRQ/VPP raised above VDD, oscillator will revert 2-pin oscillator configuration device operation will disrupted. 2-pin crystal configurations affected.
Technical Data
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Personality EPROM (MC68HC05K1 Only) PEPROM Programming
STROBE INIT MC68HC05K1 RESET IRQ/VPP OSC1 OSC2
SENSE EMIT COMPARE MC34063
IN5817
OPTIONAL GENERATOR
Figure 9-4. Programming Circuit
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Freescale Semiconductor, Inc. Technical Data PEPROM Reading
This sequence shows read PEPROM: Select writing PEBSR. Read PEDATA PESCR. Store PEDATA register. Select another changing PEBSR.
Continue reading storing PEDATA bits until required personality EPROM data stored. Reading PEPROM easiest when each PEPROM column contains byte. Selecting row-0 selects first bit, incrementing PEPROM select register (PEBSR) selects next row-1 from same column. Incrementing PEBSR seven more times selects remaining bits column selects row-0 next column, setting row-0 flag, PEPRZF. PEPROM byte that been read transferred personality EPROM select register (PEBSR) that subsequent reads PEBSR quickly yield that PEPROM byte.
Technical Data
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Technical Data MC68HC05K0 MC68HC05K1
Section Instruction
10.1 Contents
10.2 Introduction
10.3 Addressing Modes 10.3.1 Inherent 10.3.2 Immediate. 10.3.3 Direct 10.3.4 Extended 10.3.5 Indexed, Offset 10.3.6 Indexed, 8-Bit Offset. 10.3.7 Indexed, 16-Bit Offset. 10.3.8 Relative 10.4 Instruction Types 10.4.1 Register/Memory Instructions. 10.4.2 Read-Modify-Write Instructions 10.4.3 Jump/Branch Instructions. .100 10.4.4 Manipulation Instructions .102 10.4.5 Control Instructions .103 10.5 10.6 Instruction Summary .104 Opcode .109
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Technical Data
Freescale Semiconductor, Inc. Technical Data 10.2 Introduction
microcontroller unit (MCU) instruction instructions uses eight addressing modes. instructions include those M146805 complementary metal oxide semiconductor (CMOS) Family plus more: unsigned multiply (MUL) instruction. instruction allows unsigned multiplication contents accumulator index register (X). high-order product stored index register, low-order product stored accumulator.
10.3 Addressing Modes
central processor unit (CPU) uses eight addressing modes flexibility accessing data. addressing modes provide eight different ways find data required execute instruction. eight addressing modes are: Inherent Immediate Direct Extended Indexed, offset Indexed, 8-bit offset Indexed, 16-bit offset Relative
Technical Data
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Instruction Addressing Modes
10.3.1 Inherent Inherent instructions those that have operand, such return from interrupt (RTI) stop (STOP). Some inherent instructions data registers, such carry flag (SEC) increment accumulator (INCA). Inherent instructions require operand address byte long.
10.3.2 Immediate
Immediate instructions those that contain value used operation with value accumulator index register. Immediate instructions require operand address bytes long. opcode first byte, immediate data value second byte.
10.3.3 Direct Direct instructions access first memory locations with bytes. first byte opcode, second byte operand address. direct addressing, automatically uses high byte operand address.
10.3.4 Extended Extended instructions three bytes access address memory. first byte opcode; second third bytes high bytes operand address. When using Motorola assembler, programmer does need specify whether instruction direct extended. assembler automatically selects shortest form instruction.
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Freescale Semiconductor, Inc. Technical Data
10.3.5 Indexed, Offset Indexed instructions with offset 1-byte instructions that access data with variable addresses within first memory locations. index register contains byte effective address operand. automatically uses high byte, these instructions address locations $0000-$00FF. Indexed, offset instructions often used move pointer through table hold address frequently used random-access memory (RAM) input/output (I/O) location.
10.3.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions 2-byte instructions that access data with variable addresses within first memory locations. adds unsigned byte index register unsigned byte following opcode. effective address operand. These instructions access locations $0000-$01FE. Indexed 8-bit offset instructions useful selecting element n-element table. table begin anywhere within first memory locations could extend location ($01FE). value typically index register, address beginning table byte following opcode.
10.3.7 Indexed, 16-Bit Offset Indexed, 16-bit offset instructions 3-byte instructions that access data with variable addresses location memory. adds unsigned byte index register unsigned bytes following opcode. effective address operand. first byte after opcode high byte 16-bit offset; second byte byte offset. Indexed, 16-bit offset instructions useful selecting element n-element table anywhere memory.
Technical Data
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Instruction Instruction Types
with direct extended addressing, Motorola assembler determines shortest form indexed addressing.
10.3.8 Relative Relative addressing only branch instructions. branch condition true, finds effective branch destination adding signed byte following opcode contents program counter. branch condition true, goes next instruction. offset signed, two's complement byte that gives branching range -128 +127 bytes from address next location after branch instruction. When using Motorola assembler, programmer does need calculate offset, because assembler determines proper offset verifies that within span branch.
10.4 Instruction Types
instructions fall into five categories: Register/memory instructions Read-modify-write instructions Jump/branch instructions manipulation instructions Control instructions
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Freescale Semiconductor, Inc. Technical Data
10.4.1 Register/Memory Instructions These instructions operate registers memory locations. Most them operands. operand either accumulator index register. finds other operand memory. Table 10-1. Register/Memory Instructions
Instruction Mnemonic
memory byte carry accumulator memory byte accumulator memory byte with accumulator test accumulator Compare accumulator Compare index register with memory byte Exclusive accumulator with memory byte Load accumulator with memory byte Load Index register with memory byte Multiply accumulator with memory byte Subtract memory byte carry from accumulator Store accumulator memory Store index register memory Subtract memory byte from accumulator
Technical Data
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Instruction Instruction Types
10.4.2 Read-Modify-Write Instructions These instructions read memory location register, modify contents, write modified value back memory location register.
NOTE:
read-modify-write operations write-only registers. Table 10-2. Read-Modify-Write Instructions
Instruction Mnemonic BCLR(1) BSET(1) TST(2)
Arithmetic shift left (same LSL) Arithmetic shift right clear Clear register Complement (one's complement) Decrement Increment Logical shift left (same ASL) Logical shift right Negate (two's complement) Rotate left through carry Rotate right through carry Test negative zero
Unlike other read-modify-write instructions, BCLR BSET only direct addressing. exception read-modify-write sequence because does write replacement value.
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Technical Data
Freescale Semiconductor, Inc. Technical Data
10.4.3 Jump/Branch Instructions Jump instructions allow interrupt normal sequence program counter. unconditional jump instruction (JMP) jump-to-subroutine instruction (JSR) have register operand. Branch instructions allow interrupt normal sequence program counter when test condition met. test condition met, branch performed. BRCLR BRSET instructions cause branch based state readable first memory locations. These 3-byte instructions combination direct addressing relative addressing. direct address byte tested byte following opcode. third byte signed offset byte. finds effective branch destination adding third byte program counter specified tests true. tested condition (set clear) part opcode. span branching from -128 +127 from address next location after branch instruction. also transfers tested carry/borrow condition code register.
Technical Data
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Instruction Instruction Types
Table 10-3. Jump Branch Instructions
Instruction Branch carry clear Branch carry Branch equal Branch half-carry clear Branch half-carry Branch higher Mnemonic BHCC BHCS BRCLR BRSET
Branch higher same Branch high Branch Branch lower Branch lower same Branch interrupt mask clear Branch minus Branch interrupt mask Branch equal Branch plus Branch always Branch clear Branch never Branch Branch subroutine Unconditional jump Jump subroutine
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Technical Data
Freescale Semiconductor, Inc. Technical Data
10.4.4 Manipulation Instructions clear writable first bytes memory, which includes registers on-chip locations. also test branch based state first memory locations. Table 10-4. Manipulation Instructions
Instruction Mnemonic BCLR BRCLR BRSET BSET
clear Branch clear Branch
Technical Data
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Instruction Instruction Types
10.4.5 Control Instructions These instructions registers control operation during program execution. Table 10-5. Control Instructions
Instruction Clear carry Clear interrupt mask Mnemonic STOP
WAIT
operation Reset stack pointer Return from interrupt Return from subroutine carry interrupt mask Stop oscillator enable Software interrupt Transfer accumulator index register Transfer index register accumulator Stop clock enable interrupts
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Technical Data
Freescale Semiconductor, Inc. Technical Data 10.5 Instruction Summary
Table 10-6. Instruction Summary (Sheet
Address Mode Opcode Source Form
#opr opr,X opr,X #opr opr,X opr,X #opr opr,X opr,X ASLA ASLX opr,X ASRA ASRX opr,X
Operation
Description
with Carry
without Carry
Logical
Arithmetic Shift Left (Same LSL)
Arithmetic Shift Right
Branch Carry Clear
(PC)
BCLR
Clear
(b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7)
BHCC BHCS
Branch Carry (Same BLO) Branch Equal Branch Half-Carry Clear Branch Half-Carry Branch Higher Branch Higher Same
(PC) (PC) (PC) (PC) (PC)
(PC)
Technical Data
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Cycles
Effect
Operand
Instruction Instruction Summary
Table 10-6. Instruction Summary (Sheet
Address Mode Opcode Source Form
#opr opr,X opr,X
Operation
Branch High Branch
Description
(PC) (PC)
Test Accumulator with Memory Byte
Branch Lower (Same BCS) Branch Lower Same Branch Interrupt Mask Clear Branch Minus Branch Interrupt Mask Branch Equal Branch Plus Branch Always
(PC) (PC) (PC) (PC) (PC) (PC) (PC)
(PC)
BRCLR Branch Clear
(PC)
(b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7)
Branch Never
(PC)
BRSET Branch
(PC)
(b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7) (b0) (b1) (b2) (b3) (b4) (b5) (b6) (b7)
BSET
Branch Subroutine
(PC) push (PCL) (SP) push (PCH) (SP) (PC)
Clear Carry Clear Interrupt Mask
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Technical Data
Cycles
Effect
Operand
Freescale Semiconductor, Inc. Technical Data
Table 10-6. Instruction Summary (Sheet
Address Mode Opcode Source Form
CLRA CLRX opr,X #opr opr,X opr,X COMA COMX opr,X #opr opr,X opr,X DECA DECX opr,X #opr opr,X opr,X INCA INCX opr,X opr,X opr,X
Operation
Description
Clear Byte
Compare Accumulator with Memory Byte
Complement Byte (One's Complement)
Compare Index Register with Memory Byte
Decrement Byte
EXCLUSIVE Accumulator with Memory Byte
Increment Byte
Unconditional Jump
Jump Address
Technical Data
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Cycles
Effect
Operand
Instruction Instruction Summary
Table 10-6. Instruction Summary (Sheet
Address Mode Opcode Source Form
opr,X opr,X #opr opr,X opr,X #opr opr,X opr,X LSLA LSLX opr,X LSRA LSRX opr,X NEGA NEGX opr,X #opr opr,X opr,X ROLA ROLX opr,X
Operation
Description
(PC) Push (PCL); (SP) Push (PCH); (SP) Effective Address
Jump Subroutine
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Logical Shift Left (Same ASL)
Logical Shift Right
Unsigned Multiply
-(M) -(A) -(X) -(M) -(M)
Negate Byte (Two's Complement)
Operation
Logical Accumulator with Memory
Rotate Byte Left through Carry
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Technical Data
Cycles
Effect
Operand
Freescale Semiconductor, Inc. Technical Data
Table 10-6. Instruction Summary (Sheet
Address Mode Opcode Source Form
RORA RORX opr,X
Operation
Description
Rotate Byte Right through Carry
Reset Stack Pointer
$00FF (SP) Pull (CCR) (SP) Pull (SP) Pull (SP) Pull (PCH) (SP) Pull (PCL) (SP) Pull (PCH) (SP) Pull (PCL)
Return from Interrupt
#opr opr,X opr,X opr,X opr,X STOP opr,X opr,X #opr opr,X opr,X
Return from Subroutine
Subtract Memory Byte Carry from Accumulator
Carry Interrupt Mask
Store Accumulator Memory
Stop Oscillator Enable
Store Index Register Memory
Subtract Memory Byte from Accumulator
Software Interrupt
(PC) Push (PCL) (SP) Push (PCH) (SP) Push (SP) Push (SP) Push (CCR) (SP) Interrupt Vector High Byte Interrupt Vector Byte
Transfer Accumulator Index Register
Technical Data
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Cycles
Effect
Operand
Instruction Opcode
Table 10-6. Instruction Summary (Sheet
Address Mode Opcode Source Form
TSTA TSTX opr,X WAIT
Operation
Description
Test Memory Byte Negative Zero
Transfer Index Register Accumulator Stop Clock Enable Interrupts Accumulator Carry/borrow flag Condition code register Direct address operand Direct address operand relative offset branch instruction Direct addressing mode High bytes offset indexed, 16-bit offset addressing Extended addressing mode Offset byte indexed, 8-bit offset addressing Half-carry flag High bytes operand address extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag
Operand (one bytes) Program counter Program counter high byte Program counter byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical Logical Logical EXCLUSIVE Contents Negation (two's complement) Loaded with Concatenated with cleared affected
10.6 Opcode
Table 10-7.
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Technical Data
Cycles
Effect
Operand
Table 10-7. Opcode
Branch Register/Memory
Manipulation Control
Read-Modify-Write
Instruction
Technical Data
STOP WAIT
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Opcode Hexadecimal Relative Indexed, Offset Indexed, 8-Bit Offset Indexed, 16-Bit Offset
BRSET0 BSET0 NEGA NEGX BRCLR0 BCLR0 BRSET1 BSET1 BRCLR1 BCLR1 COMA COMX BRSET2 BSET2 LSRA LSRX BRCLR2 BCLR2 BCS/BLO BRSET3 BSET3 RORA RORX BRCLR3 BCLR3 ASRA ASRX BRSET4 BHCC BSET4 ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL BRCLR4 BHCS BCLR4 ROLA ROLX BRSET5 BSET5 DECA DECX BRCLR5 BCLR5 BRSET6 BSET6 INCA INCX BRCLR6 BCLR6 TSTA TSTX BRSET7 BSET7 BRCLR7 BCLR7 CLRA CLRX
Opcode Hexadecimal
MC68HC05K0 MC68HC05K1 Rev.
Inherent Immediate Direct Extended
Number Cycles BRSET0 Opcode Mnemonic Number Bytes/Addressing Mode
Technical Data MC68HC05K0 MC68HC05K1
Section Electrical Specifications
11.1 Contents
11.2 Introduction .111 Maximum Ratings .112 Equivalent Loading .112 Operating Temperature Range. .113 Thermal Characteristics .113 Power Considerations. .114 5.0-Volt Electrical Characteristics .115 3.3-Volt Electrical Specifications .116
11.3 11.4 11.5 11.6 11.7 11.8 11.9
11.10 5.0-Volt Control Timing .120 11.11 3.3-Volt Control Timing .121 11.12 Typical Oscillator Characteristics .124
11.2 Introduction
This section contains electrical timing specifications.
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Technical Data
Freescale Semiconductor, Inc. Technical Data 11.3 Maximum Ratings
Maximum ratings extreme limits which exposed without permanently damaging contains circuitry protect inputs against damage from high static voltages; however, apply voltages higher than those shown table here. Keep VOut within range (VIn VOut) VDD. Connect unused inputs appropriate voltage level, either VDD.
Rating(1) Supply voltage Current drain excluding Storage temperature range
Symbol TSTG
Value -0.3 +7.0 +150
Unit
Maximum values guaranteed operating values.
NOTE:
This device guaranteed operate properly maximum ratings. Refer 11.8 5.0-Volt Electrical Characteristics 11.9 3.3-Volt Electrical Specifications guaranteed operating conditions.
11.4 Equivalent Loading
Figure 11-1 shows equivalent input/output (I/O) loading test purposes.
TEST POINT
PINS PA3-PA0, PB1-PB0
3.26 10.91
2.38 2.38 6.32
PA7-PA4 PA3-PA0, PB1-PB0
Figure 11-1. Equivalent Test Load
Technical Data MC68HC05K0 MC68HC05K1 Rev. Electrical Specifications More Information This Product, www.freescale.com
Electrical Specifications Operating Temperature Range
11.5 Operating Temperature Range
Rating Operating temperature range MC68HC05K0/K1P(1), DW(2) MC68HC05K0/K1C(3)P, MC68HC05K0/K1V(4)P, Symbol Value Unit
+105
Plastic dual in-line package (PDIP) Small outline integrated circuit (SOIC) Extended temperature range (-40°C +85°C) Automotive temperature range (-40°C +105°C)
11.6 Thermal Characteristics
Characteristic Maximum junction temperature Thermal resistance MC68HC05K0/K1P(1) MC68HC05K0/K1DW(2)
Plastic dual in-line package (PDIP) Small outline integrated circuit (SOIC)
Symbol
Value
Unit °C/W
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Technical Data
Freescale Semiconductor, Inc. Technical Data 11.7 Power Considerations
average chip junction temperature, obtained from:
Where: ambient temperature package thermal resistance, junction ambient °C/W PINT PI/O PINT chip internal power dissipation PI/O power dissipation input output pins (user-determined) most applications, PI/O PINT neglected. Ignoring PI/O, relationship between approximately: 273°C Solving equations gives: 273°C) (PD)2
where constant pertaining particular part. determined from equation measuring equilibrium) known Using this value values obtained solving equations iteratively value
Technical Data
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Electrical Specifications 5.0-Volt Electrical Characteristics
11.8 5.0-Volt Electrical Characteristics
Characteristic(1)
Output voltage ILoad 10.0 ILoad -10.0 Output high voltage (ILoad -0.8 PA7-PA0, PB1/OSC3, Output voltage PA3-PA0, PB1/OSC3, (ILoad PA7-PA4 (ILoad
Symbol
-0.1
Unit
Input high voltage PA7-PA0, PB1/OSC3, PB0, IRQ/VPP, RESET, OSC1 Input voltage PA7-PA0, PB1/OSC3, PB0, IRQ/VPP, RESET, OSC1 Supply current Run(2) Wait(3) Stop(4) 25°C +70°C (Standard) -40°C +85°C (Extended) enabled (25°C) disabled (25°C) ports hi-z leakage current PA7-PA0, PB1/OSC3, (pulldown devices off) Input pulldown current PA7-PA0, PB1/OSC3, (pulldown devices Input current IRQ/VPP, OSC1 RESET (pulldown device off) RESET (pulldown device Capacitance Ports (input output) RESET, IRQ/VPP Low-voltage reset threshold Oscillator internal resistor (OSC1 OSC2) PEPROM programming voltage(5) PEPROM programming current
17.0
17.5
18.0
COut VLVR ROSC
±10%, typical values reflect average measurements midpoint voltage range 25°C (operating) measured using external square wave clock source (fosc MHz). inputs from rail. loads. Less than outputs. OSC2. OSC2 capacitance linearly affects IDD. Wait measured using external square wave clock source (fosc MHz) inputs from rail. loads. Less than outputs. OSC2. ports configured inputs. OSC2 capacitance linearly affects wait IDD. Stop measured with OSC1 VDD. ports configured inputs. Programming voltage measured IRQ/VPP
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Technical Data
Freescale Semiconductor, Inc. Technical Data 11.9 3.3-Volt Electrical Specifications
Characteristic
Output voltage ILoad 10.0 ILoad -10.0 Output high voltage (ILoad -0.4 PA7-PA0, PB1/OSC3, Output voltage PA3-PA0, PB1/OSC3, (ILoad PA7-PA4 (ILoad Input high voltage PA7-PA0, PB1/OSC3, PB0, IRQ/VPP, RESET, OSC1 Input voltage PA7-PA0, PB1/OSC3, PB0, IRQ/VPP, RESET, OSC1 Supply current Run(2) Wait(3) Stop(4) 25°C 70°C (standard) -40°C +85°C (extended) ports hi-z leakage current PA7-PA0, PB1/OSC3, (pulldown devices off) Input pulldown current PA7-PA0, PB1/OSC3, (pulldown devices Input current IRQ/VPP, OSC1 RESET (pulldown devices off) RESET (pulldown devices Capacitance Ports (input output) RESET, IRQ/VPP Oscillator internal resistor (OSC1 OSC2)
Symbol
Typ(1)
Unit
0.05
COut ROSC
±0.3 typical values reflect average measurements midpoint voltage range 25°C (operating) measured using external square wave clock source (fosc MHz) with inputs from rail; loads; less than outputs; OSC2. OSC2 capacitance linearly affects IDD. Wait measured using external square wave clock source (fosc MHz). inputs from rail. loads. Less than outputs. OSC2. ports configured inputs. OSC2 capacitance linearly affects wait IDD. Stop measured with OSC1 VDD. Low-voltage reset disabled. ports configured inputs.
Technical Data
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Electrical Specifications 3.3-Volt Electrical Specifications
(NOTE (NOTE -1.0 -2.0 (mA) -3.0 -4.0 -5.0 -1.0
-2.0 (mA)
-3.0
-4.0
-5.0
Notes: Shaded area indicates variation driver characteristics changes temperature normal processing tolerances. Within limited range values shown, versus curves approximately straight lines. devices specified tested -0.8 devices specified tested -0.2
Figure 11-2. Typical High-Side Driver Characteristics
0.40 (NOTE 0.35 0.30 0.25 0.20 0.15 0.10 0.05 (mA) 10.0 0.35 0.30 0.25 0.20 0.15 0.10 0.05 (mA) 10.0 (NOTE 0.40
Notes: Shaded area indicates variation driver characteristics changes temperature normal processing tolerances. Within limited range values shown, versus. curves approximately straight lines. devices specified tested devices specified tested
Figure 11-3. Typical Low-Side Driver Characteristics
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Technical Data
Freescale Semiconductor, Inc. Technical Data
25°C
SUPPLY CURRENT (mA)
INTERNAL CLOCK FREQUENCY (MHz)
Figure 11-4. Typical versus Internal Clock Frequency
25°C
SUPPLY CURRENT (mA)
INTERNAL CLOCK FREQUENCY (MHz)
Figure 11-5. Typical Wait versus Internal Clock Frequency
Technical Data
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Electrical Specifications 3.3-Volt Electrical Specifications
2500
2000 SUPPLY CURRENT (nA) 1500 1000
TEMPERATURE (°C)
Figure 11-6. Typical Stop versus Temperature
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Technical Data
Freescale Semiconductor, Inc. Technical Data 11.10 5.0-Volt Control Timing
Characteristic(1) Oscillator frequency 3-pin oscillator 2-pin oscillator Crystal(2)/ceramic resonator External clock Internal operating frequency (fosc 3-pin oscillator 2-pin oscillator Crystal(1)/ceramic resonator External clock 2-pin oscillator frequency combined stability(4) fosc MHz; ±10%; -40°C +85°C fosc MHz; ±10%; +40°C 3-pin oscillator frequency combined stability(3) fosc MHz; ±10%; -40°C +85°C fosc MHz; ±10%; +40°C Cycle time fop) oscillator stabilization time Crystal oscillator startup time Stop recovery startup time RESET pulse width Timer resolution(5) interrupt pulse width (edge-triggered) interrupt pulse period PA3-PA0 interrupt pulse width high (edge-triggered) PA3-PA0 interrupt pulse period OSC1 pulse width PEPROM programming time byte(7) Symbol 0.1(3) 0.1(2) 0.500 0.05(2) 0.05(2) 0.250 Unit
fosc
fosc
fosc tcyc tRCON tOXOV tILCH tRESL tILIH tILIL tIHIL tIHIH tOH, tEPGM
Note(6) Note(5)
tcyc tcyc tcyc tcyc
±10% only AT-cut crystals. Minimum oscillator frequency with oscillator option limited only size external leakage external Includes processing tolerances variations temperature supply voltage; excludes tolerances external 2-bit timer prescaler limiting factor determining timer resolution. minimum period, tILIL tIHIH, should less than number cycles takes execute interrupt service routine plus tcyc. Programming time byte tEPGM which accumulated during multiple programming passes.
Technical Data
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Electrical Specifications 3.3-Volt Control Timing
11.11 3.3-Volt Control Timing
Characteristic(1) Oscillator frequency 3-pin oscillator 2-pin oscillator Crystal(2)/ceramic resonator External clock Internal operating frequency (fosc 3-pin oscillator 2-pin oscillator Crystal(1)/ceramic resonator External clock 2-pin oscillator frequency combined stability(4) fosc MHz; ±0.3 -40°C +85°C fosc MHz; ±0.3 +40°C 3-pin oscillator frequency combined stability(3) fosc MHz; -40°C +85°C fosc MHz; +40°C Cycle time fop) oscillator stabilization time Crystal oscillator startup time Stop recovery startup time RESET pulse width Timer resolution(5) interrupt pulse width (edge-triggered) interrupt pulse period PA3-PA0 interrupt pulse width high (edge-triggered) PA3-PA0 interrupt pulse period OSC1 pulse width Symbol 0.1(3) 0.1(2) 0.500 0.05(2) 0.05(2) 0.250 Unit
fosc
fosc
fosc tcyc tRCON tOXOV tILCH tRESL tILIH tILIL tIHIL tIHIH tOH,
1000 Note(6) Note(5)
tcyc tcyc tcyc tcyc
±10% only AT-cut crystals. Minimum oscillator frequency with oscillator option limited only size external leakage external Includes processing tolerances variations temperature supply voltage; excludes tolerances external 2-bit timer prescaler limiting factor determining timer resolution. minimum period, tILIL tIHIH, should less than number cycles takes execute interrupt service routine plus tcyc.
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Technical Data
Freescale Semiconductor, Inc. Technical Data
tILIL IRQ/VPP tILIH
IRQ1
tILIH
IRQn
(INTERNAL)
Figure 11-7. External Interrupt Timing
(NOTE RESET tILIH IRQ/VPP (NOTE 4064 tCYC IRQ/VPP (NOTE
INTERNAL CLOCK
INTERNAL ADDRESS
03FE (NOTE
03FE
03FE
03FE
03FE
03FF
Notes: Internal clocking from OSC1 Edge-triggered external interrupt mask option Edge- level-triggered external interrupt mask option Reset vector shown example
RESET INTERRUPT VECTOR FETCH
Figure 11-8. Stop Mode Recovery Timing
Technical Data
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Electrical Specifications 3.3-Volt Control Timing
NOTE OSC1 4064 tCYC
INTERNAL CLOCK
INTERNAL ADDRESS
03FE
03FE
03FE
03FE
03FE
03FE
03FF
INTERNAL DATA Notes: Power-on reset threshold typically between Internal clock, internal address bus, internal data available externally.
Figure 11-9. Power-On Reset Timing
INTERNAL CLOCK
INTERNAL ADDRESS
03FE
03FE
03FE
03FE
03FF
INTERNAL DATA
DUMMY
CODE
Notes: Internal clock, internal address bus, internal data available externally. next rising edge internal clock after rising edge RESET initiates reset sequence.
Figure 11-10. External Reset Timing
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Technical Data
Freescale Semiconductor, Inc. Technical Data 11.12 Typical Oscillator Characteristics
Parameter Oscillator Type Nominal Frequency Units
Frequency Variation (Part-to-Part) 2-pin oscillator 3-pin oscillator
Frequency Variation with Temperature 2-pin oscillator 3-pin oscillator -2100 -1100 -1600 ppm/°C -1100
Frequency Variation with Supply Voltage 2-pin oscillator 3-pin oscillator ±1.0 ±0.3 ±0.2 ±0.1 %f/%V
Cumulative Frequency Variations(1) 2-pin oscillator 3-pin oscillator
±10%; -40°C +85°C
Technical Data
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Electrical Specifications Typical Oscillator Characteristics
EXTERNAL FREQUENCY 500.0 000.0 RESISTANCE
Figure 11-11. 2-Pin Oscillator versus Frequency (VDD
EXTERNAL FREQUENCY
500.0
000.0 RESISTANCE
Figure 11-12. 3-Pin Oscillator versus Frequency (VDD
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Technical Data
Freescale Semiconductor, Inc. Technical Data
EXTERNAL FREQUENCY
500.0
000.0 RESISTANCE
Figure 11-13. 2-Pin Oscillator versus Frequency (VDD
EXTERNAL FREQUENCY
500.0
000.0 RESISTANCE
Figure 11-14. 3-Pin Oscillator versus Frequency (VDD
Technical Data
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Technical Data MC68HC05K0 MC68HC05K1
Section Mechanical Specifications
12.1 Contents
12.2 Introduction .127 MC68HC05K0/MC68HC05K1P (PDIP) .128 MC68HC05K0/MC68HC05K1DW (SOIC) .128
12.3 12.4
12.2 Introduction
Package dimensions available time this publication provided this section. packages are: 16-pin plastic dual-in-line package (PDIP) 16-pin small outline integrated circuit (SOIC)
make sure that have latest case outline specifications, contact these: Local Motorola sales office Motorola Mfax Phone 602-244-6609 EMAIL rmfax0@email.sps.mot.com World Wide (wwweb) http://www.mcu.motsps.com
Follow Mfax wwweb on-line instructions retrieve current mechanical specifications.
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Technical Data
Freescale Semiconductor, Inc. Technical Data 12.3 MC68HC05K0/MC68HC05K1P (PDIP)
-A16
INCHES 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 0.050 0.008 0.015 0.110 0.130 0.295 0.305 0.020 0.040
MILLIMETERS 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 1.27 0.21 0.38 2.80 3.30 7.50 7.74 0.51 1.01
SEATING PLANE
0.25 (0.010)
12.4 MC68HC05K0/MC68HC05K1DW (SOIC)
-A16
0.010 (0.25)
MILLIMETERS 10.15 10.45 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 0.25 0.32 0.10 0.25 10.05 10.55 0.25 0.75
INCHES 0.400 0.411 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 0.010 0.012 0.004 0.009 0.395 0.415 0.010 0.029
0.010 (0.25)
SEATING PLANE
Technical Data
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Technical Data MC68HC05K0 MC68HC05K1
Section Ordering Information
13.1 Contents
13.2 Introduction .129 Ordering Forms .130
13.3
13.4 Application Program Media. .130 13.4.1 Diskettes. .131 13.4.2 EPROMs .132 13.5 13.6 13.7 Program Verification .132 Verification Units (RVUs). .133 Order Numbers .134
13.2 Introduction
This section contains instructions ordering custom-masked read-only memory (ROM) microcontroller units (MCU).
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Technical Data
Freescale Semiconductor, Inc. Technical Data 13.3 Ordering Forms
initiate order ROM-based MCU, first obtain current ordering form from Motorola representative. Submit these items when ordering MCUs: current ordering form that completely filled out. Contact Motorola sales office assistance. copy customer specification customer specification deviates from Motorola specification Customer's application program media listed 13.4 Application Program Media
current ordering form also available through World Wide (wwweb) http://www.mcu.motsps.com
13.4 Application Program Media
Deliver application program Motorola these media: Macintosh®1 1/2-inch diskette (double-sided double-density Kbytes double-sided high-density Mbytes) MS-DOS®2 PC-DOS®3 1/2-inch diskette (double-sided double-density Kbytes double-sided high-density 1.44 Mbytes) MS-DOS® PC-DOS® 1/4-inch diskette (double-sided double-density Kbytes double-sided high-density Mbytes) Erasable, programmable read-only memory(s) (EPROM) 2716, 2732, 2764, 27,128, 27,256, 27,512 (depending size memory MCU)
positive logic data addresses.
Macintosh registered trademark Apple Computer, Inc. MS-DOS registered trademark Microsoft, Inc. PC-DOS registered trademark International Business Machines Corporation.
Technical Data
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Ordering Information Application Program Media
13.4.1 Diskettes submitting application program diskette, clearly label diskette with this information: Customer name Customer part number Project product name Filename object code Date Name o
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