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MC68336 376


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MC68336/376
USER'S MANUAL
TouCAN trademark Motorola, Inc.
Motorola reserves right make changes without further notice products herein. Motorola makes warranty, representation guarantee regarding suitability products particular purpose, does Motorola assume liability arising application product circuit, specifically disclaims liability, including without limitation consequential incidental damages. "Typical" parameters vary different applications. operating parameters, including "Typicals" must validated each customer application customer's technical experts. Motorola does convey license under patent rights rights others. Motorola products designed, intended, authorized components systems intended surgical implant into body, other applications intended support sustain life, other application which failure Motorola product could create situation where personal injury death occur. Should Buyer purchase Motorola products such unintended unauthorized application, Buyer shall indemnify hold Motorola officers, employees, subsidiaries, affiliates, distributors harmless against claims, costs, damages, expenses, reasonable attorney fees arising directly indirectly, claim personal injury death associated with such unintended unauthorized use, even such claim alleges that Motorola negligent regarding design manufacture part. MOTOROLA registered trademarks Motorola, Inc. Motorola, Inc. Equal Opportunity/Affirmative Action Employer.
MOTOROLA, INC. 1996
TABLE CONTENTS Paragraph Title SECTION INTRODUCTION SECTION NOMENCLATURE Symbols Operators CPU32 Registers Signal Mnemonics Register Mnemonics Conventions SECTION OVERVIEW 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 3.1.9 3.1.10 Features Central Processing Unit (CPU32) System Integration Module (SIM) Standby Module (SRAM) Masked Module (MRM) 10-Bit Queued Analog-to-Digital Converter (QADC) Queued Serial Module (QSM) Configurable Timer Module Version (CTM4) Time Processor Unit (TPU) Static Module with Emulation Capability (TPURAM) 2.0B Controller Module (TouCAN) Intermodule System Block Diagram Assignment Diagrams Descriptions Signal Descriptions Internal Register 3-13 Address Space Maps 3-14 SECTION CENTRAL PROCESSOR UNIT 4.2.1 4.2.2 4.2.3 4.2.4 General CPU32 Registers Data Registers Address Registers Program Counter Control Registers
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4.2.4.1 Status Register 4.2.4.2 Alternate Function Code Registers 4.2.5 Vector Base Register (VBR) Memory Organization Virtual Memory Addressing Modes Processing States Privilege Levels 4-10 Instructions 4-10 4.8.1 M68000 Family Compatibility 4-14 4.8.2 Special Control Instructions 4-14 4.8.2.1 Low-Power Stop (LPSTOP) 4-14 4.8.2.2 Table Lookup Interpolate (TBL) 4-14 4.8.2.3 Loop Mode Instruction Execution 4-15 Exception Processing 4-15 4.9.1 Exception Vectors 4-15 4.9.2 Types Exceptions 4-17 4.9.3 Exception Processing Sequence 4-17 4.10 Development Support 4-17 4.10.1 M68000 Family Development Support 4-18 4.10.2 Background Debug Mode 4-18 4.10.3 Enabling 4-19 4.10.4 Sources 4-19 4.10.4.1 External BKPT Signal 4-20 4.10.4.2 BGND Instruction 4-20 4.10.4.3 Double Fault 4-20 4.10.4.4 Peripheral Breakpoints 4-20 4.10.5 Entering 4-20 4.10.6 Commands 4-21 4.10.7 Background Mode Registers 4-22 4.10.7.1 Fault Address Register (FAR) 4-22 4.10.7.2 Return Program Counter (RPC) 4-22 4.10.7.3 Current Instruction Program Counter (PCC) 4-23 4.10.8 Returning from 4-23 4.10.9 Serial Interface 4-23 4.10.10 Recommended Connection 4-25 4.10.11 Deterministic Opcode Tracking 4-26 4.10.12 On-Chip Breakpoint Hardware 4-26
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Paragraph (Continued) Title SECTION SYSTEM INTEGRATION MODULE General System Configuration 5.2.1 Module Mapping 5.2.2 Interrupt Arbitration 5.2.3 Show Internal Cycles 5.2.4 Register Access 5.2.5 Freeze Operation System Clock 5.3.1 Clock Sources 5.3.2 Clock Synthesizer Operation 5.3.3 External Clock 5-12 5.3.4 Low-Power Operation 5-12 System Protection 5-14 5.4.1 Reset Status 5-14 5.4.2 Monitor 5-14 5.4.3 Halt Monitor 5-15 5.4.4 Spurious Interrupt Monitor 5-15 5.4.5 Software Watchdog 5-15 5.4.6 Periodic Interrupt Timer 5-17 5.4.7 Interrupt Priority Vectoring 5-18 5.4.8 Low-Power STOP Mode Operation 5-19 External Interface 5-19 5.5.1 Control Signals 5-21 5.5.1.1 Address 5-21 5.5.1.2 Address Strobe 5-21 5.5.1.3 Data 5-21 5.5.1.4 Data Strobe 5-22 5.5.1.5 Read/Write Signal 5-22 5.5.1.6 Size Signals 5-22 5.5.1.7 Function Codes 5-22 5.5.1.8 Data Size Acknowledge Signals 5-23 5.5.1.9 Error Signal 5-23 5.5.1.10 Halt Signal 5-23 5.5.1.11 Autovector Signal 5-24 5.5.2 Dynamic Sizing 5-24 5.5.3 Operand Alignment 5-25 5.5.4 Misaligned Operands 5-25 5.5.5 Operand Transfer Cases 5-26 Operation 5-26
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5.6.1 Synchronization CLKOUT 5-26 5.6.2 Regular Cycles 5-27 5.6.2.1 Read Cycle 5-28 5.6.2.2 Write Cycle 5-29 5.6.3 Fast Termination Cycles 5-30 5.6.4 Space Cycles 5-30 5.6.4.1 Breakpoint Acknowledge Cycle 5-31 5.6.4.2 LPSTOP Broadcast Cycle 5-34 5.6.5 Exception Control Cycles 5-34 5.6.5.1 Errors 5-36 5.6.5.2 Double Faults 5-36 5.6.5.3 Retry Operation 5-37 5.6.5.4 Halt Operation 5-37 5.6.6 External Arbitration 5-38 5.6.6.1 Show Cycles 5-39 Reset 5-40 5.7.1 Reset Exception Processing 5-40 5.7.2 Reset Control Logic 5-40 5.7.3 Reset Mode Selection 5-41 5.7.3.1 Data Mode Selection 5-42 5.7.3.2 Clock Mode Selection 5-44 5.7.3.3 Breakpoint Mode Selection 5-45 5.7.4 Module Function During Reset 5-45 5.7.5 States During Reset 5-46 5.7.5.1 Reset States Pins 5-46 5.7.5.2 Reset States Pins Assigned Other Modules 5-47 5.7.6 Reset Timing 5-47 5.7.7 Power-On Reset 5-48 5.7.8 Three-State Control 5-49 5.7.9 Reset Processing Summary 5-50 5.7.10 Reset Status Register 5-50 Interrupts 5-50 5.8.1 Interrupt Exception Processing 5-50 5.8.2 Interrupt Priority Recognition 5-51 5.8.3 Interrupt Acknowledge Arbitration 5-52 5.8.4 Interrupt Processing Summary 5-53 5.8.5 Interrupt Acknowledge Cycles 5-54 Chip-Selects 5-54 5.9.1 Chip-Select Registers 5-57 5.9.1.1 Chip-Select Assignment Registers 5-57 5.9.1.2 Chip-Select Base Address Registers 5-58
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5.9.1.3 Chip-Select Option Registers 5-59 5.9.1.4 Port Data Register 5-60 5.9.2 Chip-Select Operation 5-60 5.9.3 Using Chip-Select Signals Interrupt Acknowledge 5-61 5.9.4 Chip-Select Reset Operation 5-62 5.10 Parallel Input/Output Ports 5-64 5.10.1 Assignment Registers 5-64 5.10.2 Data Direction Registers 5-64 5.10.3 Data Registers 5-64 5.11 Factory Test 5-64 SECTION STANDBY MODULE SRAM Register Block SRAM Array Address Mapping SRAM Array Address Space Type Normal Access Standby Low-Power Stop Operation Reset SECTION MASKED MODULE Register Block Array Address Mapping Array Address Space Type Normal Access Low-Power Stop Mode Operation Signature Reset SECTION QUEUED ANALOG-TO-DIGITAL CONVERTER MODULE 8.4.1 8.4.1.1 8.4.1.2 General QADC Address QADC Registers QADC Functions Port Functions Port Analog Input Pins Port Digital Input/Output Pins
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8.4.2 Port Functions 8.4.2.1 Port Analog Input Pins 8.4.2.2 Port Digital Input Pins 8.4.3 External Trigger Input Pins 8.4.4 Multiplexed Address Output Pins 8.4.5 Multiplexed Analog Input Pins 8.4.6 Voltage Reference Pins 8.4.7 Dedicated Analog Supply Pins 8.4.8 External Digital Supply 8.4.9 Digital Supply Pins QADC Interface Module Configuration 8.6.1 Low-Power Stop Mode 8.6.2 Freeze Mode 8.6.3 Supervisor/Unrestricted Address Space 8.6.4 Interrupt Arbitration Priority Test Register General-Purpose Port Operation 8.8.1 Port Data Register 8.8.2 Port Data Direction Register External Multiplexing Operation 8-10 8.10 Analog Input Channels 8-12 8.11 Analog Subsystem 8-12 8.11.1 Conversion Cycle Times 8-13 8.11.1.1 Amplifier Bypass Mode Conversion Timing 8-14 8.11.2 Front-End Analog Multiplexer 8-15 8.11.3 Digital Analog Converter Array 8-15 8.11.4 Comparator 8-16 8.11.5 Successive Approximation Register 8-16 8.12 Digital Control Subsystem 8-16 8.12.1 Queue Priority 8-16 8.12.2 Queue Boundary Conditions 8-19 8.12.3 Scan Modes 8-20 8.12.3.1 Disabled Mode Reserved Mode 8-20 8.12.3.2 Single-Scan Modes 8-20 8.12.3.3 Continuous-Scan Modes 8-22 8.12.4 QADC Clock (QCLK) Generation 8-24 8.12.5 Periodic/Interval Timer 8-27 8.12.6 Control Status Registers 8-28 8.12.6.1 Control Register (QACR0) 8-28 8.12.6.2 Control Register (QACR1) 8-28
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8.12.6.3 Control Register (QACR2) 8-28 8.12.6.4 Status Register (QASR) 8-28 8.12.7 Conversion Command Word Table 8-28 8.12.8 Result Word Table 8-31 8.13 Interrupts 8-32 8.13.1 Interrupt Sources 8-32 8.13.2 Interrupt Register 8-32 8.13.3 Interrupt Vectors 8-33 8.13.4 Initializing QADC Interrupt Driven Operation 8-34 SECTION QUEUED SERIAL MODULE 9.2.1 9.2.1.1 9.2.1.2 9.2.1.3 9.2.2 9.3.1 9.3.1.1 9.3.1.2 9.3.2 9.3.2.1 9.3.2.2 9.3.2.3 9.3.3 9.3.4 9.3.5 9.3.5.1 9.3.5.2 9.3.5.3 9.3.5.4 9.3.6 9.4.1 9.4.1.1 9.4.1.2 9.4.1.3 9.4.2 General Registers Address Global Registers Low-Power Stop Operation Freeze Operation Interrupts Control Registers Queued Serial Peripheral Interface QSPI Registers Control Registers Status Register QSPI Receive Transmit Command QSPI Pins QSPI Operation QSPI Operating Modes Master Mode 9-16 Master Wrap-Around Mode 9-19 Slave Mode 9-19 Slave Wrap-Around Mode 9-20 Peripheral Chip Selects 9-20 Serial Communication Interface 9-21 Registers 9-21 Control Registers 9-21 Status Register 9-24 Data Register 9-24 Pins 9-24
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9.4.3 Operation 9-24 9.4.3.1 Definition Terms 9-25 9.4.3.2 Serial Formats 9-25 9.4.3.3 Baud Clock 9-25 9.4.3.4 Parity Checking 9-26 9.4.3.5 Transmitter Operation 9-26 9.4.3.6 Receiver Operation 9-28 9.4.3.7 Idle-Line Detection 9-28 9.4.3.8 Receiver Wake-Up 9-29 9.4.3.9 Internal Loop 9-30 Initialization 9-30 SECTION CONFIGURABLE TIMER MODULE 10.1 General 10-1 10.2 Address 10-2 10.3 Time Base System 10-2 10.4 Interface Unit Submodule (BIUSM) 10-3 10.4.1 STOP Effect BIUSM 10-3 10.4.2 Freeze Effect BIUSM 10-3 10.4.3 LPSTOP Effect BIUSM 10-4 10.4.4 BIUSM Registers 10-4 10.5 Counter Prescaler Submodule (CPSM) 10-4 10.5.1 CPSM Registers 10-5 10.6 Free-Running Counter Submodule (FCSM) 10-5 10.6.1 FCSM Counter 10-6 10.6.2 FCSM Clock Sources 10-6 10.6.3 FCSM External Event Counting 10-6 10.6.4 FCSM Time Base Driver 10-6 10.6.5 FCSM Interrupts 10-6 10.6.6 FCSM Registers 10-7 10.7 Modulus Counter Submodule (MCSM) 10-7 10.7.1 MCSM Modulus Latch 10-8 10.7.2 MCSM Counter 10-8 10.7.2.1 Loading MCSM Counter Register 10-8 10.7.2.2 Using MCSM Free-Running Counter 10-9 10.7.3 MCSM Clock Sources 10-9 10.7.4 MCSM External Event Counting 10-9 10.7.5 MCSM Time Base Driver 10-9 10.7.6 MCSM Interrupts 10-9 10.7.7 MCSM Registers 10-10
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10.8 Double-Action Submodule (DASM) 10-10 10.8.1 DASM Interrupts 10-12 10.8.2 DASM Registers 10-12 10.9 Pulse-Width Modulation Submodule (PWMSM) 10-12 10.9.1 Output Flip-Flop 10-13 10.9.2 Clock Selection 10-13 10.9.3 PWMSM Counter 10-14 10.9.4 PWMSM Period Registers Comparator 10-14 10.9.5 PWMSM Pulse-Width Registers Comparator 10-15 10.9.6 PWMSM Coherency 10-15 10.9.7 PWMSM Interrupts 10-15 10.9.8 Frequency 10-16 10.9.9 Pulse Width 10-17 10.9.10 Period Pulse Width Register Values 10-17 10.9.10.1 Duty Cycle Boundary Cases 10-17 10.9.11 PWMSM Registers 10-17 10.10 CTM4 Interrupts 10-18 SECTION TIME PROCESSOR UNIT 11.1 11.2 11.2.1 11.2.2 11.2.3 11.2.4 11.2.5 11.2.6 11.3 11.3.1 11.3.2 11.3.3 11.3.4 11.3.5 11.3.6 11.3.7 11.4 11.4.1 11.4.2 11.4.3 11.4.4 General 11-1 Components 11-2 Time Bases 11-2 Timer Channels 11-2 Scheduler 11-3 Microengine 11-3 Host Interface 11-3 Parameter 11-3 Operation 11-3 Event Timing 11-4 Channel Orthogonality 11-4 Interchannel Communication 11-4 Programmable Channel Service Priority 11-4 Coherency 11-4 Emulation Support 11-5 Interrupts 11-5 Mask Time Functions 11-6 Discrete Input/Output (DIO) 11-6 Input Capture/Input Transition Counter (ITC) 11-6 Output Compare (OC) 11-7 Pulse-Width Modulation (PWM) 11-7
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11.4.5 Synchronized Pulse-Width Modulation (SPWM) 11-7 11.4.6 Period Measurement with Additional Transition Detect (PMA) 11-8 11.4.7 Period Measurement with Missing Transition Detect (PMM) 11-8 11.4.8 Position-Synchronized Pulse Generator (PSP) 11-8 11.4.9 Stepper Motor (SM) 11-9 11.4.10 Period/Pulse-Width Accumulator (PPWA) 11-9 11.4.11 Quadrature Decode (QDEC) 11-10 11.5 Mask Time Functions 11-10 11.5.1 Table Stepper Motor (TSM) 11-10 11.5.2 Input Capture/Transition Counter (NITC) 11-11 11.5.3 Queued Output Match (QOM) 11-11 11.5.4 Programmable Time Accumulator (PTA) 11-11 11.5.5 Multichannel Pulse-Width Modulation (MCPWM) 11-11 11.5.6 Fast Quadrature Decode (FQD) 11-12 11.5.7 Universal Asynchronous Receiver/Transmitter (UART) 11-12 11.5.8 Brushless Motor Commutation (COMM) 11-12 11.5.9 Frequency Measurement (FQM) 11-13 11.5.10 Hall Effect Decode (HALLD) 11-13 11.6 Host Interface Registers 11-13 11.6.1 System Configuration Registers 11-13 11.6.1.1 Prescaler Control TCR1 11-13 11.6.1.2 Prescaler Control TCR2 11-14 11.6.1.3 Emulation Control 11-15 11.6.1.4 Low-Power Stop Control 11-15 11.6.2 Channel Control Registers 11-15 11.6.2.1 Channel Interrupt Enable Status Registers 11-15 11.6.2.2 Channel Function Select Registers 11-16 11.6.2.3 Host Sequence Registers 11-16 11.6.2.4 Host Service Registers 11-17 11.6.2.5 Channel Priority Registers 11-17 11.6.3 Development Support Test Registers 11-17 SECTION STANDBY WITH EMULATION 12.1 12.2 12.3 12.4 12.5 12.6 12.7 General 12-1 TPURAM Register Block 12-1 TPURAM Array Address Mapping 12-1 TPURAM Privilege Level 12-2 Normal Operation 12-2 Standby Operation 12-2 Low-Power Stop Operation 12-3
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Reset 12-3 Microcode Emulation 12-3 SECTION 2.0B CONTROLLER MODULE (TouCAN)
13.1 General 13-1 13.2 External Pins 13-2 13.3 Programmer's Model 13-2 13.4 TouCAN Architecture 13-3 13.4.1 TX/RX Message Buffer Structure 13-3 13.4.1.1 Common Fields Extended Standard Format Frames 13-4 13.4.1.2 Fields Extended Format Frames 13-5 13.4.1.3 Fields Standard Format Frames 13-5 13.4.1.4 Serial Message Buffers 13-6 13.4.1.5 Message Buffer Activation/Deactivation Mechanism 13-6 13.4.1.6 Message Buffer Lock/Release/Busy Mechanism 13-6 13.4.2 Receive Mask Registers 13-7 13.4.3 Timing 13-8 13.4.3.1 Configuring TouCAN Timing 13-9 13.4.4 Error Counters 13-9 13.4.5 Time Stamp 13-10 13.5 TouCAN Operation 13-11 13.5.1 TouCAN Reset 13-11 13.5.2 TouCAN Initialization 13-11 13.5.3 Transmit Process 13-12 13.5.3.1 Transmit Message Buffer Deactivation 13-13 13.5.3.2 Reception Transmitted Frames 13-13 13.5.4 Receive Process 13-13 13.5.4.1 Receive Message Buffer Deactivation 13-14 13.5.4.2 Locking Releasing Message Buffers 13-15 13.5.5 Remote Frames 13-15 13.5.6 Overload Frames 13-16 13.6 Special Operating Modes 13-16 13.6.1 Debug Mode 13-16 13.6.2 Low-Power Stop Mode 13-17 13.6.3 Auto Power Save Mode 13-18 13.7 Interrupts 13-19
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Paragraph (Continued) Title APPENDIX ELECTRICAL CHARACTERISTICS APPENDIX MECHANICAL DATA ORDERING INFORMATION Obtaining Updated MC68336/376 Mechanical Information Ordering Information APPENDIX DEVELOPMENT SUPPORT M68MMDS1632 Modular Development System M68MEVB1632 Modular Evaluation Board APPENDIX REGISTER SUMMARY Central Processor Unit D.1.1 CPU32 Register Model D.1.2 Status Register System Integration Module D.2.1 Configuration Register D.2.2 System Integration Test Register D.2.3 Clock Synthesizer Control Register D.2.4 Reset Status Register D.2.5 System Integration Test Register (ECLK) D.2.6 Port Data Register D-10 D.2.7 Port Data Direction Register D-10 D.2.8 Port Assignment Register D-10 D.2.9 Port Data Register D-11 D.2.10 Port Data Direction Register D-11 D.2.11 Port Assignment Register D-11 D.2.12 System Protection Control Register D-12 D.2.13 Periodic Interrupt Control Register D-13 D.2.14 Periodic Interrupt Timer Register D-14 D.2.15 Software Watchdog Service Register D-14 D.2.16 Port Data Register D-15 D.2.17 Chip-Select Assignment Registers D-15 D.2.18 Chip-Select Base Address Register Boot D-17 D.2.19 Chip-Select Base Address Registers D-17 D.2.20 Chip-Select Option Register Boot D-18
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Paragraph D.2.21 D.2.22 D.2.23 D.2.24 D.2.25 D.2.26 D.3.1 D.3.2 D.3.3 D.3.4 D.4.1 D.4.2 D.4.3 D.4.4 D.4.5 D.4.6 D.5.1 D.5.2 D.5.3 D.5.4 D.5.5 D.5.6 D.5.7 D.5.8 D.5.9 D.6.1 D.6.2 D.6.3 D.6.4 D.6.5 D.6.7 D.6.8 D.6.9 D.6.10 D.6.11 D.6.12 D.6.13 (Continued) Title Page
Chip-Select Option Registers D-18 Master Shift Registers D-21 Test Module Shift Count Register D-21 Test Module Repetition Count Register D-21 Test Submodule Control Register D-21 Distributed Register D-21 Standby Module D-22 Module Configuration Register D-22 Test Register D-23 Array Base Address Register High D-23 Array Base Address Register D-23 Masked Module D-24 Masked Module Configuration Register D-24 Array Base Address Register High D-26 Array Base Address Register D-26 Signature High Register D-26 Signature Register D-26 Bootstrap Words D-27 QADC Module D-28 QADC Module Configuration Register D-28 QADC Test Register D-29 QADC Interrupt Register D-29 Port Data Register D-30 Port Data Direction Register D-30 QADC Control Registers D-31 QADC Status Register D-35 Conversion Command Word Table D-37 Result Word Table D-39 Queued Serial Module D-40 Configuration Register D-40 Test Register D-41 Interrupt Level Register D-41 Interrupt Vector Register D-42 Control Register D-42 Status Register D-45 Data Register D-46 Port Data Register D-46 Port Assignment Register/Data Direction Register D-47 QSPI Control Register D-48 QSPI Control Register D-50 QSPI Control Register D-51
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D.6.14 QSPI Control Register D-52 D.6.15 QSPI Status Register D-53 D.6.16 Receive Data D-53 D.6.17 Transmit Data D-54 D.6.18 Command D-54 Configurable Timer Module D-56 D.7.1 Module Configuration Register D-57 D.7.2 BIUSM Test Configuration Register D-58 D.7.3 BIUSM Time Base Register D-58 D.7.4 CPSM Control Register D-58 D.7.5 CPSM Test Register D-59 D.7.6 FCSM Status/Interrupt/Control Register D-59 D.7.7 FCSM Counter Register D-61 D.7.8 MCSM Status/Interrupt/Control Registers D-61 D.7.9 MCSM Counter Registers D-63 D.7.10 MCSM Modulus Latch Registers D-63 D.7.11 DASM Status/Interrupt/Control Registers D-63 D.7.12 DASM Data Register D-66 D.7.13 DASM Data Register D-67 D.7.14 Status/Interrupt/Control Register D-68 D.7.15 Period Register D-71 D.7.16 Pulse Width Register D-71 D.7.17 Counter Register D-72 Time Processor Unit (TPU) D-73 D.8.1 Module Configuration Register D-73 D.8.2 Test Configuration Register D-75 D.8.3 Development Support Control Register D-75 D.8.4 Development Support Status Register D-76 D.8.5 Interrupt Configuration Register D-77 D.8.6 Channel Interrupt Enable Register D-77 D.8.7 Channel Function Select Registers D-78 D.8.8 Host Sequence Registers D-78 D.8.9 Host Service Request Registers D-79 D.8.10 Channel Priority Registers D-79 D.8.11 Channel Interrupt Status Register D-80 D.8.12 Link Register D-80 D.8.13 Service Grant Latch Register D-80 D.8.14 Decoded Channel Number Register D-80 D.8.15 Parameter D-80 Standby Module with Emulation Capability (TPURAM) D-82 D.9.1 TPURAM Module Configuration Register D-82
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D.9.2 TPURAM Test Register D-82 D.9.3 TPURAM Module Configuration Register D-82 D.10 TouCAN Module D-84 D.10.1 TouCAN Module Configuration Register D-85 D.10.2 TouCAN Test Configuration Register D-88 D.10.3 TouCAN Interrupt Configuration Register D-88 D.10.4 Control Register D-88 D.10.5 Control Register D-90 D.10.6 Prescaler Divide Register D-91 D.10.7 Control Register D-91 D.10.8 Free Running Timer D-92 D.10.9 Receive Global Mask Registers D-93 D.10.10 Receive Buffer Mask Registers D-93 D.10.11 Receive Buffer Mask Registers D-93 D.10.12 Error Status Register D-94 D.10.13 Interrupt Mask Register D-96 D.10.14 Interrupt Flag Register D-96 D.10.15 Error Counters D-97
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Figure 4-10 4-11 4-12 5-10 5-11 5-12 5-13 5-14 5-15 5-16 5-17 5-18 5-19 5-20 5-21 Title Page
MC68336/376 Block Diagram MC68336 Assignments 160-Pin Package MC68376 Assignments 160-Pin Package MC68336/376 Address 3-13 Overall Memory 3-15 Separate Supervisor User Space 3-16 Supervisor Space (Separate Program/Data Space) 3-17 User Space (Separate Program/Data Space) 3-18 CPU32 Block Diagram User Programming Model Supervisor Programming Model Supplement Data Organization Data Registers Address Organization Address Registers Memory Operand Addressing Loop Mode Instruction Sequence 4-15 Common In-Circuit Emulator Diagram 4-19 State Analyzer Configuration 4-19 Debug Serial Block Diagram 4-24 Serial Data Word 4-25 Connector Pinout 4-25 System Integration Module Block Diagram System Clock Block Diagram System Clock Oscillator Circuit System Clock Filter Networks LPSTOP Flowchart 5-13 System Protection Block 5-14 Periodic Interrupt Timer Software Watchdog Timer 5-17 Basic System 5-20 Operand Byte Order 5-25 Word Read Cycle Flowchart 5-28 Write Cycle Flowchart 5-29 Space Address Encoding 5-31 Breakpoint Operation Flowchart 5-33 LPSTOP Interrupt Mask Level 5-34 Arbitration Flowchart Single Request 5-39 Preferred Circuit Data Mode Select Conditioning 5-43 Alternate Circuit Data Mode Select Conditioning 5-44 Power-On Reset 5-49 Basic System 5-55 Chip-Select Circuit Block Diagram 5-56 Space Encoding Interrupt Acknowledge 5-61
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Figure 8-10 8-11 9-10 9-11 10-1 10-2 10-3 10-4 10-5 10-6 11-1 11-2 11-3 13-1 13-2 13-3 13-4 13-5 (Continued) Title Page
QADC Block Diagram QADC Input Output Signals Example External Multiplexing 8-11 QADC Module Block Diagram 8-13 Conversion Timing 8-14 Bypass Mode Conversion Timing 8-15 QADC Queue Operation with Pause 8-18 QADC Clock Subsystem Functions 8-24 QADC Clock Programmability Examples 8-26 QADC Conversion Queue Operation 8-29 QADC Interrupt Vector Format 8-33 Block Diagram QSPI Block Diagram QSPI Flowchart QSPI Initialization Operation 9-10 Flowchart QSPI Master Operation (Part 9-11 Flowchart QSPI Master Operation (Part 9-12 Flowchart QSPI Master Operation (Part 9-13 Flowchart QSPI Slave Operation (Part 9-14 Flowchart QSPI Slave Operation (Part 9-15 Transmitter Block Diagram 9-22 Receiver Block Diagram 9-23 CTM4 Block Diagram 10-1 CPSM Block Diagram 10-4 FCSM Block Diagram 10-5 MCSM Block Diagram 10-8 DASM Block Diagram 10-11 Pulse-Width Modulation Submodule Block Diagram 10-13 Block Diagram 11-1 TCR1 Prescaler Control 11-14 TCR2 Prescaler Control 11-14 TouCAN Block Diagram 13-1 Typical Network 13-2 Extended Message Buffer Structure 13-3 Standard Message Buffer Structure 13-4 TouCAN Interrupt Vector Generation 13-19 CLKOUT Output Timing Diagram A-10 External Clock Input Timing Diagram A-10 ECLK Output Timing Diagram A-10 Read Cycle Timing Diagram A-11 Write Cycle Timing Diagram A-12
MC68336/376 USER'S MANUAL
MOTOROLA
LIST ILLUSTRATIONS
Figure A-10 A-11 A-12 A-13 A-14 A-15 A-16 A-17 A-18 A-19 A-20 (Continued) Title Page
Fast Termination Read Cycle Timing Diagram A-13 Fast Termination Write Cycle Timing Diagram A-14 Arbitration Timing Diagram Active Case A-15 Arbitration Timing Diagram Idle Case A-16 Show Cycle Timing Diagram A-17 Chip-Select Timing Diagram A-18 Reset Mode Select Timing Diagram A-18 Background Debugging Mode Timing Serial Communication A-20 Background Debugging Mode Timing Freeze Assertion A-20 ECLK Timing Diagram A-22 QSPI Timing Master, CPHA A-24 QSPI Timing Master, CPHA A-24 QSPI Timing Slave, CPHA A-25 QSPI Timing Slave, CPHA A-25 Timing Diagram A-26 MC68336 Assignments 160-Pin Package MC68376 Assignments 160-Pin Package 160-Pin Package Dimensions User Programming Model .D-2 Supervisor Programming Model Supplement .D-3 TouCAN Message Buffer Address .D-85
MC68336/376 USER'S MANUAL
MOTOROLA
LIST ILLUSTRATIONS
Figure (Continued) Title Page
MOTOROLA xxii
MC68336/376 USER'S MANUAL
LIST TABLES
Table Title Page
MC68336/376 Characteristics MC68336/376 Output Driver Types MC68336/376 Power Connections MC68336/376 Signal Characteristics MC68336/376 Signal Functions. 3-11 Unimplemented MC68020 Instructions. 4-10 Instruction Summary 4-11 Exception Vector Assignments 4-16 Source Summary 4-20 Polling Entry Source 4-21 Background Mode Command Summary. 4-22 Generated Message Encoding. 4-25 Show Cycle Enable Bits. Clock Control Multipliers System Frequencies from 4.194 Reference. 5-10 Monitor Period 5-15 MODCLK During Reset. 5-16 Software Watchdog Ratio 5-16 MODCLK Reset. 5-17 Periodic Interrupt Priority 5-18 Size Signal Encoding. 5-22 5-10 Address Space Encoding 5-23 5-11 Effect DSACK Signals 5-24 5-12 Operand Alignment. 5-26 5-13 DSACK, BERR, HALT Assertion Results 5-35 5-14 Reset Source Summary. 5-41 5-15 Reset Mode Selection. 5-42 5-16 Module Functions During Reset 5-46 5-17 Reset States. 5-47 5-18 Chip-Select Functions 5-57 5-19 Assignment Field Encoding 5-58 5-20 Block Size Encoding 5-59 5-21 Chip-Select Base Option Register Reset Values. 5-63 5-22 CSBOOT Base Option Register Reset Values 5-63 SRAM Array Address Space Type Array Space Type. Wait States Field. Multiplexed Analog Input Channels Analog Input Channels 8-12 Queue Priority Assertion. 8-17 QADC Clock Programmability 8-27
MC68336/376 USER'S MANUAL MOTOROLA xxiii
LIST TABLES
Table (Continued) Title Page
QADC Status Flags Interrupt Sources. 8-32 Effect DDRQS Function QSPI Pins Bits Transfer. 9-17 Pins. 9-24 Serial Frame Formats 9-25 Effect Parity Checking Data Size. 9-26 10-1 CTM4 Time Base Allocation 10-3 10-2 DASM Modes Operation. 10-10 10-3 Channel Data Register Access 10-11 10-4 PWMSM Divide Options 10-14 10-5 Pulse Frequency Ranges Using Option (20.97 MHz) 10-16 10-6 Pulse Frequency Ranges Using Option (20.97 MHz) 10-16 10-7 CTM4 Interrupt Priority Vector/Pin Allocation 10-18 11-1 TCR1 Prescaler Control. 11-14 11-2 TCR2 Prescaler Control. 11-15 11-3 Function Encodings 11-16 11-4 Channel Priority Encodings 11-17 13-1 Common Extended/Standard Format Frames. 13-4 13-2 Message Buffer Codes Receive Buffers. 13-4 13-3 Message Buffer Codes Transmit Buffers. 13-5 13-4 Extended Format Frames 13-5 13-5 Standard Format Frames. 13-6 13-6 Receive Mask Register Values. 13-7 13-7 Mask Examples Normal/Extended Messages 13-8 13-8 Example System Clock, Rate S-Clock Frequencies 13-9 13-9 Interrupt Sources Vector Addresses. 13-20 Maximum Ratings. Typical Ratings. Thermal Characteristics Clock Control Timing Characteristics Timing. Background Debug Mode Timing. A-19 ECLK Timing A-21 QSPI Timing A-23 A-10 Time Processor Unit Timing A-26 A-11 QADC Maximum Ratings A-27 A-12 QADC Electrical Characteristics (Operating) A-28 A-13 QADC Electrical Characteristics (Operating) A-29 A-14 QADC Conversion Characteristics (Operating). A-30
MOTOROLA xxiv MC68336/376 USER'S MANUAL
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Table (Continued) Title Page
A-15 FCSM Timing Characteristics. A-31 A-16 MCSM Timing Characteristics. A-31 A-17 SASM Timing Characteristics. A-32 A-18 DASM Timing Characteristics A-33 A-19 PWMSM Timing Characteristics. A-34 MC68336 Ordering Information. MC68376 Ordering Information. Module Address .D-1 T[1:0] Encoding .D-3 Address Map.D-5 Show Cycle Enable Bits .D-7 Port Assignments .D-11 Port Assignments.D-12 Software Watchdog Timing Field .D-13 Monitor Time-Out Period.D-13 Assignment Field Encoding .D-15 D-10 CSPAR0 Assignments .D-16 D-11 CSPAR1 Assignments .D-16 D-12 Reset Function CS[10:6].D-17 D-13 Block Size Field Encoding .D-18 D-14 BYTE Field Encoding.D-19 D-15 Read/Write Field Encoding .D-19 D-16 DSACK Field Encoding .D-20 D-17 Address Space Encodings.D-20 D-18 Interrupt Priority Level Field Encoding .D-20 D-19 SRAM Address Map.D-22 D-20 RASP Encoding .D-22 D-21 Address .D-24 D-22 Array Space Field .D-25 D-23 Wait States Field .D-25 D-24 QADC Address Map.D-28 D-25 Queue Operating Modes.D-32 D-26 Queue Operating Modes.D-34 D-27 Queue Status .D-36 D-28 Input Sample Times .D-37 D-29 Non-multiplexed Channel Assignments Designations .D-38 D-30 Multiplexed Channel Assignments Designations .D-38 D-31 Address Map.D-40 D-32 PQSPAR Assignments .D-47 D-33 Effect DDRQS Function.D-48 D-34 Bits Transfer .D-49
MC68336/376 USER'S MANUAL MOTOROLA
LIST TABLES
Table D-35 D-36 D-37 D-38 D-39 D-40 D-41 D-42 D-43 D-44 D-45 D-46 D-47 D-48 D-49 D-50 D-51 D-52 D-53 D-54 D-55 D-56 D-57 D-58 D-59 D-60 D-61 D-62 D-63 (Continued) Title Page
CTM4 Address .D-56 Interrupt Vector Base Number Field .D-57 Time Base Register Select Bits .D-58 Prescaler Division Ratio Select Field .D-59 Drive Time Base Field.D-60 Counter Clock Select Field.D-60 Drive Time Base Field.D-62 Modulus Load Edge Sensitivity Bits .D-62 Counter Clock Select Field.D-62 DASM Mode Flag Status States .D-64 Edge Polarity.D-65 DASM Mode Select Field .D-66 DASMA Operations.D-67 DASMB Operations.D-68 PWMSM Output Polarity Selection .D-70 PWMSM Divide Options .D-71 Register Map.D-73 TCR1 Prescaler Control Bits .D-74 TCR2 Prescaler Control Bits .D-74 FRZ[1:0] Encoding .D-76 Breakpoint Enable Bits.D-76 Channel Priorities.D-80 Parameter Address .D-81 TPURAM Address Map.D-82 TouCAN Address .D-84 MODE[1:0] Configuration .D-89 Transmit Configuration.D-89 Transmit Error Status.D-94 Fault Confinement State Encoding .D-95
MOTOROLA xxvi
MC68336/376 USER'S MANUAL
SECTION INTRODUCTION
MC68336 MC68376 highly-integrated 32-bit microcontrollers, combining high-performance data manipulation capabilities with powerful peripheral subsystems. MC68300 microcontrollers built from standard modules that interface through common intermodule (IMB). Standardization facilitates rapid development devices tailored specific applications. MC68336 incorporates 32-bit (CPU32), system integration module (SIM), time processor unit (TPU), configurable timer module (CTM4), queued serial module (QSM), 10-bit queued analog-to-digital converter module (QADC), 3.5-Kbyte emulation module (TPURAM), 4-Kbyte standby module (SRAM). MC68376 includes aforementioned modules, plus 2.0B protocol controller module (TouCANTM) 8-Kbyte masked (MRM). MC68336/376 either synthesize system clock signal from fast reference external clock input directly. Operation with 4.194 reference frequency standard. maximum system clock speed 20.97 MHz. System hardware software allow changes clock rate during operation. Because operation fully static, register memory contents affected clock rate changes. High-density complementary metal-oxide semiconductor (HCMOS) architecture makes basic power consumption low. Power consumption minimized stopping system clock. CPU32 instruction includes low-power stop (LPSTOP) instruction that efficiently implements this capability. Documentation Modular Microcontroller Family follows modular construction devices product line. Each microcontroller comprehensive user's manual that provides sufficient information normal operation device. user's manual supplemented module reference manuals that provide detailed information about module operation applications. Refer Motorola publication Advanced Microcontroller Unit (AMCU) Literature (BR1116/D) complete listing documentation.
MC68336/376 USER'S MANUAL
INTRODUCTION
MOTOROLA
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INTRODUCTION
MC68336/376 USER'S MANUAL
SECTION NOMENCLATURE
following nomenclature used throughout manual. Nomenclature used only certain sections, such register mnemonics, defined those sections. Symbols Operators Addition Subtraction negation (two's complement) Multiplication Division Greater Less Equal Equal greater Equal less equal Inclusive (OR) Exclusive (EOR) Complementation Concatenation Transferred
Exchanged Sign bit; also used show tolerance Sign extension Binary value Hexadecimal value
MC68336/376 USER'S MANUAL
NOMENCLATURE
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CPU32 Registers A6-A0 Address registers (index registers) (SSP) Supervisor stack pointer (USP) User stack pointer D7-D0 Condition code register (user portion Data registers (index registers) Alternate function code register Program counter Alternate function code register Status register
Vector base register Extend indicator Negative indicator Zero indicator Two's complement overflow indicator Carry/borrow indicator Signal Mnemonics ADDR[23:0] AN[59:48]/[3:0] AN[w, AVEC BERR BGACK BKPT CANRX0 CANTX0 CLKOUT CS[10:0] CSBOOT CPWM[8:5] CTD[10:9]/[4:3] CTM2C DATA[15:0] Address QADC Analog Input QADC Analog Input Address Strobe Autovector Error Grant Grant Acknowledge Breakpoint Request TouCAN Receive Data TouCAN Transmit Data System Clock Chip Selects Boot Chip Select CPulse Width Modulation Channel CDouble Action Channel CModulus Clock Data Data Strobe
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MC68336/376 USER'S MANUAL
DSACK[1:0] DSCLK ECLK ETRIG[2:1] EXTAL FC[2:0] FREEZE HALT IFETCH IPIPE IRQ[7:1] MA[2:0] MISO MODCLK MOSI PCS[3:0] PQA[7:0] PQB[7:0] PC[6:0] PE[7:0] PF[7:0] QUOT RESET SIZ[1:0] T2CLK TPUCH[15:0] TSTME
Data Size Acknowledge Development Serial Clock Development Serial Input Development Serial Output MC6800 Devices Peripherals Clock QADC External Trigger Crystal Oscillator Input Function Codes Freeze Halt Instruction Fetch Instruction Pipeline Interrupt Request QADC Multiplexed Address Master Slave Clock Mode Select Master Slave Peripheral Chip-Selects QADC Port QADC Port Port Port Port Quotient Read/Write Reset Read-Modify-Write Cycle Receive Data QSPI Serial Clock Size Slave Select Clock Channel Signals Three-State Control Test Mode Enable QADC High Reference Voltage
QADC Reference Voltage External Filter Capacitor XTAL Crystal Oscillator Output
MC68336/376 USER'S MANUAL
NOMENCLATURE
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Register Mnemonics BIUMCR CTM4 BIUSM Module Configuration BIUTEST CTM4 BIUSM Test Register BIUTBR CTM4 BIUSM Time Base Register CANCTRL[0:2] CANICR IFLAG IMASK CANMCR CANTCR TouCAN Control Register [0:2] TouCAN Interrupt Configuration Register TouCAN Interrupt Flags Register TouCAN Interrupt Masks Register TouCAN Module Configuration Register TouCAN Test Configuration Register
CCW[0:27] QADC Command Conversion Words [0:27] CFSR[0:3] Channel Function Select Registers [0:3] CIER Channel Interrupt Enable Register CISR Channel Interrupt Status Register CPCR CTM4 CPSM Control Register CPR[0:1] Channel Priority Registers [0:1] CPTR CR[0:F] CREG CSBARBT CSBAR[0:10] CSORBT CSOR[0:10] CSPAR[0:1] DASM[3:4]/[9:10]A DASM[3:4]/[9:10]B DASM[3:4]/[9:10]SIC DCNR DDRE DDRF DDRQA DDRQS DREG DSCR DSSR ESTAT CTM4 CPSM Test Register Command Test Control Register Chip-Select Base Address Register Boot Chip-Select Base Address Registers [0:10] Chip-Select Option Register Boot Chip-Select Option Registers [0:10] Chip-Select Assignment Registers [0:1] CTM4 DASM Registers [3:4]/[9:10] CTM4 DASM Registers [3:4]/[9:10] CTM4 DASM Status/Interrupt/Control Registers [3:4]/[9:10] Decoded Channel Number Register Port Data Direction Register Port Data Direction Register QADC Port Data Direction Register Port Data Direction Register Test Module Distributed Register Development Support Control Register Development Support Status Register TouCAN Error Status Register
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MC68336/376 USER'S MANUAL
FCSM12CNT CTM4 FCSM12 Counter Register FCSM12SIC CTM4 FCSM12 Status/Interrupt/Control Register HSQR[0:1] Host Sequence Registers [0:1] HSRR[0:1] Host Service Request Registers [0:1] LJSRR[0:27] QADC Left-Justified Signed Result Registers [0:27] LJURR[0:27] QADC Left-Justified Unsigned Result Registers [0:27] MCSM[2]/[11]CNT MCSM[2]/[11]ML MCSM[2]/[11]SIC MRMCR PEPAR PFPAR PICR PITR PORTC PORTE PORTF PORTQA PORTQB PORTQS PQSPAR PRESDIV PWM[5:8]C PWM[5:8]A PWM[5:8]B PWM[5:8]SIC QACR[0:1] QADCINT QADCMCR QADCTEST QASR QILR QIVR QSMCR QTEST Link Register CTM4 MCSM Counter Registers [2]/[11] CTM4 MCSM Modulus Latch Registers [2]/[11] CTM4 MCSM Status/Interrupt/Control Registers [2]/[11] Masked Module Configuration Register Port Assignment Register Port Assignment Register Periodic Interrupt Control Register Periodic Interrupt Timer Register Port Data Register Port Data Register Port Data Register QADC Port Data Register QADC Port Data Register Port Data Register Port Assignment Register TouCAN Prescaler Divide Register CTM4 PWMSM Counter Registers [5:8] CTM4 PWMSM Period Registers [5:8] CTM4 PWMSM Pulse Width Registers [5:8] CTM4 PWMSM Status/Interrupt/Control Registers [5:8] QADC Control Registers [0:2] QADC Interrupt Register QADC Module Configuration Register QADC Test Register QADC Status Register Interrupt Level Register Interrupt Vector Register Module Configuration Register Test Register
RAMBAH Base Address High Register
MC68336/376 USER'S MANUAL NOMENCLATURE MOTOROLA
RAMBAL Base Address Register RAMMCR Module Configuration Register RAMTST Test Register ROMBAH Base Address High Register ROMBAL Base Address Register RR[0:F] Receive RSIGHI RSIGLO ROMBS[0:3] RXGMSKHI RXGMSKLO RX[14:15]MSKHI RX[14:15]MSKLO RJURR[0:27] RXECTR SCCR[0:1] SCDR SCSR SGLR SIMCR SIMTR SIMTRE SPCR[0:3] SPSR SWSR SYNCR SYPCR TICR TIMER TPUMCR TR[0:F] TRAMBAR TRAMMCR TRAMTST TSTMSRA Signature High Register Signature Register Bootstrap Words [0:3] TouCAN Receive Global Mask High Register TouCAN Receive Global Mask Register TouCAN Receive Buffer [14:15] Mask High Registers TouCAN Receive Buffer [14:15] Mask Registers QADC Right-Justified Unsigned Result Registers Reset Status Register TouCAN Receive Error Counter Register Control Registers [0:1] Data Register Status Register Service Grant Latch Register Module Configuration Register System Integration Test Register System Integration Test Register (ECLK) QSPI Control Registers [0:3] QSPI Status Register Software Watchdog Service Register Clock Synthesizer Control Register System Protection Control Register Interrupt Configuration Register TouCAN Free Running Timer Register Module Configuration Register Transmit TPURAM Base Address Register TPURAM Module Configuration Register TPURAM Test Register Test Module Master Shift Register
TSTMSRB Test Module Master Shift Register
MOTOROLA NOMENCLATURE MC68336/376 USER'S MANUAL
TSTRC Test Module Repetition Counter Register TSTSC Test Module Shift Count Register TouCAN Test Register TXECTR TouCAN Transmit Error Counter Register
MC68336/376 USER'S MANUAL
NOMENCLATURE
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Conventions Logic level voltage that corresponds Boolean true state. Logic level zero voltage that corresponds Boolean false state. refers specifically establishing logic level bits. Clear refers specifically establishing logic level zero bits. Asserted means that signal active logic state. active signal changes from logic level logic level zero when asserted. active high signal changes from logic level zero logic level one. Negated means that asserted signal changes logic state. active signal changes from logic level zero logic level when negated. active high signal changes from logic level logic level zero. specific mnemonic within range referred mnemonic number. accumulator ADDR7 line address bus; CSOR0 chip-select option register range mnemonics referred mnemonic numbers that define range. VBR[4:0] bits four zero vector base register; CSOR[0:5] first option registers. Parentheses used indicate content register memory location rather than register memory location itself. content accumulator content word address means least significant bit. means most significant bit. References high bytes spelled out. means least significant word. means most significant word. ADDR address bus. ADDR[7:0] eight LSBs address bus. DATA data bus. DATA[15:8] eight MSBs data bus.
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MC68336/376 USER'S MANUAL
SECTION OVERVIEW
This section contains information about entire MC68336/376 modular microcontroller. lists features each module, shows device functional divisions assignments, summarizes signal functions, discusses intermodule bus, provides system memory maps. Timing electrical specifications entire microcontroller individual modules provided APPENDIX ELECTRICAL CHARACTERISTICS. Comprehensive module register descriptions memory maps provided APPENDIX REGISTER SUMMARY. Features following paragraphs highlight capabilities each microcontroller modules. Each module discussed separately subsequent section this user's manual. 3.1.1 Central Processing Unit (CPU32) 32-bit architecture Virtual memory implementation Table look-up interpolate instruction Improved exception handling controller applications High level language support Background debug mode Fully static operation 3.1.2 System Integration Module (SIM) External support Programmable chip select outputs System protection logic Watchdog timer, clock monitor monitor 8-bit dual function input/output ports 7-bit dual function output port Phase-locked loop (PLL) clock system 3.1.3 Standby Module (SRAM) 4-Kbytes static standby supply 3.1.4 Masked Module (MRM) 8-Kbyte array, accessible bytes words User selectable default base address User selectable bootstrap function User selectable verification code
MC68336/376 USER'S MANUAL OVERVIEW MOTOROLA
3.1.5 10-Bit Queued Analog-to-Digital Converter (QADC) channels internally; directly accessible channels with external multiplexing automatic channel selection conversion modes channel scan queues variable length, each with variable number subqueues result registers three result alignment formats Programmable input sample time Direct control external multiplexers 3.1.6 Queued Serial Module (QSM) Enhanced serial communications interface (SCI) Modulus baud rate generator Parity detection Queued serial peripheral interface (QSPI) 80-byte static perform queued operations automatic transfers Continuous cycling, bits transfer, first Dual function pins 3.1.7 Configurable Timer Module Version (CTM4) 16-bit modulus counter submodules (MCSMs) 16-bit free-running counter submodule (FCSM) Four double-action submodules (DASMs) Four pulse-width submodules (PWMSMs) 3.1.8 Time Processor Unit (TPU) Dedicated micro-engine operating independently CPU32 independent programmable channels pins Each channel event register consisting 16-bit capture register, 16bit compare register 16-bit comparator channel perform time function Each channel eight 16-bit parameter registers Each timer function assigned more than channel timer counter registers with programmable prescalers Each channel synchronized both counters Selectable channel priority levels 3.1.9 Static Module with Emulation Capability (TPURAM) Kbytes static External VSTBY separate standby supply used normal microcode emulation
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MC68336/376 USER'S MANUAL
3.1.10 2.0B Controller Module (TouCAN) Full implementation protocol specification, version receive/transmit message buffers bytes data length Global mask register message buffers Independent mask registers message buffers Programmable transmit-first scheme: lowest lowest buffer number 16-bit free-running timer message time-stamping power sleep mode with programmable wake-up activity Intermodule intermodule (IMB) standardized developed facilitate both design operation modular microcontrollers. contains circuitry support exception processing, address space partitioning, multiple interrupt levels, vectored interrupts. standardized modules communicate with another through IMB. uses address data lines. System Block Diagram Assignment Diagrams Figure functional diagram MCU. There one-to-one correspondence between location size blocks diagram location size integrated-circuit modules. Figure shows MC68336 assignment package; Figure shows MC68376 assignment package. Note that MC68376 pin-compatible upgrade MC68336 that provides protocol controller 8-Kbyte masked module. Both devices 160-pin plastic surfacemount package. Refer Obtaining Updated MC68336/376 Mechanical Information package dimensions. Refer subsequent paragraphs this section signal descriptions.
MC68336/376 USER'S MANUAL
OVERVIEW
MOTOROLA
TPUCH[15:0]
T2CLK
CSBOOT BR/CS0 BG/CS1 BGACK /CS2 CS[10:0] CHIP SELECTS BGACK ADDR [23:19] DSACK0 CONTROL ADDR23/CS10 /ECLK ADDR22/CS9 /PC6 PORT ADDR21/CS8 /PC5 ADDR20/CS7 /PC4 ADDR19/CS6 /PC3 FC2/CS5 /PC2 FC1/CS4 /PC1 FC0/CS3 /PC0 ADDR[18:0] SIZ1/PE7 SIZ0/PE6 AS/PE5 CONTROL PORT DS/PE4 /PE3 AVEC /PE2 DSACK1 /PE1 DSACK0 /PE0 DATA[15:0] RESET HALT BERR MODCLK/PF0 IRQ[7:1] PORT MODCLK CONTROL IRQ7/PF7 IRQ6/PF6 IRQ5/PF5 IRQ4/PF4 IRQ3/PF3 IRQ2/PF2 IRQ1/PF1 CLKOUT XTAL EXTAL
VSTBY CTM2C CTD[10:9]/CTD[4:3] CPWM[8:5] CANTX0 CANRX0
TouCAN MC68376 ONLY
MC68376 ONLY
CTM4
KBYTE TPURAM
FCSM MCSMs DASMs PWMSMs
DSACK1 AVEC SIZ0 SIZ1
TXD/PQS7 PCS3/PQS6 PCS2/PQS5 PCS1/PQS4 PCS0/SS /PQS3 SCK/PQS2 MOSI/PQS1 MISO/PQS0 PORT
QADC
SRAM
CPU32
CLOCK
PORT
PORT
VDDSYN TEST TSTME QUOT FREEZE BKPT CONTROL TSTME/TSC FREEZE/QUOT
PQA[7:0]
PQB[7:0]
IFETCH CONTROL IPIPE DSCLK BKPT/ DSCLK IFETCH/ IPIPE/DSO
VDDA
VSSA
PORT PINS INCORPORATE OPEN DRAIN PULL DOWN DRIVERS
336/376 BLOCK
Figure MC68336/376 Block Diagram
MOTOROLA
OVERVIEW
MC68336/376 USER'S MANUAL
TXD/PQS7 PCS3/PQS6 PCS2/PQS5 PCS1/PQS4 PCS0/SS /PQS3 SCK/PQS2 MOSI/PQS1 MISO/PQS0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 AN48/PQB4 AN49/PQB5 AN50/PQB6
CTM2C CTD3 CTD4 CPWM5 CPWM6 CPWM7 CPWM8 CTD9 CTD10 TPUCH0 TPUCH1 TPUCH2 TPUCH3 TPUCH4 TPUCH5 TPUCH6 TPUCH7 TPUCH8 TPUCH9 TPUCH10 VSTBY TPUCH11 TPUCH12 TPUCH13 TPUCH14 TPUCH15 T2CLK ADDR23/ CS10 /ECLK PC6/ADDR22/ PC5/ADDR21/ PC4/ADDR20/ PC3/ADDR19/
MC68336
PC2/FC2/CS5 PC1/FC1/CS4 FC0/CS3 CK/CS2 BG/CS1 BR/CS0 CSBOO DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 ADDR0 PE0/DSA PE1/DSA PE2/AVEC PE3/RMC PE4/DS PE5/AS PE6/SIZ0 PE7/SIZ1
*NOTE: MC68336 REVISION LATER (F60K LATER MASK SETS) HAVE ASSIGNED PINS CONNECT", ALLOW COMPATIBILITY WITH MC68376. REVISION (D65J MASK SET) DEVICES,
AN51/PQB7 VSSA VDDA AN52/MA0/PQA0 AN53/MA1/PQA1 AN54/MA2/PQA2 AN55/ETRIG1/PQA3 AN56/ETRIG2/PQA4 AN57/PQA5 AN57/PQA6 AN59/PQA7 XTAL VDDSYN EXTAL CLKOUT IPIPE/DSO IFETCH /DSI FREEZE/Q BKPT /DSCLK TSTME /TSC RESET HALT BERR PF7/IRQ7 PF6/IRQ6 PF5/IRQ5 PF4/IRQ4 PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 PF0/MODCLK
160-PIN
Figure MC68336 Assignments 160-Pin Package
MC68336/376 USER'S MANUAL
OVERVIEW
MOTOROLA
CANTX0 TXD/PQS7 PCS3/PQS6 PCS2/PQS5 PCS1/PQS4 PCS0/SS /PQS3 SCK/PQS2 MOSI/PQS1 MISO/PQS0 ADDR1 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 AN0/ANW/PQB0 AN1/ANX/PQB1 AN2/ANY/PQB2 AN3/ANZ/PQB3 AN48/PQB4 AN49/PQB5 AN50/PQB6
CANRX0 CTM2C CTD3 CTD4 CPWM5 CPWM6 CPWM7 CPWM8 CTD9 CTD10 TPUCH0 TPUCH1 TPUCH2 TPUCH3 TPUCH4 TPUCH5 TPUCH6 TPUCH7 TPUCH8 TPUCH9 TPUCH10 VSTBY TPUCH11 TPUCH12 TPUCH13 TPUCH14 TPUCH15 T2CLK ADDR23/ CS10 /ECLK PC6/ADDR22/ PC5/ADDR21/ PC4/ADDR20/ PC3/ADDR19/
MC68376
PC2/FC2/CS5 PC1/FC1/CS4 FC0/CS3 CK/CS2 BG/CS1 BR/CS0 CSBOO DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 ADDR0 PE0/DSA PE1/DSA PE2/AVEC PE3/RMC PE4/DS PE5/AS PE6/SIZ0 PE7/SIZ1
AN51/PQB7 VSSA VDDA AN52/MA0/PQA0 AN53/MA1/PQA1 AN54/MA2/PQA2 AN55/ETRIG1/PQA3 AN56/ETRIG2/PQA4 AN57/PQA5 AN57/PQA6 AN59/PQA7 XTAL VDDSYN EXTAL CLKOUT IPIPE/DSO IFETCH /DSI FREEZE/Q BKPT /DSCLK TSTME /TSC RESET HALT BERR PF7/IRQ7 PF6/IRQ6 PF5/IRQ5 PF4/IRQ4 PF3/IRQ3 PF2/IRQ2 PF1/IRQ1 PF0/MODCLK
160-PIN
Figure MC68376 Assignments 160-Pin Package Descriptions following tables summarize functional characteristics MC68336/376 pins. Table shows inputs outputs. Digital inputs outputs CMOS logic levels. entry "Discrete I/O" column indicates that also used general-purpose input, output, both. port designation given when applies. Refer Figure port organization. Table shows types output drivers. Table shows characteristics power pins.
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MC68336/376 USER'S MANUAL
Table MC68336/376 Characteristics
Mnemonic ADDR23/CS10/ECLK ADDR[22:19]/CS[9:6] ADDR[18:0] AN[51:48] AN[3:0]/AN[w, AN[59:57] AN[56:55]/ETRIG[2:1] AN[54:52]/MA[2:0] AVEC BERR BG/CS1 BGACK/CS2 BKPT/DSCLK BR/CS0 CLKOUT CANRX0 (MC68376 Only) CANTX0 (MC68376 Only) CSBOOT CTD[10:9]/[4:3] CPWM[8:5] CTM2C DATA[15:0] DSACK[1:0] EXTAL2 FC[2:0]/CS[5:3] FREEZE/QUOT IPIPE/DSO IFETCH/DSI HALT IRQ[7:1] MISO MODCLK MOSI PCS0/SS PCS[3:1] RESET Output Driver Input Synchronized Yes1 Yes1 Yes1 Yes1 Yes1 Yes1 Yes1 Yes1 Yes1 Input Hysteresis Special Discrete Port Designation PC[6:3] PQB[7:4] PQB[3:0] PQA[7:5] PQA[4:3] PQA[2:0] PE[1:0] PC[2:0] PF[7:1] PQS0 PQS1 PQS3 PQS[6:4] PQS2
MC68336/376 USER'S MANUAL
OVERVIEW
MOTOROLA
Table MC68336/376 Characteristics (Continued)
Mnemonic SIZ[1:0] T2CLK TPUCH[15:0] TSTME/TSC XFC2 XTAL
Output Driver
Input Synchronized Yes1
Input Hysteresis
Discrete Special Special
Port Designation PE[7:6] PQS7
NOTES: DATA[15:0] synchronized during reset only. MODCLK, QADC pins synchronized only when used input port pins. EXTAL, XTAL clock reference connections.
Table MC68336/376 Output Driver Types
Type Description Output only signals that always driven. external pull-up required. Type output that operated open-drain mode. Type output with p-channel precharge when reset. Three-state output that includes circuitry assert output before high impedance established, ensure rapid rise time. external holding resistor required maintain logic level while high-impedance state. Type output that operated open-drain mode. Three-state output that operated open-drain mode only.
Table MC68336/376 Power Connections
VSTBY VDDSYN VDDA, VSSA VRH, VSS, Description Standby power Clock synthesizer power QADC converter power QADC reference voltage Microcontroller power
MOTOROLA
OVERVIEW
MC68336/376 USER'S MANUAL
Signal Descriptions following tables define MC68336/376 signals. Table shows signal origin, type, active state. Table describes signal functions. Both tables sorted alphabetically mnemonic. pins often have multiple functions. More than description apply pin. Table MC68336/376 Signal Characteristics
Signal Name ADDR[23:0] AN[59:48]/[3:0] AN[w, AVEC BERR BGACK BKPT CLKOUT CANRX0 (MC68376 Only) CANTX0 (MC68376 Only) CS[10:0] CSBOOT CPWM[8:5] CTD[10:9]/[4:3] CTM2C DATA[15:0] DSACK[1:0] DSCLK ECLK ETRIG[2:1] EXTAL FC[2:0] FREEZE HALT IFETCH IPIPE IRQ[7:1] MA[2:0] MISO MODCLK MOSI PC[6:0] PCS[3:0] PE[7:0] PF[7:0] Module QADC QADC CPU32 TouCAN TouCAN CTM4 CTM4 CTM4 CPU32 CPU32 CPU32 QADC CPU32 CPU32 QADC Signal Type Input Input Output Input Input Output Input Input Input Output Input Output Output Output Output Input/Output Input Output Input Input Input Output Output Input Input Output Output Input/Output Output Output Input Output Input/Output Input Input/Output Output Input/Output Input/Output Input/Output Active State Serial Clock Serial Data Serial Data
MC68336/376 USER'S MANUAL
OVERVIEW
MOTOROLA
Table MC68336/376 Signal Characteristics (Continued)
Signal Name PQA[7:0] PQB[7:0] PQS[7:0] QUOT RESET SIZ[1:0] T2CLK TPUCH[15:0] TSTME/TSC XTAL Module QADC QADC Signal Type Input/Output Input Input/Output Output Output Input/Output Output Input Input/Output Output Input Input Input/Output Input Output Input Output Active State
MOTOROLA 3-10
OVERVIEW
MC68336/376 USER'S MANUAL
Table MC68336/376 Signal Functions
Mnemonic ADDR[23:0] AN[59:48]/[3:0] AN[w, AVEC BERR BGACK BKPT CLKOUT CANRX0 CANTX0 CS[10:0] CSBOOT CPWM[8:5] CTD[10:9]/[4:3] CTM2C DATA[15:0] DSACK[1:0] DSI, DSO, DSCLK ECLK ETRIG[2:1] EXTAL, XTAL FC[2:0] FREEZE HALT IFETCH IPIPE IRQ[7:1] MA[2:0] MISO MODCLK MOSI PC[6:0] PCS[3:0] PE[7:0] PF[7:0] Signal Name Address QADC Analog Input QADC Analog Input Address Strobe Autovector Error Grant Grant Acknowledge Breakpoint Request System Clock TouCAN Receive Data TouCAN Transmit Data Chip-Selects Boot Chip-Select CTM4 PWMs CTM4 Double Action Channels CTM4 Modulus Clock Data Data Strobe Data Size Acknowledge Developmental Serial Out, Clock E-Clock QADC External Trigger Crystal Oscillator Function Codes Freeze Halt Instruction Pipeline Instruction Pipeline Interrupt Request QADC Multiplexed Address Master Slave Clock Mode Select Master Out, Slave Port Peripheral Chip-Selects Port Port Function 24-bit address used CPU32 channel converter analog input pins Four input channels utilized when operating multiplexed mode Indicates that valid address address Requests automatic vector during interrupt acknowledge Indicates that error occurred Indicates that relinquished Indicates that external device assumed mastership Signals hardware breakpoint Indicates that external device requires mastership System clock output serial data input serial data output Select external devices programmed addresses Chip-select external bootstrap memory Four pulse-width modulation channels Bidirectional double action timer channels Modulus counter clock input 16-bit data used CPU32 Indicates that external device should place valid data data during read cycle that valid data been placed data during write cycle. Provides asynchronous data transfers dynamic sizing Serial clock background debug mode M6800 clock output External trigger pins used when QADC scan queue external trigger mode Connections clock synthesizer circuit reference; crystal external oscillator used Identify processor state current address space Indicates that acknowledged breakpoint Suspend external activity Indicates instruction pipeline activity Indicates instruction pipeline activity Requests interrupt specified priority level from When external multiplexing used, these pins provide addresses external multiplexer Serial input QSPI master mode; serial output from QSPI slave mode Selects source system clock Serial output from QSPI master mode; serial input QSPI slave mode digital output port signals QSPI peripheral chip-select digital input/output port signals digital input/output port signals
MC68336/376 USER'S MANUAL
OVERVIEW
MOTOROLA 3-11
Table MC68336/376 Signal Functions (Continued)
Mnemonic PQA[7:0] PQB[7:0] PQS[7:0] QUOT RESET SIZ[1:0] T2CLK TPUCH[15:0] TSTME Signal Name QADC Port QADC Port Port Quotient Read/Write Reset Read-Modify-Write Cycle Receive Data QSPI Serial Clock Size Slave Select Clock Channels Three-State Control Test Mode Enable Transmit Data External Filter Capacitor Function QADC port digital input/output port signals QADC port digital input port signals digital input/output port signals Provides quotient polynomial divider (test mode only) Indicates direction data transfer System reset Indicates indivisible read-modify-write instruction Serial input Clock output from QSPI master mode; clock input QSPI slave mode Indicates number bytes remaining transferred during cycle Starts serial transmission when QSPI slave mode; chip-select master mode clock input Bidirectional channels Places output drivers high impedance state Hardware enable test mode Serial output from Connection external phase-locked loop filter capacitor
MOTOROLA 3-12
OVERVIEW
MC68336/376 USER'S MANUAL
Internal Register Figure 3-4, ADDR[23:20] represented letter value represented determines base address module control registers. MC68336/376, equal M111, where logic state module mapping (MM) system integration module configuration register (SIMCR).
$YFF000 UNUSED $YFF080 $YFF200 $YFF400 $YFF500 UNUSED $YFF820 $YFF83F UNUSED $YFFA00 BYTES $YFFA80 UNUSED $YFFB00 $YFFB40 $YFFB48 $YFFC00 $YFFE00 $YFFFFF BYTES BYTES TPURAM CONTROL BYTES SRAM CONTROL BYTES UNUSED TPURAM ARRAY KBYTES SRAM ARRAY KBYTES CONTROL BYTES (MC68376) ARRAY KBYTES (MC68376) QADC BYTES TouCAN BYTES (MC68376) CTM4 BYTES
NOTES: Y=M111, WHERE MODMAP SIGNAL STATE IMB, WHICH REFLECTS STATE MODMAP MODULE CONFIGURATION REGISTER SYSTEM INTEGRATION MODULE. (Y=$7 ATTEMPTED ACCESSES UNUSED LOCATIONS UNUSED BITS WITHIN VALID LOCATIONS RETURN ZEROS.
336/376 ADDRESS
Figure MC68336/376 Address
MC68336/376 USER'S MANUAL
OVERVIEW
MOTOROLA 3-13
Address Space Maps Figure shows single memory space. Function codes FC[2:0] decoded externally that separate user/supervisor program/data spaces provided. Figure 3-6, decoded, resulting separate supervisor user spaces. FC[1:0] decoded, that separate program data spaces provided. Figures 3-8, FC[2:0] decoded, resulting four separate memory spaces: supervisor/program, supervisor/data, user/program user/data. exception vectors located supervisor data space, except reset vector, which located supervisor program space. Only initial reset vector fixed processor's memory map. Once initialization complete, there fixed assignments. Since vector base register (VBR) provides base address vector table, vector table located anywhere memory. Refer SECTION CENTRAL PROCESSOR UNIT more information concerning memory management, extended addressing, exception processing. Refer 5.5.1.7 Function Codes more information concerning function codes address space types.
MOTOROLA 3-14
OVERVIEW
MC68336/376 USER'S MANUAL
$000000
COMBINED SUPERVISOR USER SPACE
TYPE VECTOR VECTOR EXCEPTION OFFSET NUMBER RESET INITIAL STACK POINTER $XX0000 0000 RESET INITIAL 0004 ERROR 0008 ADDRESS ERROR 000C ILLEGAL INSTRUCTION 0010 ZERO DIVISION 0014 CHK, CHK2 INSTRUCTIONS 0018 TRAPcc, TRAPV INSTRUCTIONS 001C PRIVILEGE VIOLATION 0020 TRACE 0024 LINE 1010 EMULATOR 0028 LINE 1111 EMULATOR 002C HARDWARE BREAKPOINT 0030 (RESERVED COPROCESSOR PROTOCOL VIOLATION) 0034 FORMAT ERROR UNINITIALIZED INTERRUPT 0038 FORMAT ERROR UNINITIALIZED INTERRUPT 003C (UNASSIGNED, RESERVED) 0040-005C 16-23 SPURIOUS INTERRUPT 006C LEVEL INTERRUPT AUTOVECTOR 0064 LEVEL INTERRUPT AUTOVECTOR 0068 LEVEL INTERRUPT AUTOVECTOR 006C LEVEL INTERRUPT AUTOVECTOR 0070 LEVEL INTERRUPT AUTOVECTOR 0074 LEVEL INTERRUPT AUTOVECTOR 0078 LEVEL INTERRUPT AUTOVECTOR 007C INSTRUCTION VECTORS (0-15) 0080-00BC 32-47 (RESERVED, COPROCESSOR) 00C0-00EB 48-58 (UNASSIGNED, RESERVED) 00EC-00FC 59-63 USER-DEFINED VECTORS 0100-03FC 64-255 $XX03FC
TouCAN (MC68376) QADC $7FF000 CTM4
INTERNAL REGISTERS
$YFF000 $YFF080 $YFF200 $YFF400 $YFF500 $YFF820 $YFF83F $YFFA00 $YFFA80 $YFFB00 $YFFB40 $YFFB48 $YFFC00 $YFFE00 $YFFFFF
CONTROL (MC68376) TPURAM SRAM $FFF000 $FFFFFF
INTERNAL REGISTERS
NOTES: LOCATION EXCEPTION VECTOR TABLE DETERMINED VECTOR BASE REGISTER. VECTOR ADDRESS CONCATENATION UPPER BITS WITH 8-BIT VECTOR NUMBER INTERRUPTING MODULE. RESULT LEFT JUSTIFIED FORCE LONG WORD ALIGNMENT. LOCATION MODULE CONTROL REGISTERS DETERMINED STATE MODULE MAPPING (MM) CONFIGURATION REGISTER. M111 WHERE STATE BIT. SOME UNUSED ADDRESSES WITHIN INTERNAL REGISTER BLOCK MAPPED EXTERNALLY. REFER APPROPRIATE MODULE REFERENCE MANUAL INFORMATION MAPPING UNUSED ADDRESSES WITHIN INTERNAL REGISTER BLOCKS.
336//376 COMB
Figure Overall Memory
MC68336/376 USER'S MANUAL
OVERVIEW
MOTOROLA 3-15
$000000
VECTOR OFFSET 0000 0004 0008 000C 0010 0014 0018 001C 0020 0024 0028 002C 0030 0034 0038 003C 0040-005C 006C 0064 0068 006C 0070 0074 0078 007C 0080-00BC 00C0-00EB 00EC-00FC 0100-03FC VECTOR TYPE NUMBER EXCEPTION RESET INITIAL STACK POINTER RESET INITIAL ERROR ADDRESS ERROR ILLEGAL INSTRUCTION ZERO DIVISION CHK, CHK2 INSTRUCTIONS TRAPcc, TRAPV INSTRUCTIONS PRIVILEGE VIOLATION TRACE LINE 1010 EMULATOR LINE 1111 EMULATOR HARDWARE BREAKPOINT (RESERVED COPROCESSOR PROTOCOL VIOLATION) FORMAT ERROR UNINITIALIZED INTERRUPT FORMAT ERROR UNINITIALIZED INTERRUPT 16-23 (UNASSIGNED, RESERVED) SPURIOUS INTERRUPT LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR 32-47 INSTRUCTION VECTORS (0-15) 48-58 (RESERVED, COPROCESSOR) 59-63 (UNASSIGNED, RESERVED) 64-255 USER-DEFINED VECTORS $XX0000
$000000
SUPERVISOR SPACE
USER SPACE
$XX03FC
TouCAN (MC68376) QADC CTM4 $7FF000
INTERNAL REGISTERS
$YFF000 $YFF080 $YFF200 $YFF400 $YFF500 $YFF820 $YFF83F $YFFA00 $YFFA80 $YFFB00 $YFFB40 $YFFB48 $YFFC00 $YFFE00 $YFFFFF
INTERNAL REGISTERS
$7FF000
INTERNAL REGISTERS
CONTROL (MC68376) TPURAM SRAM $FFF000 $FFFFFF
INTERNAL REGISTERS
$FFF000 $FFFFFF
NOTES: LOCATION EXCEPTION VECTOR TABLE DETERMINED VECTOR BASE REGISTER. VECTOR ADDRESS CONCATENATION UPPER BITS WITH 8-BIT VECTOR NUMBER INTERRUPTING MODULE. RESULT LEFT JUSTIFIED FORCE LONG WORD ALIGNMENT. LOCATION MODULE CONTROL REGISTERS DETERMINED STATE MODULE MAPPING (MM) CONFIGURATION REGISTER. M111 WHERE STATE BIT. SOME UNUSED ADDRESSES WITHIN INTERNAL REGISTER BLOCK MAPPED EXTERNALLY. REFER APPROPRIATE MODULE REFERENCE MANUAL INFORMATION MAPPING UNUSED ADDRESSES WITHIN INTERNAL REGISTER BLOCKS. SOME INTERNAL REGISTERS AVAILABLE USER SPACE.
336/376
Figure Separate Supervisor User Space
MOTOROLA 3-16
OVERVIEW
MC68336/376 USER'S MANUAL
$000000
VECTOR OFFSET 0000 0004 VECTOR NUMBER EXCEPTION VECTORS LOCATED SUPERVISOR PROGRAM SPACE RESET INITIAL STACK POINTER RESET INITIAL $XX0000 $XX0004
$000000
SUPERVISOR DATA SPACE
VECTOR OFFSET 0008 000C 0010 0014 0018 001C 0020 0024 0028 002C 0030 0034 0038 003C 0040-005C 006C 0064 0068 006C 0070 0074 0078 007C 0080-00BC 00C0-00EB 00EC-00FC 0100-03FC
VECTOR EXCEPTION VECTORS LOCATED NUMBER SUPERVISOR DATA SPACE ERROR ADDRESS ERROR ILLEGAL INSTRUCTION ZERO DIVISION CHK, CHK2 INSTRUCTIONS TRAPcc, TRAPV INSTRUCTIONS PRIVILEGE VIOLATION TRACE LINE 1010 EMULATOR LINE 1111 EMULATOR HARDWARE BREAKPOINT (RESERVED COPROCESSOR PROTOCOL VIOLATION) FORMAT ERROR UNINITIALIZED INTERRUPT FORMAT ERROR UNINITIALIZED INTERRUPT 16-23 (UNASSIGNED, RESERVED) SPURIOUS INTERRUPT LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR LEVEL INTERRUPT AUTOVECTOR 32-47 INSTRUCTION VECTORS (0-15) 48-58 (RESERVED, COPROCESSOR) 59-63 (UNASSIGNED, RESERVED) 64-255 USER-DEFINED VECTORS
$XX0008
SUPERVISOR PROGRAM SPACE
$XX03FC
TouCAN (MC68376) QADC CTM4 $7FF000
INTERNAL REGISTERS
$YFF000 $YFF080 $YFF200 $YFF400 $YFF500 $YFF820 $YFF83F $YFFA00 $YFFA80 $YFFB00 $YFFB40 $YFFB48 $YFFC00 $YFFE00 $YFFFFF $FFFFFF
CONTROL (MC68376) TPURAM SRAM $FFF000 $FFFFFF
INTERNAL REGISTERS
NOTES: LOCATION EXCEPTION VECTOR TABLE DETERMINED VECTOR BASE REGISTER. VECTOR ADDRESS CONCATENATION UPPER BITS WITH 8-BIT VECTOR NUMBER INTERRUPTING MODULE. RESULT LEFT JUSTIFIED FORCE LONG WORD ALIGNMENT. LOCATION MODULE CONTROL REGISTERS DETERMINED STATE MODULE MAPPING (MM) CONFIGURATION REGISTER. M111 WHERE STATE BIT. SOME UNUSED ADDRESSES WITHIN INTERNAL REGISTER BLOCK MAPPED EXTERNALLY. REFER APPROPRIATE MODULE REFERENCE MANUAL INFORMATION MAPPING UNUSED ADDRESSES WITHIN INTERNAL REGISTER BLOCKS. SOME INTERNAL REGISTERS AVAILABLE USER SPACE.
336/376 SUPER
Figure Supervisor Space (Separate Program/Data Space)
MC68336/376 USER'S MANUAL
OVERVIEW
MOTOROLA 3-17
$000000
$000000
USER PROGRAM SPACE
USER DATA SPACE
TouCAN (MC68376) QADC CTM4 $7FF000
INTERNAL REGISTERS
$YFF000 $YFF080 $YFF200 $YFF400 $YFF500 $YFF820 $YFF83F $YFFA00 $YFFA80 $YFFB00 $YFFB40 $YFFB48 $YFFC00 $YFFE00 $YFFFFF
CONTROL (MC68376) TPURAM SRAM $FFF000
INTERNAL REGISTERS
$FFFFFF
$FFFFFF
NOTES: LOCATION MODULE CONTROL REGISTERS DETERMINED STATE MODULE MAPPING (MM) CONFIGURATION REGISTER. M111, WHERE STATE BIT. UNUSED ADDRESSES WITHIN INTERNAL REGISTER BLOCK MAPPED EXTERNALLY. "RESERVED" BLOCKS MAPPED EXTERNALLY. SOME INTERNAL REGISTERS AVAILABLE USER SPACE.
336/376 USER
Figure User Space (Separate Program/Data Space)
MOTOROLA 3-18
OVERVIEW
MC68336/376 USER'S MANUAL
SECTION CENTRAL PROCESSOR UNIT
CPU32, instruction processing module M68300 family, based industry-standard MC68000 processor. many features MC68010 MC68020, well unique features suited high-performance controller applications. This section overview CPU32. detailed information concerning operation, refer CPU32 Reference Manual (CPU32RM/AD). General Ease programming important consideration using microcontroller. CPU32 instruction format reflects philosophy emphasizing register-memory interaction. There eight multifunction data registers seven general-purpose addressing registers. data resources available operations requiring those resources. data registers readily support 8-bit (byte), 16-bit (word), 32-bit (long-word) operand lengths operations. Word long-word operations support address manipulation. Although program counter (PC) stack pointers (SP) special-purpose registers, they also available most data addressing activities. Ease program checking diagnosis further enhanced trace trap capabilities instruction level. block diagram CPU32 shown Figure 4-1. major blocks operate highly independent fashion that maximizes concurrency operation while managing essential synchronization instruction execution operation. controller loads instructions from data into decode unit. sequencer control unit provide overall chip control, managing internal buses, registers, functions execution unit.
MC68336/376 USER'S MANUAL
CENTRAL PROCESSOR UNIT
MOTOROLA
DECODE BUFFER STAGE STAGE INSTRUCTION PIPELINE STAGE
CONTROL STORE
PROGRAM COUNTER SECTION
DATA SECTION
CONTROL LOGIC EXECUTION UNIT MICROSEQUENCER CONTROL
WRITE PENDING BUFFER
PREFETCH CONTROLLER
MICROBUS CONTROLLER
ADDRESS
CONTROL SIGNALS
DATA
1127A
Figure CPU32 Block Diagram CPU32 Registers CPU32 programming model consists groups registers that correspond user supervisor privilege levels. User programs only registers user model. supervisor programming model, which supplements user programming model, used CPU32 system programmers wish protect sensitive operating system functions. supervisor model identical that MC68010 later processors. CPU32 eight 32-bit data registers, seven 32-bit address registers, 32-bit program counter, separate 32-bit supervisor user stack pointers, 16-bit status register, alternate function code registers, 32-bit vector base register. Refer Figures 4-3.
MOTOROLA
CENTRAL PROCESSOR UNIT
MC68336/376 USER'S MANUAL
DATA REGISTERS
ADDRESS REGISTERS
(SSP) USER STACK POINTER
CONDITION CODE REGISTER
CPU32 USER PROG MODEL
PROGRAM COUNTER
Figure User Programming Model
MC68336/376 USER'S MANUAL
CENTRAL PROCESSOR UNIT
MOTOROLA
(SSP) SUPERVISOR STACK POINTER
(CCR)
ALTERNATE FUNCTION CODE REGISTERS
CPU32 SUPV PROG MODEL
STATUS REGISTER
VECTOR BASE REGISTER
Figure Supervisor Programming Model Supplement 4.2.1 Data Registers eight data registers store data operands bits addresses bits. following data types supported: Bits Packed Binary-Coded Decimal Digits Byte Integers bits) Word Integers bits) Long-Word Integers bits) Quad-Word Integers bits) Each data registers D7-D0 bits wide. Byte operands occupy low-order bits; word operands, low-order bits; long-word operands, entire bits. When data register used either source destination operand, only appropriate low-order byte word byte word operations, respectively) used changed; remaining high-order portion unaffected. least significant (LSB) long-word integer addressed zero, most significant (MSB) addressed Figure shows organization various types data data registers. Quad-word data consists long words represents product 32-bit multiply dividend 32-bit divide operations (signed unsigned). Quad-words organized data registers without restrictions order pairing. There explicit instructions management this data type, although MOVEM instruction used move quad-word into registers. Binary-coded decimal (BCD) data represents decimal numbers binary form. CPU32 instructions format which byte contains digits. four contain least significant digit, four contain most significant digit. ABCD, SBCD, NBCD instructions operate digits packed into single byte.
MOTOROLA CENTRAL PROCESSOR UNIT MC68336/376 USER'S MANUAL
BYTE HIGH-ORDER BYTE MIDDLE HIGH BYTE MIDDLE BYTE LOW-ORDER BYTE
WORD HIGH-ORDER WORD LOW-ORDER WORD
LONG WORD LONG WORD
QUAD-WORD HIGH-ORDER LONG WORD
LOW-ORDER LONG WORD
CPU32 DATA
Figure Data Organization Data Registers 4.2.2 Address Registers Each address register stack pointer bits wide holds 32-bit address. Address registers cannot used byte-sized operands. Therefore, when address register used source operand, either low-order word entire long-word operand used, depending upon operation size. When address register used destination operand, entire register affected, regardless operation size. source operand word size, sign-extended bits. Address registers used primarily addresses support address computation. instruction includes instructions that subtract from, compare, move contents address registers. Figure shows organization addresses address registers.
MC68336/376 USER'S MANUAL
CENTRAL PROCESSOR UNIT
MOTOROLA
SIGN EXTENDED
16-BIT ADDRESS OPERAND
FULL 32-BIT ADDRESS OPERAND
CPU32 ADDR
Figure Address Organization Address Registers 4.2.3 Program Counter contains address next instruction executed CPU32. During instruction execution exception processing, processor automatically increments contents places value appropriate. 4.2.4 Control Registers control registers described this section contain control information supervisor functions vary size. With exception condition code register (the user portion status register), they accessed only instructions supervisor privilege level. 4.2.4.1 Status Register status register (SR) stores processor status. contains condition codes that reflect results previous operation used conditional instruction execution program. condition codes extend (X), negative (N), zero (Z), overflow (V), carry (C). user (low-order) byte containing condition codes only portion information available user privilege level; referenced condition code register (CCR) user programs. supervisor privilege level, software access full status register. upper byte this register includes interrupt priority (IP) mask (three bits), bits placing processor tracing modes disabling tracing, supervisor/user placing processor desired privilege level. Undefined bits status register reserved Motorola future definition. undefined bits read zeros should written zeros future compatibility. operations word-size operations, operations, upper byte read zeros ignored when written, regardless privilege level. Refer D.1.2 Status Register bit/field definitions diagram status register.
MOTOROLA
CENTRAL PROCESSOR UNIT
MC68336/376 USER'S MANUAL
4.2.4.2 Alternate Function Code Registers Alternate function code registers (SFC DFC) contain 3-bit function codes. Function codes considered extensions 24-bit linear address that optionally provide many eight 16-Mbyte address spaces. processor automatically generates function codes select address spaces data programs user supervisor privilege levels select address space used processor functions (such breakpoint interrupt acknowledge cycles). Registers used MOVES instruction specify explicitly function codes memory address. MOVEC instruction used transfer values from alternate function code registers. This long-word transfer; upper bits read zeros ignored when written. 4.2.5 Vector Base Register (VBR) contains base address 1024-byte exception vector table, consisting exception vectors. Exception vectors contain memory addresses routines that begin execution completion exception processing. More information exception processing found Exception Processing. Memory Organization Memory organized byte-addressable basis which lower addresses correspond higher order bytes. example, address long-word data item corresponds address most significant byte highest order word. address most significant byte low-order word address least significant byte long word CPU32 requires long-word word data instructions aligned word boundaries. Refer Figure 4-6. this does happen, exception will occur when CPU32 accesses misaligned instruction data. Data misalignment supported.
MC68336/376 USER'S MANUAL
CENTRAL PROCESSOR UNIT
MOTOROLA
DATA BYTE BITS
BYTE BYTE
BYTE BITS BYTE BYTE WORD BITS
WORD WORD WORD WORD LONG WORD BITS LONG WORD HIGH ORDER ORDER LONG WORD LONG WORD
ADDRESS ADDRESS BITS ADDRESS ADDRESS ADDRESS Most Significant Least Significant DECIMAL DATA Most Significant Digit Least Significant Digit DIGITS BYTE HIGH ORDER ORDER
1125A
Figure Memory Operand Addressing
MOTOROLA
CENTRAL PROCESSOR UNIT
MC68336/376 USER'S MANUAL
Virtual Memory full addressing range CPU32 MC68336/376 Mbytes each eight address spaces. Even though most systems implement smaller physical memory, system made appear have full Mbytes memory available each user program using virtual memory techniques. system that supports virtual memory limited amount high-speed physical memory that accessed directly processor maintains image much larger virtual memory secondary storage device. When processor attempts access location virtual memory that resident physical memory, page fault occurs. access that location temporarily suspended while necessary data fetched from secondary storage placed physical memory. suspended access then restarted continued. CPU32 uses instruction restart, which requires that only small portion internal machine state saved. After correcting fault, machine state restored, instruction fetched started again. This process completely transparent application program. Addressing Modes Addressing CPU32 register-oriented. Most instructions allow results specified operation placed either register directly memory. There need extra instructions store register contents memory. There seven basic addressing modes: Register Direct Register Indirect Register Indirect with Index Program Counter Indirect with Displacement Program Counter Indirect with Index Absolute Immediate register indirect addressing modes include postincrement, predecrement, offset capability. program counter indirect mode also index offset capabilities. addition these addressing modes, many instructions implicitly specify status register, stack pointer, and/or program counter. Processing States processor always four processing states: normal, exception, halted, background. normal processing state associated with instruction execution; used fetch instructions operands store results.
MC68336/376 USER'S MANUAL
CENTRAL PROCESSOR UNIT
MOTOROLA
exception processing state associated with interrupts, trap instructions, tracing, other exception conditions. exception internally generated explicitly instruction unusual condition arising during execution instruction. Exception processing forced externally interrupt, error, reset. halted processing state indication catastrophic hardware failure. example, during exception processing error another error occurs, processor assumes that system unusable halts. background processing state initiated breakpoints, execution special instructions, double fault. Background processing enabled pulling BKPT during RESET. Background processing allows interactive debugging system simple serial interface. Privilege Levels processor operates levels privilege: user supervisor. instructions permitted execute user level, instructions available supervisor level. Effective privilege level protect system resources from uncontrolled access. state status register determines privilege level whether user stack pointer (USP) supervisor stack pointer (SSP) used stack operations. Instructions CPU32 instruction summarized Table 4-2. instruction CPU32 very similar that MC68020. instructions have been added facilitate controller applications: low-power stop (LPSTOP) table lookup interpolate (TBLS, TBLSN, TBLU, TBLUN). Table shows MC68020 instructions that implemented CPU32. Table Unimplemented MC68020 Instructions
BFxx CALLM, RCAS, CAS2 cpxxx PACK, UNPK Memory Field Instructions (BFCHG, BFCLR, BFEXTS, BFEXTU, BFFFO, BFINS, BFSET, BFTST) Call Module, Return Module Compare Swap (Read-Modify-Write Instructions) Coprocessor Instructions (cpBcc, cpDBcc, cpGEN) Pack, Unpack Instructions Memory Indirect Addressing Modes
CPU32 traps unimplemented instructions illegal effective addressing modes, allowing user-supplied code emulate unimplemented capabilities define special purpose functions. However, Motorola reserves right currently unimplemented instruction operation codes future M68000 core enhancements.
MOTOROLA 4-10
CENTRAL PROCESSOR UNIT
MC68336/376 USER'S MANUAL
Table Instruction Summary
ABCD ADDA ADDI ADDQ ADDX ANDI ANDI ANDI SR11 (An), (An) <ea> <ea>, <ea>, #<data>, <ea> <data>, <ea> (An), (An) <ea>, <ea> <data>, <ea> <data>, <data>, <data>, <ea> <data>, <ea> label <ea> <data>, <ea> <ea> <data>, <ea> none <data> label <ea> <data>, <ea> label <ea> <data>, <ea> <ea>, <ea>, <ea> <ea>, <ea>, <data>, <ea> (An) (An) <ea>, label <ea>, none none 32/16 condition true, then number destination destination number destination destination background mode enabled, then enter background mode, else format/vector (SSP); (SSP); (SSP); (vector) breakpoint cycle acknowledged, then execute returned operation word, else trap illegal instruction number destination destination (SP); number destination (ea), then exception lower bound upper bound, then exception Destination (Destination Source), shows results (Destination Source), shows results (Destination Data), shows results (Destination Source), shows results Lower bound Upper bound, shows result condition false, then then Destination Source Destination (signed unsigned) Source10 Destination10 Destination Source Destination Destination Source Destination Destination Immediate data Destination Destination Immediate data Destination Destination Source Destination Destination Source Destination Destination Data Destination Destination Source Source
BCHG BCLR BGND BKPT BSET BTST CHK2 CMPA CMPI CMPM CMP2 DBcc DIVS/DIVU
MC68336/376 USER'S MANUAL
CENTRAL PROCESSOR UNIT
MOTOROLA 4-11
Table Instruction Summary (Continued)
DIVSL/DIVUL EORI EORI EORI EXTB ILLEGAL LINK LPSTOP1 <ea>, <ea>, <ea>, <ea> <data>, <ea> <data>, <data>, none <ea> <ea> <ea>, <data> <data>, <ea> #<data>, <ea> <ea>, <ea> <ea>, USP, CCR, <ea> <ea>, <ea> <ea>, USP, list, <ea> <ea>, list (d16, MOVEP (d16, An), MOVEQ MOVES1 MULS/MULU NBCD #<data>, <ea> <ea>, <ea>, <ea>, <ea>, <ea> 64/32 32/32 32/32 none none none Destination Source Destination (signed unsigned) Source Destination Destination Data Destination Destination Source Source Sign extended Destination Destination Sign extended Destination Destination SSP; vector offset (SSP); SSP; (SSP); SSP; (SSP); Illegal instruction vector address Destination (SP); destination <ea> (SP); Data interrupt mask EBI; STOP
MOVE MOVEA MOVEA1 MOVE from MOVE MOVE from MOVE
Source Destination Source Destination Destination Source Destination Source Listed registers Destination Source Listed registers
MOVE USP1 MOVEC1 MOVEM
24]; 16]; Immediate data Destination Destination using Source using Source Destination Destination (signed unsigned) Destination10 Destination
MOTOROLA 4-12
CENTRAL PROCESSOR UNIT
MC68336/376 USER'S MANUAL
Table Instruction Summary (Continued)
NEGX RESET1 <ea> <ea> none <ea> <ea>, <ea> #<data>, <ea> #<data>, #<data>, <ea> none #<data>, <ea> #<data>, <ea> #<data>, <ea> #<data>, <ea> none none none (An), (An) <ea> #<data> <ea>, <ea> <ea>, #<data>, <ea> #<data>, <ea> (An), (An) none none none none none Destination Destination Destination Destination Destination Destination Source Destination Destination Data Destination Destination Source Source <ea> Assert RESET line
ROXL
ROXR RTE1 SBCD STOP1 SUBA SUBI SUBQ SUBX
(SP) (SP) (SP) Restore stack according format (SP) CCR; (SP) (SP) Destination10 Source10 Destination
condition true, then destination bits one; else, destination bits cleared zero Data STOP Destination Source Destination Destination Source Destination Destination Data Destination Destination Data Destination Destination Source Destination
SWAP
TBLS/TBLU
<ea> <ea>, Dyn,
Destination Tested Condition Codes Destination Temp (Temp Temp (Dym 256) Temp
MC68336/376 USER'S MANUAL
CENTRAL PROCESSOR UNIT
MOTOROLA 4-13
Table Instruction Summary (Continued)
TBLSN/TBLUN <ea>, Dyn, #<data> none #<data> none <ea> Temp (Temp Temp Temp SSP; format/vector offset (SSP); SSP; (SSP); (SSP); vector address true, then TRAP exception set, then overflow TRAP exception Source condition codes (SP)
TRAP TRAPcc TRAPV UNLK
none none none
NOTES: Privileged instruction.
4.8.1 M68000 Family Compatibility philosophy M68000 family that user-mode programs execute unchanged future derivatives M68000 family, supervisor-mode programs exception handlers should require only minimal alteration. CPU32 thought intermediate member M68000 Family. Object code from MC68000 MC68010 executed CPU32. Many instruction addressing mode extensions MC68020 also supported. Refer CPU32 Reference Manual (CPU32RM/AD) detailed comparison CPU32 MC68020 instruction set. 4.8.2 Special Control Instructions Low-power stop (LPSTOP) table lookup interpolate (TBL) instructions have been added MC68000 instruction controller applications. 4.8.2.1 Low-Power Stop (LPSTOP) applications where power consumption consideration, CPU32 forces device into low-power standby mode when immediate processing required. low-power stop mode entered executing LPSTOP instruction. processor remains this mode until user-specified higher) interrupt level reset occurs. 4.8.2.2 Table Lookup Interpolate (TBL) maximize throughput real-time applications, reference data often precalculated stored memory quick access. Storage many data points require inordinate amount memory. table lookup instruction requires that only sample data points stored, reducing memory requirements. instruction recovers intermediate values using linear interpolation. Results rounded with round-to-nearest algorithm.
MOTOROLA 4-14
CENTRAL PROCESSOR UNIT
MC68336/376 USER'S MANUAL
4.8.2.3 Loop Mode Instruction Execution CPU32 several features that provide efficient execution program loops. these features DBcc looping primitive instruction. increase performance CPU32, loop mode been added processor. loop mode used single word instruction that does change program flow. Loop mode implemented conjunction with DBcc instruction. Figure shows required form instruction loop processor enter loop mode.
WORD INSTRUCTION DBCC
DBCC DISPLACEMENT $FFFC
1126A
Figure Loop Mode Instruction Sequence loop mode entered when DBcc instruction executed, loop displacement Once loop mode, processor performs only data cycles associated with instruction suppresses instruction fetches. termination condition count checked after each execution data operations looped instruction. CPU32 automatically exits loop mode interrupts other exceptions. single word instructions that cause change flow looped. Exception Processing exception special condition that preempts normal processing. Exception processing transition from normal mode program execution execution routine that deals with exception. 4.9.1 Exception Vectors exception vector address routine that handles exception. vector base register (VBR) contains base address 1024-byte exception vector table, which consists exception vectors. Sixty-four vectors defined processor, vectors reserved user definition interrupt vectors. Except reset vector, each vector table long word length. reset vector long words length. Refer Table information vector assignment. CAUTION Because there protection processor-defined vectors, external devices access vectors reserved internal purposes. This practice strongly discouraged.
MC68336/376 USER'S MANUAL
CENTRAL PROCESSOR UNIT
MOTOROLA 4-15
exception vectors, except reset vector stack pointer, located supervisor data space. reset vector stack pointer located supervisor program space. Only initial reset vector stack pointer fixed processor memory map. When initialization complete, there fixed assignments. Since stores vector table base address, table located anywhere memory. also dynamically relocated each task executed operating system. Table Exception Vector Assignments
Vector Number 16-23 32-47 48-58 59-63 64-255 1020 Vector Offset Space Assignment Reset: initial stack pointer Reset: initial program counter error Address error Illegal instruction Zero division CHK, CHK2 instructions TRAPcc, TRAPV instructions Privilege violation Trace Line 1010 emulator Line 1111 emulator Hardware breakpoint (Reserved, coprocessor protocol violation) Format error uninitialized interrupt Format error uninitialized interrupt (Unassigned, reserved) Spurious interrupt Level interrupt autovector Level interrupt autovector Level interrupt autovector Level interrupt autovector Level interrupt autovector Level interrupt autovector Level interrupt autovector Trap instruction vectors (0-15) (Reserved, coprocessor) (Unassigned, reserved) User defined vectors (192)
Each vector assigned 8-bit number. Vector numbers some exceptions obtained from external device; others supplied processor. processor multiplies vector number four calculate vector offset, then adds offset contents VBR. memory address vector.
MOTOROLA 4-16
CENTRAL PROCESSOR UNIT
MC68336/376 USER'S MANUAL
4.9.2 Types Exceptions exception caused internal external events. internal exception generated instruction error. TRAP, TRAPcc, TRAPV, BKPT, CHK, CHK2, RTE, instructions cause exceptions during normal execution. Illegal instructions, instruction fetches from addresses, word long-word operand accesses from addresses, privilege violations also cause internal exceptions. Sources external exception include interrupts, breakpoints, errors, reset requests. Interrupts peripheral device requests processor action. Breakpoints used support development equipment. error reset used access control processor restart. 4.9.3 Exception Processing Sequence exceptions other than reset exception, exception processing occurs following sequence. Refer Reset details reset processing. exception processing begins, processor makes internal copy status register. After copy made, processor state bits status register changed set, establishing supervisor access level, bits cleared, disabling tracing. reset interrupt exceptions, interrupt priority mask also updated. Next, exception number obtained. interrupts, number fetched from space (the cycle interrupt acknowledge). other exceptions, internal logic provides vector number. Next, current processor status saved. exception stack frame created placed supervisor stack. stack frames contain copies status register program counter RTE. type exception context which exception occurs determine what other information stored stack frame. Finally, processor prepares resume normal execution instructions. exception vector offset determined multiplying vector number four, offset added contents determine displacement into exception vector table. exception vector loaded into program counter. other exception pending, processor will resume normal execution address 4.10 Development Support following features have been implemented CPU32 enhance instrumentation development environment: M68000 Family Development Support Background Debug Mode Deterministic Opcode Tracking Hardware Breakpoints
MC68336/376 USER'S MANUAL CENTRAL PROCESSOR UNIT MOTOROLA 4-17
4.10.1 M68000 Family Development Support M68000 Family members include features facilitate applications development. These features include following: Trace Instruction Execution M68000 Family processors include instructionby-instruction tracing facility program development. MC68020, MC68030, MC68040, CPU32 also allow tracing only those instructions causing change program flow. trace mode, trace exception generated after instruction executed, allowing debugger program monitor execution program under test. Breakpoint Instruction emulator insert software breakpoints into target code indicate when breakpoint occurred. MC68010, MC68020, MC68030, CPU32, this function provided illegal instructions, $4848-$484F, serve breakpoint instructions. Unimplemented Instruction Emulation During instruction execution, when attempt made execute illegal instruction, illegal instruction exception occurs. Unimplemented instructions (F-line, A-line, utilize separate exception vectors permit efficient emulation unimplemented instructions software. 4.10.2 Background Debug Mode Microcomputer systems generally provide debugger, implemented software, system analysis lowest level. background debug mode (BDM) CPU32 unique that debugger been implemented microcode. incorporates full debugging options: registers viewed altered, memory read written test features invoked. resident debugger simplifies implementation in-circuit emulator. common setup (refer Figure 4-8), emulator hardware replaces target system processor. complex, expensive pod-and-cable interface provides communication path between target system emulator. contrast, integrated debugger supports state analyzer (BSA) incircuit emulation. processor remains target system (refer Figure 4-9) interface simplified. monitors target processor operation on-chip debugger controls operating environment. Emulation much "closer" target hardware, many interfacing problems (for example, limitations highfrequency operation, parametric mismatches, restrictions cable length) minimized.
MOTOROLA 4-18
CENTRAL PROCESSOR UNIT
MC68336/376 USER'S MANUAL
TARGET SYSTEM
IN-CIRCUIT EMULATOR
TARGET
1128A
Figure Common In-Circuit Emulator Diagram
TARGET SYSTEM
STATE ANALYZER
TARGET
1129A
Figure State Analyzer Configuration 4.10.3 Enabling Accidentally entering non-development environment lock CPU32 when serial command interface available. this reason, enabled during reset breakpoint (BKPT) signal. operation enabled when BKPT asserted (low), rising edge RESET. remains enabled until next system reset. high BKPT signal trailing edge RESET disables BDM. BKPT latched again each rising transition RESET. BKPT synchronized internally, must held least clock cycles prior negation RESET. enable logic must designed with special care. hold time BKPT (after trailing edge RESET) extends into first cycle following reset, cycle could inadvertently tagged with breakpoint. Refer Reference Manual (SIMRM/AD) timing information. 4.10.4 Sources When enabled, several sources cause transition from normal mode BDM. These sources include external breakpoint hardware, BGND instruction, double fault, internal peripheral breakpoints. enabled when exception condition occurs, exception processed normally.
MC68336/376 USER'S MANUAL CENTRAL PROCESSOR UNIT MOTOROLA 4-19
Table summarizes processing each source both enabled disabled cases. shown Table 4-4, BKPT instruction never causes transition into BDM. Table Source Summary
Source BKPT Double Fault BGND Instruction BKPT Instruction Enabled Background Background Background Opcode Substitution/ Illegal Instruction Disabled Breakpoint Exception Halted Illegal Instruction Opcode Substitution/ Illegal Instruction
4.10.4.1 External BKPT Signal Once enabled, initiated whenever assertion BKPT acknowledged. disabled, breakpoint exception (vector $0C) acknowledged. BKPT input same timing relationship data strobe trailing edge does read cycle data. There breakpoint acknowledge cycle when entered. 4.10.4.2 BGND Instruction illegal instruction, $4AFA, reserved development tools. CPU32 defines $4AFA (BGND) entry point when enabled. disabled, illegal instruction trap acknowledged. 4.10.4.3 Double Fault CPU32 normally treats double fault, faults succession, catastrophic system error, halts. When this condition occurs during initial system debug fault reset logic), further debugging impossible until problem corrected. BDM, fault temporarily bypassed, that origin fault isolated eliminated. 4.10.4.4 Peripheral Breakpoints CPU32 peripheral breakpoints implemented same external breakpoints peripherals request breakpoints asserting BKPT signal. Consult appropriate peripheral user's manual additional details generation peripheral breakpoints. 4.10.5 Entering When processor detects breakpoint double fault, decodes BGND instruction, suspends instruction execution asserts FREEZE output. This first indication that processor entered BDM. Once FREEZE been asserted, enables serial communication hardware awaits command. writes unique value indicating source transition into temporary register (ATEMP) part process entering BDM. user poll ATEMP determine source (refer Table 4-5) issuing read system register command (RSREG). ATEMP used most debugger commands temporary storage
MOTOROLA 4-20 CENTRAL PROCESSOR UNIT MC68336/376 USER'S MANUAL
imperative that RSREG command first command issued after transition into BDM. Table Polling Entry Source
Source Double Fault BGND Instruction Hardware Breakpoint ATEMP[31:16] SSW1 $0000 $0000 ATEMP[15:0] $FFFF $0001 $0000
NOTES: Special status word (SSW) described detail CPU32 Reference Manual (CPU32RM/AD).
double fault during initial stack pointer/program counter (SP/PC) fetch sequence distinguished value $FFFFFFFF current instruction other time will processor write value into this register. 4.10.6 Commands commands consist 16-bit operation word include more 16bit extension words. Each incoming word read assembled serial interface. microcode routine corresponding command executed soon command complete. Result operands loaded into output shift register shifted next command read. This process repeated each command until returns normal operating mode. Table summary background mode commands.
MC68336/376 USER'S MANUAL
CENTRAL PROCESSOR UNIT
MOTOROLA 4-21
Table Background Mode Command Summary
Command Read Register Write Register Read System Register Write System Register Read Memory Location Description Read selected address data register return RDREG/RAREG results serial interface. data operand written specified address data WDREG/WAREG register. specified system control register read. registers that RSREG read supervisor mode read background mode. operand data written into specified system control WSREG register. Read sized data memory location specified READ long-word address. source function code register (SFC) determines address space accessed. Write operand data memory location specified WRITE long-word address. destination function code (DFC) register determines address space accessed. Used conjunction with READ command dump large blocks memory. initial READ executed DUMP starting address block retrieve first result. Subsequent operands retrieved with DUMP command. Used conjunction with WRITE command fill large blocks memory. initial WRITE executed FILL starting address block supply first operand. Subsequent operands written with FILL command. pipe flushed re-filled before resuming instruction execution current Current program counter stacked location curCALL rent stack pointer. Instruction execution begins user patch code. Asserts RESET clock cycles. reset this command. Synonymous with RESET instruction. performs operation used null comNOP mand. Mnemonic
Write Memory Location
Dump Memory Block
Fill Memory Block
Resume Execution Patch User Code Reset Peripherals Operation
4.10.7 Background Mode Registers processing uses three special purpose registers keep track program context during development. description each follows. 4.10.7.1 Fault Address Register (FAR) contains address faulting cycle immediately following address error. This address remains available until overwritten subsequent cycle. Following double fault, contains address last cycle. address first fault there one) visible user. 4.10.7.2 Return Program Counter (RPC) points location where fetching will commence after transition from background mode normal mode. This register should accessed change flow program under development. Changing value will cause address error when normal mode prefetching begins.
MOTOROLA 4-22
CENTRAL PROCESSOR UNIT
MC68336/376 USER'S MANUAL
4.10.7.3 Current Instruction Program Counter (PCC) holds pointer first word last instruction executed prior transition into background mode. instruction pipelining, instruction pointed instruction which caused transition. example breakpoint released write. cycle overlap many subsequent instructions before stalling instruction sequencer. breakpoint asserted during this cycle will acknowledged until instruction executing completion cycle. will contain $00000001 entered double fault immediately reset. 4.10.8 Returning from terminated when resume execution (GO) call user code (CALL) command received. Both CALL flush instruction pipeline refetch instructions from location pointed RPC. return memory space referred status register SUPV reflect changes made during BDM. FREEZE negated prior initiating first prefetch. Upon negation FREEZE, serial subsystem disabled, signals revert IPIPE/IFETCH functionality. 4.10.9 Serial Interface Communication with CPU32 during occurs dedicated serial interface, which shares pins with other development features. Figure 4-10 block diagram interface. BKPT signal becomes serial clock (DSCLK); serial input data (DSI) received IFETCH, serial output data (DSO) transmitted IPIPE.
MC68336/376 USER'S MANUAL
CENTRAL PROCESSOR UNIT
MOTOROLA 4-23
INSTRUCTION REGISTER DATA LATCH
DEVELOPMENT SYSTEM
DATA COMMAND LATCH
SERIAL PARALLEL
PARALLEL SERIAL
PARALLEL SERIAL
SERIAL PARALLEL
STATUS EXECUTION UNIT SYNCHRONIZE MICROSEQUENCER STATUS RESULT LATCH DATA
CONTROL LOGIC
DSCLK
CONTROL LOGIC
SERIAL CLOCK
DEBUG BLOCK
Figure 4-10 Debug Serial Block Diagram serial interface uses full-duplex synchronous protocol similar serial peripheral interface (SPI) protocol. development system serves master serial link since responsible generation DSCLK. DSCLK derived from CPU32 system clock, development system serial logic unhindered operating frequency target processor. Operable frequency range serial clock from one-half processor system clock frequency. serial interface operates full-duplex mode data transmitted received simultaneously both master slave devices. general, data transitions occur falling edge DSCLK stable following rising edge DSCLK. Data transmitted first, latched rising edge DSCLK. serial data word bits wide, including data bits status/control (refer Figure 4-11). indicates status CPU-generated messages. Table shows CPU-generated message types.
MOTOROLA 4-24
CENTRAL PROCESSOR UNIT
MC68336/376 USER'S MANUAL
DATA FIELD
STATUS CONTROL
SERIAL DATA WORD
Figure 4-11 Serial Data Word
Table Generated Message Encoding
Data XXXX FFFF 0000 0001 FFFF Message Type Valid Data Transfer Command Complete; Status Ready with Response; Come Again BERR Terminated Cycle; Data Invalid Illegal Command
Command data transfers initiated development system should clear current implementation ignores this bit; however, Motorola reserves right this future enhancements. 4.10.10 Recommended Connection order provide development tools when installed system, Motorola recommends that appropriate signal lines routed male Berg connector double-row header installed circuit board with MCU, shown following figure.
RESET
BERR BKPT/DSCLK FREEZE IFETCH/DSI IPIPE/DSO
BERG
Figure 4-12 Connector Pinout
MC68336/376 USER'S MANUAL
CENTRAL PROCESSOR UNIT
MOTOROLA 4-25
4.10.11 Deterministic Opcode Tracking CPU32 function code outputs augmented supplementary signals monitor instruction pipeline. instruction pipe (IPIPE) output indicates start each instruction each mid-instruction pipeline advance. instruction fetch (IFETCH) output identifies cycles which operand loaded into instruction pipeline. Pipeline flushes also signaled with IFETCH. Monitoring these signals allows state analyzer synchronize itself instruction stream monitor activity. 4.10.12 On-Chip Breakpoint Hardware external breakpoint input on-chip breakpoint hardware allow breakpoint trap memory access. Off-chip address comparators preclude breakpoints unless show cycles enabled. Breakpoints instruction prefetches that ultimately flushed from instruction pipeline acknowledged; operand breakpoints always acknowledged. Acknowledged breakpoints initiate exception processing address exception vector number alternately enter background mode.
MOTOROLA 4-26
CENTRAL PROCESSOR UNIT
MC68336/376 USER'S MANUAL
SECTION SYSTEM INTEGRATION MODULE
This section overview system integration module (SIM) function. Refer Reference Manual (SIMRM/AD) comprehensive discussion capabilities. Refer System Integration Module information concerning address register structure. General consists functional blocks. Figure shows block diagram SIM. system configuration block controls configuration parameters. system clock generates clock signals used SIM, other modules, external devices. system protection block provides software watchdog monitors. addition, also provides periodic interrupt timer support execution time-critical control routines. external interface handles transfer information between modules external address space. chip-select block provides chip-select signals. Each chip-select signal associated base address register option register that contain programmable characteristics that chip-select. system test block incorporates hardware necessary testing MCU. used perform factory tests, normal applications supported.
MC68336/376 USER'S MANUAL
SYSTEM INTEGRATION MODULE
MOTOROLA
SYSTEM CONFIGURATION
CLOCK SYNTHESIZER
XTAL CLKOUT EXTAL MODCLK
SYSTEM PROTECTION
CHIP-SELECTS
CHIP-SELECTS
EXTERNAL EXTERNAL INTERFACE RESET
FACTORY TEST
TSTME /TSC FREEZE/QUOT
S(C)IM BLOCK
Figure System Integration Module Block Diagram System Configuration configuration register (SIMCR) governs several aspects system operation. following paragraphs describe those configuration options controlled SIMCR. 5.2.1 Module Mapping Control registers modules microcontroller mapped into 4-Kbyte block. state module mapping (MM) configuration register (SIMCR) determines where control register block located system memory map. When register addresses range from $7FF000 $7FFFFF; when register addresses range from $FFF000 $FFFFFF. 5.2.2 Interrupt Arbitration Each module that request interrupts interrupt arbitration (IARB) field. Arbitration between interrupt requests same priority performed serial contention between IARB field values. Contention must take place whenever interrupt request acknowledged, even when there only single request pending. interrupt serviced, appropriate IARB field must have non-zero value. interrupt request from module with IARB field value %0000 recognized, CPU32 processes spurious interrupt exception.
MOTOROLA
SYSTEM INTEGRATION MODULE
MC68336/376 USER'S MANUAL
Because routes external interrupt requests CPU32, IARB field value used arbitration between internal external interrupts same priority. reset value IARB %1111, reset IARB value other modules %0000, which prevents interrupts from being discarded during initialization. Refer Interrupts discussion interrupt arbitration. 5.2.3 Show Internal Cycles show cycle allows internal transfers monitored externally. SHEN field SIMCR determines what external interface does during internal transfer operations. Table shows whether data driven externally, whether external arbitration occur. Refer 5.6.6.1 Show Cycles more information. Table Show Cycle Enable Bits
SHEN[1:0] Action Show cycles disabled, external arbitration enabled Show cycles enabled, external arbitration disabled Show cycles enabled, external arbitration enabled Show cycles enabled, external arbitration enabled; internal activity halted grant
5.2.4 Register Access CPU32 operate privilege levels. Supervisor level more privileged than user level instructions system resources available supervisor level, access restricted user level. Effective privilege level protect system resources from uncontrolled access. state status register determines access level, whether user supervisor stack pointer used stacking operations. SUPV places global registers either supervisor user data space. When SUPV registers with controlled access accessible from either user supervisor privilege level; when SUPV registers with controlled access restricted supervisor access only. 5.2.5 Freeze Operation FREEZE signal halts operations during debugging. FREEZE asserted internally CPU32 breakpoint occurs while background mode enabled. When FREEZE asserted, only monitor, software watchdog, periodic interrupt timer affected. halt monitor spurious interrupt monitor continue operate normally. Setting freeze monitor (FRZBM) SIMCR disables monitor when FREEZE asserted. Setting freeze software watchdog (FRZSW) disables software watchdog periodic interrupt timer when FREEZE asserted.
MC68336/376 USER'S MANUAL
SYSTEM INTEGRATION MODULE
MOTOROLA
System Clock system clock provides timing signals modules external peripheral bus. Because fully static design, register memory contents affected when clock rate changes. System hardware software support changes clock rate during operation. system clock signal generated from sources. internal phaselocked loop (PLL) synthesize clock from fast reference, clock signal directly input from external frequency source. fast reference typically 4.194 crystal, generated sources other than crystal. Keep these sources mind while reading rest this section. Refer Table APPENDIX ELECTRICAL CHARACTERISTICS clock specifications. Figure block diagram clock submodule.
MODCLK
EXTAL
XTAL
DDSYN
CLKOUT
CRYSTAL OSCILLATOR
PHASE COMPARATOR
LOW-PASS FILTER
FEEDBACK DIVIDER
SYSTEM CLOCK CONTROL
SYSTEM CLOCK
16/32 BLOCK
Figure System Clock Block Diagram 5.3.1 Clock Sources state clock mode (MODCLK) during reset determines system clock source. When MODCLK held high during reset, clock synthesizer generates clock signal from external reference frequency. clock synthesizer control register (SYNCR) determines operating frequency mode operation. When MODCLK held during reset, clock synthesizer disabled external system clock signal must driven onto EXTAL pin. input clock referred fref, either crystal external clock source. output clock system referred fsys. Ensure that fref fsys within normal operating limits.
MOTOROLA SYSTEM INTEGRATION MODULE MC68336/376 USER'S MANUAL
generate reference frequency using crystal oscillator, reference crystal must connected between EXTAL XTAL pins. Typically, 4.194 crystal used, frequency vary between MHz. Figure shows typical circuit.
XTAL EXTAL
RESISTANCE CAPACITANCE BASED TEST CIRCUIT CONSTRUCTED WITH KDS041-18 4.194 CRYSTAL. SPECIFIC COMPONENTS MUST BASED CRYSTAL TYPE. CONTACT CRYSTAL VENDOR EXACT CIRCUIT.
OSCILLATOR
Figure System Clock Oscillator Circuit fast reference frequency provided from source other than crystal, external system clock signal applied through EXTAL pin, XTAL must left floating. When external system clock signal applied (MODCLK during reset), disabled. duty cycle this signal critical, especially operating frequencies close maximum. relationship between clock signal duty cycle clock signal period expressed follows:
Minimum External Clock Period Minimum External Clock High/Low Time -50% Percentage Variation External Clock Input Duty Cycle 5.3.2 Clock Synthesizer Operation VDDSYN used power clock circuits when system clock synthesized from either crystal externally supplied reference frequency. separa

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