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MAX3264 MAX3268 MAX3768 MAX3265 MAX3269 MAX3765 MAX3264 MAX3265 MAX3765 MAX3269 MAX3768


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19-1523; 7/03
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
1.25Gbps MAX3264/MAX3268/MAX3768 2.5Gbps MAX3265/MAX3269/MAX3765 limiting amplifiers designed Gigabit Ethernet Fibre Channel optical receiver systems. amplifiers accept wide range input voltages provide constantlevel output voltages with controlled edge speeds. Additional features include power detectors with programmable loss-of-signal (LOS) indication, optional squelch function that mutes data output signal when input voltage falls below programmable threshold, excellent jitter performance. MAX3264/MAX3265/MAX3765 feature current-mode logic (CML) data outputs that tolerant inductive connectors 16-pin TSSOP package, making these circuits ideal GBIC receivers. MAX3268/ MAX3269/MAX3768 feature standards-compliant positive-referenced emitter-coupled logic (PECL) data outputs available tiny 10-pin µMAX package that ideal small-form-factor (SFF) receivers.
Features
+3.0V +5.5V Supply Voltage Deterministic Jitter 14ps (MAX3264) 11ps (MAX3265/MAX3765) 150ps (max) Edge Speed (MAX3265/MAX3765) 300ps (max) Edge Speed (MAX3264) Programmable Signal-Detect Function Choice PECL Output Interface 10-Pin µMAX 16-Pin TSSOP Package
Ordering Information
PART MAX3264CUE MAX3264C/D MAX3265CUE MAX3265CUB MAX3265C/D MAX3265EUE MAX3268CUB MAX3268C/D MAX3269CUB MAX3269C/D MAX3765CUB TEMP RANGE +70°C +70°C +70°C +70°C +70°C -40°C +85°C +70°C +70°C +70°C +70°C +70°C PIN-PACKAGE TSSOP-EP Dice* TSSOP-EP µMAX-EP Dice* TSSOP-EP µMAX-EP Dice* µMAX-EP Dice* µMAX-EP
Applications
Gigabit Ethernet Optical Receivers Fibre Channel Optical Receivers System Interconnect AOptical Receivers
Selector Guide appears data sheet. Configurations appear data sheet.
MAX3768CUB +70°C µMAX-EP *Dice designed operate from +70°C, tested guaranteed only +25°C. Exposed paddle.
Typical Operating Circuits
CAZ1
CAZ2
0.01µF
MAX3264CUE MAX3265CUE MAX3265EUE
OUT+
RTERM 0.01µF
OUT-
0.01µF
MAX3266 MAX3267
0.01µF SQUELCH LEVEL N.C. LOSS SIGNAL N.C. N.C.
RTERM
Typical Operating Circuits continued data sheet.
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (VCC) .-0.5V +6.0V Voltage IN+, .(VCC 2.4V) (VCC 0.5V) Voltage SQUELCH, CAZ1, CAZ2, LOS, LOS, TH.-0.5V (VCC 0.5V) Voltage LEVEL.-0.5V +2.0V Current into LOS, .-1mA +9mA Differential Input Voltage (IN+ IN-) .2.5V Continuous Current Outputs (OUT+, OUT-) .-25mA +25mA Continuous Current PECL Outputs (OUT+, OUT-) .50mA Continuous Power Dissipation +70°C) 16-Pin TSSOP (derate 27mW/°C above +70°C) .2162mW 10-Pin µMAX (derate 20mW/°C above +70°C) .1600mW Operating Ambient Temperature Range .-40°C +85°C Storage Temperature Range .-55°C +150°C Processing Temperature (dice) .+400°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(Data outputs terminated Figure +3.0V +5.5V, +70°C. Typical values +3.3V, +25°C, unless otherwise noted.) (Note PARAMETER Data Rate Input Voltage Range Deterministic Jitter Random Jitter CONDITIONS MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 MAX3264/MAX3268/MAX3768 (Notes MAX3265/MAX3269/MAX3765 (Notes MAX3264/MAX3268/MAX3768 (Notes MAX3265/MAX3269/MAX3765 (Notes MAX3264 (Note Data Output Edge Speed MAX3265/MAX3765 (Note MAX3268/MAX3768 (Note MAX3269 (Note Hysteresis Assert/Deassert Time Assert Level Deassert Level (Notes (Notes 2.5k 2.5k MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 1.20 2.20 1.25 1200 1200 UNITS Gbps psp-p psRMS
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
ELECTRICAL CHARACTERISTICS (continued)
(Data outputs terminated Figure +3.0V +5.5V, +70°C. Typical values +3.3V, +25°C, unless otherwise noted.) (Note
PARAMETER Medium Assert Level Medium Deassert Level High Assert Level High Deassert Level Squelch Input Current Differential Input Resistance Input-Referred Noise Output Voltage PECL Output High Voltage PECL Output Voltage Output High Voltage Output Voltage Output Signal When Squelched Power-Supply Rejection Ratio Low-Frequency Cutoff Output Resistance (Single Ended) INMAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 LEVEL open, RLOAD LEVEL GND, RLOAD Referenced Referenced ILOS -30µA ILOS +1.2mA Outputs AC-coupled 2MHz open 0.1µF MAX3264/MAX3265/MAX3765 MAX3268/MAX3269/MAX3768 MAX3268 MAX3269 MAX3264 Power-Supply Current Figure Output squelched Output squelched MAX3265 MAX3765 MAX3768 MAX3765 1100 -1.025 -1.810 1270 CONDITIONS MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 MAX3264/MAX3268/MAX3768 MAX3265/MAX3269/MAX3765 18.0 21.6 41.5 1200 1800 -0.880 +1.620 19.8 40.5 UNITS µVRMS
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
ELECTRICAL CHARACTERISTICS-MAX3265EUE
(Data outputs terminated Figure +3.0V +5.5V, -40°C +85°C. Typical values +3.3V, +25°C, unless otherwise noted.) (Note PARAMETER Data Rate Input Voltage Range Deterministic Jitter Random Jitter Data Output Edge Speed Hysteresis Assert/Deassert Time Assert Level Deassert Level Medium Assert Level Medium Deassert Level High Assert Level High Deassert Level Squelch Input Current Differential Input Resistance Input-Referred Noise Output Voltage Output High Voltage Output Voltage Output Signal When Squelched Power-Supply Rejection Ratio Low-Frequency Cutoff Output Resistance (single ended) Power-Supply Current Figure LEVEL open, RLOAD LEVEL GND, RLOAD ILOS -30µA ILOS +1.2mA Outputs AC-coupled 2MHz open 0.1µF 1100 0.450 1270 IN(Notes (Notes (Note (Notes (Notes 2.5k 2.5k 18.0 2.20 41.5 1200 1800 43.0 13.6 CONDITIONS 1200 UNITS Gbps psp-p psRMS µVRMS
Note Specifications Input Voltage Range, Assert/Deassert Levels, Output Voltage refer total differential peak-to-peak signal applied measured. PECL output voltages absolute (single-ended) voltages measured single output. Note Input edge speed controlled using four-pole, lowpass Bessel filters with bandwidth approximately maximum data rate. Note Deterministic jitter measured with K28.5 pattern (0011 1110 1011 0000 0101). Deterministic jitter peak-to-peak deviation from ideal time crossings, measured zero-level crossings differential output ANSI X3.230, Annex Note Random jitter measured with minimum input signal applied after filtering with four-pole, lowpass, Bessel filter (frequency bandwidth maximum data rate). Fibre Channel Gigabit Ethernet applications, peak-topeak random jitter 14.1-times random jitter. Note Input signal applied after 933MHz Bessel filter. Note Input signal applied after 1.8GHz Bessel filter. Note Input assert/deassert hysteresis tests repeating K28.5 pattern. Hysteresis defined 20log (VLOS-DEASSERT VLOS-ASSERT). Note Response time 10dB change input power.
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Typical Operating Characteristics
+25°C, unless otherwise noted.)
OUTPUT VOLTAGE INPUT VOLTAGE
MAX3264/5/8/9 TOC01a
MAX3264 HYSTERESIS TEMPERATURE
MAX3264/5/8/9 TOC03a
MAX3265EUE HYSTERESIS TEMPERATURE
MAX3264/5/8/9 TOC03
1700 1500 OUTPUT VOLTAGE (mV) MAX3264/MAX3268 1300 1100 MAX3265/MAX3269/MAX3765
HYSTERESIS (dB)
HYSTERESIS (dB) 4.6k
INPUT VOLTAGE (mV)
TEMPERATURE (°C)
TEMPERATURE (°C)
MAX3264/MAX3268/MAX3768 DETERMINISTIC JITTER INPUT AMPLITUDE
MAX3264/5/8/9 TOC04
MAX3264/MAX3268/MAX3768 RANDOM JITTER INPUT AMPLITUDE
JITTER (ps)
MAX3264/5/8/9 TOC05
MAX3265/MAX3269/MAX3765 DETERMINISTIC JITTER INPUT AMPLITUDE
MAX3264/5/8/9 TOC06
JITTER (ps) 1000
JITTER (ps)
1200 INPUT AMPLITUDE (mV) INPUT AMPLITUDE (mV)
1000
1200
INPUT AMPLITUDE (mV)
MAX3265/MAX3269/MAX3765 RANDOM JITTER INPUT AMPLITUDE
MAX3264/5/8/9 TOC07
LOSS SIGNAL WITH SQUELCH
MAX3264/5/8/9 TOC08
MAX3268/MAX3768 DATA OUTPUT DIAGRAM (MINIMUM INPUT)
MAX3264/5/8/9 TOC09
JITTER (ps)
VOUT 300mV/div
VLOS
500ns/div
200ps/div
INPUT AMPLITUDE (mV)
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Typical Operating Characteristics (continued)
+25°C, unless otherwise noted.)
MAX3264 DATA OUTPUT DIAGRAM 1.25Gbps (MINIMUM INPUT)
MAX3264/5/8/9 TOC10
MAX3264 DATA OUTPUT DIAGRAM 1.25Gbps (MAXIMUM INPUT)
MAX3264/5/8/9 TOC11
MAX3265/MAX3765 DATA OUTPUT DIAGRAM 2.5Gbps (MINIMUM INPUT)
MAX3264/5/8/9 TOC12
150mV/div
50mV/div
150mV/div
200ps/div
200ps/div
100ps/div
MAX3265/MAX3765 DATA OUTPUT DIAGRAM 2.5Gbps (MAXIMUM INPUT)
MAX3264/5/8/9 TOC13
POWER-SUPPLY REJECTION RATIO FREQUENCY
PSRR (dB)
MAX3264/5/8/9 TOC14
OUTPUT VSWR FREQUENCY
MAX3264/5/8/9 TOC15
VSWR
150mV/div
100ps/div
100k
FREQUENCY (Hz)
100M
FREQUENCY (GHz)
MAX3264 LOSS-OF-SIGNAL THRESHOLD
MAX3264/5/8/9 TOC18
MAX3265/MAX3765 LOSS-OF-SIGNAL THRESHOLD
MAX3264/5/8/9 TOC19
COMMON-MODE REJECTION RATIO FREQUENCY
CMRR (dB) MAX3265/MAX3765 MAX3268/MAX3768
MAX3264/5/8/9 TOC20
ASSERT THRESHOLD (mV)
ASSERT THRESHOLD (mV)
100M FREQUENCY (Hz)
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Description
NAME µMAX TSSOP INTH Supply Ground Noninverted Input Signal Inverted Input Signal Loss-of-Signal Threshold. resistor connected from this ground sets input signal level which loss-of-signal (LOS) output(s) asserted. Refer Typical Operating Characteristics Design Procedure. Inverted Loss-of-Signal Output. high when level input signal above preset threshold input. asserted when signal level drops below threshold. Supply Voltage Inverted Data Output Noninverted Data Output Offset-Correction-Loop Capacitor. capacitor connected between this CAZ2 extends time constant offset correction loop. Offset-Correction-Loop Capacitor. capacitor connected between this CAZ1 extends time constant offset correction loop. Refer Design Procedure. Output Current Level. When this connected, output current approximately 16mA. When this connected ground, output current increases approximately 20mA. MAX3265CUB/MAX3765CUB, LEVEL internally connected ground.) Noninverted Loss-of-Signal Output. when level input signal above preset threshold input. asserts high when signal level drops below threshold. Squelch Input. squelch function disabled when SQUELCH connected level. When SQUELCH high level asserted, data outputs, OUT+, OUT-, forced static levels. sections PECL Output Buffer Output Buffer more information. MAX3265/MAX3268/MAX3269 10-pin µMAX, SQUELCH connected. MAX3765/MAX3768, SQUELCH internally connected VCC.) Connection Ground. exposed paddle must soldered circuit-board ground proper thermal performance. FUNCTION
OUTOUT+ CAZ1
CAZ2
LEVEL
SQUELCH
N.C. Exposed Paddle
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
RTERM COUT RLOAD RTERM COUT RLOAD
COUT
COUT
MAX3264 MAX3265 MAX3765 MAX3264/MAX3265/MAX3765 WITH TERMINATION
MAX3264 MAX3265 MAX3765 MAX3264/MAX3265/MAX3765 WITH TERMINATION
MAX3268 MAX3269 MAX3768
OUTOUT+
RTERM
MAX3268/MAX3269/MAX3768 OUTPUT TERMINATION
Figure Data Output Termination
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
IOUT
MAX3264CUE: OPEN MAX3265CUE: OPEN SQUELCH MAX3265CUB: (INTERNAL) MAX3765CUB: (INTERNAL) MAX3264 MAX3265 MAX3765 CONTROL LEVEL MAX3264CUE: OPEN MAX3265CUE: OPEN MAX3265CUB: (INTERNAL) MAX3765CUB: (INTERNAL)
2.5k
SUPPLY CURRENT (ICC)
OUT+
OPEN
MAX3268 MAX3269 MAX3768 2.5k
OUTOPEN
PECL SUPPLY CURRENT (ICC)
Figure Power-Supply Current Measurement
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
_Detailed Description
Figure functional diagram MAX3264/ limiting amplifiers. linear input buffer drives multistage limiting amplifier power-detection circuit. Offset correction with lowpass filtering ensures deterministic jitter. output buffer produces limited output signal. MAX3264/MAX3265/MAX3765 produce output, while MAX3268/MAX3269/ MAX3768 produce PECL-compatible output signal. Schematics these input/output circuits shown Figures through
Power Detect with Loss-of-Signal Indicator
power detector looks signal from input buffer compares threshold resistor (see Typical Operating Characteristics appropriate resistor values). signal-detect information provided outputs, which internally terminated with (MAX3265/MAX3269/MAX3765) (MAX3264/MAX3268/MAX3768) pullup resistors. outputs meet voltage specifications when loaded with resistor 4.7k.
MAX3264 MAX3265 MAX3268 MAX3269 MAX3765 MAX3768
RLOS (MAX3265/MAX3269/MAX3765) RLOS (MAX3264/MAX3268/MAX3768) RLOS POWER DETECT WITH COMPARATOR
RLOS
ININPUT BUFFER
GAIN OUT+ OUTPUT BUFFER OUT-
SQUELCH LOWPASS OFFSET CORRECTION 100pF CONTROL LEVEL
CAZ1 TOTAL GAIN 55dB (MAX3264/MAX3268/MAX3768) TOTAL GAIN 49dB (MAX3265/MAX3269/MAX3765)
CAZ2
Figure Functional Diagram
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Input Buffer
input buffer designed accept input signals from MAX3266/MAX3267 transimpedance amplifiers. input buffer provides input impedance between IN-. Input VSWR typically less than frequencies less than 2GHz. DC-coupling inputs recommended; this prevents offset-correction circuitry from functioning properly.
Output Buffer
MAX3264/MAX3265/MAX3765 output circuits (Figure provide high tolerance impedance mismatches inductive connectors. output current levels. When LEVEL left unconnected, output current approximately 16mA. Connecting LEVEL ground sets output current approximately 20mA. squelch function enabled when SQUELCH TTL-high level connected VCC. squelch function holds OUT+ OUT- static voltage whenever input signal power drops below loss-of-signal threshold. 10-pin µMAX package MAX3265/MAX3268/MAX3269, SQUELCH function left internally unconnected. MAX3765/ MAX3768, SQUELCH function always enabled internally connecting VCC. SQUELCH operation MAX3264/MAX3265 described Table
Gain Stage Offset Correction
limiting amplifier provides approximately 55dB (MAX3264/MAX3268/MAX3768) 49dB (MAX3265/ MAX3269/MAX3765) gain. This large gain makes amplifier susceptible small offsets input signal. offsets reduce accuracy power-detection circuit cause deterministic jitter. low-frequency feedback loop integrated into limiting amplifier reduce input offset, typically less than 100µV. external capacitor connected between CAZ1 CAZ2, parallel with internal capacitance, determines time constant offset-correction circuit. offset-correction circuit requires average data-input mark density prevent increase dutycycle distortion ensure deterministic jitter.
Table
LEVEL Open VOLTAGE WHEN SQUELCHED OUTVCC 100mV 100mV OUT+ 100mV
Internal Input/Output Schematics
0.25pF IN0.25pF
STRUCTURES
STRUCTURE
(MAX3265/MAX3269/MAX3765) (MAX3264/MAX3268/MAX3768)
Figure Input Circuit
Figure Output Circuit
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
STRUCTURES STRUCTURES OUT+ OUTOUT+ OUT-
LEVEL
Figure PECL Output Circuit
Figure Output Circuit
buffer's output impedance determined parallel combination internal external pullup resistors, which chosen match impedance transmission line (Figure output buffer DC-coupled load.
minimized when input low-frequency cutoff (fIN) placed frequency: [2(50)(C)] Fibre Channel, Gigabit Ethernet, other applications using 8B/10B data coding, select (CIN, COUT) 0.01µF, which provides 320kHz. ATM/SONET other applications using scrambled data, select (CIN, COUT) 0.1µF, which provides 32kHz.
PECL Output Buffer
MAX3268/MAX3269/MAX3768 offer industrystandard PECL output. PECL outputs should terminated Figure shows PECL output circuit. squelch function forces OUT+ high level OUT- level when input below programmed threshold. 10-pin µMAX, SQUELCH left unconnected.
Select Offset-Correction Capacitor (MAX3264/MAX3265 TSSOP Only)
maintain stability, important keep onedecade separation between low-frequency cutoff (fOC) associated with DC-offset-correction circuit. (CAZ 100pF)] (CAZ 100pF) Fibre Channel, Gigabit Ethernet, other applications using 8B/10B data coding, leave pins CAZ1, CAZ2 open (fOC 2MHz). ATM/SONET other applications using scrambled data, select 0.1µF, which typically provides 2kHz.
_Design Procedure
Program Assert Threshold
loss-of-signal threshold programmed external resistor RTH. Threshold graph Typical Operating Characteristics.
Select Coupling Capacitors
coupling capacitors (CIN, COUT) should selected minimize receiver's deterministic jitter. Jitter
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Applications Information
Optical Hysteresis
optical receiver, electrical power change limiting amplifier optical power change. example, receiver's optical input power increases factor two, preamplifier linear, then voltage input limiting amplifier also increases factor two. optical power change 10log(2x 10log(2) +3dB. limiting amplifier, electrical power change
10log
VCC_MODULE HOST VCC_HOST
GBIC MODULE
4.7k
(2VIN
VIN2
10log(22 20log(2)
MAX3264 MAX3265 MAX3268 MAX3269 MAX3765 MAX3768
GENERALPURPOSE
typical voltage hysteresis 4.4dB. This provides optical hysteresis 2.2dB.
Figure Recommended GBIC Circuit
GBIC Loss Signal
GBIC application, GBIC's output must high impedance when VCC_MODULE GND. Figure shows recommended circuit maintain high impedance. protection diodes MAX3264/ outputs turned when HOST VCC_MODULE.
OUT+
MAX3268 MAX3269 MAX3768
OUT470
PECL Terminations
standard PECL termination recommended best performance output characteristics (see Figure data outputs operate high speed should always drive transmission lines with matched, balanced terminations. Figure shows alternate method terminating data outputs. technique provides approximately bias current, with load, output termination. This technique useful viewing output oscilloscope changing PECL reference voltage.
DRIVING GROUND
Figure Alternative PECL Termination
Wire Bonding Dice
high current density reliable operation, MAX3264/MAX3265/MAX3268/MAX3269 gold metalization. Make connections dice with gold wire only, ballbonding techniques (wedge bonding recommended). Die-pad size 4-mils square, with 6-mil pitch. thickness mils (0.375mm).
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Typical Operating Circuits (continued)
0.01µF
MAX3268CUB MAX3269CUB MAX3768CUB
OUT+
OUT50 SIGNAL DETECT
MAX3266 MAX3267
0.01µF
Configurations
VIEW
CAZ1 CAZ2 LEVEL N.C. SQUELCH INGND OUT+ OUTVCC
MAX3264 MAX3265
OUT+ OUT11
MAX3265 MAX3268 MAX3269 MAX3765 MAX3768 µMAX
TSSOP
NOTE: EXPOSED PADDLE GROUND.
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Selector Guide
PART MAX3264 MAX3265 MAX3268 MAX3269 MAX3765 MAX3768 *LEVEL grounded OUTPUT PECL PECL PECL DATA RATE (Gbps) 1.25 1.25 1.25 PINPACKAGE TSSOP-EP TSSOP-EP µMAX-EP µMAX-EP µMAX-EP µMAX-EP µMAX-EP SQUELCH FUNCTION Selectable Selectable Disabled Disabled Disabled Enabled Enabled OUTPUT LEVEL Selectable Selectable Maximum* Maximum*
Chip Topographies
MAX3264/MAX3265/MAX3765
CAZ1 N.C.
MAX3268/MAX3269/MAX3768
CAZ1 N.C.
CAZ2 INGND LEVEL
SQUELCH OUT+ OUTVCC 0.061" (1.55mm)
CAZ2 INGND
SQUELCH OUT+ OUTVCC 0.061" (1.55mm)
N.C. 0.061" (1.55mm)
N.C. 0.061" (1.55mm)
MAX3264/MAX3265/MAX3765 TRANSISTOR COUNT: MAX3268/MAX3269/MAX3768 TRANSISTOR COUNT: SUBSTRATE CONNECTED
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
10LUMAX.EPS
INCHES 0.043 0.006 0.002 0.030 0.037 0.120 0.116 0.118 0.114 0.116 0.120 0.114 0.118 0.187 0.199 0.0157 0.0275 0.037 0.007 0.0106 0.0197 0.0035 0.0078 0.0196
MILLIMETERS 1.10 0.05 0.15 0.75 0.95 2.95 3.05 2.89 3.00 2.95 3.05 2.89 3.00 4.75 5.05 0.40 0.70 0.940 0.177 0.270 0.500 0.090 0.200 0.498
0.50±0.1 0.6±0.1
0.6±0.1
VIEW
BOTTOM VIEW
GAGE PLANE
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, uMAX/uSOP
APPROVAL DOCUMENT CONTROL REV.
21-0061
+3.0V +5.5V, 1.25Gbps/2.5Gbps Limiting Amplifiers
Package Information (continued)
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
TSSOP.EPS
VIEW
BOTTOM VIEW
DETAIL
SEATING PLANE
WITH PLATING
SIDE VIEW
VIEW
PARTING LINE BASE METAL
0.25
DETAIL
SECTION
NOTES: DIMENSIONS REFERENCE DATUMS INCLUDE MOLD FLASH. MOLD FLASH PROTRUSIONS EXCEED 0.15MM SIDE, 0.25MM SIDE. CONTROLLING DIMENSION: MILLIMETERS. THIS PART COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS, REFERS NUMBER LEADS. LEAD TIPS MUST WITHIN SPECIFIED ZONE. THIS TOLERANCE ZONE DEFINED PARALLEL PLANES. PLANE SEATING PLANE, DATUM (-C-), OTHER PLANE SPECIFIED DISTANCE FROM (-C-) DIRECTION INDICATED.
TITLE:
SEMICONDUCTOR
PROPRIETARY INFORMATION
DALLAS
PACKAGE OUTLINE, TSSOP, 6.1mm BODY
APPROVAL DOCUMENT CONTROL REV.
21-0155
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
_Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2003 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

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