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3.3V-5V Kbit (32Kb TIMEKEEPER® SRAM
INTEGRATED ULTRA-LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT BATTERY FREQUENCY TEST OUTPUT REAL TIME CLOCK YEAR 2000 COMPLIANT AUTOMATIC POWER-FAIL CHIP DESELECT WRITE PROTECTION WATCHDOG TIMER WRITE PROTECT VOLTAGE (VPFD Power-Fail Deselect Voltage): M48T37Y: 4.2V VPDF 4.5V M48T37V: 2.7V VPFD 3.0V PACKAGING INCLUDES 44-LEAD SOIC SNAPHAT® Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION SNAPHAT which CONTAINS BATTERY CRYSTAL MICROPROCESSOR POWER-ON RESET (Valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT ACTIVE BATTERY BACKED-UP DESCRIPTION M48T37Y/37V TIMEKEEPER® 32Kb non-volatile static real time clock. monolithic chip available special package which provides highly integrated battery backedup memory real time clock solution. Table Signal Names
A0-A14 DQ0-DQ7 IRQ/FT October 1998 Address Input Data Input Output Interrupt Frequency Test Output (Open Drain) Power Fail Reset Output (Open Drain) Watchdog Input Chip Enable Output Enable Write Enable Supply Voltage Ground 1/20 SNAPHAT (SH) Battery/Crystal
Figure Logic Diagram
A0-A14 M48T37Y M48T37V DQ0-DQ7 IRQ/FT
Table Absolute Maximum Ratings
Symbol Parameter Ambient Operating Temperature TSTG TSLD(2) Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature seconds Input Output Voltages M48T37Y M48T37V Supply Voltage Output Current Power Dissipation M48T37Y M48T37V SNAPHAT SOIC Value -0.3 -0.3 -0.3 -0.3 Unit
Notes: Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods time affect reliability. Soldering temperature exceed 260°C seconds (total thermal budget exceed 150°C longer than seconds). CAUTION: Negative undershoots below -0.3 volts allowed while Battery Back-up mode. CAUTION: wave solder SOIC avoid damaging SNAPHAT sockets.
Figure SOIC Connections
DESCRIPTION (Cont'd) lead 330mil SOIC package provides sockets with gold-plated contacts both ends direct connection separate SNAPHAT housing containing battery crystal. unique design allows SNAPHAT battery package mounted SOIC package after completion surface mount process. Insertion SNAPHAT housing after reflow prevents potential battery crystal damage high temperatures required device surface-mounting. SNAPHAT housing keyed prevent reverse insertion. SOIC battery packages shipped separately plastic anti-static tubes Tape &Reel form. lead SOIC, battery/crystal package (i.e. SNAPHAT) part number "M4T28BR12SH1". Figure shows, static memory array roll oscil M48T37Y/37V integrated silicon chip. memory locations, provide user accessible BYTEWIDE clock information bytes with addresses 7FF1 7FF9h-7FFFh (located Table 11). clock locations contain century, year, month, date, day, hour, minute, second hour format. Corrections (leap year-compliant until year 2100), months made automatically.
Warning: Connected. 2/20
Figure Block Diagram
OSCILLATOR CLOCK CHAIN 32,768 CRYSTAL POWER BATTERY A0-A14 BiPORT SRAM ARRAY
LITHIUM CELL VOLTAGE SENSE SWITCHING CIRCUITRY VPFD
32,752 SRAM ARRAY
Table Operating Modes
Mode Deselect Write Read Read Deselect Deselect VPFD (min) 4.5V 5.5V (M48T37Y) 3.0V 3.6V (M48T37V) DQ0-DQ7 High DOUT High High High Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Notes: VIL; Battery Back-up Switchover Voltage. Table details.
Table Measurement Conditions
Input Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages 1.5V
DEVICE UNDER TEST
Figure Testing Load Circuit
Note that Output Hi-Z defined point where data longer driven.
Parameter Input Capacitance Input Output Capacitance
Test Condition VOUT
Notes: Effective capacitance measured with power supply Sampled only, 100% tested. Outputs deselected
Table Characteristics 70°C)
M48T37Y Symb Parameter Test Condition 4.5V 5.5V
M48T37V 3.0V 3.6V -0.3 Unit
Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) Supply Current (Standby) CMOS Input Voltage Input High Voltage Output Voltage (standard)
VOUT Outputs open 0.2V -0.3 2.1mA 10mA -1mA
Output Voltage (open drain) Output High Voltage
Notes: Outputs Deselected. Negative spikes allowed 10ns once Cycle.
Table Power Down/Up Trip Points Characteristics 70°C)
Symbol VPFD Parameter Power-fail Deselect Voltage (M48T37Y, Power-fail Deselect Voltage (M48T37V, 3.3V) Battery Back-up Switchover Voltage (5V) Battery Back-up Switchover Voltage (3.3V) Expected Data Retention Time (25°C) Grade Grade VBAT VPFD -100mV Unit YEARS
Notes: voltages referenced VSS. Using larger M4T32-BR12SH6 SNAPHAT (recommended industrial temperature grade device).
Table Power Down/Up Mode Characteristics 70°C)
Parameter VPFD (max) VPFD (min) Fall Time VPFD (min) Fall Time VPFD(min) VPFD (max) Rise Time VPFD (min) Rise Time VPFD (max) High
Notes: VPFD (max) VPFD (min) fall time less than result deselection/write protection occurring until after passes VPFD (min). VPFD (min) fall time less than cause corruption data. tREC (min) 20ms industrial temperature grade device.
Table Read Mode Characteristics 70°C)
M48T37Y Symbol Parameter 4.5V 5.5V tAVAV tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAXQX
M48T37V 3.0V 3.6V -100 Unit
Read Cycle Time Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable Output Transition Output Enable Output Transition Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition
Notes: 100pF (see Figure (see Figure
Figure Power Down/Up Mode Waveforms
VPFD (max) VPFD (min) tREC
HIGH-Z OUTPUTS VALID VALID
Figure Read Mode Waveforms
tAVAV A0-A14 tAVQV tELQV tELQX tGLQV tGLQX DQ0-DQ7 VALID
VALID tAXQX tEHQZ
Note: Write Enable High.
Figure Write Enable Controlled, Write Waveforms
tAVAV A0-A14 VALID tAVWH tAVEL tWLWH tAVWL tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
Figure Chip Enable Controlled, Write Waveforms
tAVAV A0-A14 VALID tAVEH tAVEL tAVWL tEHDX DQ0-DQ7 DATA INPUT tDVEH
Table Write Mode Characteristics 70°C)
M48T37Y Symbol Parameter 4.5V 5.5V tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ
M48T37V 3.0V 3.6V -100 Unit
Write Cycle Time Address Valid Write Enable Address Valid Chip Enable Write Enable Pulse Width Chip Enable Chip Enable High Write Enable High Address Transition Chip Enable High Address Transition Input Valid Write Enable High Input Valid Chip Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable Output Hi-Z Address Valid Write Enable High Address Valid Chip Enable High Write Enable High Output Transition
tAVWH tAVE1H tWHQX
Notes: (see Figure goes simultaneously with going low, outputs remain high impedance state.
DESCRIPTION (Cont'd) Byte 7FF8h clock control register. This byte controls user access clock information also stores clock calibration setting. Byte 7FF7h contains watchdog timer setting. watchdog timer redirects out-of-control microprocessor provides reset interrupt Byte 7FF2h-7FF5h reserved clock alarm programming. These bytes used alarm. This will generate active signal IRQ/FT when alarm bytes match date, hours, minutes seconds clock. eight clock bytes actual clock counters themselves; they memory locations consisting BiPORT® M48T37Y/37V includes clock control circuit which updates clock bytes with current information once second. information accessed user same manner other location static memory array. M48T37Y/37V also Power-fail Detect circuit. control circuitry constantly moni8/20
tors single supply tolerance condition. When tolerance, circuit writes protects SRAM, providing high degree data security midst unpredictable system operation brought VCC. falls below Battery Back-up Switchover Voltage (VSO), control circuitry connects battery which maintains data clock operation until valid power returns. READ MODE M48T37Y/37V Read Mode whenever Write Enable high Chip Enable low. unique address specified Address Inputs defines which 32,752 bytes data accessed. Valid data will available Data pins within Address Access time (tAVQV) after last address input signal stable, providing that Output Enable access times also satisfied. access times met, valid data will available after latter Chip Enable Access time (tELQV) Output Enable Access time (tGLQV).
Address 7FFFh 7FFEh 7FFDh 7FFCh 7FFBh 7FFAh 7FF9h 7FF8h 7FF7h 7FF6h 7FF5h 7FF4h 7FF3h 7FF2h 7FF1h 7FF0h RPT4 RPT3 RPT2 RPT1 BMB4 Years Date Data Year Month Date Hours Minutes Seconds Calibration BMB2 BMB1 BMB0 Function/Range Format Year Month Date Hour Minutes Seconds Control Watchdog Interrupts Alarm Date Alarm Hours Alarm Minutes Alarm Seconds Century Flags 01-31 00-23 00-59 00-59 00-99 00-99 01-12 01-31 01-07 00-23 00-59 00-59
Hours Minutes Seconds BMB3
Alarm Date Alarm Hours Alarm Minutes Alarm Seconds Years
Alarm Minutes Alarm Seconds 1000 Years
Keys: SIGN FREQUENCY TEST READ WRITE STOP Must Read only
Watchdog Steering Alarm Flag Battery Flag Watchdog Steering BMB0-BMB4 Watchdog Multiplier Bits RB0-RB1 Watchdog Resolution Bits Alarm Flag Enable Alarm Battery Back-up Mode Enable RPT1-RPT4 Alarm Repeat Mode Bits Watchdog Flag
READ MODE (Cont'd) state eight three-state Data signals controlled outputs activated before tAVQV, data lines will driven indeterminate state until tAVQV. Address Inputs changed while remain active, output data will remain valid Output Data Hold time (tAXQX) will indeterminate until next Address Access. WRITE MODE M48T37Y/37V Write Mode whenever low. start write referenced from latter occurring falling edge write terminated earlier rising edge addresses must held valid throughout cycle. must return high minimum
tEHAX from Chip Enable tWHAX from Write Enable prior initiation another read write cycle. Data-in must valid tDVWH prior write remain valid tWHDX afterward. should kept high during write cycles avoid contention; although, output been activated will disable outputs tWLQZ after falls. DATA RETENTION MODE With valid applied, M48T37Y/37V operates conventional BYTEWIDEstatic RAM. Should Supply Voltage decay, will automatically power-fail deselect, write protecting itself when falls within VPFD (max), VPFD (min) window. outputs become high impedance, inputs treated "don't care".
Note: power failure during write cycle corrupt data currently addressed location, does jeopardize rest RAM's content. voltages below VPFD(min), user assured memory will write protected state, provided fall time less than M48T37Y/37V respond transient noise spikes that reach into deselect window during time device sampling VCC. Therefore, decoupling power supply lines recommended. When drops below VSO, control circuit switches power internal battery which preserves data powers clock. internal button cell will maintain data M48T37Y/37V accumulated period least years room temperature when less than VSO. system power returns rises above VSO, battery disconnected, power supply switched external VCC. Normal operation resume tREC after reaches VPFD(max). more information Battery Storage Life refer Application Note AN1012. POWER-ON RESET M48T37Y/37V continuously monitors VCC. When falls power fail detect trip point, pulls (open drain) remains power-up 40ms 200ms after passes VPFD. valid conditions. open drain output appropriate resistor should chosen control rise time. PROGRAMMABLE INTERRUPTS M48T37Y/37V provides programmable interrupts; alarm watchdog. When interrupt condition occurs, M48T37Y/37V sets appropriate flag flag register 7FF0h. interrupt enable bits (AFE ABE) 7FF6h Watchdog Steering (WDS) 7FF7h allow interrupt activate IRQ/FT pin. interrupt flags IRQ/FT output cleared read flags register. interrupt condition reset will occur unless addresses stable flag location least 15ns while device read mode shown Figure IRQ/FT open drain output requires pull-up resistor (10k recommended). remains high impedance state unless interrupt occurs frequency test mode enabled. CLOCK OPERATIONS Reading Clock Updates TIMEKEEPER registers should halted before clock data read prevent reading data transition. Because BiPORT TIMEKEEPER cells array only data registers, actual clock counters, updating registers halted without disturbing clock itself. Updating halted when written READ bit, Control Register 7FF8h. long remains that position, updating halted. After halt issued, registers reflect count; that day, date, time that were current moment halt command issued. TIMEKEEPER registers updated simultaneously. halt will interrupt update progress. Updating will resume within second after reset `0'.
Figure Clock Calibration
Setting Clock Control Register 7FF8h WRITE bit. Setting WRITE `1', like READ bit, halts updates TIMEKEEPER registers. user then load them with correct day, date, time data hour format (see Table 11). Resetting WRITE then transfers values time registers 7FF9h-7FFFh actual TIMEKEEPER counters allows normal operation resume. After WRITE reset, next clock update will occur approximately second. Note: Upon power-up following power failure, both WRITE READ will reset '0'. Stopping Starting Oscillator oscillator stopped time. device going spend significant amount time shelf, oscillator turned minimize current drain battery. STOP seconds register. Setting stops oscillator. M48T37Y/37V shipped from with STOP `1'. When reset `0', M48T37Y/37V oscillator starts within second. Note: necessary WRITE when setting resetting FREQUENCY TEST (FT) STOP (ST). Calibrating Clock M48T37Y/37V driven quartz controlled oscillator with nominal frequency 32,768 devices tested exceed (parts million) oscillator frequency error 25°C, which equates about 1.53 minutes month. With calibration bits properly set, accuracy each M48T37Y/37V improves better than 25°C. oscillation rate crystal changes with temperature (see Figure 10). Most clock chips compensate crystal frequency temperature shift error with cumbersome trim capacitors. M48T37Y/37V design, however, employs periodic counter correction. calibration circuit adds subtracts counts from oscillator divider circuit divide stage, shown Figure number times pulses blanked (subtracted, negative calibration) split (added, positive calibration) depends upon value loaded into five Calibration byte found Control Register. Adding counts speeds clock subtracting counts slows clock down. Calibration byte occupies five lower order bits (D4-D0) Control Register 7FF8h. These bits represent value between binary form. Sign bit; indicates positive calibration, indicates negative calibration. Calibration occurs within minute cycle. first minutes cycle may, once minute, have second either shortened lengthened oscillator cycles. binary loaded into register, only first minutes minute cycle will modified; binary loaded, first will affected, Therefore, each calibration step effect adding subtracting oscillator cycles every 125, 829, minutes seconds/minute 32,768 cycles/second) actual oscillator cycles, that +4.068 -2.034 adjustment calibration step calibration register. Assuming that oscillator fact running exactly 32,768 each increments Calibration byte would represent +10.7 -5.35 seconds month which corresponds total range +5.5 -2.75 minutes month. methods available ascertaining much calibration given M48T37Y/37V require. first involves simply setting clock, letting month comparing known accurate reference (like broadcasts). While that seem crude, allows designer give user ability calibrate clock environment require, even after final product packaged non-user serviceable enclosure. designer provide simple utility that accesses Calibration byte. second approach better suited manufacturing environment, involves IRQ/FT pin. will toggle 512Hz when Stop (ST, 7FF9h) `0', Frequency Test (FT, 7FFCh) `1', Alarm Flag Enable (AFE, 7FF6h) `0', Watchdog Steering (WDS, 7FF7h) Watchdog Register reset (7FF7h=0). deviation from indicates degree direction oscillator frequency shift test temperature. example, reading 512.01024 would indicate oscillator frequency error, requiring -10(WR001010) loaded into Calibration Byte correction. Note that setting changing Calibration Byte does affect Frequency test output frequency. IRQ/FT open drain output which requires pull-up resistor proper operation. 500-10k resistor recommended order control rise time. cleared power-up.
Figure Crystal Accuracy Across Temperature
Frequency (ppm) -100 -120 -140 -160 -0.038
SETTING ALARM CLOCK REGISTERS 7FF5h-7FF2h contain alarm settings. alarm configured predetermined time specific month repeat every day, hour, minute, second. also programmed while M48T37Y/37V battery back-up mode operation serve system wake-up call. RPT1-RPT4 alarm repeat mode operation. Table shows possible configurations. Codes listed table default once second mode quickly alert user incorrect alarm setting. When clock information matches alarm clock settings based match criteria defined
RPT1-RPT4, set. also set, alarm condition activates IRQ/FT pin. alarm flag IRQ/FT output cleared read Flags register shown Figure IRQ/FT also activated battery back-up mode. IRQ/FT will alarm occurs both Alarm Battery Back-up Mode Enable (ABE) set. bits reset during power-up, therefore alarm generated during power-up will only user read Flag Register system boot-up determine alarm generated while M48T37Y/37V deselect mode during power-up. Figure illustrates back-up mode alarm timing.
WATCHDOG TIMER watchdog timer used detect out-of-control microprocessor. user programs watchdog timer setting desired amount time-out into eight Watchdog Register, address 7FF7h. five bits (BMB4-BMB0) store binary multiplier lower order bits (RB1-RB0) select resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, 11=4 seconds. amount time-out then determined multiplication five multiplier value with resolution. (For example: writing 00001110 Watchdog Register seconds). processor does reset timer within specified period, M48T37Y/37V sets Watchdog Flag (WDF) generates watchdog interrupt microprocessor reset. most significant Watchdog Register Watchdog Steering Bit. When `0', watchdog will activate IRQ/FT when timedout. When `1', watchdog will output negative pulse duration 40ms 200ms. Watchdog register will reset Watchdog time-out when `1'. watchdog timer resets when microprocessor performs re-write Watchdog Register edge transition, (low high high low) occurs. time-out period then starts over. watchdog timer disabled writing value 00000000 eight bits Watchdog Register. Should watchdog timer time out, value needs written Watchdog Register inorder clear IRQ/FT pin. watchdog function automatically disabled upon power-up Watchdog Register cleared. watchdog function output IRQ/FT frequency test function activated, watchdog function prevails frequency test function denied. contains pull-down resistor which greater than 100k, therefore left unconnected used. Table Alarm Repeat Mode
RPT4 RPT3 RPT2 RPT1 Alarm Activated Once Second Once Minute Once Hour Once
Figure Interrupt Reset Waveforms
ADDRESS 7FF0h 15ns
BATTERY FLAG M48T37Y/37V automatically performs periodic battery voltage monitoring upon power-up factory-programmed time intervals hours. Battery Flag (BL), Flags Register 7FF0h, will asserted high internal SNAPHAT battery found less than approximately 2.5V. flag will remain active until completion battery replacement subsequent battery monitoring tests, either during next power-up sequence next scheduled 24-hour interval. battery generated during power-up sequence, this indicates that battery voltage below 2.5V (approx.), which insufficient maintain data integrity. Data should considered suspect verified correct. fresh battery should installed. battery indication generated during 24-hour interval check, this indicates that battery near life. However, data been compromised fact that nominal supplied. order insure data integrity during subsequent periods battery back-up mode, recommended that battery replaced. Note: Battery monitoring useful technique only when performed periodically. M48T37Y/37V only monitors battery when nominal applied device. Thus applications which require extensive durations battery back-up mode should powered-up periodically least once every months) order this technique beneficial. Additionally, battery indicated, data integrity should verified upon power-up checksum other technique. POWER-ON DEFAULTS Upon application power device, following register bits state: WDS; BMB0BMB4; RB0-RB1; AFE; ABE;
Figure Back-up Mode Alarm Waveforms
VPFD (max) VPFD (min)
IRQ/FT HIGH-Z HIGH-Z
POWER SUPPLY DECOUPLING UNDERSHOOT PROTECTION transients, including those produced output switching, produce voltage fluctuations, resulting spikes bus. These transients reduced capacitors used store energy, which stabilizes bus. energy stored bypass capacitors will released going spikes generated energy will absorbed when overshoots occur. ceramic bypass capacitor value 0.1µF shown Figure recommended order provide needed filtering. addition transients that caused normal SRAM operation, power cycling generate negative voltage spikes that drive values below much Volt. These negative spikes cause data corruption SRAM while battery backup mode. protect from these voltage spikes, recommended connect schottky diode from (cathode connected VCC, anode VSS). Schottky diode 1N5817 recommended through hole MBRS120T3 recommended surface mount. Figure Supply Voltage Protection
ORDERING INFORMATION SCHEME Example: M48T37Y
Supply Voltage Write Protect Voltage 4.5V 5.5V VPFD 4.2V 4.5V 3.0V 3.6V VPFD 2.7V 3.0V
Speed 70ns 100ns
Temp. Range 70°C 85°C
Shipping Method SOIC blank Tubes Tape Reel
Note: SOIC package (SOH44) requires battery/crystal package (SNAPHAT) which ordered separately under part number "M4TXX-BR12SH1" plastic tube "M4TXX-BR12SH1TR" Tape Reel form. Caution: place SNAPHAT battery/crystal package "M4TXX-BR12SH1" conductive foam since this will drain lithium button-cell battery.
list available options (Package, etc.) further information aspect this device, please contact STMicroelectronics Sales Office nearest you.
SOH44 lead Plastic Small Outline, battery SNAPHAT
Symb 0.81 0.05 2.34 0.36 0.15 17.71 8.23 3.20 11.51 0.41 0.10 3.05 0.36 2.69 0.46 0.32 18.49 8.89 3.61 12.70 1.27 0.032 0.002 0.092 0.014 0.006 0.697 0.324 0.126 0.453 0.016 0.004 inches 0.120 0.014 0.106 0.018 0.012 0.728 0.350 0.142 0.500 0.050
M4T28-BR12SH SNAPHAT Housing lead Plastic Small Outline
Symb 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 inches 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090
M4T32-BR12SH SNAPHAT Housing lead Plastic Small Outline
Symb 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 inches 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics 1998 STMicroelectronics Rights Reserved TIMEKEEPER SNAPHAT registered trademarks STMicroelectronics
BiPORT trademark STMicroelectronics
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