M48T02 M48T12 M48T02 M48T12
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M48T02 - M48T02
M48T12 - M48T12
M48T02 - M48T02
M48T12 - M48T12
M48T02 M48T12
Kbit (2Kb TIMEKEEPER® SRAM
INTEGRATED ULTRA POWER SRAM, REAL TIME CLOCK POWER-FAIL CONTROL CIRCUIT BYTEWIDERAM-LIKE CLOCK ACCESS CODED YEAR, MONTH, DAY, DATE, HOURS, MINUTES SECONDS TYPICAL CLOCK ACCURACY MINUTE MONTH, 25°C SOFTWARE CONTROLLED CLOCK CALIBRATION HIGH ACCURACY APPLICATIONS AUTOMATIC POWER-FAIL CHIP DESELECT WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD Power-fail Deselect Voltage): M48T02: 4.5V VPFD 4.75V M48T12: 4.2V VPFD 4.5V Figure Logic Diagram
PCDIP24 (PC) Battery/Crystal CAPHAT
SELF-CONTAINED BATTERY CRYSTAL CAPHAT PACKAGE FUNCTION COMPATIBLE with JEDEC STANDARD SRAMVCC
DESCRIPTION M48T02/12 TIMEKEEPER® non-volatile static real time clock which functional compatible with DS1642. special 600mil CAPHATpackage houses M48T02/12 silicon with quartz crystal long life lithium button cell form highly integrated battery backed-up memory real time clock solution. Table Signal NameA0-A10 DQ0-DQ7 July 2000 Address Inputs Data Inputs Outputs Chip Enable Output Enable Write Enable Supply Voltage Ground
A0-A10
DQ0-DQ7
M48T02 M48T12
AI01027
1/15
M48T02, M48T12
Table Absolute Maximum Ratings
Symbol TSLD
Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature seconds Input Output Voltages Supply Voltage Output Current Power Dissipation
Value -0.3 -0.3
Unit
Note: Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods time affect reliability. Soldering temperature exceed 260°C seconds (total thermal budget exceed 150°C longer than seconds).
CAUTION: Negative undershoots below -0.3V allowed while Battery Back-up mode.
Table Operating ModeMode Deselect Write Read Read Deselect Deselect VPFD (min) 4.75V 5.5V 4.5V 5.5V DQ0-DQ7 High DOUT High High High Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Note: VIL; Battery Back-up Swit chover Voltage.
Figure Connection
M48T02 M48T12
AI01028
M48T02/12 button cell sufficient capacity storage life maintain data clock functionality accumulated time period least years absence power over operating temperature range. M48T02/12 non-volatile function equivalent JEDEC standard SRAM. also easily fits into many ROM, EPROM, EEPROM sockets, providing non-volatility PROMs without requirement special write timing limitations number writes that performed. Figure shows, static memory array quartz controlled clock oscillator M48T02/12 integrated silicon chip. circuits interconnected upper eight memory locations provide user accessible BYTEWIDE clock information bytes with addresses 7F8h-7FFh. clock locations contain year, month, date, day, hour, minute, second hour format. Corrections (leap year), months made automatically.
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M48T02, M48T12
Figure Block Diagram
OSCILLATOR CLOCK CHAIN 32,768 CRYSTAL POWER
BiPORT SRAM ARRAY
A0-A10
LITHIUM CELL VOLTAGE SENSE SWITCHING CIRCUITRY
2040 SRAM ARRAY VPFD
DQ0-DQ7
AI01329
Byte 7F8h clock control register. This byte controls user access clock information also stores clock calibration setting. eight clock bytes actual clock counters themselves; they memory locations consisting BiPORTread/write memory cells. M48T02/12 includes clock control circuit which updates clock bytes with current information once second. information accessed user same manner other location static memory array. M48T02/12 also Power-fail Detect circuit. control circuitry constantly monitors single supply tolerance condition. When tolerance, circuit write protects SRAM, providing high degree data security midst unpredic system operation brought VCC. falls below approximately control circuitry connects battery which maintains data clock operation until valid power returns.
Table Measurement ConditionInput Rise Fall Times Input Pulse Voltages Input Output Timing Ref. Voltages 1.5V
Note that Output Hi-Z defined point where data longer driven.
Figure Testing Load Circuit
1.8k DEVICE UNDER TEST
100pF
includes capacitance
AI01019
3/15
M48T02, M48T12
Table Capacitance 1MHz)
Symbol Parameter Input Capacitance Input Output Capacitance Test Condit VOUT Unit
Note: Effective capacitance measured with power supply Outputs deselected.
Table Characteristics 4.75V 5.5V 4.5V 5.5V)
Symbol ICC1 ICC2 Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) Supply Current (Standby) CMOS Input Voltage Input High Voltage Output Voltage Output High Voltage 2.1mA -1mA Test Conditio VOUT Outputs open 0.2V -0.3 Unit
Note: Outputs deselected. Measured with Control Bits follows: '1'; '0'.
Table Power Down/Up Trip Points Characteristics
Symbol VPFD Parameter M48T02 Power-fail Deselect Voltage M48T12 Battery Back-up Switchover Voltage Expected Data Retention Time YEARS 4.75 Unit
Note: voltages referenced VSS. 25°C.
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M48T02, M48T12
Table Power Down/Up Characteristics
Symbol tREC Parameter before Power Down VPFD (max) VPFD (min) Fall Time VPFD (min) Fall Time VPFD (min) VPFD (max) Rise Time VPFD (min) Rise Time before Power Unit
Note: VPFD (max) VPFD (min) fall time less than result deselection/write protection occurring until 50µs after passes VPFD (min). VPFD (min) fall time less than cause corruption data.
Figure Power Down/Up Mode Waveform
VPFD (max) VPFD (min) INPUTS
RECOGNIZED
DON'T CARE
tREC
NOTE RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI00606
Note: Inputs recognized this time. Caution should taken keep high rises past VPFD (min). Some systems perform inadvertent write cycles after rises above VPFD (min) before normal system operations begin. Even though power reset being applied processor, reset condition occur until after system clock running.
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M48T02, M48T12
Table Read Mode Characteristics 4.75V 5.5V 4.5V 5.5V)
M48T02/M48T12 Symbol Parameter tAVAV tAVQV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tAXQX Read Cycle Time Address Valid Output Valid Chip Enable Output Valid Output Enable Output Valid Chip Enable Output Transition Output Enable Output Transition Chip Enable High Output Hi-Z Output Enable High Output Hi-Z Address Transition Output Transition -150 -200 Unit
Figure Read Mode Waveforms.
tAVAV A0-A10 tAVQV tELQV tELQX tGLQV tGLQX DQ0-DQ7 VALID
AI01330
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable High.
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M48T02, M48T12
Table Write Mode Characteristics 4.75V 5.5V 4.5V 5.5V)
M48T02/M48T12 Symbol Parameter tAVAV tAVWL AVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ tAVWH tAVEH WHQX Write Cycle Time Address Valid Write Enable Address Valid Chip Enable Write Enable Pulse Width Chip Enable Chip Enable High Write Enable High Address Transition Chip Enable High Address Transition Input Valid Write Enable High Input Valid Chip Enable High Write Enable High Input Transition Chip Enable High Input Transition Write Enable Output Hi-Z Address Valid Write Enable High Address Valid Chip Enable High Write Enable High Output Transition -150 -200 Unit
READ MODE M48T02/12 Read Mode whenever (Write Enable) high (Chip Enable) low. device architecture allows ripple-through access data from eight 16,384 locations static storage array. Thus, unique address specified Address Inputs defines which 2,048 bytes data accessed. Valid data will available Data pins within Address Access time (tAVQV) after last address input signal stable, providing that access times also satisfied. access times met, valid data will available after latter Chip Enable Access time (tELQV) Output Enable Access time GLQV). state eight three-state Data signals controlled outputs activated before tAVQV, data lines will driven indeterminate state until tAVQV. Address
puts changed while remain active, output data will remain valid Output Data Hold time (tAXQX) will indeterminate until next Address Access. WRITE MODE M48T02/12 Write Mode whenever active. start write referenced from latter occurring falling edge write terminated earlier rising edge addresses must held valid throughout cycle. must return high minimum tEHAX from Chip Enable tWHAX from Write Enable prior initiation another read write cycle. Data-in must valid tDVWH prior write remain valid WHDX afterward. should kept high during write cycles avoid contention; although, output been activated will disable outputs tWLQZ after falls.
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M48T02, M48T12
Figure Write Enable Controlled, Write Waveform
tAVAV A0-A10 VALID tAVWH tAVEL tWLWH tAVWL tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01331
tWHAX
tWHQX
Figure Chip Enable Controlled, Write Waveform
tAVAV A0-A10 VALID tAVEH tAVEL tAVWL tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01332B
tELEH
tEHAX
8/15
M48T02, M48T12
DATA RETENTION MODE With valid applied, M48T02/12 operates conventional BYTEWIDE static RAM. Should supply voltage decay, will automatically power-fail deselect, write protecting itself when falls within VPFD (max), VPFD (min) window. outputs become high impedance, inputs treated "don't care." Note: power failure during write cycle corrupt data currently addressed location, does jeopardize rest RAM's content. voltages below VPFD (min), user assured memory will write protected state, provided fall time less than M48T02/12 respond transient noise spikes that reach into deselect window during time device sampling VCC. Therefore, decoupling power supply lines recommended. power switching circuit connects external disconnects battery when rises above VSO. rises, battery voltage checked. voltage low, internal Battery (BOK) flag will set. flag checked after power flag set, first write attempted will blocked. flag automatically cleared after first write, normal operation resumes. Figure illustrates check routine could structured. more information Battery Storage Life refer Application Note AN1012. CLOCK OPERATIONS Reading Clock Updates TIMEKEEPER registers should halted before clock data read prevent reading data transition. Because BiPORT TIMEKEEPER cells array only data registers, actual clock counters, updating registers halted without disturbing clock itself. Updating halted when written READ bit, seventh control register. long remains that position, updating halted. After halt issued, registers reflect count; that day, date, time that were current moment halt command issued. TIMEKEEPER registers updated simultaneously. halt will interrupt update progress. Updating within second after read reset '0'. Figure Checking Flag StatuPOWER-UP
READ DATA ADDRESS
WRITE DATA COMPLEMENT BACK SAME ADDRESS
READ DATA SAME ADDRESS AGAIN
DATA COMPLEMENT OFFIRST READ? (BATTERY
(BATTERY LOW)
NOTIFY SYSTEM BATTERY (DATA CORRUPTED)
WRITE ORIGINAL DATA BACK SAME ADDRESS
CONTINUE
AI00607
Setting Clock eighth control register WRITE bit. Setting WRITE '1', like READ bit, halts updates TIMEKEEPER registers. user then load them with correct day, date, time data hour format (see Table 10). Resetting WRITE then transfers values time registers (7F9h7FFh) actual TIMEKEEPER counters allows normal operation resume. bits marked Table must written allow normal TIMEKEEPER operation. Application Note AN923 "TIMEKEEPER rolling into 21st century" more information Century Rollover.
9/15
M48T02, M48T12
Stopping Starting Oscillator oscillator stopped time. device going spend significant amount time shelf, oscillator turned minimize current drain battery. STOP seconds register. Setting stops oscillator. M48T02/12 shipped from STMicroelectronics with STOP '1'. When reset '0', M48T02/12 oscillator starts within second. Calibrating Clock M48T02/12 driven quartz controlled oscillator with nominal frequency 32,768Hz. typical M48T02/12 accurate within minute month 25°C without calibration. devices tested exceed (parts million) oscillator frequency error 25°C, which equates about ±1.53 minutes month. oscillation rate crystal changes with temperature (see Figure 10). Most clock chips compensate crystal frequency temperature shift error with cumbersome trim capacitors. M48T02/12 design, however, employs periodic counter correction. calibration circuit adds subtracts counts from oscillator divider circuit divide stage, shown Figure number times pulses blanked (subtracted, negative calibration) split (added, positive calibration) depends upon value loaded into five Calibration byte found Control Register. Adding counts speeds clock subtracting counts slows clock down. Table Register
Data Address 7FFh 7FEh 7FDh 7FCh 7FBh 7FAh 7F9h 7F8h
Keys:
Calibration byte occupies five lower order bits Control register. This byte represent value between binary form. sixth sign bit; indicates positive calibration, indicates negative calibration. Calibration occurs within minute cycle. first minutes cycle may, once minute, have second either shortened lengthened oscillator cycles. binary loaded into register, only first minutes minute cycle will modified; binary loaded, first will affected, Therefore, each calibration step effect adding subtracting oscillator cycles every 125,829,120 actual oscillator cycles, that +4.068 -2.034 adjustment calibration step calibration register. Assuming that oscillator fact running exactly 32,768Hz, each increments Calibration byte would represent +10.7 -5.35 seconds month which corresponds total range +5.5 -2.75 minutes month. methods available ascertaining much calibration given M48T02/12 require. first involves simply setting clock, letting month comparing known accurate reference (like broadcasts). While that seem crude, allows designer give user ability calibrate clock environment require, even after final product packaged non-user serviceable enclosure. designer provide simple utility that accesses Calibration byte.
Year
Function/Rang Format Year Month Date 00-99 01-12 01-31 01-07 00-23 00-59 00-59
Years
Month Date Hours Minutes Seconds Calibration
WRITE STOP Must
Date
Hour Minutes Seconds Control
Hours Minutes Seconds
SIGN FREQUENCY TEST READ
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M48T02, M48T12
Figure Crystal Accuracy Across Temperature
-0.038
-100
AI02124
Figure Clock Calibration
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
11/15
M48T02, M48T12
second approach better suited manufacturing environment, involves some test equipment. When Frequency Test (FT) bit, seventh-most significant Register, '1', oscillator running 32,768Hz, (DQ0) Seconds Register will toggle 512Hz. deviation from 512Hz indicates degree direction oscillator frequency shift test temperature. example, reading 512.01024Hz would indicate oscillator frequency error, requiring -10(WR001010) loaded into Calibration Byte correction. Note that setting changing Calibration Byte does affect Frequency test output frequency. device must selected address 7F9h must held constant when reading 512Hz DQ0. must using same method used clock, using Write bit. Seconds Register monitored holding M48T02/12 extended read Seconds Register, without having Read set. MUST reset normal clock operations resume. more information calibration, Application Note AN924 "TIMEKEEPER Calibration". POWER SUPPLY DECOUPLING UNDERSHOOT PROTECTION transients, including those produced output switching, produce voltage fluctuations, resulting spikes bus. These transients reduced capacitors used store energy, which stabilizes bus. energy stored bypass capacitors will released going spikes generated energy will absorbed when overshoots occur. bypass capacitor value 0.1µF shown Figure recommended order provide needed filtering. addition transients that caused normal SRAM operation, power cycling generate negative voltage spikes that drive values below much Volt. These negative spikes cause data corruption SRAM while battery backup mode. protect from these voltage spikes, recommended connect schottky diode from (cathode connected VCC, anode VSS). Schottky diode 1N5817 recommended through hole MBRS120T3 recommended surface mount. Figure Supply Voltage Protection
0.1µF
DEVICE
AI02169
12/15
M48T02, M48T12
Table Ordering Information Scheme
Example: Device Type M48T Supply Voltage Write Protect Voltage 4.75V 5.5V; 4.5V 4.75V 4.5V 5.5V; VPFD 4.2V 4.5V Speed 70ns -150 150ns -200 200ns Package PCDIP24 Temperature Range M48T02
list available options (Speed, Package, etc.) further information aspect this device, please contact Sales Office nearest you.
Table Revision History
Date 07/13/00 tREC change (Table Revision Detail
13/15
M48T02, M48T12
Table PCDIP24 Plastic DIP, battery CAPHAT, Package Mechanical Data
Symb 8.89 0.38 8.38 0.38 1.14 0.20 34.29 17.83 2.29 25.15 15.24 3.05 9.65 0.76 8.89 1.78 0.31 34.80 18.34 2.79 30.73 16.00 3.81 0.350 0.015 0.330 0.015 0.045 0.008 1.350 0.702 0.090 0.990 0.600 0.120 0.380 0.030 0.350 0.021 0.070 0.012 1.370 0.722 0.110 1.210 0.630 0.150 inche
Figure PCDIP24 Plastic DIP, battery CAPHAT, Package Outline
PCDIP
Drawing scale.
14/15
M48T02, M48T12
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics 2000 STMicroelectronics Rights Reserved other names property their respective owners. STMicroelectronics GROUP COMPANIES Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom U.S.A http://w ww.st.com
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