M44C260 M48C260
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M44C260/M48C260
MARC4 4-bit Microcontroller
M44C260 M48C260 members TEMIC family 4-bit single chip microcontrollers. M48C260 user programmable version M44C260. contains EEPROM program memory instead ROM. Both microcontroller types contain RAM, EEPROM data memory, parallel ports, timer with watchdog function, 8/16-bit multifunction timer/counter on-chip clock generation.
4-bit HARVARD architecture instruction cycle 8-bit application program memory 4-bit 8-bit EEPROM
Benefits
power consumption Power down mode supply voltage Self test functions High level programming language qFORTH User programmable with application program
bidirectional I/O's hard software interrupt levels 8-bit multifunction timer/counter
Interval timer with watchdog on-chip oscillator
NRST OSCIN OSCOUT
Reset
Test Sleep
Clock
EEPROM EEPROM
Timer Watchdog Intervall timer
Timer Timer
MARC4 4-bit core
Timer
Interrupt inputs
Input Port
INT6 Port Port Port Port IP43
9038
IP40
Figure Block diagram
TELEFUNKEN Semiconductors Rev. 17-Jun-96
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Preliminary Information
M44C260/M48C260
BP02 BP03
BP01
BP00 BP33 BP32 BP31 BP02 BP03 NRST BP20 BP10 BP11 BP01 BP00 BP31 BP30
M44C260 M48C260
BP30 IP40-INT6 IP41-TA IP42-TB IP43 BP13 BP12
9039
M44C260
IP40 INT6- IP41 BP13 BP12
NRST BP20
BP21 BP22 BP23
BP10 BP11
Figure connections SSO28-FN Table description
Figure connections SSO20
BP00 BP03 BP10 BP13 BP20 BP23 BP30 BP33 IP40-INT6 IP41-TA IP42-TB IP43 OSCIN OSCOUT NRST Power supply voltage +2.4 +6.2 Circuit ground bidirectional lines Port bidirectional lines Port bidirectional lines Port bidirectional lines Port with alternate interrupt function. negative transition BP30/BP31 requests INT2-, BP32/BP33 INT3-interrupt corresponding interrupt-mask set. Input port line/interrupt input negative transition this input requests INT6 interrupt mask set. Timer/counter I/O/Input Port line This line used programmable counter Port input. Timer/counter I/O/input Port line This line used programmable counter Port input. Input Port line EEPROM write protect input, logic this input protects EEPROM rows Oscillator input (32-kHz crystal). Oscillator output (32-kHz crystal). Reset input/output, logic this resets device. internal watchdog reset indicated level this pin. External system clock I/O. This used input provide with external clock output internal system clock. Testmode input. This input used control test modes function pin.
Name
Function
ports have CMOS output buffers. input they available with pull-up pull-down resistors. Please ordering information.
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Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
Contents
MARC4 Architecture General Description Components MARC4 Core 1.2.1 Program Memory (ROM EEPROM) 1.2.2 Data Memory (RAM) 1.2.3 Registers 1.2.4 1.2.5 Instruction Cycles 1.2.6 1.2.7 Interrupt Structure Software Interrupts Hardware Interrupts Reset Clock Generation 1.4.1 Clock Status/Control Register (CSC) 1.4.2 Signal Power Down Modes Peripheral Modules Addressing Peripherals 2.1.1 Input Port 2.1.2 Bidirectional Ports 2.1.3 External Interrupt Inputs Timer 2.2.1 Timer Control Register 2.2.2 Watchdog Control Register Timer 2.3.1 Timer Status/Control Register (T2SC) 2.3.2 Timer Subport (T2SUB) 2.3.3 Timer Reload Register 2.3.4 Timer Capture Register 2.3.5 Timer Mode Register (TAM1) 2.3.6 Timer Mode Register (TAM2) 2.3.7 Timer Mode Register (TBM1) 2.3.8 Timer Mode Register (TBM2) 2.3.9 Timer Prescaler Control Register (T2PC) 2.3.10 Timer Interrupt Control Register (T2IC) 2.3.11 Timer (TA/TB) EEPROM 2.4.1 EEPROM SubPort (ESUB) 2.4.2 EEPROM Mode/Status Register (EMS)
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Preliminary Information
M44C260/M48C260
Contents (continued)
Appendix Emulation Programming EEPROM Program Memory MARC4 Instruction 3.3.1 MARC4 Instruction Overview 3.3.2 qFORTH Language Overview qFORTH Language -Quick Reference Guide 3.4.1 Arithmetic/Logical 3.4.2 Comparisons 3.4.3 Control Structures 3.4.4 Stack Operations 3.4.5 Memory Operations 3.4.6 Predefined Structures 3.4.7 Assembler Mnemonics Electrical Characteristics Absolute Maximum Ratings Operating Characteristics Characteristics Schmitt-Trigger Inputs Layout Package Information Standard Design M48C260 Ordering Information M44C260
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Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
MARC4 Architecture
General Description
Reset
Reset Clock
System clock
Sleep
MARC4 microcontroller consists advanced stack based 4-bit core on-chip peripherals. based HARVARD architecture with physically separate program memory (ROM EEPROM) data memory (RAM). Three independent buses instruction bus, memory used parallel communication between program memory, peripherals. This enhances program execution speed allowing both instruction prefetching, simultaneous communication on-chip peripheral circuitry. integrated powerful interrupt controller with eight prioritized interrupt levels, supports fast processing hardware events. MARC4 designed high level programming language qFORTH. core contains both FORTH stacks, expression stack return stack. This architecture allows high level language programming without loss efficiency code density.
Components MARC4 Core
core contains program memory, RAM, ALU, program counter, address register, instruction decoder
TELEFUNKEN Semiconductors Rev. 17-Jun-96
MARC4 CORE
Program memory
4-bit
Instruction
Instruction decoder Interrupt controller
Memory
On-chip peripheral modules
Figure MARC4 core
8973
interrupt controller. following sections describe each these parts.
1.2.1
Program Memory (ROM EEPROM)
mask programmed with application program during fabrication microcontroller. EEPROM programmed customer using special programming device (see chapter "Progamming EEPROM Program Memory"). program memory addressed 12-bit wide program counter, thus limiting program size maximum Kbytes. M44C260 contains additional Kbyte test software. program memory starts with byte segment (zero page) which contains predefined start addresses interrupt service routines special subroutines accessible with single byte instructions (SCALL). corresponding memory shown figure 4.Look-up tables constants also held program memory accessed MARC4's built-in TABLE instruction.
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Preliminary Information
M44C260/M48C260
FFFh
Program memory
8-bit)
1F8h 1F0h 1E8h 1E0h
1E0h 1C0h
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
SCALL addresses
180h
Zero page
140h 100h 0C0h 080h 040h
1FFh 000h
Self test bank (1K) only M44C260
3FFh
Zero page
000h
020h 018h 010h 008h 000h
1.2.2
Data Memory (RAM)
MARC4 contains 4-bit wide static random access memory (RAM). used expression stack, return stack data memory variables arrays. addressed four 8-bit wide address registers
Expression Stack
4-bit wide expression stack addressed with expression stack pointer (SP). arithmetic, memory reference operations take their operands from, return their result expression stack. MARC4 performs operations with stack items (TOS TOS-1). register contains
Global variables
address register:
TOS-1
Expression stack
Return stack
Return stack Global variables
Figure
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Preliminary Information
008h 000h
$RESET $AUTOSLEEP
8974
Figure Program memory
element expression stack works like accumulator. This stack also used passing parameters between subroutines, scratchpad area temporary storage data.
Return Stack
12-bit wide return stack addressed return stack pointer (RP). used storing return addresses subroutines, interrupt routines keeping loop index counts. return stack also used temporary storage area. MARC4 instruction supports exchange data between elements expression stack return stack. stacks within have user definable location maximum depth.
(256 4-bit) Autosleep
Expression stack
TOS-1 TOS-2 4-bit
12-bit
8975
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
1.2.3 Registers
MARC4 controller programmable registers condition code register. They shown figure
Program Counter (PC)
program counter (PC) 12-bit register that contains address next instruction fetched from program memory. Instructions currently being executed decoded instruction decoder determine internal micro operations. linear code calls branches) program counter incremented with every instruction cycle. branch-, call-, return-instruction interrupt executed program counter loaded with address. program counter also used with TABLE instruction fetch 8-bit wide constants. Address Register addressed with four 8-bit wide address registers: These registers allow access nibbles.
Expression Stack Pointer (SP)
stack pointer (SP) contains address next-totop 4-bit item (TOS-1) expression stack. pointer automatically pre-incremented nibble moved onto stack, post-decremented nibble TELEFUNKEN Semiconductors Rev. 17-Jun-96
Program counter Return stack pointer Expression stack pointer address register address register stack register Condition code register
Interrupt enable Branch Unused Carry borrow
8976
Figure Programming model
removed from stack. Every post-decrement operation moves item (TOS-1) register before decremented. After reset, stack pointer initialized with allocate start address expression stack area.
Return Stack Pointer (RP)
return stack pointer points element 12-bit wide return stack. pointer automatically preincrements element moved onto stack post-decrements element removed from stack. return stack pointer increments decrements steps This means that every time 12-bit element stacked, 4-bit location left unwritten. This location used qFORTH compiler allocate 4-bit variables. After reset return stack pointer initialized with
Address Register
registers used address 4-bit item RAM. fetch operation moves addressed nibble onto TOS. store operation moves addressed location. using either pre-increment post-decrement addressing mode arrays compared, filled moved.
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Preliminary Information
M44C260/M48C260
Stack (TOS)
stack register accumulator MARC4. arithmetic/logic, memory reference operations this register. register gets data from ALU, program memory, bus. Branch branch flag controls conditional program branching. When branch flag been previous instructions conditional branch taken. This flag affected arithmetic, logic, shift, rotate operations. Interrupt Enable interrupt enable flag enables disables interrupt processing global basis. After reset executing instruction, interrupt enable flag reset interrupts disabled. does process further interrupt requests until interrupt enable flag again either executing SLEEP instruction.
Condition Code Register (CCR)
4-bit wide condition code register contains branch, carry interrupt enable flag. These bits indicate current state CPU. flags reset operations. instructions SET_BCF, TOG_BF, CCR! allow direct manipulation condition code register. Carry/Borrow carry/borrow flag indicates that borrow carry arithmetic logic unit (ALU) occurred during last arithmetic operation. During shift rotate operations this used fifth bit. Boolean operations have affect flag.
1.2.4
4-bit performs arithmetic, logical, shift rotate operations with elements expression stack (TOS TOS-1) returns result TOS. operations affect carry/borrow branch flag condition code register (CCR).
1.2.5
Instruction Cycles
MARC4 instruction word bytes long executed within four machine-cycles. machine-cycle consists system clocks (SYSCL). MARC4 zero address machine. Most instructions byte long executed only machine-cycle. instruction pipeline, which allows controller fetch next instruction from program memory same time present instruction being executed. more information section "MARC4 Instruction Overview".
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TOS-1 TOS-2 TOS-3 TOS-4
Figure zero address operations
8977
1.2.6
ports registers peripheral modules (Timer Timer EEPROM) mapped. communication between core on-chip peripherals takes place associated control bus. These buses used different functions: read write accesses, interrupt generation, reset peripherals SLEEP mode. With MARC4 IN-instruction OUT-instruction allows direct read write access addresses. More about access on-chip peripherals described section "Peripheral modules". buses internal buses accessible customer final microcontroller device, they used interface MARC4 emulation (see also section "Emulation").
Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
1.2.7 Interrupt Structure
MARC4 handle interrupts with eight different priority levels. They generated from internal external interrupt sources software interrupt from itself. Each interrupt level hard-wired priority associated vector service routine (see table programmer enable disable interrupts together setting resetting interrupt enable flag CCR. Interrupt Processing processing eight interrupt levels, MARC4 contains interrupt controller with 8-bit wide interrupt pending interrupt active register. interrupt controller samples interrupt requests during every non-I/O instruction cycle latches them interrupt pending register. higher priority interrupt present interrupt active register signals interrupt current program execution. interrupt enable processor enters interrupt acknowledge cycle. During this cycle SHORT CALL instruction
INT7
service routine executed current saved return stack. interrupt service routine finished with instruction. This instruction sets interrupt enable flag, resets corresponding bits interrupt pending/active register fetches return address from return stack program counter. When interrupt enable flag reset (interrupts disabled), execution interrupts inhibited logging interrupt requests interrupt pending register. execution interrupt will delayed until interrupt enable flag again. note that interrupts lost interrupt request occurs during corresponding pending register still set. After reset (power-on, external watchdog reset), interrupt enable flag interrupt pending interrupt active register reset. Interrupt Latency interrupt latency time from falling edge interrupt interrupt service routine being activated. MARC4 this takes between machine cycles depending state core.
Priority level
TELEFUNKEN Semiconductors Rev. 17-Jun-96
INT7 active INT5 INT5 active INT3 INT2 INT3 active INT2 pending INT2 active SWI0 INT0 pending INT0 active Main Autosleep Main Autosleep
Time
8978
Figure Interrupt handling
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Preliminary Information
M44C260/M48C260
Table Interrupt priority table
Interrupt INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7
Priority lowest
100h (SCALL 100h) 140h 180h 1C0h 1E0h (SCALL 140h) (SCALL 180h) (SCALL 1C0h) highest (SCALL 1E0h) Software interrupt (SWI0) EEPROM write ready External hardware interrupt, neg. edge BP30 BP31 External hardware interrupt, neg. edge BP32 BP33 Timer interrupt Timer interrupt External hardware interrupt, neg. edge IP40 Software interrupt (SWI7)
Vector Address 040h 080h 0C0h
Interrupt Opcode (Acknowledge) (SCALL 040h) (SCALL 080h) (SCALL 0C0h)
Function
Software Interrupts
programmer generate interrupts using software interrupt instruction (SWI) which supported qFORTH predefined macros named SWI0 SWI7. software triggered interrupt operates exactly hardware triggered interrupt. instruction takes elements from expression stack writes corresponding bits interrupt
Table Hardware interrupts
pending register. using instruction thius way, interrupts re-prioritized lower priority processes scheduled later execution.
Hardware Interrupts
M44C260/M48C260 incorporates eleven hardware interrupt sources with different levels. Each these sources enabled disabled separately with interrupt mask IMR1 IMR2 register.
Interrupt EEPROM write ready External interrupt Port (BP30 BP31) External interrupt Port (BP32 BP33) Timer interrupt Timer interrupt
Priority INT1 INT2 INT3 INT4 INT5
Ext. interrupt IP40 input INT6 EEPROM write cycle Negative edge BP30 Negative edge BP31 Negative edge BP32 Negative edge BP33 Timer Timer space/underflow Timer pulse/capture Timer space/underflow Timer pulse/capture Negative edge IP40 input
Mask Register IMEP IMR1 IM30 IM31 IMR1 IM32 IM33 IMR2 IMT1 T2IC IMAS IMAP IMBS IMBP IMR2
Interrupt Source
Reset
reset puts into well-defined condition. reset triggered switching supply voltage, break-down supply voltage, watchdog timer pulling NRST low. After reset branch-, carry- interrupt enable flag Condition Code Register (CCR) interrupt pending register interrupt active register reset.
During reset-cycle control signals 'reset mode' thereby initializing on-chip peripherals.
reset finished with short call instruction (opcode C1h) program memory address 008h. This activates initialization routine $RESET. With that routine stack pointers, variables peripheral must initialized.
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Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
Power-on Reset M44C260/M48C260 incorporates on-chip power-on reset (POR) circuitry which provides internal chip reset most power-up situations. power-on reset ensures that core activated before operating supply voltage been reached. will function normally under conditions. below device will either function normally device reset will globally activated brown-out circuit. actual brown-out trip point function temperature process parameters. External Reset (NRST) external reset triggered with NRST pin. external reset should minimum machine-cycles. Watchdog Timer Reset watchdog timer function Timer enabled, reset triggered with every watchdog counter overflow. suppress that, watchdog counter must reset access CWD-register (see also Timer 1/watchdog counter). power-on reset watchdog reset indicated same external reset NRST pad.
Clock Generation
M44C260/M48C260 oscillators, oscillator system clock generation additional 32-kHz crystal oscillator. system clock generator provides core Timer with clock. system clock frequency programmable MHz. crystal oscillator used exact time base Timer exact timing required, controller does need external crystal. this case Timer provided with system clock. configuration both oscillators programmable with clock status control register (CSC), which subport register located port CSUB. required configuration initialized after reset $RESET routine. default setting after reset system clock active 32-kHz crystal oscillator. After power-on SLEEP instruction clock generator needs start-up time until runs with exact timing. CRDY register indicates start-up phase.
OSCIN
OSCOUT
OSC32
Stop
fOSC=
OSCS OSCS
CL32
TIMER
OSCS EERDY SLEEP
CSC3 OSCS CRDY
EEPROM
Stop
/122
Systemclock Generator
SYSCL TIMER CORE
Figure Clock module
TELEFUNKEN Semiconductors Rev. 17-Jun-96
Preliminary Information
Controllogic
8979
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M44C260/M48C260
1.4.1 Clock Status/Control Register (CSC)
Address: Subaddress:
CSC3 OSCS CRDY Reset value: 0000h CSC3 This must always zero Oscillator Stop OSCS OSCS runs with 32-kHz crystal oscillator Timer OSCS 32-kHz oscillator stops. operation without crystal, this must after reset. that case Timer provided from internal oscillator. CRDY indicates start-up time oscillators. CRDY indicates that clock ready exact timing. selects system clock (SYSCL/TCL) selects system clock (SYSCL/TCL) CRDY Clock Ready (status bit) Core Clock Select
1.4.2
Signal
used input supply controller with external clock. this configuration, must held least during reset cycle. controller working with clock frequencies MHz. also possible output supply peripherals with system clock. this case must connected level must have high impedance load.
sleep mode only kept when none interrupt pending active register bits set. application $AUTOSLEEP routine ensures correct function sleep mode. total power consumption directly proportional active time rough estimation expected average system current consumption, following formula should used: Itotal (VDD, fOsc) ISleep (IDD Tactive/Ttotal)
Power Down Modes
depends fOsc. Systemclock Generator Stop M44C260/M48C260 different power down modes. When MARC4 core enters sleep mode on-chip peripheral needs clock signal (SYSCL), system clock oscillator stopped. Therefore programmer should stop Timer Timer during sleep mode they required. 32-kHz oscillator used, should stopped. Under this condition, power consumption extremely (see following table). Osc. 32-kHzOsc. [OSCS] STOP STOP STOP PowerConsumption
sleep mode shutdown condition which used reduce average system power consumption applications where fully utilized. this mode system clock stopped. sleep mode entered with SLEEP instruction. This instruction sets interrupt enable condition code register enable interrupts stops core. During sleep mode peripheral modules remain active able generate interrupts. exits sleep mode with interrupt reset.
Table Power consumption different power down modes
Mode
CPUCore SLEEP SLEEP SLEEP SLEEP
STOP STOP (51)
TIMER [T1R] TIMER [TAR, TBR] EEPROM [EERDY] T1R=0 TAR=0 TBR=0 EERDY=1 T1R=X, TAR=0 TBR=0 EERDY=1 T1R=1 TAR=1 TBR=1 EERDY=0 T1R=X, TAR=1 TBR=1 EERDY=0 T1R=X, TAR=X, TBR=X, EERDY=X T1R=X, TAR=X, TBR=X, EERDY=X
Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
Peripheral Modules
Addressing Peripherals
lows access subports. first OUT-instruction writes subport address subaddress register, second OUT-instruction reads data from writes data addressed subport.
access peripheral modules (ports, registers) executed bus. OUT-instruction allows direct addressing ports. peripherals with large number registers, extended addressing used. With operations, extended port alTable I/O-addressing
Operation Port T2SC, read write T2SUB, CSUB Extended read Extended write qFORTH Instructions Description port data port Read data from port Write data port Extended short read ESUB Extended read (byte) subaddress port port subaddress port data port port subaddress port port port subaddress port data port data port Write subaddress port Read data from subaddress Write subaddress port Write data subaddress Read data from current subaddress Extended write (byte) Write subaddress port Read data high nibble from subaddress Read data nibble from subaddress Write subaddress port Write data nibble subaddress Write data high nibble subaddress
Subport Subport Subport Subaddress Register subaddress port Subport Subport Subport Subport data port port
port
Subport
port
Figure Extended addressing
8980
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Preliminary Information
Table Peripheral addresses
M44C260/M48C260
(51) Addr.
Name Port Port Port Port Port T2SC T2SUB
ESUB CSUB
Subport EEPROM Subport watchdog, Timer interrupt masks, clock generator
Subport Timer
Bidirectional port Bidirectional port Bidirectional port Bidirectional port Input port
Preliminary Information
Subaddress address TARH TARL TBRCH TARCH TBRCL TARCL IMR1 IMR2 Function
Timer status control register SubName Register
TBRH TBRL TAM1 TAM2 TBM1 TBM2 T2IC T2PC EEPROM status register Name Register
Timer control register Interrupt mask register Interrupt mask register
Watchdog control register Clear watchdog counter Clock status/control register
Timer space reload/capture register, high nibble Timer space reload/capture register, nibble Timer pulse reload register Timer pulse reload register Timer space reload/capture register, high nibble Timer space reload/capture register, nibble Timer pulse reload register Timer pulse reload register Timer mode register Timer mode register Timer mode register Timer mode register Timer interrupt control Timer prescaler control
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
2.1.1 Input Port
Port input port pins IP40, IP43, IP40 also interrupt input INT6, normally used timer functions.
Input Port IP43 TB/IP42 TA/IP41 IP40/INT6
Pull-up
Pull-up
IP40/INT6
IP43 INT6
Pull-down
optional
8981
Figure Input port IP40, IP43
2.1.2
Bidirectional Ports
Ports bidirectional 4-bit wide ports used data input output. data direction programmable complete port only. port switched output with OUT-instruction input with IN-instruction. data written port will stored into output latches appears immediately after OUT-instruction port pin. After RESET output latches ports switched input mode. Note: Care must taken when switching bidirectional ports from output input. capacitive load this port cause data read same last data written this port. avoid this when switching direction, following approaches should used.
IN-instructions DROP first data
nibble read. first switches port from output input, DROP removes first invalid nibble second reads valid nibble.
OUT-instruction followed IN-instruction. With OUT-instruction, capacitive load charged discharged depending optional pull-up /pull-down configuration. Write pins with pull-up resistors pins with pulldown resistors.
TELEFUNKEN Semiconductors Rev. 17-Jun-96
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Preliminary Information
M44C260/M48C260
BPxy
Reset Reset
optional pull-up pull-down resistor
8982
Figure Bidirectional port
Interrupt logic (INT2 INT3)
BP3y
Reset PortX_OUT PortX_IN Reset
optional pull-up pull-down resistor
8983
Figure Bidirectional Port with interrupt input
2.1.3
External Interrupt Inputs
pins IP40 BP30 BP33 used external interrupt inputs. IP40 used INT6, BP32 BP33 used INT3, BP30 BP31 used INT2. IP40 also used input port BP30 BP33
bidirectional port (see figure 14). Each these external interrupt sources enabled disabled with individual interrupt mask bits. negative transition these inputs requests interrupt, when corresponding mask set. interrupt masks placed subport registers IMR1 IMR2 port CSUB.
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Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
IMR1: IM33 IM32 IM31 IM30
BP33 BP32 BP31 BP30 IP40
Interrupt interface Interrupt interface Interrupt interface
INT3
INT2
INT6
IMR2:
IMT1
8984
Figure External interrupt inputs
Timer
interrupt maskable with IMT1 bit. time interval watchdog reset programmed with watchdog control register 0.5, 2.0, 16.0 When watchdog active (WDR controller reset with overflow 3-bit watchdog counter. application software ensure that watchdog counter reset write access port before overflows.
Timer interval timer generating interrupts. Additionally, Timer used watchdog timer. timer consists programmable stage divider which supplied with 32-kHz clock 3-bit counter watchdog function (see figure 16). time interval Timer interrupt (INT4) programmed with timer control register from Timer
T1C2 T1C1 T1C0
T1C2 T1C1 T1C0
Decoder
DIVIDER CL32
RESET Decoder WRITE (T1C)
Divider
WDC1 WDC0
TELEFUNKEN Semiconductors Rev. 17-Jun-96
Preliminary Information
IMR2
WDR=0
IMT1=0 INT4 IMT1=1 IMT1
Watchdog counter
Divider
RESET (NRST)
Divider RESET
WDC1 WDC0
WDR=1
WRITE
8985
Figure Timer
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2.2.2
WDM0 WDM1
2.2.1
T1C0 T1C1 T1C2 T1C2
registers Timer I/O-mapped. They subport register port CSUB access made extended operations. interval timer controlled
Timer register
M44C260/M48C260
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Watchdog Control Register
Timer Control Register
Both these bits control time interval watchdog reset.
Watchdog mode
Watchdog mode
Watchdog watchdog counter inactive reset watchdog counter active able generate reset when Timer running
This three bits select time interval Timer interrupt.
Timer control
Timer control
Timer control
Timer reset Write (T1R resets interval timer
T1C1
T1C2
Preliminary Information
T1C0 WDM1 T1C1 Divider 1024 4096 16384 65536 262144 WDM0 T1C0
prescaler control register T1C. interrupt mask IMT1 placed interrupt mask register IMR2. watchdog timer controlled watchdog control register port CWD. write access resets watchdog counter.
Address: `C'h Subaddress
Address: `C'h Subaddress
TELEFUNKEN Semiconductors Rev. 17-Jun-96 Reset value: 0x00b Reset value: 0000b Time Interval 0.9765625 1.953125 7.8125 31.25
M44C260/M48C260
Timer
TA/TB used counter output. duty cycle programmed with pulse space reload register. Timer consists timer/counter blocks Timer Timer Each block 8-bit downcounter programmable prescaler. clock inputs programmed count system clocks, Timer clocks external clocks. maximum clock rate external clocks half system clock frequency (SYSCL/2). Each counter reload register pulse time reload register space time. Every counter underflow toggles output reloads downcounter alternately from pulse reload register from space reload register. This allows generation duty cycles. addition, both counters have capture mode. this mode external signal Counter output causes current counter value captured into corresponding capture register. timer pins, Timer Timer Used output, pins have high level during pulse time level during space time timer. input, pins used external counter clock capture signal. inputs have programmable edge detection select active edge external clock capture signal. Interrupts generated when counter underflow capture event occurs. interrupt function Timer programmed with interrupt control register. Both counter blocks share interrupt vector (INT5).
Divider 2048 8192 32768 524288
Delay Time Reset
Capture mode
Counter supplied system clock. TA/TB used input. external signal input causes current counter value captured into capture register.
Event counter
Counter counts external clocks TA/TB pin. capture register contains current counter value read.
Combined Timer Modes
16-bit timer
Counter supplied with system clock output coupled with input Counter this mode counter used generate timer interrupts.
capture mode
Counter supplied with system clock Counter with output Counter external signal causes current counter value will captured into capture registers.
16-bit event counter
output Counter coupled with input Counter count external clocks capture register both counters contain current counter values.
Timer Modes There various timer/counter modes both blocks Timer They used separately combined. timer modes programmed with timer control mode registers. Single Timer Modes
Burst generator
Counter supplied with system clock output coupled with input Counter output Counter controls output signal Counter pin. output enabled during pulse disabled during space Counter
8-bit timer
Counter supplied system clock used generate timer interrupts.
Event counter with time gate
Counter counts clocks Counter supplied with system clock. Each underflow Counter causes counter value Counter captured into capture register.
Pulse width modulation
Counter supplied system clock.
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Preliminary Information
M44C260/M48C260
Timer Register timer register mapped. access Timer status control register (T2SC) done with direct operation T2SC. status read with operation command control timer written with operation. remaining registers Timer subport registers port T2SUB. access those registers needs extended operation. timer function configured with mode registers TAM1, TAM2, TBM1, TBM2 interrupt control register T2IC. timing depends contents prescaler control register T2PC reload registers. capture registers used read counter value.
SYSCL
TAM1
Counter
TARCH[r]
TAM1
TAM1
TAM2
TAM2
AE1AE0
TBM1
INTERRUPT
INT5
BCS1 BCS0 SYSCL
T2IC T2SC [READ]
Counter
TBM2
TBM2
TBM1
8987
TBRCH[r]
Note: control switches shown value
Figure Timer
Reload register
PULSE
TxRH[w] TxRL[w]
SPACE
TxRCH[w]TxRCL[w]
T2PC
Input Counter
Prescaler
Output Counter
DOWN COUNTER
Toggle
T2SC[w] Counter Counter READ WRITE
Capture register
TxRCH[r] TxRCL[r]
Capture Input
Figure Counter
8986
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Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
TBM, TBR: Timer control bits start stop Timer TAM, TAR: Timer control bits start stop Timer TAPC: TASU: TBPC: TBSU: Read (T2SC) capture enable control bits timer mode registers TAM2 TBM2. Timer pulse/capture status bit. When this will pulse time Counter When this will when capture event Counter occurs. Timer space/underflow status bit. When ACE* this will space time Counter When this will with each Counter underflow. Timer pulse/capture status bit. When this will pulse time Counter When this will when capture event Counter occurs. Timer space/underflow status bit. When BCE* this will space time Counter When this will with every Counter underflow. TBSU STOP_A-RUN_B RUN_A-STOP_B RUN_AB STOP_AB RUN_B STOP_B RUN_A STOP_A Timer Commands TBPC TASU pulse reload register. taking value from counter with next clock command starts prescaler counter. STOP command resets TAPC Reset value: 0000b
2.3.1
Status register Control register Write (T2SC)
TELEFUNKEN Semiconductors Rev. 17-Jun-96
status bits TASU, TAPC, TBSU, TBPC will reset after READ access T2SC!
Timer Status/Control Register (T2SC)
Preliminary Information
M44C260/M48C260
Reset value: 0000b
Address:
(51)
M44C260/M48C260
2.3.2 Timer Subport (T2SUB)
Address:
Table Timer subports
Low-nibble High-nibble Low-nibble High-nibble Low-nibble IMBS BPC1 High-nibble Low-nibble BCS1 BCS0 IMBP IMAS BPC0 APC1 IMAP APC0 write only, read only
Subaddr. Name TARCH [w]* TARCH [r]* TARCL [w]* TARCL [r]* TARH TARL TBRCH [w]* TBRCH [r]* TBRCL [w]* TBRCL [r]* TBRH TBRL TAM1 TAM2 TBM1 TBM2 T2IC T2PC
Meaning Timer reload high Timer capture high Timer reload Timer capture Timer reload high Timer reload Timer reload high Timer capture high Timer reload Timer capture Timer reload high Timer reload Timer mode register Timer mode register Timer mode register Timer mode register Timer interrupt control Timer prescaler control
High-nibble
2.3.3
Timer Reload Register
register value from pulse reload register toggles counter output. pulse space width calculated following: Pulse time: Pulse (n+1) prescaler clocks Spacetime: Space (m+1) prescaler clocks
8-bit wide reload registers Timer used program pulse space width counter output signal. first clock after start command loads downcounter with value from pulse reload register sets counter output downcounter decrements with each following clock each underflow reloads alternately value from space reload
Prescaler Counter
PULSE
SPACE
(51)
Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
Timer Space Reload Register space reload register Timer programmed write accesses subport addresses TARCH TARCL TBRCH TBRCL Timer subport T2SUB. value space reload register determines space width. pulse, downcounter reloads 8-bit value from space reload register with next clock prescaler output. Space width: Space (m+1) prescaler clocks Timer Pulse Reload Register pulse reload register Timer programmed write accesses subport addresses TERH TARL TBRH TBRL Timer subport T2SUB. value pulse reload register determines space width. space downcounter reloads 8-bit value from pulse reload register with next clock prescaler output. Pulse width: Pulse (n+1) prescaler clocks
2.3.4
Timer Capture Register
capture register used capture current downcounter value when capture event occurs. value kept capture register until next capture event read independent state downcounter. capture events programmable with timer mode registers TAM2 TBM2. capture registers also used read counter value when external capture mode disabled. this case 8-bit counter value transferred into capture register reading high nibble TARCH TBRCH. 16-bit event counter mode enabled complete 16-bit value captured reading first high nibble TARCH Timer This mechanism ensures coherence counter high nibble during read access.
2.3.5
Timer Mode Register (TAM1)
Address: Subaddress:
TAM1 Reset value: 0000b Counter output gated Counter output enables burst generation mode. output Timer enabled during pulse time Counter disabled (TA= during space time Counter Counter clock select This selects source Counter clock. When timer supplied with internal SYSCL. When timer supplied with external clock pin. Timer output enable disables counter output enables counter output TELEFUNKEN Semiconductors Rev. 17-Jun-96 (51)
Preliminary Information
2.3.7
BCS0 BCS1 BCS1 TBM1 BCS0
2.3.6
M44C260/M48C260
(51)
TAM2
Timer Mode Register (TBM1)
Timer Mode Register (TAM2)
Timer edge select With these bits active edge counter clocks capture signal selected.
Timer edge select
Timer capture enable enables capture mode Counter occurrence capture event causes that current downcounter value loaded into capture register.
Timer captured Timer Selects capture source Timer When signal used generate capture event. When each transition Counter output used generate capture event Timer
Timer output enable disables counter output enables counter output
These bits select source Counter clock.
Timer clock select
Timer clock select
Counter Input Signal System clock (SYSCL) Output signal Counter External input signal
Active Edge Counter Clock/Capture Events positive edge negative edge first positive edge after timer start then each transition first negative edge after timer start then each transition
BCS1
Preliminary Information
BCS0
Address: Subaddress:
Address: Subaddress:
TELEFUNKEN Semiconductors Rev. 17-Jun-96 Reset Value: 0000b Reset value: 0000b
2.3.9
APC0 APC1 BPC0 BPC1 BPC1/APC1 T2PC
2.3.8
TBM2
TELEFUNKEN Semiconductors Rev. 17-Jun-96 BPC0/APC0 BPC1
Timer Prescaler Control Register (T2PC)
Timer Mode Register (TBM2)
Timer prescaler control These bits determine divider prescaler Timer
Timer prescaler control
Timer prescaler control These bits determine divider prescaler Timer
Timer prescaler control
Timer edge select With these bits active edge counter clocks capture signal selected.
Timer edge select
Timer capture enable enables capture mode Counter capture event loads current downcounter value into capture register.
Timer captured with Timer capture signal. With external capture signal Timer used capture Timer simultaneously with Timer
Active Edge Clock/Capture Events positive edge negative edge first positive edge after start timer then each transition first negative edge after start timer then each transition
BPC0
Preliminary Information
Divider APC1 APC0
M44C260/M48C260
Address: Subaddress:
Address: Subaddress:
Reset value: 0000b
Reset Value: 0000b
(51)
M44C260/M48C260
2.3.10 Timer Interrupt Control Register (T2IC)
Address: Subaddress: T2IC IMBS IMBP IMAS IMAP Reset value: 0000b
IMBS Interrupt mask Timer space/underflow IMBS enables INT5 interrupt, BCE* space Counter each Counter underflow. Interrupt mask Timer pulse/capture IMBP enables INT5 interrupt, pulse Counter with capture event Counter IMBP IMAS Interrupt mask Timer space/underflow IMAS enables INT5 interrupt, ACE* space Counter each Counter underflow. Interrupt mask Timer pulse/capture IMAP enables INT5 interrupt, pulse Counter with capture event Counter IMAP Each interrupt source enabled disabled individually setting corresponding maskbit. capture enable control bits timer mode registers TAM2 TBM2.
T2SC[r] TBSU TBPC TASU TAPC
Timer pulse capture Timer space underflow Timer pulse capture Timer space underflow INT5
T2IC
IMBS
IMBP
IMAS
IMAP
READ
8988
Figure Timer interrupt mask register
(51)
Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
2.3.11 Timer (TA/TB)
input mode, when AOE/BOE switched output mode. pins also read with INinstruction Port with IP41 with IP42). timer pins used input external clock capture signal output counter. mode controlled with control bit. When AOE/BOE switched
(IP41/IP42) Port4_IN Counter input (edge sense) Counter output
TA/TB
AOE/AOB-controlbit optional pull-up pull-down resistor
8989
Figure Timer (TA/TB)
TELEFUNKEN Semiconductors Rev. 17-Jun-96
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Preliminary Information
M44C260/M48C260
EEPROM
EEPROM M44C260/M48C260 wide organized array 16*8-bit. EEPROM rows mapped subports port ESUB. access 8-bit EEPROM done extended 8-bit operation special postincrement access. EEPROM rows write protected hardware software.
High nibble nibble
Write protectable
Memory
Control logic
ESUB
8990
Figure EEPROM
2.4.1
EEPROM SubPort (ESUB) Address: Subaddress: 0-Fh
Read operation read operation needs OUT- IN-instructions port ESUB. First operation writes adqFORTH example: address ESUB ESUB ESUB
dress. following IN-instructions read high nibble then nibble addressed row.
--Data_High) Data_High Data_Low)
(Data_High
Write operation write operation needs three OUT-instructions port ESUB. first operation writes address. following OUT-instructions write nibble
then high nibble addressed row. After reset, rows write protected. enable write operations these rows write enable (EWE) must set. cases write accesses these rows disabled when low.
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Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
qFORTH example: address ESUB ESUB ESUB (Data_High Data_Low (Data_High Data_Low (Data_High Data_High Data_Low) --Data_High)
internal EEPROM write cycle needs about (with connected quartz crystal running crystal oscillator). During this cycle EEPROM ready reset (EPR After data high nibble written port ESUB, internal write cycle started. During internal write cycle (while only read write accesses register possible. other EEPROM accesses have effect. Postincrement operations postincrement mode supports fast access consecutive EEPROM rows. postincrement access started setting EEPROM mode register (EMS) followed writing start address port ESUB. After that, read write operations consecutive EEPROM area, beginning start
dress, need only OUT-instructions read write data. address incremented automatically after each complete access nibbles). write access EEPROM mode register (EMS) terminates postincrement mode. Note: postincrement mode, possible change from read write operations vice versa before current postincrement operation finished.
Write ready interrupt (INT1) internal write cycle interrupt generated when interrupt mask IMEP EEPROM mode register set. With this interrupt, successive write operations executed interrupt controlled within INT1 interrupt service routine.
2.4.2
EEPROM Mode/Status Register (EMS)
Address:
IMEP Reset value: 0000b Reset value: xxx1b Status register Read (EMS) EEPROM write enable disables write accesses rows 12-15 enables write accesses rows 12-15 when high EEPROM postincrement mode enable activates postincrement access after next address written port ESUB Interrupt mask EEPROM write ready interrupt When IMEP INT1 generated with internal EEPROM write cycle EEPROM ready status flag indicates that EEPROM ready read write operations internal write cycle executed) indicates that EEPROM ready read write operations IMEP After write access EMS-Register, postincrement operations terminated incomplete EEPROM read write sequence must started again! TELEFUNKEN Semiconductors Rev. 17-Jun-96 (51)
Mode register Write (EMS)
Preliminary Information
M44C260/M48C260
Appendix
Emulation
single byte instructions. These operations performed source destination address information Only BRANCH, CALL access instructions need address information length bytes long address operations. total, there five types instruction formats with length bytes. Zero address operations such arithmetical, logical, shift rotate operations performed with data placed expression stack (TOS TOS-1). Also I/O- stack operations single byte zero address operations performed with expression stack location. literal 4-bit constant value which placed data stack. MARC4 native code they represented LIT_<value>, where <value> hexadecimal representation from (0.F). This range result MARC4's 4-bit data width. 6-bit short address 12-bit long address formats both used address byte-wide CALL conditional branch instructions. This results address space 8-bit words. MARC4 instruction includes both short long call instructions well conditional branch instructions. execution address part instruction's word directly loaded into program counter. Long call branch instructions jump anywhere within program memory area. lower bits from short call (SCALL) short branch (SBRA) instruction handled different way. SCALL address multiplied three then loaded into This allows calls within zero page (000 1FFh). SBRA address loaded immediately into lower bits This allows jumps within byte segment addressed upper bits CALL SCALL instructions write incremented program counter contents return stack. This address loaded back when associated EXIT instruction encountered. long address format used four 8-bit address registers which pre-increment, post-decrement loaded directly from MARC4's internal bus. This results direct accessible address space 4-bit.
emulation MARC4 controllers have special emulation mode. activated setting logic HIGH level during reset. this mode internal core inactive buses available Port Port allow emulator access on-chip peripherals. emulator contains special emulation with MARC4 core additional breakpoint logic takes over core function. basic function emulator evaluate customer's program hardware real time. Thus, analysation timing, hardware software problems simulation application possible. more information about emulation "Emulator Manual".
Programming EEPROM Program Memory
Programming 8-bit EEPROM program memory done using special PC-controlled programming device. Details this device corresponding software given Programming Device User Manual. start programming data memory, microcontroller switched special mode, where core peripherals inactive buses available Port (data) Port (control). Then customer application data transfered controller Port blocks nibble size. Programming started automatically after each block. programming high voltage generated chip. After programming memory, verify started where just written data read compared original source file. This ensures that content error free.
MARC4 Instruction
MARC4 instruction optimized high level programming language qFORTH. MARC4 instructions qFORTH words. This enables compiler generate fast compact program code. MARC4 zero address machine with compact efficient instruction code. Most instructions
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Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
Zero address operation (ADD,SUB, INC, OR,.) Immediate data operation Literal (LIT_0, LIT_1, Short address operation (SCALL, SBRA) Long address operation (CALL, BRA) address operation (>SP, >X,.) Opcode Opcode Opcode Opcode Opcode Figure MARC4 opcode formats data
8708
address address
address
3.3.1
MARC4 Instruction Overview
Description Arithmetic operations: with carry Subtract Subtract with borrow Decimal adjust Increment Decrement Decrement. 4-bit index return stack Compare operations: Compare equal Compare equal Compare less than Compare less equal Compare greater than Compare greater equal Logical operations: Exclusive complement Shift left into carry Shift right into carry Rotate left through carry Rotate right through carry Cycles/ Bytes
Mnemonic
Description Flag operations: Toggle branch flag branch flag Disable interrupts Store into Fetch onto Program branching: Conditional long branch Long call (current page) Conditional short branch Short call (zero page) Return from subroutine Return from interrupt Software interrupt Activate sleep mode operation Register operations: Fetch current Fetch current Fetch contents Fetch contents Move into Move into Move into Move into Store direct address Store direct address Store direct address into Store direct address into
Mnemonic
Cycles/ Bytes
ADDC SUBB DECR
CMP_EQ CMP_NE CMP_LT CMP_LE CMP_GT CMP_GE
TELEFUNKEN Semiconductors Rev. 17-Jun-96
Preliminary Information
TOG_BF SET_BFC CCR! CCR@ $xxx CALL $xxx SBRA $xxx SCALL$xxx EXIT SLEEP
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M44C260/M48C260
Mnemonic Description Stack operations: Exchange nibble Copy TOS-1 Duplicate nibble Move TOS-2 Remove nibble Move nibble onto return stack Move nibble onto return stack Move nibble onto return stack Copy nibble from return stack Copy nibbles from return stack Copy nibbles from return stack Remove return stack (12-Bit) Push immediate value Cycles/ Bytes Mnemonic Description Memory operations: Fetch nibble from indirect addressed Y-register Fetch nibble from indirect addr. pre-increm. Y-register Fetch nibble from indirect addr. post-dejcrem. Y-register Fetch nibble from direct addressed Y-register Store nibble into indirect addressed Store nibble into indirect addressed preincremented Store nibble into indirect addr. post-decrem. Y-register Store nibble into direct addressed Y-register operations: Read I/O-Port onto Write port Cycles/ Bytes SWAP OVER DROP
DROPR LIT_n
TABLE
nibble) onto data operations: Fetch 8-bit constant from
3.3.2
qFORTH Language Overview
MARC4 controllers programmed high level language qFORTH which based FORTH-83 language standard. qFORTH compiler generates native code 4-bit FORTH-architecture single chip microcomputer, TEMIC MARC4.MARC4 applications programmed qFORTH which designed specifically efficient real time control. Since qFORTH compiler generates highly optimized codes, there advantage point programming MARC4 assembly code. high level code efficiency generated qFORTH compiler achieved modern optimization techniques such branch-instruction size minimization, fast procedure calls, pointer tracking many peephole optimizations.
(51)
Preliminary Information
[X]@ [Y]@ [+X]@ [+Y]@ [X-]@ [Y-]@ [>X]@ [>Y]@ [X]! [Y]! [+X]! [+Y]! [X-]! [Y-]! [>X]! [>Y]!
Language features:
Expandability Many fundamental qFORTH operations directly implemented MARC4 instruction set. Stack oriented operations communicate with another data stack reverse polish form notation (RPN) Structured programming qFORTH supports structured programming Reentrant Different tasks share same code. Recursive qFORTH routines call themselves. Native code inclusion qFORTH there separation high level constructs from native code mnemonics.
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
3.4.1
qFORTH Language Quick Reference Guide
Arithmetic/Logical
n1-n2 n1+n2 n1+/n+/C n1+n2+C d1+d2 d1-d2 n1^n2 Subtract nibbles 4-bit values compl. subtract with borrow with carry values Increment value Decrement value Multiply value Divide 4-bit value 8-bit values Subtract 8-bit values Divide 8-bit value Multiply 8-bit value 4-bit 8-bit value Subtract 4-bit from 8-bit value Bitwise values Bitwise values Rotate left through carry Rotate right through carry Shift value left into carry Shift value right into carry complement value complement 8-bit value complement value Bitwise Ex-OR values
DD2/ MAND NEGATE DNEGATE
3.4.2
D0<> DMAX DMIN
Comparisons
dMax dMin nMax nMin n1>n2, then branch flag n1<n2, then branch flag n1>=n2, then branch flag n1<=n2, then branch flag n1<>n2, then branch flag n1=n2, then branch flag <>0, then branch flag then branch flag d1>d2, then branch flag d1<d2, then branch flag d1>=d2, then branch flag d1<=d2, then branch flag d1=d2, then branch flag d1<>d2, then branch flag <>0, then branch flag then branch flag 8-bit maximum value 8-bit minimum value 4-bit maximum value 4-bit minimum value
TELEFUNKEN Semiconductors Rev. 17-Jun-96
(51)
Preliminary Information
M44C260/M48C260
3.4.3
AGAIN BEGIN CASE ELSE ENDCASE ENDOF EXECUTE EXIT LOOP REPEAT THEN UNTIL WHILE +LOOP #LOOP ?LEAVE -?LEAVE
Control Structures
limit start u|limit|start ROMAddr ROMAddr u|limit|I u|limit|I+n u|u|n u|u|I--u|u|I-1 Limit Start Ends infinite loop BEGIN AGAIN BEGIN most control structures Begin CASE ENDCASE block Initializes iterative DO.LOOP Executed when condition false CASE.ENDCASE block ENDOF block Execute word located ROMAddr Unstructured EXIT from `:'-definition Conditional ELSE THEN block Repeat LOOP, index+1<limit Execute CASE block, Unconditional branch BEGIN BEGIN WHILE REPEAT Closes statement Branch BEGIN, condition false Execute WHILE REPEAT block, condition true Repeat LOOP, limit Execute #LOOP block n-times Decrement loop index downto zero start=limit, skip LOOP block Exit loop, condition true Exit loop, condition false
3.4.4
<name> <ROT ?DUP DEPTH DROP
Stack Operations
ROMAddr u|u|n u|u|I u|u|I u|u|J u|u|I u|u|J u|u|I n[x] u|u|n u|u|n u|u|n Push 4-bit literal stack Places address colon-definition <name> stack Move value stack pos. Move value onto return stack Duplicate value, current expression stack depth Remove 4-bit value Duplicate 4-bit value Copy loop index from return expression stack Fetch index value outer loop [2nd return stack level entry] Drop second 4-bit value Copy over 4-bit value Copy x-th value from expression stack onto unused stack entries Move 4-bits from return expression stack Copy 4-bits from return expression stack Move n-th value within stack
OVER PICK RFREE ROLL
(51)
Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
SWAP TUCK u|n2|n1 u|n2|n1 u|n2|n1 u|n2|n1) n3|n2|n1 n3|n2|n1 n3|n2|n1 n3|n2|n1 Move stack value pos. Exchange values stack Duplicate value, move under second item Move values from expression return stack Drop values from stack Duplicate 8-bit value Drop 8-bit value from stack Copy 8-bit value over value Move 8-bit value pos'n Move 8-bits from return expression stack Copy 8-bits from return expression stack Move 8-bit value value Exchange 8-bit values Tuck 8-bits under byte Move nibbles from expression onto return stack Remove nibbles from stack Duplicate 12-bit value Move nibbles from return expression stack Copy nibbles entry) from return expression stack
2DROP 2DUP 2NIP 2OVER 2<ROT 2ROT 2SWAP 2TUCK 3DROP 3DUP
3.4.5
Memory Operations
addr addr addr addr addr addr addr addr addr ROMAddr addr addr addr from ROMAddr addr addr addr addr addr addr addr Store 4-bit value Fetch 4-bit value from 4-bit value contents Increment 4-bit value Decrement 4-bit value Store 8-bit value Fetch 8-bit value from 8-bit value byte Subtract 8-bit value from byte Indexed fetch constant Exclusive-OR 8-bit value with byte Sets memory cells Fill memory cells with Move n-digit array memory Fetch 8-bit constant Ex-OR value address with Store 12-bit value into array Fetch 12-bit value from 12-bits cells Subtract 12-bits from nibble array byte nibble array Subtract byte from nibble array
DTABLE@ DTOGGLE ERASE FILL MOVE ROMByte@ TOGGLE TD+! TD-!
TELEFUNKEN Semiconductors Rev. 17-Jun-96
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Preliminary Information
M44C260/M48C260
3.4.6 Predefined Structures
In-line comment definition Comment until line Begin colon definition Exit; ends colon definition Index (=0) first array element Index last array element Begins in-line macro definition Ends In-line macro definition Allocates space 4-bit array Allocates space 8-bit array Defines 4-bit constant Defines 8-bit constant Allocates space long 4-bit array with elements Allocates space long byte array Run-time array access using variable array index Define look-up table with 8-bit values Allocates memory 4-bit value Creates 8-bit variable Allocate space <n+1> nibbles un-initialized Fixed <address> placement Interrupt service routine entry Entry point address return stack underflow Entry point power-on reset ccccccc) ccccccc <name> [FIRST] [LAST] CODE END-CODE ARRAY 2ARRAY CONSTANT 2CONSTANT LARRAY 2LARRAY Index ROMCONST VARIABLE 2VARIABLE ALLOT <address> INTx $AutoSleep $RESET
ROMAddr (n|d addr--addr')
ROMAddr
3.4.7
Assembler Mnemonics
n1+n2 n1+n2+C n+6) 10+/n+C u|u|I u|u|I-1 u|u|u ROMAddr port data 4-bit values with carry values Write value into Fetch onto stack n1=n2, then branch flag n1>=n2, then branch flag n1>n2, then branch flag n1<=n2, then branch flag n1<n2, then branch flag n1<>n2, then branch flag Clear branch carry flag branch carry flag Toggle branch flag arithmetic adjust [addition] complement subtract Decrement value Decrement value return stack Disable interrupts Drop element from return stack Exit from current `:'-definition Enable interrupts Read data from port Increment value operation complement value TELEFUNKEN Semiconductors Rev. 17-Jun-96
ADDC CCR! CCR@ CMP_EQ CMP_GE CMP_GT CMP_LE CMP_LT CMP_NE CLR_BCF SET_BCF TOG_BF DECR DROPR EXIT (51)
Preliminary Information
M44C260/M48C260
SLEEP SWI0 SWI7 SUBB TABLE [X]@ [+X]@ [X-]@ [>X]@ [X]! [+X]! [X-]! [>X]! [Y]@ [+Y]@ [Y-]@ [>Y]@ [Y]! [+Y]! [Y-]! [>Y]! RETAddr n1-n2 n1+/n2+C RetAddr RomAddr data port Store return stack pointer Fetch current stack pointer Return from interrupt routine Enter 'sleep-mode', enable interrupts Software triggered interrupt Store stack pointer Fetch current stack pointer complement subtraction compl. subtract with borrow Fetches 8-bit constant from address Write data port Fetch current register contents Indirect fetch contents Pre-incr. indirect fetch Postdecr. indirect fetch Direct fetch, addressed Move 8-bit address register Indirect store contents Pre-incr. indirect store Postdecr. indirect store Direct store, addressed Fetch current register contents Indirect fetch contents Pre-incr. indirect fetch Postdecr. indirect fetch Direct fetch, addressed Move address register Indirect store contents Pre-incr. indirect store Postdecr. indirect store Direct store, addressed return stack pointer expression stack pointer register immediate register immediate
Notes: True condition False condition addr ROMaddr Return address stack effects Expression data) stack effects Means branch flag Means branch flag reset 4-bit data value 8-bit data value 8-bit address 12-bit address
TELEFUNKEN Semiconductors Rev. 17-Jun-96
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Preliminary Information
M44C260/M48C260
Electrical Characteristics
Absolute Maximum Ratings
Symbol tshort Tamb Tstg RthJA Tsld Value -0.3 +0.3 indefinite +130 Unit
Voltages given relative VSS.
Stresses greater than those listed under absolute maximum ratings cause permanent damage device. This stress rating only functional operation device condition above those indicated operational section this specification implied. Exposure absolute maximum rating condition extended period affect device reliability. inputs outputs protected against high electrostatic voltages electric fields. However, precautions minimize build-up electrostatic charges during handling recommended. Reliability operation enhanced unused inputs connected appropriate logic voltage level (e.g., VDD).
Parameters Supply voltage Input voltage pin) Output short circuit duration Operating temperature range Storage temperature range Thermal resistance (PLCC) Soldering temperature
Operating Characteristics
Test Conditions Pins Symbol Min. Typ. Max. values M48C260 (1.3) (2.1) (1.8) (2.9) (2.7) (4.0) (4.4) (6.4) (0.9) (1.6) (1.0) (1.7) (1.3) (2.0) (1.9) (2.3) (0.4) (1.0) (0.5) (1.0) (0.8) (0.8) Unit
Supply voltage Tamb +85°C, unless otherwise specified. Parameters Power supply Active current (CPU active)
fSYSCL=1MHz
fSYSCL=2MHz fSYSCL=1MHz fSYSCL=2MHz fSYSCL=1MHz fSYSCL=2MHz fSYSCL=1MHz fSYSCL=2MHz
Power down current (CPU sleep, oscillator active) Sleep current (CPU sleep, oscillator inactive) Sleep current (CPU sleep, oscillator inactive)
Tamb 25°C
ISleep
ISleep
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Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
Supply voltage Tamb 25°C, unless otherwise specified
Supply voltage Tamb 25°C, unless otherwise specified Parameters Test Conditions Pins Symbol Min. Typ. Brown-out voltage: 1.75 Schmitt-trigger input voltage: INT6, Port Port Negative-going threshold voltage Positive-going threshold 0.7*VDD voltage Hysteresis VT-) 0.1*VDD Input voltage: NRST, NWP, TCL, Port Port Input voltage Input voltage HIGH 0.8*VDD Input current: Bidirectional Ports input Port with pull-up resistor NRST, TCL, INT6 Input current VDD= VIL= -2.7 -6.7 VDD= Input current: Bidirectional Ports input Port with pull-down resistor NWP, Input HIGH current Output current: Bidirectional Ports Output current ,VOL 0.2*VDD Output HIGH current -0.6 -1.3 0.8*VDD -7.5 Output current: Output current 0.2*VDD Output HIGH current -1.2 -2.6 0.8*VDD
TELEFUNKEN Semiconductors Rev. 17-Jun-96
Parameters Test Conditions Pins Timer input timing Timer input clock Timer input time Rise/fall time Timer input HIFG time Rise/fall time Interrupt request input timing Int. request time Rise/fall time Int. request HIGH time Rise/fall time
Characteristics
Preliminary Information
Symbol tIRL tIRH tTIL tTIH
M44C260/M48C260
Min.
Typ.
0.2*VDD
0.3*VDD
SYSCL
Max.
Max.
-103
-4.4
-2.2
2.25
(51) Unit Unit
Note With connected crystal (pin after start time crystal oscillator.
Note This parameter tested initially after design process change that effects parameter.
Note Dependent connected quartz crystal.
M44C260/M48C260
(51) External crystal parameters Crystal frequency Series resistance Static capacitance Dynamic capacitance fall time Reset timing Power-on reset time NRES input time Data EEPROM EEPROM write time Note EEPROM write cycles Note EEPROM data retention Note Program EEPROM (M48C260 only) EEPROM write cycles Note Operation cycle time System clock cycle Note oscillator Frequency Note Stability Note Stabilization time Note oscillator Frequency Start time Stability Note Integrated input/output capacitances Parameters clock input clock input time input HIGH time rise time Test Conditions Pins Symbol tSYSCL fTCL tTCLL tTCLH tTCLR COUT tTCLF TPOR TPOR tEEW fRC1 4*SYSCL 5*105 0.250 0.250 Min.
Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96 32.768 32.768 1000 2000 1000 1000 1000 Typ. Max. years Unit
M44C260/M48C260
Crystal Brown-out voltage
OSCIN OSCOUT
8991
VBOmax
Equivalentcircuit:
VBOmin
Tamb
Figure Equivalent crystal circuit
8998
Figure Brown-out voltage ambient temperature
0.2@VDD Tamb 25°C
0.8@VDD Tamb 25°C
8999
Figure Output current supply voltage
OL25
9000
Figure Output HIGH current supply voltage
OH25
9001
Tamb
Tamb
Figure Output current standardized 25°C temp.
Figure Output HIGH current standardized 25°C temp.
TELEFUNKEN Semiconductors Rev. 17-Jun-96
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Preliminary Information
M44C260/M48C260
8992
max. min. min. max. Tamb 25°C
8995
typ.
typ.
Tamb 25°C
Figure Output HIGH current output HIGH voltage
8993
Figure Output current output voltage
max.
min. typ. max. Tamb 25°C
8996
typ.
min.
Tamb 25°C
Figure Output HIGH current output HIGH voltage
min. max.
8994
Figure Output current output voltage
typ. min. Tamb 25°C
8997
max.
typ.
Tamb 25°C
Figure Output HIGH current output HIGH voltage
Figure Output current output voltage
(51)
Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
max.
9002
min. typ. Tamb 25°C
9005
Tamb 25°C
max.
typ.
min.
Figure Input current input voltage
min.
Figure Input HIGH current input HIGH voltage
Tamb 25°C max.
typ.
typ.
max.
Tamb 25°C
9006
min.
9003
Figure Input current input voltage
Figure Input HIGH current input HIGH voltage
typ. -100 -120
9004
min.
Tamb 25°C
max.
typ.
max.
Tamb 25°C
9007
min.
Figure Input current input voltage
Figure Input HIGH current input HIGH voltage
TELEFUNKEN Semiconductors Rev. 17-Jun-96
(51)
Preliminary Information
M44C260/M48C260
9008
Tamb 25°C
9009
Tamb 25°C
Figure Input current supply voltage
IL25 IH25
9010
Figure Input HIGH current supply voltage
9011
Tamb
Tamb
Figure Input current standardized 25°C temperature
Figure Input HIGH current standardized 25°C temperature
(51)
Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
Note:
Schmitt-Trigger Inputs
values switch levels standardized supply voltage.
following figures show Schmitt-trigger input specs used timer inputs interrupt inputs.
(VIn /VDD
max. typ. min.
-)/V
Tamb
Tamb
9014
Tamb
9013
Figure Schmitt-trigger positive going threshold voltage
Figure Schmitt-trigger hysteresis supply voltage
VThres
9015
(VIn
min. max. typ.
Tamb
9012
Tamb
Figure Schmitt-trigger negative going threshold voltage
Figure Threshold temperature drift
Note:
pulse recognizable, must minimum long with rise time
TELEFUNKEN Semiconductors Rev. 17-Jun-96
(51)
Preliminary Information
Table coordinates
M44C260 also available form mounting. Therefore substrate, i.e., backside die, sould connected VSS.
size:
size:
Thickness:
M44C260/M48C260
(51) Number
Layout
3.46 4.19
Name BP22 BP23 BP10 BP11 BP12 BP13 IP43 IP42 IP41 IP40 dig. ana. BP30 BP31
ana.
dig.
XTALO
XTALI
NRST
BP20
Point 404.5 809.0 1398.5 1811.0 2223.5 2686.5 3056.0 3056.0 3056.0 3056.0 3056.0 3056.0 3056.0 3056.0
BP21
BP22
Preliminary Information
BP23 BP03 BP10
Point 509.0 965.0 1363.0 1792.0 2247.5 2457.5 2720.5 3301.0
M44C260
Figure layout
BP02
BP11
BP12
BP01 BP00 BP33
Number
BP13
IP43
Name BP32 BP33 BP00 BP01 BP02 BP03 XTALI XTALO dig. ana. NRST BP20 BP21
ana. dig.
BP30
BP32
IP41
IP40
BP31
IP42
10245
TELEFUNKEN Semiconductors Rev. 17-Jun-96 Point 3056.0 2651.5 2247.0 1830.5 1136.5 720.0 303.5 24.0 Point 3741.5 3741.5 3741.5 3741.5 3741.5 3741.5 3741.5 3660.0 3103.0 2625.0 2315.0 2044.0 1707.0 1164.5 424.5
Table coordinates
TELEFUNKEN Semiconductors Rev. 17-Jun-96 size: size: Thickness: Number 4.00 8.55 Name BP22 BP23 BP10 BP11 BP12 BP13 IP43 IP42 IP41 IP40 dig. ana. BP30 BP31
XTALI BP20 BP11
M48C260 also available form mounting. Therefore substrate, i.e., backside die, sould connected VSS.
dig. ana.
XTALO
Point 3577.5 3577.5 3577.5 3577.5 3577.5 3577.5 3577.5 3577.5 3577.5 3577.5 3577.5
NRST
BP21
BP03
BP10
BP23
BP22
Preliminary Information
BP02
Point 1668.0 1060.0 456.0 -3.5 452.5 978.5 1667.5 2463.5 3261.5 4063.5 4757.0 4990.0 5667.0 6462.5
Figure layout
M48C260
Number
M44C260/M48C260
BP01
Name BP32 BP33 BP00 BP01 BP02 BP03 XTALI XTALO dig. ana. NRST BP20 BP21
BP00
BP13
IP43
BP33
ana. dig.
BP12
IP42
BP30
BP31
BP32
IP41
IP40
1xxxx
Point 3577.5 3577.5 3577.5 3109.0 476.0 -4.0 -4.0 -4.0 -4.0 -4.0 -4.0 34.0
Point 7265.0 7768.0 8080.0 8080.0 8080.0 8080.0 7770.0 7264.5 6465.5 5662.5 4990.0 4725.0 4063.0 3263.0 2462.0
(51)
M44C260/M48C260
Package Information
12.9 12.7 9.25 8.75
Package SSO28
Dimensions
2.35 0.30
0.80
0.25 0.25 0.10 10.4 10.50 10.20
technical drawings according specifications
11494
Package SSO20
Dimensions
7.33 7.07
6.39 6.00 5.38 5.20
1.78 1.68 0.38 0.25 0.21 0.05 5.85
0.20 0.09 7.90 7.65
0.65
technical drawings according specifications
11495
(51)
Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
Standard Design M48C260
above standard design, given below please consult TEMIC. BP00
realised). case customer wants another configuration,
BP23
BP01
BP02
BP03
BP10
BP11
BP12
BP13
BP20
BP21
BP22
CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down
BP30
BP31
BP32
BP33
IP40-INT6 IP41-TA
IP42-TB
IP43
CMOS Open drain Open drain Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down
TELEFUNKEN Semiconductors Rev. 17-Jun-96
(51)
Preliminary Information
M44C260/M48C260
BP00
Ordering Information M44C260
Please insert select option setting from list below.
BP01
BP02
BP03
BP10
BP11
BP12
BP13
BP20
BP21
BP22
CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down _.HEX
BP23
BP30
BP31
BP32
BP33
IP40-INT6 IP41-TA
IP42-TB
IP43
CMOS Open drain Open drain Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down CMOS Open drain Open drain Pull-up Pull-down Pull-up Pull-down CMOS Pull-up Pull-down CMOS Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down Pull-up Pull-down
File
CRC: Type: Normal Short Size: KByte
Approval
Date: _._._
Signature:
(51)
Preliminary Information
TELEFUNKEN Semiconductors Rev. 17-Jun-96
M44C260/M48C260
reserve right make changes improve technical design without further notice. Parameters vary different applications. operating parameters must validated each customer application customer. Should buyer TEMIC products unintended unauthorized application, buyer shall indemnify TEMIC against claims, costs, damages, expenses, arising directly indirectly, claim personal damage, injury death associated with such unintended unauthorized use. TEMIC TELEFUNKEN microelectronic GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 7131 2831, Number: 7131 2423
TELEFUNKEN Semiconductors Rev. 17-Jun-96
(51)
Preliminary Information
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