M24C16 M24C08 M24C04 M24C02 M24C01

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M24C16 M24C08 M24C04 M24C02 M24C01

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M24C16, M24C08 M24C04, M24C02, M24C01
16/8/4/2/1 Kbit Serial EEPROM
Wire Serial Interface Supports Protocol
SBGA
Single Supply Voltage: 4.5V 5.5V M24Cxx 2.5V 5.5V M24Cxx-W 1.8V 5.5V M24Cxx-R 1.8V 3.6V M24Cxx-S
PDIP8 (BN) 0.25 frame
SBGA5 (EA) width
Write Control Input BYTE PAGE WRITE Bytes) RANDOM SEQUENTIAL READ Modes Self-Timed Programming Cycle Automatic Address Incrementing Enhanced ESD/Latch-Up Behavior More than Million Erase/Write Cycles More than Year Data Retention
(MN) width
TSSOP8 (DW) width
DESCRIPTION These I2C-compatible electrically erasable programmable memory (EEPROM) devices organized 2048/1024/512/256/128 (M24C16, M24C08, M24C04, M24C02, M24C01), operate with power supply down (for version each device), down (for versions each device). M24C16, M24C08, M24C04, M24C02, M24C01 available Plastic Dual-in-Line, Plastic Small Outline Thin Shrink Small Outline packages. M24C16-S also available Chip Scale package. Table Signal NameE0, Chip Enable
Figure Logic Diagram
E0-E2 M24Cxx
Serial Data Serial Clock Write Control Supply Voltage Ground
AI02033
April 2001
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M24C16, M24C08, M24C04, M24C02, M24C01
Figure ConnectionM24Cxx 16Kb /8Kb /4Kb /2Kb /1Kb
AI02034D
Note: Connected
Figure ConnectionM24Cxx 16Kb /8Kb /4Kb /2Kb /1Kb
AI02035D
Note: Connected
Figure TSSOP ConnectionM24Cxx 16Kb /8Kb /4Kb /2Kb /1Kb
AI02036D
Note: Connected
Figure SBGA Connections (top view, marking side, with balls underside)
M24C16
Ball
AI02796E
2/21
M24C16, M24C08, M24C04, M24C02, M24C01
Table Absolute Maximum Ratings
Symbol TSTG TLEAD VESD Parameter Ambient Operating Temperature Storage Temperature Lead Temperature during Soldering Input Output range Supply Voltage Electrostatic Discharge Voltage (Human Body model) PDIP8: seconds SO8: seconds (max) TSSOP8: seconds (max) Value -0.6 -0.3 4000 Unit
Note: Except rating "Operating Temperature Range", stresses above those listed Table "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, operation device these other conditions above those indicated Operating sections this specification implied. Exposure Absolute Maximum Rating conditions extended periods affect device reliability. Refer also SURE Program other relevant quality documents. IPC/JEDEC J-STD-020A JEDEC JESD22-A114A (C1=100 R1=1500 R2=500
These devices compatible with memory protocol. This wire serial interface that uses bi-directional data serial clock. devices carry built-in 4-bit Device Type Identifier code (1010) accordance with definition. device behaves slave protocol, with memory operations synchronized serial clock. Read Write operations initiated Start condition, generated master. Start condition followed Device Select Code described Table terminated acknowledge bit.
When writing data memory, device inserts acknowledge during time, following master's 8-bit transmission. When data read master, master acknowledges receipt data byte same way. Data transfers terminated Stop condition after Write, after NoAck Read. Power Reset: Lock-Out Write Protect order prevent data corruption inadvertent Write operations during Power-up, Power Reset (POR) circuit included. internal reset held active until reached
Figure Maximum Value versus Capacitance (CBUS) BuVCC Maximum value CBUS (pF)
AI01665
MASTER 100kHz 400kHz CBUS
CBUS 1000
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M24C16, M24C08, M24C04, M24C02, M24C01
Figure Protocol
Input Change
START Condition
STOP Condition
START Condition
STOP Condition
AI00792B
threshold value, operations disabled device will respond command. same way, when drops from operating voltage, below threshold value, operations disabled device will respond command. stable valid must applied before applying logic signal.
SIGNAL DESCRIPTION Serial Clock (SCL) This input signal used strobe data device. applications where this signal used slave devices synchronize slower clock, master must have open drain output, pull-up resistor must connected from Serial Clock (SCL) (Figure indicates value pull-up resistor calculated). most applications, though,
this method synchronization employed, pull-up resistor necessary, provided that master push-pull (rather than open drain) output. Serial Data (SDA) This bi-directional signal used transfer data device. open drain output that wire-OR'ed with other open drain open collector signals bus. pull resistor must connected from Serial Data (SDA) VCC. (Figure indicates value pull-up resistor calculated). Chip Enable (E0, These input signals used value that looked three least significant bits (b3, 7-bit Device Select Code. These inputs must tied VSS, establish Device Select Code.
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M24C16, M24C08, M24C04, M24C02, M24C01
Table Device Select Code
Device Type Identifier M24C01 Select Code M24C02 Select Code M24C04 Select Code M24C08 Select Code M24C16 Select Code Chip Enable
Note: most significant bit, sent first. compared against respective external pins memory device. A10, represent most significant bits address.
Write Control (WC) This input signal useful protecting entire contents memory from inadvertent write operations. Write operations disabled entire memory array when Write Control (WC) driven High. When unconnected, signal internally read VIL, Write operations allowed. When Write Control (WC) driven High, Device Select Address bytes acknowledged, Data bytes acknowledged.
DEVICE OPERATION device supports protocol. This summarized Figure device that sends data defined transmitter, device that reads data receiver. device that controls data transfer known master, other slave device. data transfer only initiated master, which will also provide serial clock synchronization. M24Cxx device always slave communication.
Start Condition Start identified falling edge Serial Data (SDA) while Serial Clock (SCL) stable High state. Start condition must precede data transfer command. device continuously monitors (except during Write cycle) Serial Data (SDA) Serial Clock (SCL) Start condition, will respond unless given. Stop Condition Stop identified rising edge Serial Data (SDA) while Serial Clock (SCL) stable driven High. Stop condition terminates communication between device master. Read command that followed NoAck followed Stop condition force device into Stand-by mode. Stop condition Write command triggers internal EEPROM Write cycle. Acknowledge (ACK) acknowledge used indicate successful byte transfer. transmitter, whether master slave device, releases Serial Data (SDA) after sending eight bits data. During clock pulse period, receiver pulls Serial Data (SDA) acknowledge receipt eight data bits.
Table Operating ModeMode Current Address Read Random Address Read Sequential Read Byte Write Page Write
Note: VIL.
Bytes
Initial Sequence START, Device Select, START, Device Select, Address reSTART, Device Select,
Similar Current Random Address Read START, Device Select,
START, Device Select,
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M24C16, M24C08, M24C04, M24C02, M24C01
Figure Write Mode Sequences with WC=1 (data write inhibited)
Byte Write START DATA STOP DATA
BYTE ADDR
Page Write START DATA
BYTE ADDR
DATA
(cont'd) Page Write (cont'd)
DATA STOP
AI02803C
Data Input During data input, device samples Serial Data (SDA) rising edge Serial Clock (SCL). correct device operation, Serial Data (SDA) must stable during rising edge Serial Clock (SCL), Serial Data (SDA) signal must change only when Serial Clock (SCL) driven Low. Memory Addressing start communication between master slave device, master must initiate Start condition. Following this, master sends Device Select Code, shown Table Serial Data (SDA), most significant first). Device Select Code consists 4-bit Device Type Identifier, 3-bit Chip Enable "Address" (E2, E0). address memory array, 4bit Device Type Identifier 1010b. When Device Select Code received Serial Data (SDA), device only responds
Chip Enable Address same value Chip Enable (E0, inputs. Read/Write (RW). This Read Write operations. match occurs Device Select code, corresponding device gives acknowledgment Serial Data (SDA) during time. device does match Device Select code, deselects itself from bus, goes into Standby mode. Devices with larger memory capacities (the M24C16, M24C08 M24C04) need more address bits. available devices that need address line available devices that need address line available devices that need address line (see Figures Table details). Using inputs pins, eight M24C02 M24C01), four M24C04, M24C08 M24C16 device connected bus. each case,
6/21
M24C16, M24C08, M24C04, M24C02, M24C01
Figure Write Mode Sequences with WC=0 (data write enabled)
BYTE WRITE START DATA STOP DATA DATA
BYTE ADDR
PAGE WRITE START DATA
BYTE ADDR
(cont'd)
PAGE WRITE (cont'd) DATA
STOP
AI02804
hybrid cases, this gives total memory capacity Kbits, KBytes (except where M24C01 devices used). Write Operations Following Start condition master sends Device Select Code with reset device acknowledges this, shown Figure waits address byte. device responds address byte with acknowledge bit, then waits data byte. Writing memory inhibited Write Control (WC) driven High. Write instruction with Write Control (WC) driven High (during period time from Start condition until address bytes) will modify memory contents, accompanying data bytes acknowledged, shown Figure When master generates Stop condition immediately after bit" time slot), either Byte Write Page
Write, internal memory Write cycle triggered. Stop condition other time slot does trigger internal Write cycle. During internal Write cycle, Serial Data (SDA) disabled internally, device does respond requests. Byte Write After Device Select code address byte, master sends data byte. addressed location Write-protected, Write Control (WC) being driven High, device replies with NoAck, location modified. instead, addressed location Writeprotected, device replies with Ack. master terminates transfer generating Stop condition, shown Figure Page Write Page Write mode allows bytes written single Write cycle, provided that they located same 'row' memory:
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M24C16, M24C08, M24C04, M24C02, M24C01
Figure Write Cycle Polling Flowchart using
WRITE Cycle Progres
START Condition DEVICE SELECT with
First byte instruction with already decoded device
Returned
Next Operation Addressing Memory
ReSTART
Send Address Receive
STOP
START Condition
DATA WRITE Operation
DEVICE SELECT with
Continue WRITE Operation
Continue Random READ Operation
AI01847C
that most significant memory address bits (b7-b4) same. more bytes sent than will row, condition known `roll-over' occurs. This should avoided, data starts become overwritten implementation dependent way. master sends from bytes data, each which acknowledged device Write Control (WC) Low. Write Control (WC) High, contents addressed memory location modified, each data byte followed NoAck. After each byte transferred, internal byte address counter (the least significant address bits only) incremented. transfer terminated master generating Stop condition.
Minimizing System Delays Polling During internal Write cycle, device disconnects itself from bus, writes copy data from internal latches memory cells. maximum Write time (tw) shown Tables typical time shorter. make this, polling sequence used master. sequence, shown Figure Initial condition: Write cycle progress. Step master issues Start condition followed Device Select Code (the first byte instruction). Step device busy with internal Write cycle, will returned master goes back Step device terminated internal Write cycle, responds with Ack, indicating that device ready receive second part instruction (the
8/21
M24C16, M24C08, M24C04, M24C02, M24C01
Figure Read Mode SequenceACK CURRENT ADDRESS READ START DATA STOP START
RANDOM ADDRESS READ START
DATA STOP
AI01942
BYTE ADDR
SEQUENTIAL CURRENT READ START
DATA
DATA STOP
SEQUENTIAL RANDOM READ START
START
BYTE ADDR
DATA
DATA STOP
Note: seven most significant bits Device Select Code Random Read bytes) must identical.
first byte this instruction having been sent during Step Read Operations Read operations performed independently state Write Control (WC) signal. Random Address Read dummy Write performed load address into address counter shown Figure without sending Stop condition. Then, master sends another Start condition, repeats Device Select Code, with
device acknowledges this, outputs contents addressed byte. master must acknowledge byte, terminates transfer with Stop condition. Current Address Read device internal address counter which incremented each time byte read. Current Address Read operation, following Start condition, master only sends Device Select Code with device acknowledges this, outputs byte addressed internal address counter. counter then incremented. master
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M24C16, M24C08, M24C04, M24C02, M24C01
terminates transfer with Stop condition, shown Figure without acknowledging byte. Sequential Read This operation used after Current Address Read Random Address Read. master does acknowledge data byte output, sends additional clock pulses that device continues output next byte sequence. terminate stream bytes, master must acknowledge last byte, must generate Stop condition, shown Figure output data comes from consecutive addresses, with internal address counter automatically incremented after each byte output. After last memory address, address counter `rolls-over', device continues output data from memory address 00h. Acknowledge Read Mode Read commands, device waits, after each byte read, acknowledgment during time. master does drive Serial Data (SDA) during this time, device terminates data transfer switches Stand-by mode.
Table Measurement ConditionInput Rise Fall Times Input Pulse Voltages Input Output Timing Reference Voltages 0.2VCC 0.8VCC 0.3VCC 0.7VCC
Figure Testing Input Output Waveform0.8VCC 0.7VCC 0.3VCC
AI00825
0.2VCC
Table Input Parameters1 kHz)
Symbol ZWCL ZWCH Parameter Input Capacitance (SDA) Input Capacitance (other pins) Input Impedance Input Impedance Pulse width ignored (Input Filter SDA) 0.7VCC Single glitch Test Condition Min. Max. Unit
Note: Sampled only, 100% tested.
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M24C16, M24C08, M24C04, M24C02, M24C01
Table Characteristics
Symbol Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Test Condition VOUT VCC, Hi-Z VCC=5V, fc=400kHz (rise/fall time 30ns) series: =2.5V, fc=400kHz (rise/fall time 30ns) Supply Current series: =1.8V, fc=100kHz (rise/fall time 30ns) series: =1.8V, fc=400kHz (rise/fall time 30ns) ICC1 Supply Current (Stand-by) series: -R,S series: Input Voltage (E0, SCL, SDA) series: -R,S series: 0.7VCC 0.7VCC Output Voltage series: -R,S series:
Note: This preliminary data.
Min.
Max. 0.81 0.81 0.31 VCC1 0.25 VCC1 VCC+1 VCC+1 0.21
Unit
Input High Voltage (E0, SCL, SDA) Input Voltage (WC) Input High Voltage (WC)
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M24C16, M24C08, M24C04, M24C02, M24C01
Table Characteristics1
Symbol ICC1 Parameter Input Leakage Current (SCL, SDA) Output Leakage Current Supply Current Supply Current (Stand-by) Input Voltage (E0, SCL, SDA) Input High Voltage (E0, SCL, SDA) Input Voltage (WC) Input High Voltage (WC) Output Voltage Test Condition VOUT VCC, Hi-Z VCC=5V, fc=400kHz (rise/fall time 30ns) 0.7VCC 0.7VCC Min. Max. VCC+1 VCC+1 Unit
Note: This preliminary data.
Table CharacteristicM24C16, M24C08, M24C04, M24C02, M24C01 Symbol Alt. Parameter VCC=4.5 TA=-40 85°C tCH1CH2 tCL1CL2 tDH1DH2 tDL1DL2 tCHDX tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV tCLQX
Note:
VCC=4.5 TA=-40 125°C4
Unit
tSU:STA tHIGH tHD:STA tHD:DAT tLOW tSU:DAT tSU:STO tBUF fSCL
Clock Rise Time Clock Fall Time Rise Time Fall Time Clock High Input Transition Clock Pulse Width High Input Clock (START) Clock Input Transition Clock Pulse Width Input Transition Clock Transition Clock High Input High (STOP) Input High Input (Bus Free) Clock Data Valid Data Hold Time After Clock Clock Frequency Write Time
reSTART condition, following write cycle. Sampled only, 100% tested. avoid spurious START STOP conditions, minimum delay placed between SCL=1 falling rising edge SDA. This preliminary data.
12/21
M24C16, M24C08, M24C04, M24C02, M24C01
Table CharacteristicM24C16, M24C08, M24C04, M24C02, M24C01 Symbol Alt. Parameter series series series VCC=2.5 VCC=1.8 VCC=1.8 Unit TA=-40 85°C TA=-40 85°C4 TA=-40 85°C4 tCH1CH2 tCL1CL2 tDH1DH2
1000
tSU:STA tHIGH tHD:STA
Clock Rise Time Clock Fall Time Rise Time Fall Time Clock High Input Transition Clock Pulse Width High Input Clock (START)
4700 4000 4000 4000
1000
tDL1DL2 tCHDX tCHCL tDLCL tCLDX tCLCH tDXCX tCHDH tDHDL tCLQV tCLQX
Note:
tHD:DAT Clock Input Transition tLOW tSU:DAT Clock Pulse Width Input Transition Clock Transition
tSU:STO Clock High Input High (STOP) tBUF fSCL Input High Input (Bus Free) Clock Data Valid Data Hold Time After Clock Clock Frequency Write Time
3500
reSTART condition, following write cycle. Sampled only, 100% tested. avoid spurious START STOP conditions, minimum delay placed between SCL=1 falling rising edge SDA. This preliminary data.
13/21
M24C16, M24C08, M24C04, M24C02, M24C01
Figure WaveformtCHCL tCLCH
tDLCL tCHDX START Condition Input tCLDX tDXCX Change tCHDH tDHDL START STOP Condition Condition
tCHDH STOP Condition Write Cycle tCHDX START Condition
tCLQV Data Valid tCLQX
AI00795C
14/21
M24C16, M24C08, M24C04, M24C02, M24C01
Table Ordering Information Scheme
Example: M24C08
Memory Capacity Kbit (2048 Kbit (1024 Kbit (512 Kbit (256 Kbit (128
Option Tape Reel Packing
Temperature Range
Operating Voltage blank (400 kHz) (400 kHz) (100 kHz) (400 kHz)
Package PDIP8 (0.25 frame) (150 width) TSSOP8 (169 width) SBGA5 width)
Note: SBGA5 package available only M24C16, 1.8V 3.6V (400 kHz), -40°C 85°C (M24C16-SEA6)
ORDERING INFORMATION Devices shipped from factory with memory content (FFh). notation used device number shown Table list available options (speed, package, etc.) further information aspect this device, please contact your nearest Sales Office.
15/21
M24C16, M24C08, M24C04, M24C02, M24C01
PDIP8 Plastic DIP, 0.25mm lead frame
PDIP-8
Note: Drawing scale.
PDIP8 Plastic DIP, 0.25mm lead frame
Symb. Typ. 3.30 2.92 3.30 0.46 1.52 0.25 9.27 7.87 6.35 2.54 7.62 0.38 2.92 0.36 1.14 0.20 9.02 7.62 6.10 4.95 0.56 1.78 0.36 10.16 8.26 7.11 10.92 3.81 0.130 0.115 0.130 0.018 0.060 0.010 0.365 0.310 0.250 0.100 0.300 Min. Max. 5.33 0.015 0.115 0.014 0.045 0.008 0.355 0.300 0.240 0.195 0.022 0.070 0.014 0.400 0.325 0.280 0.430 0.150 Typ. Min. Max. 0.210 inche
16/21
M24C16, M24C08, M24C04, M24C02, M24C01
narrow lead Plastic Small Outline, mils body width
SO-a
Note: Drawing scale.
narrow lead Plastic Small Outline, mils body width
Symb. Typ. 1.27 Min. 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 0.10 Max. 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 0.90 0.050 Typ. Min. 0.053 0.004 0.013 0.007 0.189 0.150 0.228 0.010 0.016 0.004 Max. 0.069 0.010 0.020 0.010 0.197 0.157 0.244 0.020 0.035 inche
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M24C16, M24C08, M24C04, M24C02, M24C01
TSSOP8 lead Thin Shrink Small Outline
TSSOP
Note: Drawing scale.
TSSOP8 lead Thin Shrink Small Outline
Symb. Typ. 0.65 0.05 0.85 0.19 0.09 2.90 6.25 4.30 0.50 0.08 Min. Max. 1.10 0.15 0.95 0.30 0.20 3.10 6.50 4.50 0.70 0.026 0.002 0.033 0.007 0.004 0.114 0.246 0.169 0.020 0.003 Typ. Min. Max. 0.043 0.006 0.037 0.012 0.008 0.122 0.256 0.177 0.028 inche
18/21
M24C16, M24C08, M24C04, M24C02, M24C01
SBGA5 (EA) Underside view (ball side)
BALL
SBGA-00
Note: Drawing scale.
SBGA5 ball Shell Ball Grid Array
Symb. Typ. ball diameter 0.430 0.180 1.900 1.190 1.750 1.070 0.800 0.350 Min. 0.380 0.150 1.870 1.160 1.720 1.040 0.770 0.320 Max. 0.480 0.210 1.930 1.220 1.780 1.100 0.830 0.380 Typ. 0.017 0.007 0.075 0.047 0.069 0.042 0.031 0.014 Min. 0.015 0.006 0.074 0.046 0.068 0.041 0.030 0.013 Max. 0.019 0.008 0.076 0.048 0.070 0.043 0.033 0.015 inche
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M24C16, M24C08, M24C04, M24C02, M24C01
Table Revision History
Date 10-Dec-1999 18-Apr-2000 05-May-2000 23-Nov-2000 Rev. Description Revision TSSOP8 Turned-Die package removed order information) Lead temperature added TSSOP8 table Labelling change Fig-2D, correction values main caption Tab-13 Extra labelling Fig-2D SBGA package information removed annex document range changed being range, range added SBGA package information back this document Lead Soldering Temperature Absolute Maximum Ratings table amended Write Cycle Polling Flow Chart using illustration updated References PSDIP changed PDIP Package Mechanical data updated Wording brought line with standard glossary Revision characteristics serie
19-Feb-2001
20-Apr-2001
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M24C16, M24C08, M24C04, M24C02, M24C01
Information furnished believed accurate reliable. However, STMicroelectronics assumes responsibility consequences such information infringement patents other rights third parties which result from use. license granted implication otherwise under patent patent rights STMicroelectronics. Specifications mentioned this publication subject change without notice. This publication supersedes replaces information previously supplied. STMicroelectronics products authorized critical components life support devices systems without express written approval STMicroelectronics. logo registered trademark STMicroelectronics other names property their respective owners 2001 STMicroelectronics Rights Reserved STMicroelectronics GROUP COMPANIES Australia Brazil China Finland France Germany Hong Kong India Italy Japan Malaysia Malta Morocco Singapore Spain Sweden Switzerland United Kingdom U.S.A. www.st.com
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M24C16 M24C08 M24C04 M24C02 M24C01

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