LXT983 983A

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LXT983/983A
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
LXT983 5-port 10/100 Class Repeater that fully compliant with IEEE 802.3 standards. Four ports directly support 100BASE-TX/10BASE-T copper media also support 100BASE-FX fiber media pseudo-ECL (PECL) interfaces. fifth port, 100-Mbps Media Independent Interface (MII), connects Media Access Controllers (MACs) bridge/ switch applications. Mbps, also configured interface another device, such LXT970. This data sheet applies LXT983 products (LXT983, LXT983A, subsequent variants), except specifically noted. LXT983 provides auto-negotiation with parallel detection four ports. These ports also configured user. LXT983 provides internal repeater state machines-one operating Mbps Mbps. Once configured, LXT983 automatically connects each port appropriate repeater. LXT983 provides Inter-Repeater Backplanes (IRBs) expansion-one operating Mbps Mbps. ports logically combined into repeater.
Product Features
Four 10/100 ports include: Complete twisted-pair PHYs with integrated filters. 100BASE-FX PECL interfaces. 10/100 port connection either PHY. Independent segments Mbps operation.
Cascadable IRBs. Integrated per-port drivers with userselectable modes. Integrated per-segment drivers collisions activity. Available 208-pin package. Case Temperature Range: 0-115°C.
January 2001, this document replaces Level document LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater.
Order Number: 249112-001 January 2001
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. LXT983/983A contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2001 *Third-party brands names property their respective owners.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Contents
Assignments Signal Descriptions Functional Description.16
Introduction.16 2.1.1 TP/FX Port Configuration 2.1.2 Port Configuration 2.1.3 Interface Descriptions.18 2.1.4 Repeater Operation.21 Requirements 2.2.1 Power 2.2.2 Clock 2.2.3 Bias Current 2.2.4 Reset 2.2.5 Pull-ups Operation.23 2.3.1 Power-Up Reset Conditions 2.3.2 Port LEDs 2.3.3 Segment LEDs Operation.25 2.4.1 Access.26 Port Operation 2.5.1 Mode Operation 2.5.2 Mode Operation.28 2.5.3 Port Timing Considerations Design Recommendations 3.1.1 General Design Guidelines 3.1.2 Power Supply Filtering 3.1.3 Power Ground Plane Layout Considerations 3.1.4 Terminations.32 3.1.5 RBIAS 3.1.6 Twisted-Pair Interface 3.1.7 Fiber Interface 3.1.8 Magnetics Information Typical Application Circuitry
Application Information
Test Specifications Mechanical Specifications.56
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figures
LXT983/983A Block Diagram. LXT983 Assignments Typical Managed Repeater Architectures Typical Hybrid Switch/Repeater Application Typical Application Block Diagram Block Diagram (Port Operation Timing Issues Unmanaged 10/100 Repeater Stack Hybrid Switch/Repeater Application Balanced 10/100 Performance. Hybrid Switch/Repeater Application Weighted Toward 100M Performance Power Ground Connections Typical Fiber Port Interface Typical Twisted-Pair Port Interface Typical Mbps Implementation Typical Mbps Implementation Typical Reset Circuit (983reset.vsd) Mbps Port-to-Port Delay Timing 100BASE-TX Transmit Timing Mode 100BASE-TX Receive Timing Mode 100BASE-TX Transmit Timing Mode 100BASE-TX Receive Timing Mode 100BASE-FX Transmit Timing Mode 100BASE-FX Receive Timing Mode 100BASE-FX Transmit Timing Mode 100BASE-FX Receive Timing Mode 10BASE-T Transmit Timing Mode 10BASE-T Receive Timing Mode Mbps Timing Mbps Receive Timing Mbps Transmit Timing LXT983 Package Specifications
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Tables
Mode Control Signal Descriptions Twisted-Pair Port Signal Descriptions Fiber Port Signal Descriptions. Mode Signal Descriptions Mode Signal Descriptions.10 Inter-Repeater Backplane Signal Descriptions.11 Signal Descriptions.13 Power Supply Indication Signal Descriptions Miscellaneous Signal Descriptions.15 Manual Speed Selection Mode Indications Mode Indications Mode Indications Signal Types.27 Signal Details (Port Mode Speed Control Magnetics Specifications.34 Absolute Maximum Ratings.40 Operating Conditions.40 Input Clock Requirements Electrical Characteristics Mbps Electrical Characteristics Mbps Electrical Characteristics 100BASE-TX Transceiver Electrical Characteristics.42 100BASE-FX Transceiver Electrical Characteristics.43 10BASE-T Transceiver Electrical Characteristics Mbps Port-to-Port Delay Timing Parameters 100BASE-TX Transmit Timing Parameters Mode 100BASE-TX Receive Timing Parameters Mode 100BASE-TX Transmit Timing Parameters Mode 100BASE-TX Receive Timing Mode 100BASE-FX Transmit Timing Parameters Mode 100BASE-FX Receive Timing Mode MII.49 100BASE-FX Transmit Timing Mode 100BASE-FX Receive Timing Mode 10BASE-T Transmit Timing Parameters Mode 10BASE-T Receive Timing Parameters Mode Mbps Timing Parameters Mbps Receive Timing Parameters1 Mbps Transmit Timing Parameters
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Revision History
Revision Date Description
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure LXT983/983A Block Diagram
LXT983
Mbps Backplane 10BASE-T Repeater Port Switching Logic 10/100 E'net 10/100 E'net 10/100 E'net 10/100 E'net Twisted Pair_I/O Fiber_I/O Twisted Pair_I/O Fiber_I/O Twisted Pair_I/O Fiber_I/O Twisted Pair_I/O Fiber_I/O Reversible
100M
Mbps Backplane
100BASE-T Repeater
Control Port Segment Status Indicators
Control Logic Clocking
Drivers
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Assignments Signal Descriptions
Figure LXT983 Assignments
IR100CLK IR100DAT4 IR100DAT3 IR100DAT2 IR100DAT1 IR100DAT0 IR100DV IR100DEN IR100COL IR100SNGL IR100CFSBP IR100CFS MII_RXD3 MII_RXD2 MII_RXD1 MII_RXD0 GNDA MII_RXDV MII_RXCLK MII_RXER MII_TXER MII_TXCLK MII_TXEN MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3 MII_COL MII_CRS IR10CLK IR10DAT IR10ENA IR10DEN IR10CFSBP IR10COLBP IR10COL IR10CFS RESET CLK25 AUTO_BLINK/GND MACACTIVE HOLDCOL COL10_LED COL100_LED ACT10_LED ACT100_LED VCCV GNDV PORT5_SEL PORT5_SPD GNDR
Part
LXT983 XXXXXX XXXXXXXX
.LEDSEL0 .LEDSEL1 .VCC .VCC .VCC .VCC .GND .VCC .GND .N/C .N/C .N/C .N/C .N/C .N/C .N/C .N/C .N/C .N/C .PORT1_SPD0 .PORT1_SPD1 .PORT2_SPD0 .PORT2_SPD1 .PORT3_SPD0 .PORT3_SPD1 .PORT4_SPD0 .PORT4_SPD1 .PORT1_LED1 .PORT1_LED2 .PORT1_LED3 .GND .PORT2_LED1 .PORT2_LED2 .PORT2_LED3 .GND .PORT3_LED1 .PORT3_LED2 .PORT3_LED3 .VCC .VCCV .GNDV .GND .PORT4_LED1 .PORT4_LED2 .PORT4_LED3 .GND .PORT5_LED1 .PORT5_LED2 .PORT5_LED3 .GND .GND .FIBIP1
*Note: Signal Description, Table page (LXT983) Table page (LXT983A).
Package Topside Markings Marking Part Definition LXT983 unique identifier this product family. Identifies particular silicon "stepping" (Refer Specification Update additional stepping information.) Identifies batch. Identifies Finish Process Order.
TPIP4. TPIN4. VCCR. TPOP4. GNDT. TPON4. VCCT. FIBOP4. FIBON4. SIGDET4. FIBIN4. FIBIP4. GNDR. TPIP3. TPIN3. VCCR. TPOP3. GNDT. TPON3. VCCT. FIBOP3. FIBON3. SIGDET3. FIBIN3. FIBIP3. GNDA. RBIAS. GNDR. TPIP2. TPIN2. VCCR. TPOP2. GNDT. TPON2. VCCT. FIBOP2. FIBON2. SIGDET2. FIBIN2. FIBIP2. GNDR. TPIP1. TPIN1. VCCR. TPOP1. GNDT. TPON1. VCCT. FIBOP1. FIBON1. SIGDET1. FIBIN1.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Table
Mode Control Signal Descriptions
Symbol Type1 Description Speed Select Ports through These pins configure associated port follows: Input, Latched reset, SPD1 Input, SPD0 Mode Allow 10/100 Auto-Negotiation/Parallel Detection. Force 10BASE-T. Force 100BASE-FX. Force 100BASE-TX.
PORT1_SPD0 PORT1_SPD1 PORT2_SPD0 PORT2_SPD1 PORT3_SPD0 PORT3_SPD1 PORT4_SPD0 PORT4_SPD1
PORT5_SPD
Speed Select Port Selects operating speed (MAC) interface. Also selects which segment statistics kept. High Mbps, Mbps. (Port speed Mbps available when mode selected.) Mode Select Port Selects operating mode interface. monitored power-up reset. Subsequent changes have effect. High Mode (LXT983 acts side MII). Mode (LXT983 acts side MII).
PORT5_SEL
Input
Input contains pull-up. Transistor-Transistor Logic.
Table
149, 136, 121, 108, 146, 133, 118, 105,
Twisted-Pair Port Signal Descriptions
Symbol Type Analog Output Description Twisted-Pair Outputs Ports through These pins positive negative outputs from respective ports twisted-pair line drivers. These pins left open when used. Twisted-Pair Inputs Ports through These pins positive negative inputs respective ports twisted-pair receivers. These pins left open when used.
TPOP1, TPON1 TPOP2, TPON2 TPOP3, TPON3 TPOP4, TPON4 TPIP1, TPIN1 TPIP2, TPIN2 TPIP3, TPIN3 TPIP4, TPIN4 Analog Input
Table
153, 140, 125, 112, 157, 144, 129, 116,
Fiber Port Signal Descriptions
Symbol Type Description Fiber Outputs Ports through These pins positive negative outputs from respective ports PECL drivers. These pins left open when used.
FIBOP1, FIBON1 FIBOP2, FIBON2 FIBOP3, FIBON3 FIBOP4, FIBON4 FIBIP1, FIBIN1 FIBIP2, FIBIN2 FIBIP3, FIBIN3 FIBIP4, FIBIN4 SIGDET1 SIGDET2 SIGDET3 SIGDET4 Signal Detect Ports through Signal detect fiber ports. These pins left open when used. PECL Input Fiber Inputs Ports through These pins positive negative inputs respective ports PECL receivers. These pins left open when used. PECL Output
PECL Input
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Table
Mode Signal Descriptions
Symbol Type1 Output Output Output Output Input Output Input Input Output Output Description Receive Data. LXT983 transmits received data controller these outputs. Data driven falling edge MII_RXCLK. Receive Data Valid. Active High signal, synchronous MII_RXCLK, indicates valid data MII_RXD<3:0>. Receive Clock. receive clock expansion port. This clock derived from CLK25 input (refer Table Receive Error. Active High signal, synchronous MII_RXCLK, indicates invalid data MII_RXD<3:0>. Transmit Error. This 100M-only signal. asserts this input when error occurred transmit data stream. LXT983 responds sending `Invalid Code Symbols' line. Transmit Clock. continuous output derived from input clock. Transmit Enable. External controllers drive this input High indicate that data being transmitted MII_TXD<3:0> pins. this input unused. Transmit Data. External controllers these inputs transmit data LXT983. device samples MII_TXD<3:0> rising edge MII_TXCLK, when MII_TXEN High. Collision. LXT983 drives this signal High indicate that collision occurred. Carrier Sense. Active High signal indicates that LXT983 transmitting receiving.
MII_RXD0 MII_RXD1 MII_RXD2 MII_RXD3 MII_RXDV MII_RXCLK MII_RXER
MII_TXER
MII_TXCLK MII_TXEN MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3 MII_COL MII_CRS
interface pins reverse direction based PHY/MAC mode. Direction listed mode.
Table
Mode Signal Descriptions
Symbol MII_RXD0 MII_RXD1 MII_RXD2 MII_RXD3 MII_RXDV Input Input Input Output Input Receive Data Valid. asserts this active High signal, synchronous MII_RXCLK, indicate valid data MII_RXD<3:0>. Receive Clock. receive clock expansion port. This clock. Receive Error. asserts this active High signal, synchronous MII_RXCLK, indicate invalid data MII_RXD<3:0>. Transmit Error. LXT983 asserts this signal when error occurred Transmit data stream. Transmit Clock. continuous input clock. Must supplied from same source CLK25 system clock. Input Receive Data. LXT983 receives data from these pins. Data sampled rising edge MII_RXCLK. Type1 Description
MII_RXCLK
MII_RXER
MII_TXER MII_TXCLK
interface pins reverse direction based PHY/MAC mode. Direction listed mode.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Table
Mode Signal Descriptions (Continued)
Symbol MII_TXEN MII_TXD0 MII_TXD1 MII_TXD2 MII_TXD3 MII_COL MII_CRS Input Input Collision. asserts this active High signal notify LXT983 that collision occurred. Carrier Sense. asserts this active High signal notify LXT983 that transmitting receiving. Output Transmit Data. LXT983 drives these outputs transmit data PHY. device drives MII_TXD<3:0> rising edge MII_TXCLK, when MII_TXEN High. Type1 Output Description Transmit Enable. LXT983 drives this output High indicate that data being transmitted MII_TXD<3:0> pins.
interface pins reverse direction based PHY/MAC mode. Direction listed mode.
Table
Inter-Repeater Backplane Signal Descriptions
Symbol Type1 Mbps Signals Description2
IR100DAT0 IR100DAT1 IR100DAT2 IR100DAT3 IR100DAT4 Tri-state Schmitt CMOS I/O, Mbps Clock. This bidirectional, non-continuous, clock recovered from received network traffic. Schmitt triggering used increase noise immunity. This signal must pulled when idle. pull-up resistor both sides `245 buffer recommended. Mbps Driver Enable. This output provides directional control external bidirectional transceiver (`245) used buffer Mbps multiboard applications. must pulled resistor. When there multiple devices board, IR100DEN outputs together. IR100DEN tied directly `245, attach on-board IR100DAT, IR100CLK IR100DV signals side `245, connect off-board signals side `245. Mbps Data Valid. This active signal indicates repeater port activity. IR100DV frames clock data packet backplane. This signal must pulled resistor. Mbps Collision Force Sense. This three-level signal determines number active ports "logical repeater". High level (5V) indicates ports active; Mid-level (approx. 2.8V) indicates port active; level (0V) indicates more than port active, resulting collision. IR100CFS connects between chips same board. connect between boards. This signal requires pull-up resistor. Tri-state Schmitt CMOS I/O, Mbps Data. These bidirectional signals carry data Mbps IRB. Data driven falling edge sampled rising edge IR100CLK. These signals buffered between boards.
IR100CLK
IR100DEN
Output,
IR100DV
Schmitt CMOS I/O,
IR100CFS
Analog
Clamp. will clamp input absence power. Input contains pull-up. Input contains pull-down. Input Output. Open Drain Transistor-Transistor Logic. Even used, required pull-up resistors must installed listed above.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Table
Inter-Repeater Backplane Signal Descriptions (Continued)
Symbol Type1 Analog Schmitt CMOS I/O, Schmitt I/O, Description2 Mbps Collision Force Sense Backplane. IR100CFSBP functions same IR100CFS; however, IR100CFSBP connects between chips with ChipID different boards. This signal requires single pull-up resistor each stack. Mbps Single Driver State. This active signal asserted device with ChipID when packet being received from more ports. should connected between boards. Mbps Multiple Driver State. This active signal asserted device with ChipID when packet being received from more than port (collision). should connected between boards. Mbps Signals CMOS Tri-state Schmitt CMOS I/O, Mbps Data. This bidirectional signal carries data corresponding IRB. Data driven sampled rising edge corresponding IRCLK. This signal must pulled resistor. Between boards, this signal buffered. Mbps Clock. This bidirectional, non-continuous, clock recovered from received network traffic. During idle periods, output tristated. Schmitt triggering used increase noise immunity. Mbps Driver Enable. This output provides directional control external bidirectional transceiver (`245) used buffer IRBs multi-board applications. must pulled resistor. When there multiple devices board, IR10DEN outputs together. IR10DEN tied directly `245, attach on-board IR10DAT, IR10CLK, IR10ENA signals side `245, connect off-board signals side `245. Mbps Enable. This active output indicates carrier presence IRB. pull-up resistor required pull IR10ENA output High when idle. When there multiple devices, IR10ENA outputs together. This signal buffered between boards. Mbps Collision. This output driven indicate that collision occurred Mbps segment. resistor required each pull this signal High when there collision. This signal should connected between boards buffered. Mbps Collision Backplane. This active output same function IR10COL, used between boards. Attach this signal only from device with ChipID backplane connector, without buffering. output must pulled resistor system. Mbps Collision Force Sense. This three-state analog signal indicates transmit collision when driven Low. requires 680, resistor. connect between boards, buffer.
IR100CFSBP
IR100SNGL
IR100COL
IR10DAT
IR10CLK
IR10DEN
Output,
IR10ENA
CMOS
IR10COL
CMOS
IR10COLBP
CMOS
IR10CFS
Analog I/O,
Clamp. will clamp input absence power. Input contains pull-up. Input contains pull-down. Input Output. Open Drain Transistor-Transistor Logic. Even used, required pull-up resistors must installed listed above.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Table
Inter-Repeater Backplane Signal Descriptions (Continued)
Symbol Type1 Analog Description2 Mbps Collision Force Sense Backplane. This signal functions same IR10CFS, connects between boards. Attach this signal only from device with ChipID backplane connector, without buffering. This signal requires 330, pull-up resistor system. Active. TTL-level signal which external MAC's transmit enable attached. Macactive allows repeater-not MAC-to drive three-level IRCFS pin. Active High input allows external ASICs connect with Mbps IRB. Driving data onto requires external ASIC assert MACACTIVE High clock cycle, then assert IR10ENA Low. ASIC monitors IR10COL (active Low) collisions. (See "MAC Access" page 26.) Hold Collision Mbps Mode. This active High signal driven device with extend non-local transmit collision other devices same board. HOLDCOL signals from different boards should attached together.
IR10CFSBP
MACACTIVE
Input
HOLDCOL
Clamp. will clamp input absence power. Input contains pull-up. Input contains pull-down. Input Output. Open Drain Transistor-Transistor Logic. Even used, required pull-up resistors must installed listed above.
Table
Signal Descriptions
Symbol Type Input Mode Select. Must static. Mode Mode Mode Description
LEDSEL0 LEDSEL1 PORT1_LED1 PORT2_LED1 PORT3_LED1 PORT4_LED1 PORT5_LED1 PORT1_LED2 PORT2_LED2 PORT3_LED2 PORT4_LED2 PORT5_LED2 PORT1_LED3 PORT2_LED3 PORT3_LED3 PORT4_LED3 PORT5_LED3 COL10_LED
Output
Driver Ports through Programmable driver. Active Low. "Port LEDs" page
Output
Driver Ports through Programmable driver. Active Low. "Port LEDs" page
Output
Driver Ports through Programmable driver. Active Low. "Port LEDs" page
Output
Mbps Collision Driver. Active indicates collision segment.
Input contains pull-down. Transistor-Transistor Logic.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Table
Signal Descriptions (Continued)
Symbol Type Output Output Output Description Mbps Collision Driver. Active indicates collision 100M segment. Mbps Activity Driver. Active indicates activity segment. Mbps Activity Driver. Active indicates activity 100M segment.
COL100_LED ACT10_LED ACT100_LED
Input contains pull-down. Transistor-Transistor Logic.
Table
170, 201, 203-206 158, 159, 163, 167, 174, 178, 200,
Power Supply Indication Signal Descriptions
Symbol Type Description Power Supply Inputs. Each these pins must connected common power supply. de-coupling capacitor ground should supplied every these pins.
Digital
Ground. Connect each these pins ground. Digital using LXT983 LXT980-based design, LXT983 Chip Chip have tied ground.
(LXT983) VCCV GNDV VCCT
Digital
Ground. Connect this digital ground. Note: LXT983A, refer Table page Supply Inputs. Each these pins must connected common power supply. de-coupling capacitor GNDV should supplied every these pins Ground. Transmitter Supply Inputs. Each these pins must connected common power supply. de-coupling capacitor GNDT should supplied every these pins. Transmitter Ground. Receiver Supply Inputs. Each these pins must connected common power supply. de-coupling capacitor GNDR should supplied every these pins Receiver Ground. RBIAS. Provides bias current internal circuitry. bias current provided through external 22.1 resistor GNDA. Analog Ground.
111, 124, 139, 109, 122, 137, 107, 120, 135, 104, 117, 132, 145,
Analog Analog Analog
GNDT
Analog
VCCR
Analog
GNDR RBIAS GNDA
Analog Analog Analog
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Table
Miscellaneous Signal Descriptions
Symbol Type1 Schmitt, CMOS Input, Schmitt CMOS Input Description Reset. This active input causes internal circuits state machines reset. power-up, devices should brought reset until power supply stabilized reached When there multiple devices, recommended that supplied common reset that driven `LS14 similar device. system clock. Drive with levels. First Position Select. multi-chip configurations, this identifies device each board that will drive HOLDCOL signal extend nonlocal collisions other devices board. first device PCB. High other devices PCB. using LXT983 LXT980-based design, Chip LXT980 must renamed LXT983. LXT983 Chip 1and Chip have tied ground.
RESET
CLK25
Input
58-70, 101, 102, 103, 190-199
AUTO_BLINK (LXT983A)
Input,
Auto_Blink. Setting this High disables Blink indication (used show Link" condition) Mode PortnLED3. Note: LXT983, refer Table page
Connects. Leave these pins unconnected.
Clamp. will clamp input absence power. Pull Down Transistor-Transistor Logic
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Functional Description
Introduction
fully integrated IEEE 802.3 repeater capable Mbps Mbps functionality, LXT983 very versatile device allowing great flexibility Ethernet design solutions. Figure Figure show some typical applications, Figure shows more complete circuit. Refer "Application Information" page specific circuit implementations. This multi-port repeater provides four 10BASE-T/100BASE-TX/100BASE-FX ports. addition, there bidirectional Media Independent Interface (MII) expansion port which connected either 10/100 MAC, Mbps PHY. LXT983 provides repeater state machines Inter-Repeater Backplanes (IRB) single chip-one Mbps operation Mbps operation. Mbps repeater fully meets IEEE 802.3 Class requirements. Each port's operating speed selected independent other ports. auto-negotiation capability LXT983 allows poll connected nodes configure itself accordingly. segmented backplane simplifies dual-speed operation, allows multiple devices stacked function logical repeater.
2.1.1
TP/FX Port Configuration
LXT983 reads hardware configuration pins power-up, hardware reset, software reset (but repeater reset), determine operating conditions each twisted-pair (TP) fiber (FX) ports. Each four media ports configuration pins that individually configured. There four possible configurations each four media ports. four possible configurations summarized Table
Table Manual Speed Selection
SPD1 SPD0 Speed Selection Allow 10/100 auto-negotiation/parallel detection copper media Force port 10BASE-T mode Force port 100BASE-FX mode Force port 100BASE-TX mode
2.1.1.1
Forced Operation
port directly configured operate three modes-100FX, 100TX, 10T. When port configured forced operation, immediately begins operating selected mode. Forced operation only enable 100FX operation. links established halfduplex only. repeater, LXT983 cannot support full-duplex operation.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
2.1.1.2
Auto-Negotiation
port configured establish link auto-negotiation. port link partner establish link conditions exchanging Fast Link Pulse (FLP) bursts. When auto-negotiation enabled, capabilities advertised LXT983 predetermined cannot changed. LXT983 always advertises half-duplex half-duplex. never advertises fullduplex. link partner does support auto-negotiation, LXT983 determines link state listening Mbps IDLE symbols Mbps link pulses. detects either these signals, configures port updates status registers appropriately.
2.1.1.3
Link Establishment Port Connection
Once port establishes link, LXT983 automatically connects appropriate repeater state machine. link loss detected auto-negotiation enabled, port returns autonegotiation state.
2.1.2
Port Configuration
power-up reset, configured external pins three modes operation:
Mbps, side interface-or interfacing Mbps MAC. Mbps, side interface-for interfacing Mbps MAC. Mbps, side interface-to drive fifth Mbps port LXT970 other MIIcompliant PHY. this mode, external must configured either 100TX 100FX connection. Figure Typical Managed Repeater Architectures
LXT983 LXT983
10/100 LXT983 Mbps 10BASE-T E'net 10/100 Backplane Repeater Mbps 10BASE-T E'net 10/100 Backplane Repeater Mbps 10BASE-T E'net Backplane Repeater 10/100 E'net 10/100 E'net Mbps 100BASE-T 10/100 Backplane Repeater E'net Mbps 100BASE-T Repeater 100BASE-T 10/100 Repeater E'net 10/100 E'net 10/100 E'net Control 10/100 Logic Control E'net 10/100 Logic Drivers Control E'net 10/100 Logic Drivers E'net Drivers Backplane Mbps Backplane
Chassis Backplanes
Backplane
Buffer
Backplane
100M Backplane
Buffer
100M Backplane
MII-to-MII Bridge (Any Raptors)
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure Typical Hybrid Switch/Repeater Application
LXT983 LXT983 10/100 Mbps 10BASE-T E'net Backplane Repeater 10/100 Mbps 10BASE-T E'net Backplane Repeater
10/100 E'net 10/100 E'net
Backplane
100M Backplane
Mbps 100BASE-T Backplane Repeater Mbps 100BASE-T Backplane Repeater 10/100 E'net 10/100 E'net Drivers Drivers Control Logic Control Logic
Switch Connections each 100M
10/100 E'net 10/100 E'net
2.1.3
Interface Descriptions
LXT983 provides four network interface ports. Each port provides both twisted-pair fiber interface. twisted-pair interface directly supports 100BASE-TX (100TX) 10BASE-T (10T) Ethernet applications. common termination circuit used both media types. fiber interface indirectly supports 100BASE-FX (100FX) media through PECL connection external fiber-optic transceiver. Both interfaces fully comply with IEEE 802.3 standards
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure Typical Application Block Diagram
LXT983
(Port Mode)
MII_RXCLK MII_RXD<3:0> MII_RXDV MII_RXER MII_COL MII_CRS MII_TXCLK MII_TXD<3:0> MII_TXEN MII_TXER TPOP1 TPON1 TPIP1 TPIN1
Xfmrs
RJ45s Ports Independently switchable either backplane
Fiber Module
Input allows drive (10M Only)
MACACTIVE FIBOP1 FIBON1 FIBIP1 FIBIN1 SIGDET1
Ports
First Position Select
Independent IRBs,
IRCOL IRCFS HOLDCOL IRENA IRDAT IRCLK
Resistor Packs
PORT1_LED1 PORT1_LED2 PORT1_LED3 PORT2_LED1 PORT2_LED2 PORT2_LED3 PORT3_LED1 PORT3_LED2 PORT3_LED3 PORT4_LED1 PORT4_LED2 PORT4_LED3 PORT5_LED1 PORT5_LED2 PORT5_LED3 COL10_LED ACT10_LED COL100_LED ACT100_LED
Local onboard LXT980
'245
InterModule stack connector
IRB10
Port LEDs
IRDEN IRCOLBP IRCFSBP
Local Inter-Module
IRB100
Per-Segment LEDs
2.1.3.1
Twisted-Pair Interface
twisted-pair interface each port consists differential signal pairs-one transmit receive. transmit signal pair TPOP/TPON, receive signal pair TPIP/TPIN. twisted-pair interface given port enabled when port configuration autonegotiate, forced forced 100TX operation. twisted-pair interface disabled when 100FX selected. transmitter current driven requires magnetics with turns ratio. resistive load should placed across TPOP/N pair, parallel with magnetics. center primary side transmit winding must tied quiet proper operation. When twisted-pair interface disabled, transmitter outputs tri-stated.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
receiver requires magnetics with turns ratio, load 100. When twisted-pair port enabled, receiver actively biases inputs approximately When twisted-pair interface disabled, biasing provided. load always present across TPIP/TPIN pair. When used 100TX applications, LXT983 sends receives continuous, scrambled Mbaud MLT-3 waveform. absence data, IDLE symbols sent received keep link When used applications, LXT983 sends receives non-continuous, Mbaud Manchester-encoded waveform. maintain link during idle periods, LXT983 sends link pulses every expects receive them every Each 10BASE-T port automatically detects sends link pulses, disables transmitter link pulses detected. Each receiver also configured ignore link pulses, leave transmitter enabled time (link pulse transmission cannot disabled). Each 10BASE-T port detect automatically correct polarity reversal TPIP/N inputs. 10BASE-T interface provides integrated filters using Intel's patented filter technology, which facilitate low-cost system designs meeting requirements. applications where twisted-pair interface used, inputs outputs left unconnected.
2.1.3.2
Fiber Interface
Each fiber interface consists FIBOP/FIBON (transmit) FIBIP/FIBIN (receive) signal pair. Each interface also provides Signal Detect input that tied corresponding output fiber transceiver determine signal presence quality. transmit pair biased approximately 1.5V generally must AC-coupled transceiver. receive pair will accommodate input bias range, DCcoupled transceiver. Refer Figure page typical circuit. fiber interface each port enabled when speed select 100FX, disabled other cases. When disabled, outputs pulled ground, inputs tri-stated. input output pins unused fiber ports left unconnected. Each fiber port transmits receives continuous, peak-to-peak, non-scrambled, NRZI waveform. LXT983 does support scrambling auto-negotiation fiber interface.
Remote Fault Reporting
detects signal quality reports remote fault signal quality starts degrade. Loss signal quality will also block further data from being received causes loss link. remote fault code consists consecutive followed single transmitted least three times. LXT983 transmits remote fault code sets associated interrupts when both following conditions true:
Fiber mode selected. Signal Detect indicates signal, receive cannot lock.
2.1.3.3 Media Independent Interface
LXT983 supports standard Media Independent Interface (MII) interface. This interface programmed operate either side interface.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
When operating side interface (MAC mode), always operates Mbps. When operating side interface (PHY mode), programmed operate either Mbps Mbps. Once configured, LXT983 automatically connects corresponding internal repeater. LXT983, always operates nibble-wide (4B) interface. Symbol mode interface) supported LXT983 MII. Note: does auto-negotiate, auto speed select, partition.
2.1.4
Repeater Operation
LXT983 contains internal repeater state machines -one operating Mbps other Mbps. LXT983 automatically switches each port correct repeater, once operational state that port been determined. Each repeater connects ports configured same speed (including MII), corresponding Inter-Repeater Backplane. Both repeaters perform standard jabber, partition, isolate functions required.
2.1.4.1
Mbps Repeater Operation
LXT983 contains complete Mbps Repeater State Machine (100RSM) that fully IEEE 802.3 Class compliant. port configured Mbps operation automatically connected Mbps repeater. This includes four media ports they configured 100TX 100FX operation, port configured Mbps operation. 100RSM Inter-Repeater Backplane (100IRB). Multiple LXT983s cascaded 100IRB operate repeater segment. Data from port will forwarded other port cascade. 100IRB 5-bit symbol-mode interface designed stackable. LXT983 performs following Mbps repeater functions:
Signal amplification, wave-shape restoration, data-frame forwarding. Handling received code violations. LXT983 will substitute symbol
invalid received codes.
SOP, SOJ, EOP, delay <46BT (class compliant). Collision Enforcement. During 100M collision, LXT983 drives 1010 signal
(encoded Data links) ports until collision ends. There minimum enforcement time.
Partition. LXT983 partitions port participating excess consecutive collisions
collision approximately 575.2 long. Once partitioned, LXT983 continues monitoring transmitting port, does repeat data received from port until properly unpartitions. 450-560 times without collision that port.
Un-partition. LXT983 un-partitions port only when data transmitted port Isolate. LXT983 will isolate port that transmit more than successive false carrier
events. false carrier event defined packet that does start with /J/K symbol pair. Note: this same function 100IRB isolate function, which involves segmenting backplane.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Un-isolate. LXT983 will un-isolate port that remains IDLE state 33000 +/25% that receives valid frame least 450-500BT length.
Jabber. LXT983 ignores receiver remaining active more than 57,500 times.
LXT983 exits this state when jabbering receivers return idle condition. isolate symbol error functions apply port.
2.1.4.2
Mbps Repeater Operation
LXT983 contains complete Mbps Repeater State Machine (10RSM) that fully IEEE 802.3 compliant. port configured Mbps operation automatically connected Mbps repeater. This includes four media ports they configured 10BT operation, port configured Mbps operation. 10RSM Inter-Repeater Backplane (10IRB). Multiple LXT983s cascaded 10IRB operate repeater segment. Data from port will forwarded other port cascade. 10IRB 1-bit wide runs 10MHz. designed stackable. LXT983 performs following Mbps repeater functions:
Signal amplification, wave-shape restoration, data-frame forwarding. Preamble regeneration. outgoing packets will have minimum bits preamble
bits SFD.
SOP, SOJ, EOP, delays meet requirements IEEE 802.3 section 9.5.5 9.5.6. Collision Enforcement. During collision, LXT983 drives signal ("1010")
ports minimum times until collision ends.
Partition. LXT983 will partition port that participates excess consecutive
collisions. Once partitioned, LXT983 will continue monitoring transmitting port, will repeat data received from port until properly un-partitions.
Un-partition. LXT983 un-partitions port when data either received transmitted
from port 450-560 times without collision that port.
Jabber. LXT983 will assert minimum-IFG idle period when port remains actively
transmitting longer than 40,000 75,000 times.
2.2.1
Requirements
Power
LXT983 four types power supply input pins: VCC, VCCV, VCCR, VCCT. These inputs supplied from single power supply although ferrites should used filter analog digital power planes. matter good practice, these supplies should clean possible. Specific operating recommendations shown Test Specifications section, Table page Each supply input should decoupled respective ground. Refer Table power ground assignments, "General Design Guidelines" page layout guidelines.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
2.2.2
Clock
stable, external system clock source (CMOS) required LXT983. This connected CLK25 pin. Refer Test Specifications, Table page clock input requirements.
2.2.3
Bias Current
LXT983 requires 22.1 resistor connecting RBIAS input ground.
2.2.4
Reset
power-up, reset input must held until reaches least 4.5V. `LS14 equivalent should used drive reset there multiple LXT983 devices.
2.2.5
Pull-ups
Even when LXT983 used stand-alone configuration, pull-up resistors required signals listed below. Figure Figure sample circuits.
100M IR100CFS IR100CFSBP IR100DV IR100CLK IR10DAT IR10ENA IR10COL IR10CFS IR10COLBP IR10CFSBP
Operation
LXT983 provides types indicators: port segment (refer Table page 13). Three user-selectable modes determine which conditions indicated which pins, particular conditions indicated. mode selected LEDSEL<1:0> pins. addition states, some drivers provide blink state output.
2.3.1
Power-Up Reset Conditions
During reset power-up, LEDs turn steady remain approximately seconds after reset cleared.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
2.3.2
Port LEDs
Port LEDs provide status four twisted-pair ports port. LXT983 driver pins each port described Table These pins drive standard LEDs. Three userselectable modes provided port LEDs. Port states also affected port speed auto-negotiation status. information conveyed port states each mode listed Table through Table
2.3.2.1
Link Loss
During link loss, Speed indicates 10M, Partition indicates Partition," regardless actual partition status.
2.3.3
Segment LEDs
These outputs directly drive LEDs indicate activity collision status segment basis. They affected mode selection. Pulse stretchers used extend on-time these LEDs.
2.3.3.1
Collision LEDs
collision LEDs turn approximately when LXT983 detects collision respective 100M segment. During time that collision additional collisions ignored collision logic.
2.3.3.2
Activity LEDs
activity LEDs turn approximately when LXT983 detects activity respective 100M segment. During time that activity additional activity ignored activity logic.
Table Mode Indications
PORTnLED1 Mbps operation Mbps operation PORTnLED2 Mbps operation Auto-neg enabled PORTnLED3 Auto-neg disabled Mbps link selected, link down Link partitioned, isolated 100Mbps link link (0.4s blink rate)1 other state other state other state Link partitioned, isolated other state other state Operating Mode Mbps operation Link partitioned Blink other state
Setting AUTO_BLINK (Pin High disables blink (LXT983A only).
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Table Mode Indications
Operating Mode 10M: Port enabled, link partitioned PORTnLED1 100M: Port enabled, link partitioned, isolated Receive activity pulse) Mbps link Mbps selected, link down Hardware Control Blink 10M: Port enabled, link partitioned 100M: Port enabled, link (partitioned isolate) (slow blink) link (0.4s blink rate)1 other state
PORTnLED2
(LXT983)
PORTnLED2
Mbps Auto-neg enabled
Always other state Mbps link Mbps selected, link down
(LXT983A)
PORTnLED3 Auto-neg disabled
Setting AUTO_BLINK (Pin High disables blink (LXT983A only).
Table Mode Indications
Operating Mode Mbps operation PORTnLED1 Mbps operation PORTnLED2 Mbps operation Auto-neg enabled PORTnLED3 Auto-neg disabled 100M link selected, link down link selected, link down Link partitioned Link partitioned, isolated Receive activity pulse) 100M link link (0.4s blink rate)1 Blink other state other state other state link
Setting AUTO_BLINK (Pin High disables blink (LXT983A only).
Operation
Inter Repeater Backplane (IRB) allows multiple devices operate single logical repeater, exchanging data collision status information. Each segment LXT983 complete, independent IRB. This backplane uses combination digital analog signals. signals characterized connection type Local (connected between devices same board), Stack (connected between boards) Full (connected between devices same board between different boards). Refer Table page Table page details buffering pull-up requirements, Figure page Figure page application circuitry.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
2.4.1
Access
MACACTIVE allows external other digital ASIC interface directly Mbps IRB. When MACACTIVE asserted, LXT983 will drive IR10CFS IR10CFSBP signals behalf external device, allowing participate collision detection functions.
Figure Block Diagram
Digital Signals Analog Signals
Board
'245
HOLDCOL IRDEN Digital Signals
LXT983
LXT983
Board
Analog Signals
'245
HOLDCOL IRDEN Digital Signals Analog Signals
LXT983
LXT983
Board
'245 HOLDCOL IRDEN LXT983 LXT983
This diagram shows single IRB. LXT983 actually independent IRBs, speed/segment. Digital signals include IRnDAT, IR1nDEN, IRnENA IRnCLK. Local Analog signals include IR100SNGL, IRnCOL IRnCFS. Inter-Board Analog signals include IRnCOLBP IRnCFSBP. HOLDCOL used 10Mbps Only.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Table Signal Types
Connection Type Full Local Stack Connections Between Devices (same board) Connect Connect devices with High, pull-up each device interconnect. Connections Between Boards Connect using buffers connect Connect devices with between boards. pull-up resistor stack.
Table Signal Details
Name Type Buffer Mbps Signals IR100DAT<4:0> IR100CLK IR100DV IR100CFS IR100CFSBP IR100COL IR100SNGL IR100DEN Digital Digital Digital, Open Drain Analog Analog Digital Digital Digital, Open Drain N/A1 Mbps Signals IR10DAT IR10CLK IR10ENA IR10CFS IR10CFSBP IR10COL IR10COLBP IR10DEN Digital, Open Drain Digital Digital, Open Drain Analog Analog Analog Analog Digital, Open Drain N/A1 680, 330, 330, 330, Full Full Full Local Stack Local Stack Local 240, Full Full Full Local Stack Local Local Local Pull-up Connection Type
Driver Enable signals provided control external bidirectional transceiver. resistors provide greater noise immunity. Systems using resistors backwards stackable with systems using resistors.
Port Operation
LXT983 allows directly connect into repeater environment. port (Port operate either Mbps. Utilizing LXT983s allows user have interface both Mbps segments. LXT983 does provide MDIO/MDC capability.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
LXT983 emulate either (PHY Mode) (MAC Mode) side shown Figure Mode speed control provided PORT5_SPD PORT5_SEL pins listed Table
2.5.1
Mode Operation
Mode available both Mbps. allows LXT983 interface Mbps MAC. When operating Mbps, LXT983 passes full bits preamble through before sending SFD. When operating Mbps, LXT983 sends data across starting with 8-bit preamble bits).
2.5.2
Mode Operation
Mode (available Mbps only) allows user attach additional LXT983. this mode provides both MII_TXCLK MII_RXCLK. MII_TXCLK clock must frequency-locked oscillator used LXT983. LXT983 does provide elasticity buffer compensate frequency differences. When operating mode, LXT983 generates full bits preamble before sending across MII.
Table (Port Mode Speed Control
PORT5_SPD High High PORT5_SEL High High Speed Mbps Mbps Mbps Mode
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure (Port Operation
MII_TXD<3:0>
LXT983 port reversible.
LXT983
Ports Port Port Port Port Port
MII_TXEN MII_TXER MII_TXCLK MII_RXCLK MII_RXD<3:0> MII_RXDV MII_RXER MII_CRS MII_COL MII_TXD<3:0>
When mode selected, LXT983 acts side MII. this mode external sends Data LXT983 repeated network. LXT983 repeats network data Data lines.
10/100
Port
Mode
LXT983
When mode selected, LXT983 acts side MII. this mode LXT983 repeats network data Data lines. external sends data LXT983 repeated network Data lines.
Ports Port Port Port Port Port
MII_TXEN MII_TXER MII_TXCLK MII_RXCLK MII_RXD<3:0> MII_RXDV MII_RXER MII_CRS MII_COL
Port
Mode
Mbps
2.5.3
Port Timing Considerations
IEEE 802.3u specification provides propagation delay constraints standard devices Section 24.6, repeater devices Section LXT983 port hybrid that does either these categories. critical specification that applies LXT983 port overall end-to-end system propagation delay (132 times maximum). LXT983 supports this requirement. Figure summarizes propagation delay issues relevant LXT983 port. LXT983 architecture treats port fifth repeater port. timing delay (latency) from port other port meets requirements Class repeater BT). does meet requirements standard MII-PHY interface BT). When operating mode with connected LXT983 port (Figure 8B), fifth port does have latency characteristics Class repeater with respect other ports. With connected LXT983 port (Figure 8D), maximum latency other times (not including cable delay). connected LXT983 advantage relative other MACs because less transceiver delay.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure Timing Issues
Propagation Delay Requirements IEEE 802.3u:- prop delay (MII-TP) must Class Repeater prop delay (TP-TP) must
Class RPTR Prop Delay Prop Delay
Class RPTR Prop Delay
Port
Port LXT983
MII-to-MII Prop Delay
Prop Delay
Port Does Meet Class RPTR Prop Delay
Ports Meets Class RPTR Prop Delay
Prop Delay Class RPTR Prop Delay
LXT983 Port (MII) operating Mode, connected device.
LXT983 Port (MII) operating Mode, connected device.
Class RPTR Prop Delay Prop Delay
Class RPTR Prop Delay Prop Delay
Class RPTR Prop Delay Prop Delay
Prop Delay
PHY-to-MAC Prop Delay
Prop Delay
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Application Information
Design Recommendations
LXT983 been designed comply with IEEE requirements provide outstanding receive long-line-length performance. testing shown that LXT983 perform well beyond required distance 100m. with finely crafted device, reaping full benefits LXT983 requires attention detail good design practice.
3.1.1
General Design Guidelines
Adherence generally accepted design practices essential minimize noise levels power ground planes. noise considered acceptable. noise considered marginal. High-frequency switching noise reduced, effects eliminated, following these simple guidelines throughout design:
Fill unused areas signal planes with solid copper attach them with vias
ground plane that located adjacent signal layer.
ample bulk decoupling capacitors throughout design value
recommended decoupling caps).
Provide ample power ground planes. Provide termination high-speed switching signals clock lines. Provide impedance matching long traces prevent reflections. Route high-speed signals next continuous, unbroken ground plane. Filter shield DC-DC converters, oscillators, etc. route digital signals between LXT983 RJ-45 connectors edge board. board. this area chassis ground, leave void.
extend circuit power ground plane past center magnetics edge
3.1.2
Power Supply Filtering
Power supply ripple digital switching noise plane cause problems degrade line performance. generally difficult predict advance performance design, although certain factors greatly increase risk having these problems:
Poorly-regulated over-burdened power supplies. Wide data busses (>32-bits) running high clock rate. DC-to-DC converters.
Many these issues improved just following good general design guidelines. addition, Intel also recommends filtering between power supply analog pins LXT983. Filtering benefits. First, keeps digital switching noise analog circuitry inside LXT983, which helps line performance. Second, planes laid correctly, keeps digital switching noise away from external connectors, reducing problems.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
recommended implementation divide plane into sections. digital section supplies power digital external components. analog section supplies power VCCH, VCCT, VCCR pins LXT983. break between planes should under device. designs with more than LXT983, single continuous analog plane used supply them all. digital analog planes should joined more points ferrite beads. beads should produce least impedance MHz. beads should placed that current flow evenly distributed. maximum current rating beads should least 150% current that actually expected flow through them. Each LXT983 draws maximum from analog supply beads rated should used. bulk (2.2 should placed each side each ferrite bead stop switching noise from traveling through ferrite. addition, high-frequency bypass (.01 should placed near each analog pin.
3.1.2.1
Ground Noise
best approach minimize ground noise strict good general design guidelines filtering plane.
3.1.3
Power Ground Plane Layout Considerations
Great care needs taken when laying power ground planes. following guidelines recommended:
Follow guidelines LXT980 Design Layout Guide locating split between
digital analog planes.
Keep digital plane away from TPOP/N TPIP/N signals, away from
magnetics, away from RJ-45 connectors.
Place layers that TPOP/N TPIP/N signals routed near next
ground plane. reasons, more important shield TPOP TPIP/N.
3.1.3.1
Chassis Ground
reasons, good design practice create separate chassis ground that encircles board isolated moats keep-out areas from circuit-ground planes active signals. Chassis ground should extend from RJ-45 connectors magnetics, used terminate unused signal pairs (`Bob Smith' termination). single-point grounding applications, provide single connection between chassis circuit grounds with isolation capacitor. multi-point grounding schemes (chassis circuit grounds joined multiple points), provide isolation Smith termination.
3.1.4
Terminations
Series termination resistors recommended signals driven LXT983. proper value nominal trace impedance minus nominal trace impedance known,
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
3.1.5
RBIAS
LXT983 requires 22.1 resistor directly connected between RBIAS ground. Place RBIAS resistor close RBIAS possible. etch directly from resistor, sink other side resistor ground. Surround RBIAS trace with ground; high-speed signals next RBIAS.
3.1.6
Twisted-Pair Interface
Because LXT983 transmitter uses magnetics, system designers must take extra precautions minimize parasitic shunt capacitance order meet return loss specifications. These steps include:
compensating inductor output stage (Figure 14). Place magnetics close possible LXT983. Keep transmit pair traces short. route transmit pair adjacent ground plane. possible, eliminate planes under transmit traces completely. Otherwise, keep planes layers away. performance. these improved magnetics increases return loss budget available system designer.
Some magnetic vendors producing magnetics with higher than average return loss Improve performance filtering output centertap. single ferrite bead used
supply centertap current four ports. addition, follow standard guidelines twisted-pair interface:
Route signal pairs differentially, close together. Allow nothing come between them. Keep distances short possible; both traces should have same length. Avoid vias layer changes much possible. Keep transmit receive pairs apart avoid cross-talk. possible, place entire receive termination network side transmit other. Keep termination circuits close together same side board. Always termination circuits close source circuit. Bypass common-mode noise ground in-board side magnetics using 0.01 capacitors.
3.1.7
Fiber Interface
fiber interface consists pseudo-ECL (PECL) transmit receive pair external fiber optic transceiver. transmit pair should coupled transceiver, biased 3.7V with equivalent impedance. receive pair DC-coupled, should biased 3.0V with equivalent impedance. Figure page shows correct bias networks achieve these requirements.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
3.1.8
Magnetics Information
LXT980 requires ratio receive transformers ratio transmit transformers. transformer isolation voltage should rated protect circuitry from static voltages across connectors cables. Refer Table transformer specifications Magnetic Manufacturers Networking Product Applications (Application Note reference list compatible magnetic components. Before committing specific component, designers should test validate magnetics specific application verify that system requirements met.
Table Magnetics Specifications
Parameter turns ratio turns ratio Insertion loss Primary inductance Transformer isolation Differential common mode rejection Return Loss standard Return Loss improved Units Test Condition
Typical Application Circuitry
Figure Figure simplified block diagrams showing typical applications. Figure through Figure show application circuitry details.
Figure Unmanaged 10/100 Repeater Stack
Bridge
100M Inter-Repeater Backplanes LXT983 100M 100M TP/Fiber Ports LXT983 TP/Fiber Ports 100M 100M LXT983 TP/Fiber Ports
Inter-Repeater Backplanes LXT983 TP/Fiber Ports
10/100 Ports
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure Hybrid Switch/Repeater Application Balanced 10/100 Performance
Memory
Ethernet Switch
10/100 10/100
Control
10/100
10/100
Inter-Repeater Mbps LXT983 100M Backplanes LXT983 100M Mbps Mbps
Inter-Repeater Backplanes Mbps LXT983 100M 100M
LXT983
TP/Fiber Ports
TP/Fiber Ports
TP/Fiber Ports
TP/Fiber Ports
10/100 Ports
Figure Hybrid Switch/Repeater Application Weighted Toward 100M Performance
Memory
Ethernet Switch
Mbps Mbps
Control
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps Inter-Repeater Backplanes LXT983 100M LXT983 100M LXT983 100M LXT983 100M
TP/Fiber Ports
TP/Fiber Ports
TP/Fiber Ports
TP/Fiber Ports
10/100 Ports
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure Power Ground Connections
LXT983
VCCT
Output Magnetics Center
.1µF
.01µF
GNDT VCCV
.1µF .01µF
GNDV
22.1
RBIAS GNDA VCCR
.1µF .01µF 10µF
GNDR Analog Supply Plane
Ferrite Beads
Digital Supply Plane
10µF
0.1µF
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure Typical Fiber Port Interface
0.01µF
VCCT
GNDA
FIBONn FIBOPn 0.01µF
Fiber Network
GNDA
LXT983
SIGDETn
Fiber Txcvr
VCCR
GNDA
FIBINn FIBIPn
GNDA
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure Typical Twisted-Pair Port Interface
Output Stage with Compensating Inductor
0.1µF
GNDR
TPIP
RJ45
TPIN TPOP
LXT983
TPON
0.001µF/2kV
VCCT
0.1µF .01µF
GNDT
Receiver common mode bypass improve performance systems with noisy power supplies. single ferrite bead used supply center current ports.
Twisted-Pair Network
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure Typical Mbps Implementation
Stack Segment Connector IR100CLKBP IR100DATBP IR100DVBP\ '245 IR100CLK IR100DAT IR100DV\ IR100DEN\ ISOLATE IR100CFSBP\ IR100DAT <4:0> IR100DV\ IR100DEN\ IR100COL\ IR100CFS\ IR100SNGL IR100CFSBP\
LXT983 Chip
LXT983 Chip
LXT983 Chip
stacked configurations, devices with ChipID tied together IR100CFSBP. entire stack must pulled only resistor signal. Pull-up resistor installed base board only. devices with ChipID require individual pull-up resistors IR100CFSBP. resistors provide greater noise immunity. Systems using resistors backwards stackable with systems using resistors.
Figure Typical Mbps Implementation
Stack Segment Connector IR10CLKBP IR10DATBP IR10ENABP\ '245 IR10CLK IR10DAT IR10ENA\ IR10DEN\ IR10CLK IR10CFSBP\ IR10CFSBP\ IR10DAT IR10ENA\ IR10DEN\ IR10COL\ IR10CFS\ HOLDCOL
IR10COLBP\
ISOLATE IR10COLBP\ IR10CFSBP\
LXT983 Chip
LXT983 Chip
LXT983 Chip
stacked configurations, devices with ChipID tied together IR100CFSBP IR10CFSBP. entire stack must pulled only resistor signal. Pull-up resistor installed base board only. devices with ChipID require individual pull-up resistors IR100CFSBP IR10CFSBP.
Figure Typical Reset Circuit (983reset.vsd)
t(CR1) Power Supply Ramp Time discharges when supply goes away needed multiple LXT983 devices.
IR10COLBP\
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Test Specifications
Table through Figure Figure through Figure represent performance specifications LXT983/983A. These specifications guaranteed test except where noted design." Minimum maximum values listed Table through Table apply over recommended operating conditions specified Table
Table Absolute Maximum Ratings
Parameter Supply voltage Ambient Operating temperature Case Storage temperature TOPC +130 +150 Symbol TOPA -0.3 Units
Caution:
Exceeding these values cause permanent damage. Functional operation under these conditions implied. Exposure maximum rating conditions extended periods affect device reliability.
Table Operating Conditions
Parameter VCCV Recommended supply voltage VCCR VCCT Ambient Recommended operating temperature Case 100BASE-TX, ports active Power consumption 100BASE-FX, ports active TOPC TOPA 4.75 4.75 5.25 5.25 4.75 4.75 5.25 5.25 Units
Table Input Clock Requirements
Parameter1 Frequency Frequency Tolerance Duty Cycle Typ2 ±100 Units
This table lists requirements which apply external clock supplied LXT983, LXT983 test specifications. Typical values 25°C design only. guaranteed subject production testing.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Table Electrical Characteristics
Parameter Input voltage Input High voltage VCC-1.0 Hysteresis voltage Output voltage Output voltage (LED) Output High voltage Input current Input High current Output rise fall time VOLL -100 Typ1 Units Test Conditions inputs CMOS inputs Schmitt triggers inputs CMOS inputs Schmitt triggers Schmitt triggers IOLL
Typical values design only; guaranteed subject production testing. Does apply pins. Refer Table Table characteristics. Applies RESET CLK25 pins only.
Table Mbps Electrical Characteristics
Parameter Symbol 20.0 20.5 25.0 55.0 4.35 IR100CLK (Schmitt trigger) CMOS inputs IR100CLK (Schmitt trigger) IR100CLK (Schmitt trigger) single drive IRCFS current collision single drive IRCFSBP current collision single drive IRCFSBP voltage collision Typical values design only; they guaranteed subject production testing. resistors provide greater noise immunity. Systems using resistors backwards stackable with systems using resistors. Typ1 Units Test Conditions CMOS inputs
Output voltage Output rise fall time Input High voltage Input voltage Hysteresis voltage
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Table Mbps Electrical Characteristics
Parameter Output voltage Output rise fall time Input High voltage Symbol Input voltage Hysteresis voltage IRCFS current IRCFSBP current IR10CLK (Schmitt trigger) IR10CLK (Schmitt trigger) IR10CLK (Schmitt trigger) CMOS inputs Typ1 Units Test Conditions CMOS inputs
Typical values design only; they guaranteed subject production testing.
Table 100BASE-TX Transceiver Electrical Characteristics
Parameter Peak differential output voltage Signal amplitude symmetry Signal rise/fall time Rise/fall time symmetry Duty cycle distortion Overshoot Symbol Trfs 0.95 Typ1 1.05 Units Note Note Note Note Offset from pulse width pulse peak, Test Conditions
Typical values design only; guaranteed subject production testing. Measured line side transformer, line replaced (±1%) resistor.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Table 100BASE-FX Transceiver Electrical Characteristics
Parameter Symbol Typ1 Transmitter Peak differential output voltage (single ended) Signal rise/fall time Jitter (measured differentially) Receiver Peak differential input voltage Common mode input range VCMIR 0.55 2.25 load Units Test Conditions
Typical values design only; guaranteed subject production testing.
Table 10BASE-T Transceiver Electrical Characteristics
Parameter Symbol Typ1 Transmitter Peak differential output voltage Transmit timing jitter addition2 Transmit timing jitter added sections2, ±6.4 ±3.5 Receiver Receive input impedance Differential Squelch Threshold Between TPIP/TPIN square wave input, mVpp ±5.5 Measured line side transformer, line replaced resistor line length internal After line model specified IEEE 802.3 10BASE-T internal Units Test Conditions
Typical values design only; guaranteed subject production testing. Parameter guaranteed design; subject production testing. IEEE 802.3 specifies maximum jitter additions cable, from encoder, from MAU.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure Mbps Port-to-Port Delay Timing
Normal Propagation
Input
Output
Collision Jamming
Input Input
Output
Table Mbps Port-to-Port Delay Timing Parameters
Parameter TPIP/N FIBIP/N TPOP/N FIBOP/N, start transmission TPIP/N FIBIP/N TPOP/N FIBOP/N, transmission TPIP/N FIBIP/N collision TPOP/N FIBOP/N, start TPIP/N FIBIP/N idle TPOP/N FIBOP/N, Units1
Test Conditions
time (BT) defined duration transferred from reciprocal rate. 100BASE-T 10-8 sec.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure 100BASE-TX Transmit Timing Mode
TX_CLK
TXD, TX_EN, TX_ER
TPOP/N
Table 100BASE-TX Transmit Timing Parameters Mode
Parameter TXD, TX_EN, TX_ER Setup TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled asserted TX_EN sampled de-asserted TX_EN sampled TPOP/N active latency) Units1 Test Conditions
time (BT) defined duration transferred from reciprocal rate. 100BASE-T 10-8 sec.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure 100BASE-TX Receive Timing Mode
TPIP/N
RXD, RX_DV, RX_ER
RX_CLK
Table 100BASE-TX Receive Timing Parameters Mode
Parameter TPIP/N asserted TPIP/N quiet de-asserted asserted RXD, RX_DV, RX_ER de-asserted RXD, RX_DV, RX_ER de-asserted RX_CLK falling edge RXD, RX_DV, RX_ER valid TPIP/N asserted TPIP/N quiet de-asserted Units1 Test Conditions
time (BT) defined duration transferred from reciprocal rate. 100BASE-T 10-8 sec.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure 100BASE-TX Transmit Timing Mode
RX_CLK
RXD, RX_DV, RX_ER
TPOP/N
Table 100BASE-TX Transmit Timing Parameters Mode
Parameter RXD, RX_DV, RX_ER Setup RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK High sampled asserted sampled de-asserted Units1 Test Conditions
time (BT) defined duration transferred from reciprocal rate. 100BASE-T 10-8 sec.
Figure 100BASE-TX Receive Timing Mode
TPIP/N
TXD, TX_EN, TX_ER
TX_CLK
Table 100BASE-TX Receive Timing Mode
Parameter TPIP/N TXD, TX_EN, TX_ER TPIP/N quiet de-asserted TX_CLK rising edge TXD, TX_EN, TX_ER valid Units1 Test Conditions
time (BT) defined duration transferred from reciprocal rate. 100BASE-T 10-8 sec.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure 100BASE-FX Transmit Timing Mode
TX_CLK
TXD, TX_EN, TX_ER
FIBOP/N
Table 100BASE-FX Transmit Timing Parameters Mode
Parameter TXD, TX_EN, TX_ER Setup TX_CLK High TXD, TX_EN, TX_ER Hold from TX_CLK High TX_EN sampled asserted TX_EN sampled de-asserted TX_EN sampled FIBOP/N latency) Units1 Test Conditions
time (BT) defined duration transferred from reciprocal rate. 100BASE-T 10-8 sec.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure 100BASE-FX Receive Timing Mode
FIBIP/N
RXD, RX_DV, RX_ER
RX_CLK
Table 100BASE-FX Receive Timing Mode
Parameter FIBIP/N asserted FIBIP/N quiet de-asserted asserted RXD, RX_DV, RX_ER de-asserted RXD, RX_DV, RX_ER deasserted RX_CLK falling edge RXD, RX_DV, RX_ER valid FIBIP/N asserted FIBIP/N quiet de-asserted Units1 Test Conditions
time (BT) defined duration transferred from reciprocal rate. 100BASE-T 10-8 sec.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure 100BASE-FX Transmit Timing Mode
RX_CLK
RXD, RX_DV, RX_ER
FIBOP/N
Table 100BASE-FX Transmit Timing Mode
Parameter RXD, RX_DV, RX_ER Setup RX_CLK High RXD, RX_DV, RX_ER Hold from RX_CLK High sampled FIBOP/N asserted sampled FIBOP/N de-asserted Units1 Test Conditions
time (BT) defined duration transferred from reciprocal rate. 100BASE-T 10-8 sec.
Figure 100BASE-FX Receive Timing Mode
FIBIP/N
TXD, TX_EN, TX_ER
TX_CLK
Table 100BASE-FX Receive Timing Mode
Parameter FIBIP/N TXD, TX_EN, TX_ER FIBIP/N quiet de-asserted TX_CLK rising edge TXD, TX_EN, TX_ER valid Units1 Test Conditions
time (BT) defined duration transferred from reciprocal rate. 100BASE-T 10-8 sec.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure 10BASE-T Transmit Timing Mode
TX_CLK
t10A
TXD, TX_EN, TX_ER
t10B
t10C
Table 10BASE-T Transmit Timing Parameters Mode
Parameter Note: TXD, TX_EN, TX_ER Setup TX_CLK High Note: TXD, TX_EN, TX_ER Hold from TX_CLK High Note: TX_EN sampled asserted Typ1 Units2 Test Conditions
t10A t10B t10C
Typical values design only; guaranteed subject production testing. time (BT) defined duration transferred from reciprocal rate. 10BASE-T, time 10-7 sec.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure 10BASE-T Receive Timing Mode
TPIP/N
t11A
RXD, RX_DV, RX_ER
t11B
t11C
RX_CLK
t11D
Table 10BASE-T Receive Timing Parameters Mode
Parameter TPIP/N asserted asserted RXD, RX_DV, RX_ER RX_CLK falling edge RXD, RX_DV, RX_ER valid TPIP/N asserted Typ1 Units2 Test Conditions
t11A t11B t11C t11D
Typical values design only; guaranteed subject production testing. time (BT) defined duration transferred from reciprocal rate. 10BASE-T, time 10-7 sec.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure Mbps Timing
TPIP/N FIBIP/N
t12A
IR100DV IR100CFS 1R100COL IR100DAT<4:0>
t12B
IR100CLK
t12C
Table Mbps Timing Parameters
Parameter TPIP/N FIBP/N IR100DV IR100DAT IR100CLK setup time. IR100DAT IR100CLK hold time. Typ1 Units2 Test Conditions
t12A t12B t12C
Typical values design only; guaranteed subject production testing. time (BT) defined duration transferred from reciprocal rate. 100BASE-T, time 10-8 sec.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure Mbps Receive Timing
TPIP/N
t13A
IR10ENA
t13B
IR10DAT
t13C
IR10CLK
Table Mbps Receive Timing Parameters1
Parameter TPIP/N IR10ENA IR10CLK rising edge IR10DAT rising edge.3 IR10CLK rising edge IR10DAT falling edge. Symbol Typ2 Units4 pullup, load IR10DAT. pullup, load IRCLK. measurements 2.5V. Test Conditions
t13A t13B t13C
This table contains propagation delays from ports normal repeater operation. values this table output timings. Typical values design only; guaranteed subject production testing. There delay approximately times between assertion IR10ENA assertion IR10CLK IR10DAT. This delay does affect repeater operation because downstream devices begin generating preamble soon IR10ENA asserted. time (BT) defined duration transferred from reciprocal rate. 10BASE-T, time 10-7 sec.
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Figure Mbps Transmit Timing
MACACTIVE
t14A
IR10ENA
IR10DAT
t14C t14B
IR10CLK
TPOP/N
t14D
Table Mbps Transmit Timing Parameters
Parameter MACACTIVE IR10ENA assertion delay IR10DAT (input) IR10CLK setup time IR10CLK IR10DAT (input) hold time IR10ENA asserted TPOP/N active Symbol Typ1 Units2 Test Conditions MACACTIVE High IR10ENA IR10DAT valid IR10CLK rising edge4 IR10CLK rising edge IR10DAT change
t14A t14B t14C t14D
Typical values design only; they guaranteed subject production testing. time (BT) defined duration transferred from reciprocal rate. 10BASE-T, time 10-7 sec. External devices should allow least clock cycle between assertion MACACTIV IR10ENA. Input
LXT983/983A Dual Speed, 5-Port Fast Ethernet Repeater
Mechanical Specifications
Figure LXT983 Package Specifications
208-Pin Plastic Quad Flat Package Part Number LXT983QC LXT983AHC Commercial Temperature Range (0°C 70°C)
Millimeters
4.10 3.60 0.27 30.90 28.30 30.90 28.30 BASIC
0.25 3.20 0.17 30.30 27.70 30.30 27.70
0.50 1.30
0.75

LXT983 983A

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