LXT3108

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LXT3108
Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Intel® LXT3108 octal 3.3V long haul short haul T1/E1/J1 Line Interface Unit (LIU). This flexible allows design T1/E1/J1 long haul short haul multi-service cards with single design bill-of-material. LXT3108 configured port basis through software allowing design multi-service card meet international standards requirements. Intel's proven design robustness makes LXT3108 perfect device high-density T1/E1/J1 applications. increase network reliability, Intel's LXT3108 incorporates DSP-based architecture with features such Intel® Hitless Protection Switching (Intel® HPS) Intel® Pulse Template Matching (Intel® PTM). DSP-based architecture less sensitive power supply temperature variations allows adapt varying line conditions. Intel® allows design redundant cards without relays well ability switch from card another without loss frame synchronization. Intel® Psoftware allows transmitter shape output pulse meet varying board conditions, without need change external components.
Applications
Voice over packet gateways Integrated Multi-service Access Platforms (IMAPs) Integrated Access Devices (IADs) Inverse multiplexing A(IMA)
Wireless base stations Routers Frame relay access devices, CSU/DSU equipment
Product Features
Intel® protection without relays Intel® Pfor pulse output adjustment through software without component board change Interfaces directly with IXF3208, Octal E1/J1 Framer with Chip (100 Ohm), Ohm), (110 Ohm) LH/SH selectable port through software without component change Receiver sensitivity exceeds 36dB 43db 1024 cable attenuation providing margin board cable variations 3.3V power supply with tolerant inputs
chip CLAD that allows master clock T1/E1/J1 applications (1X, clock) BPV/Excess Zero counters port B8ZS/HDB3 encoders decoders, unipolar/bipolar modes selectable port Digital Jitter Attenuator (DJA) either receive transmit path Meets exceeds specifications ANSI T1.102, T1.403 T1.408; I.431, CRT12/13, G.703, G.736, G.775 G.823; ETSI 300-166 300-233; AT&T 62411 Available 17x17mm PBGA (LXT3108 (LXT3108 package
Notice: This document contains preliminary information products production. specifications subject change without notice. Verify with your local Intel sales office that have latest datasheet before finalizing design.
Order Number: 249543-001 June 2001
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Information this document provided connection with Intel® products. license, express implied, estoppel otherwise, intellectual property rights granted this document. Except provided Intel's Terms Conditions Sale such products, Intel assumes liability whatsoever, Intel disclaims express implied warranty, relating sale and/or Intel products including liability warranties relating fitness particular purpose, merchantability, infringement patent, copyright other intellectual property right. Intel products intended medical, life saving, life sustaining applications. Intel make changes specifications product descriptions time, without notice. Designers must rely absence characteristics features instructions marked "reserved" "undefined." Intel reserves these future definition shall have responsibility whatsoever conflicts incompatibilities arising from future changes them. LXT3108 contain design defects errors known errata which cause product deviate from published specifications. Current characterized errata available request. Contact your local Intel sales office your distributor obtain latest specifications before placing your product order. Copies documents which have ordering number referenced this document, other Intel literature obtained calling 1-800548-4725 visiting Intel's website http://www.intel.com. Copyright Intel Corporation, 2001 *Third-party brands names property their respective owners.
Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit LXT3108
Contents
Assignments Signal Descriptions Signal Descriptions Functional Description.22
Jitter Attenuator Functional Description Reset Operation Tolerant pins Power Supply Requirements.29 4.3.1 Ground Plane 4.3.2 Analog Power Supply 4.3.3 Digital Power Supply Transmit Line Interface.31 5.1.1 Transmit Impedance Termination.32 5.1.2 Transmit Return Loss Performance Transmit Digital Interface 5.2.1 Transmit Idle Operation Tristating Drivers.35 Master Reference Clock.36 Receiver Digital Interface 6.2.1 Receiver Idle Conditions Receiver Line Interface 6.3.1 Receive Termination Impedance.37 6.3.2 Receiver Sensitivity Programming Receiver Status Information Digital Jitter Attenuator (DJA) Status.40 Diagnostic Modes.40 8.1.1 In-Band Network Loop Down Code Generator/Detector 8.1.2 Analog Loopback.41 8.1.3 Digital Loopback.41 8.1.4 Remote Loopback 8.1.5 Transmit Ones (TAOS).42 Line Coding 8.2.1 Alternate Mark Inversion (AMI).44 Network Maintenance Functions 8.3.1 Loss Signal (LOS) 8.3.2 Alarm Indication Signal (AIS) 8.3.3 NLOOP Status.47
Initialization
Transmitter.30
Receiver
Jitter Attenuation (JA)
Network Control Maintenance Functions
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
8.3.4
Line Coding Violations
Host Interface
Supported Processors Connections. 9.1.1 MPC860/M68360 9.1.2 M68302 9.1.3 I960/I486 9.1.4 8051 Mode Interrupts 9.2.1 Interrupt Enable. 9.2.2 Interrupt Clearing Global Registers. Port Page Register Bank (PPRB) Architecture Controller. JTAG Register Description. 11.3.1 Boundary Scan Register (BSR). 11.3.2 Device Identification Register (IDR) 11.3.3 Bypass Register (BYR) 11.3.4 Instruction Register (IR) Supported Microprocessors Connections 12.1.1 MPC860/M68360 12.1.2 M68302 12.1.3 I960/I486 12.1.4 Intel 8051 mode Timing Diagrams Referenced Standards
10.0
Register Definitions
10.1 10.2
11.0
JTAG Boundary Scan
11.1 11.2 11.3
12.0
Test Specifications
12.1
13.0
Host Interface Timing Specifications.
13.1 13.2
14.0 15.0
Mechanical Specification Glossary
Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit LXT3108
Figures
LXT3108 Block Diagram LXT3108 Assignment.10 LXT3108 Plastic Ball Grid Array (PBGA) Assignments.11 LXT3108 Port Block LXT3108 Port Circuit Transmitter Circuit with Balun Coaxial Cable.25 T1/E1/J1 Block Diagram Diode Protection Network When Inputs Power Before Supplies Encoding.30 Typical Transmitter Interface Connections.31 Typical Output Pulse Transmit Interface Timing.35 TCLK Power Down Timing Receiver Output Timing.37 Typical Receiver Interface Connections.38 Jitter Attenuation Loop Analog Loopback.41 Digital Loopback.42 Remote Loopback TAOS Data Path.43 TAOS with Digital Loopback.43 TAOS with Analog Loopback Interrupt Processing FlowChart.53 LXT3108 JTAG Architecture JTAG State Diagram Transmit Clock Timing Diagram Receive Clock Timing Diagram LXT3108 Output Jitter CTR12/13 Applications JTAG Timing G.703 Mask Templates.77 T1.102 Mask Templates.78 LXT3108 Jitter Tolerance Performance LXT3108 Jitter Transfer Performance MPC860 Write Timing MPC860 Read Timing M68302 Write Timing M68302 Read Timing I486/I960 Write Timing I486/I960 Read Timing 8051 Write Timing 8051 Read Timing LXT3108 PBGA Mechanical Specification LXT3108 Mechanical Specifications
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Tables
LXT3108 Description Transformer Specifications LXT3108. Preset Pulse Shaping Settings Conditions. Transmit Return Loss Specifications Frequency Range Magnitude Powering Down Transmitter with Static TCLK Receiver Sensitivity. Jitter Attenuation Specifications Selection Defaults Service Condition Variations Excess Zero (EXZ) Definitions MPC860/M68360 Mode 8-Bit Mode. 68302 8-bit mode i960/i486 Mode. 8051 Mode Port Page Select Register, CPS, Register, 01h. Interrupt Status Register, ISR, Register Names Port Master Control Page Register, Port Receive Enable Page Register, 02h. Transmit Control Page Register, 03h. Receive Control Page Register, 04h. Termination Control Page Register, 05h. Receiver Equalizer Status Zero Page Register, 06h. Receiver Equalizer Status Page Register, Receiver Equalizer Status Page Register, Window Page Register, Threshold Page Register, Reset Threshold Page Register, Loopback Enable Page Register, 10h. Interrupt Enable Page Register, 11h. Alarm Status Page Register, Interrupt Status Page Register, Line Coding Control Page Register, Control Page Register, Counter High Byte Page Register, Counter Byte Page Register, Transmit Coefficient Page Register Range, 40h-6Fh State Description. Device Identification Register (IDR) Instruction Register (IR) Absolute Maximum Ratings Recommended Operating Conditions Electrical Characteristics (Over Recommended Operating Conditions) Transmitter Analog Characteristics. Receiver Analog Characteristics. Transmitter Analog Characteristics. Receiver Analog Characteristics. General Analog Performance.
Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit LXT3108
Master Transmit Clock Timing Characteristics.73 Jitter Attenuator Characteristics Receive Timing Characteristics Operation.75 Receive Timing Characteristics Operation JTAG Timing Characteristics.76 G.703 2.048 Mbps Pulse Mask Specifications T1.102 1.544 Mbps Pulse Mask Specifications.77 MPC860/M68360 Mode M68302 Mode I960/I486 Mode I8051 Mode MPC860 Write Timing Characteristics MPC860 Read Timing Characteristics M68302 Write Timing Characteristics M68302 Read Timing Characteristics I486 Write Timing Characteristics I486/I960 Read Timing Characteristics 8051 Write Timing Characteristics 8051 Read Timing Characteristics
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Revision History
Revision Date Description
DIGITAL LOOPBACK
ANALOG LOOPBACK
REMOTE LOOPBACK
MODE DB7.0 HARDWARE SOFTWARE CONTROL AD7.0 MCLK
JTAG SERIAL PORT, PARALLEL PORT
Figure LXT3108 Block Diagram
Equalizer
RTIP DATA CLOCK CLOCK RECOVERY B8ZS HDB3 DECODER JITTER ATTENUATOR PATH
RPOS RCLK RNEG
RRING LINE DRIVER
TTIP PULSE PULSE SHAPER JITTER ATTENUATOR PATH
TPOS B8ZS HDB3 ENCODER TCLK TNEG
TRING
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
VCCIO DVCC DVSS AVCC RRING1 RTIP1 AVSS TXVSS TXVCC TVSS TRING1 TTIP1 TVSS DVSS DVCC TVSS TTIP2 TRING2 TVSS TXVCC TXVSS AVSS RTIP2 RRING2 AVCC DVSS DVCC AVCC RRING3 RTIP3 AVSS TXVSS TXVCC TVSS TRING3 TTIP3 TVSS DVCC DVSS TVSS TTIP4 TRING4 TVSS TXVCC TXVSS AVSS RTIP4 RRING4 AVCC DVSS DVCC GNDIO
Figure LXT3108 Assignment
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Assignments Signal Descriptions
LXT3108
VCCIO JRST TClK RSTB LOS1 LOS2 LOS3 LOS4 LOS5 LOS6 LOS7 LOS8 TYPE2 TYPE1 MCLK VMOAT RBIAS QVSS QVCC GNDIO VCCIO GNDIO VCCIO GNDIO VCCIO MPI_CLK/ALE 208. GNDI0 207. DVCC 206. DVSS 205. AVCC 204. RRING8 203. RTIP8 202. AVSS 201. TXVSS 200. TXVCC 199. TVSS 198. TRING8 197. TTIP8 196. TVSS 195. DVSS 194. DVCC 193. TVSS 192. TTIP7 191. TRING7 190. TVSS 189. TXVCC 188. TXVSS 187. AVSS 186. RTIP7 185. RRING7 184. AVCC 183. DVSS 182. DVCC 181. AVCC 180. RRING6 179. RTIP6 178. AVSS 177. TXVSS 176. TXVCC 175. TVSS 174. TRING6 173. TTIP6 172. TVSS 171. DVCC 170. DVSS 169. TVSS 168. TTIP5 167. TRING5 166. TVSS 165. TXVCC 164. TXVSS 163. AVSS 162. RTIP5 161. RRING5 160. AVCC 159. DVSS 158. DVCC INTR
GNDIO TCLK1 TNEG1 TPOS1/ TDATA1 RCLK1 RNEG1 RPOS1/ RDATA1 TCLK2 TNEG2 TPOS2/ TDATA2 RCLK2 RNEG2 RPOS2/ RDATA2 TCLK3 TNEG3 TPOS3/ TDATA3 RCLK3 RNEG3 RPOS3/ RDATA3 TCLK4 TNEG4 TPOS4/ TDATA4 RCLK4 RNEG4 RPOS4/ RDATA4 VCCIO GNDIO TCLK5 TNEG5 TPOS5/ TDATA5 RCLK5 RNEG5 RPOS5/ RDATA5 TCLK6 TNEG6 TPOS6/ TDATA6 RCLK6 RNEG6 RPOS6/ RDATA6 TCLK7 TNEG7 TPOS7/ TDATA7 RCLK7 RNEG7 RPOS7/ RDATA7 TCLK8 TNEG8 TPOS8/ TDATA8 RCLK8 RNEG8 RPOS8/ RDATA8 VCCIO
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Figure LXT3108 Plastic Ball Grid Array (PBGA) Assignments
View
VCCIO
DVCC
TTIP8
TTIP7
TXVCC
AVCC
RRING6
TTIP6
TTIP5
AVCC
DVCC
RRING8 TXVCC
TRING5 TXVCC RRING5
RPOS8 RNEG8
RTIP8
TRING8
DVCC
TRING7 RTIP7
AVCC
TRING6
RTIP5
INTR
TPOS8 TNEG8
AVCC
RRING7
RTIP6
TXVCC
DVCC
ALE/ MPI_CLK
RNEG7 RCLK7 RPOS7
TCLK8
RCLK8
DVCC
ACK/
TCLK7 RPOS6 TNEG7
TPOS7
VCCIO
RCLK6 TNEG6 TPOS6 RNEG6
VCCIO
RPOS5 RCLK5
RNEG5 TCLK6
TNEG5
TCLK5 TPOS5
VCCIO
VCCIO RCLK4
RNEG4 RPOS4
LXT3108
RBIAS
TST1/
TPOS4 RNEG3
TCLK4 TNEG4
VMOAT
TST2/
TYPE1
RPOS3 TCLK3
TPOS3
RCLK3
QVCC
TYPE2
LOS6
TNEG3 TPOS2 RNEG2 RPOS2
MCLK
LOS7
LOS5
LOS3
RCLK2 RPOS1 TNEG2
RNEG1 RCLK1
DVCC
AVCC
LOS8
LOS4
LOS2
LOS1
TCLK2 TNEG1
TCLK1
TXVCC
RRING2
AVCC
TXVCC
RSTB
TPOS1 VCCIO RRING1 TXVCC TRING1
TTIP2
RTIP2
AVCC
RTIP3
TRING3
DVCC
RTIP4
DVCC
JRST
DVCC
DVCC
AVCC
RTIP1
TTIP1
DVCC
TRING2
RRING3
TXVCC
TTIP3
TTIP4
TRING4
RRING4
VCCIO
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table
Signal Descriptions
LXT3108 Description
Symbol VCCIO Power (I/O). Receive Positive Data/Receive Data Output (Ch. bipolar mode this digital framer interface acts positive side bipolar data output pair, RPOS8 RNEG8, recovered from line interface. unipolar mode, RDATA8 digital framer interface acts single non-return-to-zero (NRZ) output data recovered from line interface. Description
PBGA
RPOS8/ RDATA8
Bipolar Mode: This acts active high non-return-to-zero (NRZ) receive data output. High signal RPOS8 corresponds receipt positive pulse RTIP/RRING. High signal RNEG8 corresponds receipt negative pulse RTIP/ RRING. This signal along with RNEG8 valid falling edge RCLK8. Unipolar Mode: RDATA8 acts receive data output. Receive Negative Data (Ch. bipolar mode this digital framer interface acts negative side bipolar data output pair, RPOS8 RNEG8, recovered from line interface. Bipolar Mode:
RNEG8
This acts active high non-return-to-zero (NRZ) receive signal output. High signal RNEG8 corresponds receipt negative pulse RTIP/ RRING. This signal along with RPOS8 valid falling edge RCLK8. Unipolar Mode: Reserved TBD. Receive Clock Output (Ch. This digital framer interface provides recovered clock from signal received RTIP8 RRING8. Under conditions there transition from RCLK8 signal (derived from recovered data) MCLK signal RCLK8 output. Transmit Positive Data/Transmit Data Input (Ch. bipolar mode this digital framer interface acts positive side bipolar data input pair, TPOS8 TNEG8, which controls signal transmitted line interface. unipolar mode, TDATA8 digital framer interface acts single non-return-to-zero (NRZ) input data controlling signal transmitted line interface. Bipolar Mode: TPOS8 active high input that operates together with TNEG8. TPOS8 starts transmission positive pulse TTIP8/TRING8, whereas TNEG8 starts transmission negative pulse TTIP8/TRING8.
RCLK8
TPOS8/ TDATA8
TPOS8
Unipolar Mode:
TNEG8 Space
Selection
Positive Mark Negative Mark Space
TDATA8 acts single non-return-to-zero (NRZ) input controlling signal transmitted line interface.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table
LXT3108 Description (Continued)
Symbol Description Transmit Negative Data (Ch. bipolar mode this digital framer interface acts negative side bipolar data input pair, TPOS8 TNEG8, which controls signal transmitted line interface. Unipolar Mode: TNEG8 high unipolar mode. Transmit Clock Input (Ch. During normal operation TCLK8 toggles line rate, which 1.544 T1/J1 operation, 2.048 operation. TPOS8 TNEG8, TDATA8, sampled falling edge TCLK8.
PBGA
TNEG8
TCLK Clocked
TCLK8
Operating Mode Normal operation Driver outputs tristated, powered redundancy. Driver outputs tristated powered down reduced power draw.
Note: Transmit Ones (TAOS) generator uses MCLK timing reference. order assure that output frequency within specification limits, MCLK must have applicable stability. RPOS7/ RDATA7 Receive Positive Data/Receive Data Output (Ch. bipolar mode this acts positive side bipolar data output pair, RPOS7 RNEG7, recovered from line interface. unipolar mode, RDATA7 acts single nonreturn-to-zero (NRZ) output data recovered from line interface. Receive Negative Data (Ch. bipolar mode this acts negative side bipolar data output pair, RPOS7 RNEG7, recovered from line interface. Receive Clock Output (Ch. Transmit Positive Data/Transmit Data Input (Ch. bipolar mode this acts positive side bipolar data input pair, TPOS7 TNEG7, which controls signal transmitted line interface. unipolar mode, TDATA7 acts single non-return-to-zero (NRZ) input data controlling signal transmitted line interface. Transmit Negative Data (Ch. bipolar mode this acts negative side bipolar data input pair, TPOS7 TNEG7, which controls signal transmitted line interface. Transmit Clock Input (Ch. Receive Positive Data/Receive Data Output (Ch. bipolar mode this acts positive side bipolar data output pair, RPOS6 RNEG6, recovered from line interface. unipolar mode, RDATA6 acts single nonreturn-to-zero (NRZ) output data recovered from line interface. Receive Negative Data (Ch. bipolar mode this acts negative side bipolar data output pair, RPOS6 RNEG6, recovered from line interface. Receive Clock Output (Ch. Transmit Positive Data/Transmit Data Input (Ch. bipolar mode this acts positive side bipolar data input pair, TPOS6 TNEG6, which controls signal transmitted line interface. unipolar mode, TDATA6 acts single non-return-to-zero (NRZ) input data controlling signal transmitted line interface.
RNEG7 RCLK7
TPOS7/ TDATA7
TNEG7 TCLK7 RPOS6/ RDATA6
RNEG6 RCLK6
TPOS6/ TDATA6
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table
LXT3108 Description (Continued)
Symbol TNEG6 TCLK6 RPOS5/ RDATA5 Description Transmit Negative Data (Ch. bipolar mode this acts negative side bipolar data input pair, TPOS6 TNEG6, which controls signal transmitted line interface. Transmit Clock Input (Ch. Receive Positive Data/Receive Data Output (Ch. bipolar mode this acts positive side bipolar data output pair, RPOS5 RNEG5, recovered from line interface. unipolar mode, RDATA5 acts single nonreturn-to-zero (NRZ) output data recovered from line interface. Receive Negative Data (Ch. bipolar mode this acts negative side bipolar data output pair, RPOS5 RNEG5, recovered from line interface. Receive Clock Output (Ch. Transmit Positive Data/Transmit Data Input (Ch. bipolar mode this acts positive side bipolar data input pair, TPOS5 TNEG5, which controls signal transmitted line interface. unipolar mode, TDATA5 acts single non-return-to-zero (NRZ) input data controlling signal transmitted line interface. Transmit Negative Data (Ch. bipolar mode this acts negative side bipolar data input pair, TPOS5 TNEG5, which controls signal transmitted line interface. Transmit Clock Input (Ch. Ground (I/O) Power (I/O) Receive Positive Data/Receive Data Output (Ch. bipolar mode this acts positive side bipolar data output pair, RPOS4 RNEG4, recovered from line interface. unipolar mode, RDATA4 acts single nonreturn-to-zero (NRZ) output data recovered from line interface. Receive Negative Data (Ch. bipolar mode this acts negative side bipolar data output pair, RPOS4 RNEG4, recovered from line interface. Receive Clock Output (Ch. Transmit Positive Data/Transmit Data Input (Ch. bipolar mode this acts positive side bipolar data input pair, TPOS4 TNEG4, which controls signal transmitted line interface. unipolar mode, TDATA4 acts single non-return-to-zero (NRZ) input data controlling signal transmitted line interface. Transmit Negative Data (Ch. bipolar mode this acts negative side bipolar data input pair, TPOS4 TNEG4, which controls signal transmitted line interface. Transmit Clock Input (Ch. Receive Positive Data/Receive Data Output (Ch. bipolar mode this acts positive side bipolar data output pair, RPOS3 RNEG3, recovered from line interface. unipolar mode, RDATA3 acts single nonreturn-to-zero (NRZ) output data recovered from line interface. Receive Negative Data (Ch. bipolar mode this acts negative side bipolar data output pair, RPOS3 RNEG3, recovered from line interface. Receive Clock Output (Ch.
PBGA
RNEG5 RCLK5
TPOS5/ TDATA5
TNEG5 TCLK5 GNDIO VCCIO RPOS4/ RDATA4
RNEG4 RCLK4
TPOS4/ TDATA4
TNEG4 TCLK4 RPOS3/ RDATA3
RNEG3 RCLK3
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table
LXT3108 Description (Continued)
Symbol Description Transmit Positive Data/Transmit Data Input (Ch. bipolar mode this acts positive side bipolar data input pair, TPOS3 TNEG3, which controls signal transmitted line interface. unipolar mode, TDATA3 acts single non-return-to-zero (NRZ) input data controlling signal transmitted line interface. Transmit Negative Data (Ch. bipolar mode this acts negative side bipolar data input pair, TPOS3 TNEG3, which controls signal transmitted line interface. Transmit Clock Input (Ch. Receive Positive Data/Receive Data Output (Ch. bipolar mode this acts positive side bipolar data output pair, RPOS2 RNEG2, recovered from line interface. unipolar mode, RDATA2 acts single nonreturn-to-zero (NRZ) output data recovered from line interface. Receive Negative Data (Ch.2). bipolar mode this acts negative side bipolar data output pair, RPOS2 RNEG2, recovered from line interface. Receive Clock Output (Ch. Transmit Positive Data/Transmit Data Input (Ch. bipolar mode this acts positive side bipolar data input pair, TPOS2 TNEG2, which controls signal transmitted line interface. unipolar mode, TDATA2 acts single non-return-to-zero (NRZ) input data controlling signal transmitted line interface. Transmit Negative Data (Ch. bipolar mode this acts negative side bipolar data input pair, TPOS2 TNEG2, which controls signal transmitted line interface. Transmit Clock Input (Ch. Receive Positive Data/Receive Data Output (Ch. bipolar mode this acts positive side bipolar data output pair, RPOS1 RNEG1, recovered from line interface. unipolar mode, RDATA1 acts single nonreturn-to-zero (NRZ) output data recovered from line interface. Receive Negative Data (Ch. bipolar mode this acts negative side bipolar data output pair, RPOS1 RNEG1, recovered from line interface. Receive Clock Output (Ch.1) Transmit Positive Data/Transmit Data Input (Ch. bipolar mode this acts positive side bipolar data input pair, TPOS1 TNEG1, which controls signal transmitted line interface. unipolar mode, TDATA1 acts single non-return-to-zero (NRZ) input data controlling signal transmitted line interface. Transmit Negative Data (Ch. bipolar mode this acts negative side bipolar data input pair, TPOS1 TNEG1, which controls signal transmitted line interface. Transmit Clock Input (Ch. Ground (I/O). Power (I/O). Digital Power 3.3V. Digital Ground. Analog Power 3.3V.
PBGA
TPOS3/ TDATA3
TNEG3 TCLK3 RPOS2/ RDATA2
RNEG2 RCLK2
TPOS2/ TDATA2
TNEG2 TCLK2 RPOS1/ RDATA1
RNEG1 RCLK1
TPOS1/ TDATA1
TNEG1 TCLK1 GNDIO VCCIO DVCC DVSS AVCC
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table
LXT3108 Description (Continued)
Symbol RRING1 Description Receive Ring Input (Ch. This pair inputs, RRING1/RTIP1, differential line receiver line interface port. Data clock recovered output digital framer interface output pins. Receive Input (Ch. This pair inputs, RRING1/RTIP1, differential line receiver line interface port. Data clock recovered output digital framer interface output pins. Analog Ground. Transmit Ground. Ground transmit logic. Transmit Power Supply. Power supply transmit logic, 3.3V. Transmit Driver Ground. Ground output driver. Transmit Ring Output (Ch. This pair differential line driver outputs line interface pins, TTIP1/TRING1. TTIP1/TRING1 will high impedance state TCLK static Low. TTIP1/TRING1 tristated port-by-port basis writing TXPD "Port Master Control Page Register, 01h" page "Transmit Control Page Register, 03h" page Please refer "Transmit Idle Operation Tristating Drivers" page details. Transmit Output (Ch. This pair differential line driver outputs line interface pins, TTIP1/TRING1. Transmit Driver Ground. Ground output driver. Digital Ground. Digital Power. 3.3V Transmit Driver Ground. Ground output driver. Transmit Output (Ch. This pair differential line driver outputs line interface pins, TTIP2/TRING2. Transmit Ring Output (Ch. This pair differential line driver outputs line interface pins, TTIP2/TRING2. Transmit Driver Ground. Ground output driver. Transmit Power Supply. Power supply transmit logic, 3.3V. Transmit Ground. Ground transmit logic. Analog Ground Receive Input (Ch. This pair inputs, RRING2/RTIP2, differential line receiver line interface port. Receive Ring Input (Ch. This pair inputs, RRING2/RTIP2, differential line receiver line interface port. Analog Power 3.3V. Digital Ground. Digital Power 3.3V. Analog Power 3.3V. Receive Ring Input (Ch. This pair inputs, RRING3/RTIP3, differential line receiver line interface port. Receive Input (Ch. This pair inputs, RRING3/RTIP3, differential line receiver line interface port. Analog Ground.
PBGA
RTIP1 AVSS TXVSS TXVCC TVSS
TRING1
TTIP1 TVSS DVSS DVCC TVSS TTIP2 TRING2 TVSS TXVCC TXVSS AVSS RTIP2 RRING2 AVCC DVSS DVCC AVCC RRING3 RTIP3 AVSS
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table
LXT3108 Description (Continued)
Symbol TXVSS TXVCC TVSS TRING3 TTIP3 TVSS DVCC DVSS TVSS TTIP4 TRING4 TVSS TXVCC TXVSS AVSS RTIP4 RRING4 AVCC DVSS DVCC GNDIO VCCIO JRST Description Transmit Ground. Ground transmit logic. Transmit Power Supply. Power supply transmit logic, 3.3V. Transmit Driver Ground. Ground output driver. Transmit Ring Output (Ch. This pair differential line driver outputs line interface pins, TTIP3/TRING3. Transmit Output (Ch. This pair differential line driver outputs line interface pins, TTIP3/TRING3. Transmit Driver Ground. Ground output driver. Digital Power 3.3V. Digital Ground. Transmit Driver Ground. Ground output driver. Transmit Output (Ch. This pair differential line driver outputs line interface pins, TTIP4/TRING4. Transmit Ring Output (Ch. This pair differential line driver outputs line interface pins, TTIP4/TRING4. Transmit Driver Ground. Ground output driver. Transmit Power Supply. Power supply transmit logic, 3.3V. Transmit Ground. Ground transmit logic. Analog Ground. Receive Input (Ch. This pair inputs, RRING4/RTIP4, differential line receiver line interface port. Receive Ring Input (Ch. This pair inputs, RRING4/RTIP4, differential line receiver line interface port. Analog Power 3.3V. Digital Ground. Digital Power 3.3V. Ground (I/O). Power (I/O). JTAG Controller Reset Input. Input used reset JTAG controller. This should tied ground through resistor. JTAG Test Mode Select Input. Used control test logic state machine. Sampled rising edge TCK. pulled internally left disconnected. JTAG Data Output. During JTAG operation, this Test Data Output JTAG. Used reading serial configuration test data from internal test logic. updated falling edge TCK. JTAG Data Input. This Test Data input JTAG. Used loading serial instructions data into internal test logic. Sampled rising edge TCK. pulled internally left disconnected. JTAG Clock Input. This clock input JTAG. Connect when used. Reset. This reset LXT3108 octal LIU. microsecond after RSTB goes Low, internal registers will restored their default values.
PBGA
RSTB
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table
LXT3108 Description (Continued)
Symbol Description Loss Signal Output (Ch. When LOS1 output High, indicates loss signal port's line interface receiver. goes active after incoming signal insufficient transitions specified time interval, which determined page global register settings. condition cleared output returns when incoming signal sufficient number transitions specified time interval, determined register settings. Loss Signal Output (Ch. Loss Signal Output (Ch. Loss Signal Output (Ch. Loss Signal Output (Ch. Loss Signal Output (Ch.6). Loss Signal Output (Ch.7). Loss Signal Output (Ch. Microprocessor Type Select Inputs. These pins control which microprocessor interface active:.
PBGA
LOS1
LOS2 LOS3 LOS4 LOS5 LOS6 LOS7 LOS8 TYPE2
TYPE2
TYPE1
TYPE1
Microprocessor
MPC860, M68360 i960, i486 M68302 8051 mux-mode
Chip Select. This active input initiates each access parallel microprocessor interface. each read write operation, must transition from High Low, remain Low. Master Clock Input. MCLK independent, free-running reference clock. It's frequency 8.192MHz T1/E1/J1 operation. This reference clock used generate several internal reference signals: Timing reference integrated clock recovery unit.
MCLK
Timing reference integrated digital jitter attenuator. Generation RCLK signal during loss signal condition. Reference clock during blue alarm transmit ones (TAOS) condition. Reference timing parallel processor wait state generation logic.
VMOAT RBIAS QVSS QVCC
GND. GND. Substrate Ground. Resistor Bias Input. Ohm, resistor must connected from this analog ground. Ground Analog Bias Circuit. Power analog bias circuit. Output Driver Enable Input. this asserted every port's analog driver/ transmitter output immediately enters high impedance state support redundancy applications without external mechanical relays. other internal circuitry stays active. TTIP TRING each port also tristated individually writing TXPD "Port Master Control Page Register, 01h" page "Transmit Control Page Register, 03h" page Please refer "Transmit Idle Operation Tristating Drivers" page details. Ground (I/O).
GNDIO
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table
LXT3108 Description (Continued)
Symbol VCCIO GNDIO VCCIO GNDIO VCCIO DI/O DI/O DI/O DI/O DI/O DI/O DI/O DI/O This functions depending microprocessor interface selected TYPE1 TYPE2 inputs. Read/Write Input (Motorola Mode). Read Enable Input (Intel mode). This functions depending microprocessor interface selected TYPE1 TYPE2 inputs. Data Strobe Input (Motorola Mode). Write Enable Input (Intel mode) This functions depending microprocessor interface selected TYPE1 TYPE2 inputs. Data Transfer Acknowledge Output. (Motorola Mode). Ready Output (Intel mode). Motorola Mode: signal during read operation indicates that information data valid. signal during write operation acknowledges that data transfer into addressed register been accepted (acknowledge signal). This functions depending microprocessor interface selected TYPE1 TYPE2 inputs. Address Latch Enable Input (Intel Mode). address multiplexed address/data clocked into device with falling edge ALE. Microprocessor Clock (Intel I486 Mode). This used input microprocessor clock synchronous i486 mode. Address Input. non-multiplexed mode these inputs function address input pins microprocessor bus. Ground (I/O). Power (I/O). Ground (I/O). Power (I/O). Data Input/Output. When non-multiplexed microprocessor interface selected, these pins function bi-directional 8-bit data bus. When multiplexed microprocessor interface selected, these pins carry both bi-directional 8-bit data address inputs -A7. Power (I/O). Description
PBGA
MPI_CLK
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table
LXT3108 Description (Continued)
Symbol Description Interrupt. This active Low, maskable, open drain output requires external pull-up resistor. corresponding interrupt enable enabled, INTR goes flag microprocessor when LXT3108 changes state (see details interrupt handling section). microprocessor interrupt input should level triggering. Digital Power 3.3V. Digital Ground. Analog Power 3.3V. Receive Ring Input (Ch. This pair inputs, RRING5/RTIP5, differential line receiver line interface port. Receive Input (Ch. This pair inputs, RRING5/RTIP5, differential line receiver line interface port. Analog Ground. Transmit Ground. Ground transmit logic. Transmit Power Supply. Power supply transmit logic, 3.3V. Transmit Driver Ground. Ground output driver. Transmit Ring Output (Ch. This pair differential line driver outputs line interface pins, TTIP5/TRING5. Transmit Output (Ch. This pair differential line driver outputs line interface pins, TTIP5/TRING5. Transmit Driver Ground. Ground output driver. Digital Ground. Digital Power. 3.3V Transmit Driver Ground. Ground output driver. Transmit Output (Ch. This pair differential line driver outputs line interface pins, TTIP6/TRING6. Transmit Ring Output (Ch. This pair differential line driver outputs line interface pins, TTIP6/TRING6. Transmit Driver Ground. Ground output driver. Transmit Power Supply. Power supply transmit logic, 3.3V. Transmit Ground. Ground transmit logic. Analog Ground. Receive Input (Ch. This pair inputs, RRING6/RTIP6, differential line receiver line interface port. Receive Ring Input (Ch. This pair inputs, RRING6/RTIP6, differential line receiver line interface port. Analog Power 3.3V. Digital Power 3.3V. Digital Ground. Analog Power 3.3V. Receive Ring Input (Ch. This pair inputs, RRING7/RTIP7, differential line receiver line interface port.
PBGA
INTR
DVCC DVSS AVCC RRING5 RTIP5 AVSS TXVSS TXVCC TVSS TRING5 TTIP5 TVSS DVSS DVCC TVSS TTIP6 TRING6 TVSS TXVCC TXVSS AVSS RTIP6 RRING6 AVCC DVCC DVSS AVCC RRING7
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table
LXT3108 Description (Continued)
Symbol RTIP7 AVSS TXVSS TXVCC TVSS TRING7 TTIP7 TVSS DVCC DVSS TVSS TTIP8 TRING8 TVSS TXVCC TXVSS AVSS RTIP8 RRING8 AVCC DVSS DVCC GNDIO Description Receive Input (Ch. This pair inputs, RRING7/RTIP7, differential line receiver line interface port. Analog Ground. Transmit Ground. Ground transmit logic. Transmit Power Supply. Power supply transmit logic, 3.3V. Transmit Driver Ground. Ground output driver. Transmit Ring Output (Ch. This pair differential line driver outputs line interface pins, TTIP7/TRING7. Transmit Output (Ch. This pair differential line driver outputs line interface pins, TTIP7/TRING7. Transmit Driver Ground. Ground output driver. Digital Power 3.3V. Digital Ground. Transmit Driver Ground. Ground output driver. Transmit Output (Ch. This pair differential line driver outputs line interface pins, TTIP8/TRING8. Transmit Ring Output (Ch. This pair differential line driver outputs line interface pins, TTIP8/TRING8. Transmit Driver Ground. Ground output driver. Transmit Power Supply. Power supply transmit logic, 3.3V. Transmit Ground. Ground transmit logic. Analog Ground. Receive Input (Ch. This pair inputs, RRING8/RTIP8, differential line receiver line interface port. Receive Ring Input (Ch. This pair inputs, RRING8/RTIP8, differential line receiver line interface port. Analog Power 3.3V. Digital Ground. Digital Power 3.3V. Ground (I/O).
PBGA
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table
LXT3108 Description (Continued)
Symbol DVCC Digital Power 3.3V. Connect. Description
PBGA D8,M9 F10, F11, F12, G10, G11, G12, H10, H11, H12, J10, J11, J12, K10, K11, K12, L10, L11,
Ground.
Functional Description
LXT3108 port-by-port programmable, fully integrated eight-port with jitter attenuator network control maintenance functions. Each LXT3108 port suitable mixed long haul short haul,T1/E1/J1 telecommunications applications allowing full-duplex transmission digital data over existing cable installations. Under microprocessor control with single MCLK source, each port individually operate: either T1/J1 line rates separate line termination impedance settings with preset transmitter pulse shape with preset customized receiver sensitivity with jitter attenuator either transmit receive path, disabled with without zero suppression line coding
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Figure LXT3108 Port Block
LXT3108 Port Block Transmitter
TCLK TPOS TNEG
Network Control Maintenance
TTIP TRING
RCLK RPOS RNEG
RTIP RRING
Receiver
*Jitter Attenuator either transmitter receiver path. disabled.
eight-bit wide data conveys commands from microprocessor each port individually ports same time two-step process. First, writing port number global register described Table "Port Page Select Register, CPS, 00h" page chooses port. next read write operation thenreach port page registers, PPR's, adjusting preset port parameters. Besides PPR's, designer also access ATWG registers described Table "Transmit Coefficient Page Register Range, 40h-6Fh" page LXT3108 fully T1/E1/J1 switchable without need change external components twisted pair applications, allowing development single board design support designs. line rate transformer configuration same cable, will refer both operation throughout this document. line interface cables through standard telecommunications transformers resistors. Each front-end interfaces with twisted pairs: pair transmit, pair receive. These pairs comprise digital data loop full duplex transmission.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Figure LXT3108 Port Circuit
3.3V
TTIP
LXT3108 Port
100p
LINE
TRING
RTIP
LINE
RRING
Framed unframed data clocked TCLK TPOS/TNEG TDATA inputs activates waveshaping line driver circuits. port's transmitter will drive lines from TTIP TRING pins standard telecommunications transformers. line driver handle both CEPT 30/ISDN-PRI lines long haul (CSU) short haul (DSX-1) lines Preset programmable pulse shaping suits both long haul short haul environments. Each port provides eight built-in equalization settings short haul applications line build outs long haul applications. addition, program with Graphical User Interface (GUI) simplifies ATWG control. This allows transmitter performance tuned wide variety line conditions special applications. ATWG provides bits amplitude resolution either (T1) (E1) phases time resolution Unit Intervals (UI). combination proven preset wave-shaping settings ATWG means designer increased flexibility meeting design challenges copper interfaces.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
simplified transmitter circuit configuration offers: Port-by-port programmable line impedance matching. Reduced port component count. Current limiting short-circuits. programming internal transmitter termination, matching line impedance requires component changes twisted pair applications, only balun coaxial cable, shown Figure Figure Transmitter Circuit with Balun Coaxial Cable
LINE
TTIP TRING 1:1:0.8 100/120
Trimming each port's transmitter circuit components single transformer capacitor increases design flexibility. transmitter's current mode driver self-limiting provide built short circuit protection. Efficient flexible line circuit configuration increases designer options maintains line protection. single mandatory clock reference, MCLK, shared between eight clock recovery circuits, enables each receiver LXT3108 recover clock data signals from line interface. After smoothing recovered signals through jitter attenuator, selected, RCLK clocks RDATA RPOS/RNEG port's digital framer interface. Each port's receiver sensitivity ranges from -43dB operation operation. This translates cable reach kilometers 0.63mm cables (E1) 6000 feet cables (T1). analog waveform from line transformer coupled into port's RTIP RRING pins through LXT3108's convenient internal receive termination. This programmable input termination switched between 100, 110, applications, eliminating need change external components twisted-pair cable. designer option selecting software internal receive line termination, bypassing this option with external terminating resistors. cable accomplished with external balun.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Jitter Attenuator
LXT3108 jitter attenuator enhances compatibility with existing network complying with jitter control standards jitter performance LXT3108 conforms stringent specifications AT&T Pub. 62411 TBR12/13. jitter attenuator completely digital does require external crystal. LXT3108 capability insert Jitter Attenuator (JA) either transmit receive data path individually each port. LXT3108 meets long haul short haul specifications pulse shape, pulse variation, cable reach, wander, noise immunity, jitter tolerance, jitter transfer, return loss, short circuit current limiting, loss signal alarm, ones indication, zero code suppression. LXT3108 complies with ANSI T1.403, ANSI T1.408, AT&T 62411, G.703, G.704, G.706, G.775, G.823, I.431, O.151, O.161, ETSI 166, JTG.703, JTI.431, JJ-20.1, TBR12 TBR13. LXT3108 assists network maintenance control with alarm indicators, zero suppression coding detecting, diagnostic modes. Alarm reporting features include interrupts from loss signal, ones indication, AIS. Software controls individually selectable B8ZS/HDB3 line coders decoders each port. Diagnostic modes loop back paths locate line faults provide blue alarm ones pattern line. Each port also generate detect in-band loop codes. Transport physical level alarms, line coding functions, diagnostic modes increase ability maintain control network health.
Functional Description
Each port consists transmitter receiver with jitter attenuator switched between each path. Access host device microprocessor parallel interface configured either Intel Motorola mode. JTAG built-in test chains enable verification on-board digital pins functions.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Figure T1/E1/J1 Block Diagram
TCLK Transmit
TPOS TNEG
Transmit DSP/Control
Transmit
TTIP TRING
DATA0:7
On-Chip
Analog Loopback Local Switchable
Voltage/Current References
Remote Loopback
RPOS RNEG RCLK
Timing/Data Recovery
Decision Feedback Equalizer
Digital Noise Filter Equalizer
Analog
Noise
Filter
Internal Line Termination
RTIP RRING
MCLK
Clock Generator
ENABLE
Activation/Control Logic
Each eight transmitters consists current mode output driver, second-order charge pump PLL, simple digital filter switched-current DAC. filter combination with transmitter provides shaped pulses fitting pulse shape various pulse templates. used store coefficients settings digital transmit waveform generator. Each eight receivers' Analog Front (AFE) consists amplifier, anti-aliasing filter, ADC. digital section consists digital noise filter, root-f equalizer, decision feedback equalizer, timing recovery, adaptation control logic, shown Figure page used store coefficients settings receiver digital filters. programmer controls overall device operation LXT3108 through global registers. Each individual separately controlled Port Page Registers (PPR's). There eight sets PPR, each port. also possible write ports same time case where ports need with same configuration.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Initialization
During power Power-On-Reset (POR) circuit initiates reset sequence after power supply reaches approximately VCC. During power-up, internal reset places registers their default values resets status state machines AIS. MCLK mandatory chip operation.
Reset Operation
LXT3108 reset ways: Writing reset shown "Port Page Select Register, CPS, 00h" page asserting reset low. software, writing reset initiates microsecond reset cycle. reset pulse width must minimum then recommended wait another after reset de-asserted before performing read/write access port registers. This operation sets LXT3108 registers their default values. same way, setting hardware reset pin, RSTB, forces reset condition places registers their default value.
Tolerant pins
digital input pins will tolerate volts compatible with logic. Please note that recommended keep digital input pins less than volts above analog digital supplies. V-tolerance LXT3108 only applicable when 3.3V (nominal) supplies present. Note: External devices such pull-up resistors, logic, microprocessors, system-bus peripherals potential sources signals digital pins. Power-cycling power-supply failure potentially cause situations where LXT3108 powered down, while external devices powered power supply guaranteed prevent this situation, diode network used shown Figure diodes must capable handling entire load capacity either 3.3V supply, whichever greater.
Figure Diode Protection Network When Inputs Power Before Supplies
Supply
supply
supply fails, will helded around volts 3.3V supply. 3.3V supply fails, will held-up around volts supply. Each these conditions safe tolerant pins.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Power Supply Requirements
This section identifies recommended practice layout decoupling power ground planes. Long-term reliability this device might compromised these guidelines followed.
4.3.1
Ground Plane
ground pins should connected solid ground plane with shortest possible path minimize inductive effects. pins with names containing GND, VSS, ground pins. VMOAT should also connected ground plane.
4.3.2
Analog Power Supply
analog supply pins listed below require 3.3V (nominal) supply, which should filtered separately from digital supply. TXVCC TVCC AVCC QVCC recommended method connect analog pins wide trace, connect trace power plane. Bypass capacitors from ground plane analog supply trace should placed close possible following pins: 0.082 capacitor between each TXVCC ground. 0.082 capacitor between each AVCC ground. 0.082 capacitor between each DVCC ground. recommended that analog digital power come from same power supply. prevent excessive current through device, supplies failing sequential power-cycling, suggested that supplies connected back same point.
4.3.3
Digital Power Supply
Digital power supply pins, power DVCC, should connected solid power plane with shortest possible path. Four 0.01 bypass capacitors, side, should placed close possible LXT3108 filter ground power planes circuit board. addition, circuit board should contain tantalum 0.01 ceramic capacitors where power supplied board. with analog power supply, recommended that analog digital power come from same power supply. prevent excessive current through device, supplies failing sequential power-cycling, suggested that supplies connected back same point.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Transmitter
Each eight ports' transmitters offers several features when interfacing from framer device's port transmitter control signals TCLK TDATA TPOS/TNEG. With TCLK clocking line rate TDATA TPOS/TNEG carrying digital traffic, line driver will output E1/J1 signal through center tapped transformer transmit cable pair. eight power transmitters LXT3108 identical. Along with fourteen proven preprogrammed pulse shape shown Table "Transmit Control Page Register, 03h" page designer choose Arbitrary Transmit Waveform Generator (ATWG) tailor pulse shapes application. ATWG, engineers innovative, GUI-based program, supplied Intel. There forty-eight 8-bit registers described Table "Transmit Coefficient Page Register Range, 40h-6Fh" page that redefine transmit waveform. analog current driver uses programmable internal resistive feedback synthesize output impedance either 100, Ohms twisted-pair applications. impedance programmable through port page register Table "Termination Control Page Register, 05h" page When TCLK supplied, transmitter remains powered down TTIP/TRING outputs held high impedance state. eight transmitters simultaneously tristated setting low. Also, programmer port's output enable control individually tristate port transmitters shown "Transmit Control Page Register, 03h" page Please refer "Transmit Idle Operation Tristating Drivers" page details. Transmit data clocked serially into device TPOS/TNEG bipolar mode TDATA unipolar mode. transmit clock (TCLK) supplies input synchronization. Unipolar selected setting appropriate bits described Table "Line Coding Control Page Register, 1Ch" page transmitter samples TPOS/TNEG TDATA inputs falling edge TCLK. Refer Test Specifications Section, Table "Master Transmit Clock Timing Characteristics" page MCLK TCLK timing characteristics.
Figure Encoding
TTIP Cell TRING
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Transmit Line Interface
Each eight transmitters pre-programmed, proven, preset pulse shapes suited driving twisted-pair cables long haul short haul applications. signal from TTIP TRING each port coupled center-tapped transformer shown Figure
Figure Typical Transmitter Interface Connections
3.3V
TTIP
100p
LINE
TRING
center-tapped transformer readily available many packages specified below. Table
Tx/Rx
Transformer Specifications LXT3108
Frequency Turns Ratio Primary Inductance (minimum) Leakage Inductance (max) 0.80 1.10 Interwinding Capacitance (max) (maximum) 0.70 1.20 1.10 1.10 Dielectric1 Breakdown (minimum) 1500 VRMS2 1500 VRMS2
1.544/2.048 1.544/2.048
Some ETSI applications require dielectric breakdown voltage. Some applications require transformers with center line side transformer (Long haul applications with current E1/T1 loop).
programmer control from Port Page Register Bank: Matching line impedance transmitter "Termination Control Page Register, 05h" page Long haul short haul pulse shape "Transmit Control Page Register, 03h" page port line clock rate "Port Master Control Page Register, 01h" page Note: transformer must placed more than inch from respective TTIP/TRING pins. distance greater than inch then Psoftware have used meet pulse template.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
5.1.1
Transmit Impedance Termination
LXT3108's transmitter will synthesize output impedance match either Ohm, Ohm, line TXTERM bits "Termination Control Page Register, 05h" page Preset pulse shaping controls transmit pulse equalization determine transmitted pulse shape shown Table "Transmit Control Page Register, 03h" page Table provides more detail about settings. order port accurately produce desired pulse, software must:
line clock rate "Port Master Control Page Register, 01h". transmit line termination "Termination Control Page Register, 05h". Load preset pulse shape setting "Transmit Control Page Register, 03h".
Table Preset Pulse Shaping Settings Conditions
T1/E1/J1 TCLK Frequency, 1.544 1.544 1.544 1.544 1.544 1.544 1.544 1.544 1.544 2.048 2.048 2.048 2.048 1.544 Cable Range Feet1, Register Bits
Line Build Out,
Cable Impedance, Ohms
Cable Attenuation, 28.5 13.5
DSX1 DSX1 DSX1 DSX1 DSX1
-7.5dB -15dB -22.5dB
5.1.2
Transmit Return Loss Performance
LXT3108 transmitter will meet applicable standard transmit return loss, there several requirements. Because transmit return loss depends match between transmitter circuit output impedance characteristic cable impedance, limits reflections match specifying minimum transmit return loss. ANSI currently does specify this parameter. order compare performance performance, standard adapted show similar minimum return loss. This bench mark that might suitable some applications.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
appropriate software control internal transmit impedance "Termination Control Page Register, 05h", transmit return loss will maximized. There three standards that checked minimum transmit return loss. line rate, G.703 recommends ETSI 300166. line rate, facto standard, however, ETSI 300166 adapted 1.544 MHz, shown Table Table Transmit Return Loss Specifications Frequency Range Magnitude
Transmit Return Loss T1/E1 Frequency Band 51-102 102-2048 2048 3072 39-77 77-1544 1544 2316 Actual Performance Notes
G.703 specification
Adapted benchmark
Figure Typical Output Pulse
Voltage
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
5.1.2.1
Pulse Template Matching (PTM)
output signal LXT3108 adjusted using Psoftware. Each transmit baud, divided into either (E1) (T1) sub-phases. pulse amplitude during each phase described bit, compliment, binary word. Thus, each pulse described with timing resolution Tper/16 amplitude resolution Full Scale/128. transmit words used allowing each shaped pulse extend three baud. Typically short haul pulses only words although bytes available. Long haul pulse shaping extend over three baud. order PTM, operations must take place.
desired words must loaded into LXT3108's local memory. This
done through host API. coding complement from +127 -127 where code +127 creates full scale pulse output. Each approximately 1/127 Care must taken users, possible create nonsensical pulse shapes either miscoding saturating DAC.
After words loaded, assert ATWG_EN loading value "01h"as shown "Transmit
Control Page Register, 03h" page transmit will codes from local registers. These settings maintained long power applied device reset asserted. They overwritten anytime lost when transmitter powered-down shown Figure page contents local memory lost when power removed from chip initialized zeros when reset asserted. user must careful assert ATWG_EN contents local memory have been properly initialized.
Transmit Digital Interface
Input data transmission onto line clocked serially into device TCLK rate. TPOS TNEG bipolar data inputs, TDATA accepts unipolar data. Software controls input data passes through:
jitter attenuator, according Control Page Register, 1Dh" page B8ZS/HD3 encoder, according "Line Coding Control Page Register, 1Ch"
page Data clocked falling edge TCLK shown Figure "Transmit Interface Timing" page
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Figure Transmit Interface Timing
TCLK
tsut
TPOS TNEG
5.2.1
Transmit Idle Operation Tristating Drivers
When transmitter being used, designer conserves power powering down driver circuit. There ways power down transmitter:
Hold port TCLK high clock cycles. Assert TXPD "Port Master Control Page Register, 01h" page software.
this state, TTIP TRING high impedance, analog circuitry associated with transmitter turned off. After restarting TCLK clearing TXPD bit, take several milliseconds transmitter achieve steady state performance. redundancy applications, desirable tristate each driver while leaving transmitter circuitry turned this case there three ways tristate drivers.
Hold port TCLK clock cycles. low, which affects eight ports same time. high "Transmit Control Page Register, 03h" page
this state, TTIP TRING will enter high impedance state. However, this state transmitter will remain powered This will allow transmitters connected parallel redundancy applications. Table Powering Down Transmitter with Static TCLK
TXCLK TXCLK MCLK cycles TXPD TXCLK MCLK cycles Effect Transmitter enters Powered-down State. TTIP TRING enter high_impedence state. TTIP TRING enter high-impedance state.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Figure TCLK Power Down Timing
MCLK
TCLK
MCLK cycles
Power
Receiver
eight receivers LXT3108 identical operate independently. following paragraphs describe operation receiver. receiver coupled line through transformer. input common mode level on-chip. Recovered data presented port's RPOS/RNEG RDATA pins. recovered clock present port's RCLK pin. Upon loss signal, RCLK derived from MCLK. Refer test specification section receiver timing.
Master Reference Clock
MCLK input LXT3108 8.192 clock. MCLK mandatory chip operation. data timing recovery circuits provide input jitter tolerance significantly better than required AT&T 62411 G.823. Test Specifications section Table Table Figure more information.
Receiver Digital Interface
recovered data goes Loss Signal (LOS) Monitor, through Alarm Indication Signal (AIS, Blue Alarm) Monitor. Received data through either B8ZS HDB3 decoder neither. Finally, data sent framer either unipolar bipolar data RDATA RPOS/RNEG pins, recovered clock drives RCLK pin. Received data clocked rising edge RCLK shown Figure receiver function monitors received signal level indicates signal drops below levels given Table unipolar mode with encoding/decoding, receiver reports detecting bipolar violations setting high incrementing counter operation. unipolar mode with B8ZS operation) HDB3 operation) encoding/decoding, device reports B8ZS/HDB3 code violations zero substitution violations also setting high incrementing counter.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
6.2.1
Receiver Idle Conditions
receiver powers down tristates digital pins RCLK, RPOS/RDATA, RNEG, under either following conditions:
When RXPD described "Port Master Control Page Register, 01h" page set. When CHANEN described "Port Receive Enable Page Register, 02h" page
set. Figure Receiver Output Timing
prop
Receiver Line Interface
LXT3108 receiver line interface provides
Programmable line termination described "Termination Control Page Register, 05h"
page
Programmable sensitivity described "Receive Control Page Register, 04h" page Monitor mode, also "Receive Control Page Register, 04h".
LXT3108 internally terminates input line twisted pair applications with combination single external resistor programming termination register match line impedance. advanced DSP- based receiver provides equalization timing recovery signals with 43dB cable loss (E1) cable loss (T1) presence input noise jitter specified ANSI T1.408. receiver provides sensitivity 1024 (E1) sensitivity @772 (T1) steps approximately under software control described "Receive Control Page Register, 04h". advantage these features provide industry standard performance without component changes.
6.3.1
Receive Termination Impedance.
receiver coupled line through transformer. Since part receive termination on-chip input impedance.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Figure Typical Receiver Interface Connections
RTIP
LINE
RRING
receive input impedance parallel combination precision external resistor internal resistor. With external resistor Figure total input impedance user setting appropriate bits register RXTERM, address <x05>, page registers.
6.3.2
Receiver Sensitivity Programming
Under some conditions desirable limit sensitivity receiver. This done programing "Receive Control Page Register, 04h" page This limits range receiver equalizer approximate values shown Table designer selects affected port described "Port Page Select Register, CPS, 00h" page ports simultaneously each port individually.
Table
Receiver Sensitivity
RXCON RX[4:0] T1/E1 Maximum receiver sensitivity (dB) T1/E1 Maximum receiver sensitivity (dB)
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
6.3.2.1
Receiver Monitor Mode
receive equalizer LXT3108 used Monitor Mode applications. Monitor Mode applications require resistive attenuation signal addition small amount cable attenuation (less than dB). Asserting "Receive Control Page Register, 04h" page configures device work Monitor Mode. device must long haul receiver mode Monitor Mode which controlled RXSH "Receive Control Page Register, 04h". With device Monitor Mode, receive equalizer handles signals attenuated resistively plus cable attenuation both applications.
Receiver Status Information
status receiver monitored though "Receiver Equalizer Status Zero Page Register, 06h" page while equalizer settings checked with "Receiver Equalizer Status Page Register, 07h" page "Receiver Equalizer Status Page Register, 08h" page "Receiver Equalizer Status Page Register, 08h" contains status bits that indicate LOS, LOL, overflow conditions DSP. contents "Receiver Equalizer Status Zero Page Register, 06h"and "Receiver Equalizer Status Page Register, 07h" used estimate line attenuation, which translated line length.
Jitter Attenuation (JA)
digital Jitter Attenuation Loop (JAL) combined with Elastic Store (ES) FIFO provides Jitter attenuation. FIFO depth selectable either bits, through Control Page Register, 1Dh" page internal does require external crystal highfrequency (higher than line rate) reference clock. placed either receive transmit data path. Control Page Register, 1Dh" selects enabled disabled, selects receive transmit path.
Figure Jitter Attenuation Loop
FIFO64
TPOS RPOSi TNEG RNEGi
TPOSo RPOS
FIFO
TNEGo RNEG
TCLK RCLKi
DPLL
TCLK RCLK
JASEL0-1
JASEL0-1
MCLK
JACF
control bits
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
FIFO 2-bit 2-bit register (selected register x1D). Data clocked into FIFO with associated clock signal (TCLK RCLK) clocked FIFO with dejittered clock, seen Figure When FIFO within bits overflowing underflowing, FIFO adjusts output clock period. Jitter Attenuator produces constant delay bits associated path. Please refer "Test Specifications" details. This feature used switching redundancy applications. This advanced digital jitter attenuator meets latest jitter attenuation specifications shown Table Table Jitter Attenuation Specifications
AT&T 62411 GR-253-CORE
ITU-T G.735 ITU-T G.7423 ITU-T G.7834
TR-TSY-000009
ETSI CTR12/13 BAPT
Digital Jitter Attenuator (DJA) Status
status detection both underflow overflow conditions reported "Alarm Status Page Register, 12h" page maskable processor interrupts controlled "Interrupt Enable Page Register, 11h" page Details about both types interrupt status reported "Interrupt Status Page Register, 13h" page
Network Control Maintenance Functions
Diagnostic Modes
LXT3108 offers following diagnostic modes:
Network Loop (NLOOP) Code Generator/Detector. Analog loopback (ALOOP) digital transmitter analog transmitter/receiver pins back
digital receiver pins.
Remote loopback (RLOOP) analog receiver analog transmitter pins. Digital loopback (DLOOP) digital transmitter digital receiver pins. Transmit Ones (TAOS) signal sent transmitter driver line.
LXT3108 offers three loopback modes diagnostic purposes: Analog, Remote, Digital Loopback. Network Loop codes activate Remote Loopback from pattern contained signal traffic passing through receiver. Loopbacks selected writing appropriate port's ALOOP "Port Master Control Page Register, 01h" page DLOOP, NLOOP RLOOP bits "Loopback Enable Page Register, 10h" page Transmit Ones control "Transmit Control Page Register, 03h" page
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
8.1.1
In-Band Network Loop Down Code Generator/Detector
LXT3108 transmit in-band Network Loop Loop Down code. Loop code 00001; Loop Down code 001. Loop code transmission occurs when respective bits register x10, set. Loop Down code transmission occurs when respective bits register x10, set. Network Loopback (NLOOP) initiated only when Network Loopback detect function enabled. Writing NLOOP "Loopback Enable Page Register, 10h"enables this mode. With NLOOP detection enabled, receiver looks NLOOP data patterns (00001 enable, disable) input data stream. When receiver detects NLOOP enable data pattern repeated minimum five seconds, device enables RLOOP. device responds both framed unframed NLOOP patterns. Once NLOOP detection enabled chip activated appropriate data pattern, identical Remote Loopback (RLOOP). NLOOP disabled receiving pattern five seconds, activating RLOOP ALOOP, disabling NLOOP detection software.
8.1.2
Analog Loopback
Analog Loopback (ALOOP) exercises maximum number functional blocks. ALOOP operation disconnects RTIP/RRING signal path inputs from line routes transmit outputs back into receive inputs. This tests transmitter, receiver timing recovery sections. ALOOP function overrides other loopback modes. When analog loopback selected receive line still terminated internal termination. When selected, transmitter outputs (TTIP TRING) connected internally receiver inputs (RTIP RRING) shown Figure Data clock output RCLK, RPOS RNEG pins corresponding LIU. Note that signals RTIP RRING pins ignored during analog loopback. ALOOP in"Loopback Enable Page Register, 10h".
Figure Analog Loopback
HDB3/B8ZS Encoder*
TCLK TPOS TNEG
Timing Control
TTIP TRING
RCLK RPOS RNEG
HDB3/B8ZS Decoder*
Timing Recovery
RTIP RRING
Enabled
8.1.3
Digital Loopback
When digital loopback selected, transmit clock data inputs (TCLK, TPOS TNEG) looped back output RCLK, RPOS RNEG pins (see Figure 18). data presented TCLK, TPOS TNEG also output TTIP TRING pins. Note that signals RTIP RRING pins ignored during digital loopback.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Figure Digital Loopback
TCLK TPOS TNEG HDB3/B8ZS Encoder*
Timing Control
TTIP TRING
RCLK RPOS RNEG
HDB3/B8ZS Decoder*
Timing Recovery
RTIP RRING
Enabled
8.1.4
Remote Loopback
During remote loopback shown Figure RTIP RRING inputs routed transmit circuits output TTIP TRING pins. Note that input signals TCLK, TPOS TNEG pins ignored during remote loopback.
Figure Remote Loopback
HDB3/B8ZS Encoder*
TCLK TPOS TNEG
Timing Control
TTIP TRING
RCLK RPOS RNEG
HDB3/B8ZS Decoder*
Timing Recovery
RTIP RRING
Enabled
8.1.5
Transmit Ones (TAOS)
TAOS mode asserting TAOS "Transmit Control Page Register, 03h". Note that TAOS generator uses MCLK timing reference. order assure that output frequency within specification limits, MCLK must have applicable stability shown Table "Master Transmit Clock Timing Characteristics" page Both DLOOP ALOOP modes function correctly with TAOS active. However, TAOS inhibited when RLOOP mode active.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Figure TAOS Data Path
MCLK TAOS mode HDB3/B8ZS Encoder* TCLK TPOS TNEG Timing Control TTIP TRING (ALL 1's)
RCLK RPOS RNEG
HDB3/B8ZS Decoder*
Timing Recovery
RTIP RRING
Enabled
Figure TAOS with Digital Loopback
MCLK TAOS Mode HDB3/B8ZS Encoder* TCLK TPOS TNEG Timing Control TTIP TRING (ALL 1's)
RCLK RPOS RNEG
HDB3/B8ZS Decoder*
Timing Recovery
RTIP RRING
Enabled
Figure TAOS with Analog Loopback
MCLK TAOS Mode TCLK TPOS TNEG HDB3/B8ZS Encoder* Timing Control TTIP TRING (ALL 1's)
RCLK RPOS RNEG
HDB3/B8ZS Decoder*
Timing Recovery
RTIP RRING
Enabled
Line Coding
This section describes LXT3108 functionality related line coding monitoring. LIU's digital framer interface performs functions:
Provides bipolar unipolar interface framer.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Offers line coding decoding AMI, B8ZS HDB3.
Each these functions described detail below: digital framer interface operated functional modes described Table "Line Coding Control Page Register, 1Ch" page
BIPOLAR Digital Positive/Negative/Clock signals, indicating signal polarity. UNIPOLAR- Digital Data/Clock, indicating data. this mode receive will
counted counter reported Table "BPV Counter High Byte Page Register, 1Eh" page Table "BPV Counter Byte Page Register, 1Fh" page
8.2.1
Alternate Mark Inversion (AMI)
(per: G.703) Return-to-Zero (RZ) format where binary "one" (mark) represented either positive negative going pulse binary "zero" (space) represented absence pulse. LXT3108 supports either standards listed below user selection Table "Line Coding Control Page Register, 1Ch" page well Table "LOS Window Page Register, 0Bh" page through Table Page coding alone does provide method ensuring compliance mark/space requirements. term "AMI coding" often used mean that specific methods used suppress excess zeroes signal. ANSI T1.403: more than consecutive zeros. least ones each every time window 8*(N+1) bits, where through Part 68.318: more than consecutive zeroes. average ones density least 12.5%. Each consecutive pulse should alternate polarity (i.e., positive pulse should always followed negative pulse negative pulse should always followed positive pulse) regardless number intervening spaces between pulses. comes from this: alternating marks inversion. consecutive pulses same polarity known bipolar violation (BPV). LXT3108 actively monitors line signal provides count detected BPVs performance monitoring purposes. definition, line signals basic line coding. However, because receivers rely presence marks signal recover clocking, various standards specify maximum space minimum mark density requirements. These cited below:
8.2.1.1
Bipolar with Eight Zero Substitution (B8ZS)
(per: ANSI T1.102) LXT3108 allows separately controlled transmit receive B8ZS encoding each port line rate described "Line Coding Control Page Register, 1Ch" page LXT3108 performs both B8ZS coding transmitted signal) B8ZS decoding received signal). Received BPVs that part B8ZS pattern counted BPVs coding error counter.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
B8ZS overcomes limitations discussed below allows support clear port kbps) data. compatible with standard framing formats. B8ZS coding, eight consecutive zeroes data stream will replaced B8ZS substitution pattern "000VB0VB", which intentional BiPolar Violation (BPV) valid bipolar mark. Note that polarity BPVs marks depends upon polarity last mark before "eighth zero" occurs. This substitution made regardless where eight consecutive zeroes occur datastream, including framing, signaling, alarm bits. opposed ZCS, which operates data within port, B8ZS coding occur across frame boundaries.
8.2.1.2
High Density Bipolar Three (HDB3)
(per: G.703) LXT3108 allows separately controlled transmit receive HDB3 encoding each port line rate described "Line Coding Control Page Register, 1Ch" page Receive side HDB3 decoding selected setting decoding "Line Coding Control Page Register, 1Ch". Similarly, transmit side HDB3 encoding selected setting encoding "Line Coding Control Page Register, 1Ch". Received BPVs that part HDB3 pattern counted BPVs coding violation error counter. HDB3 coding, four consecutive zeroes data stream will replaced HDB3 substitution pattern either "000V" "B00V, which intentional bipolar violation (BPV) valid bipolar mark. This limits maximum number consecutive spaces three. choice substitution pattern made that number pulses between consecutive pulses (i.e., successive pulses alternate polarity). This substitution made regardless where four consecutive zeroes occur datastream, including framing, signaling, alarm bits. LXT3108 performs both HDB3 coding transmitted signal HDB3 decoding received signal.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
8.3.1
Network Maintenance Functions
Loss Signal (LOS)
While appears each port's pin, detected software reading "Receiver Equalizer Status Page Register, 08h" page maskable processor interrupt controlled "Interrupt Enable Page Register, 11h" page available. Details about interrupt status reported "Interrupt Status Page Register, 13h" page Depending whether port configured service, will cleared appropriate zeros density after detection discussed below. Three user registers provided customizing received marks density detector. Users select:
number consecutive spaces that must received declare "LOS Window
Page Register, 0Bh" page
number marks that must received within that window clear "LOS
Threshold Page Register, 0Ch" page
number consecutive zeros that, received while asserted, will continue reassert "LOS Reset Threshold Page Register, 0Dh" page default values given Table Each receiver multi-function detector that used meet T1.231 G.775 requirements systems. These detectors monitor both received signal amplitude received marks density according following table.
Table
Selection Defaults
T1/E1 Window Size Marks Window Clear Marks Window Reset
Users change these values setting USR_LOS "Port Master Control Page Register, 01h" page this set, then desired Window, Set, Reset values must programmed proper operation. short haul operation operates based peak received amplitude during fixed window. G.775 window length programmed "LOS Window Page Register, 0Bh". minimum data density required clear LOS. receiver monitor loads digital counter RCLK frequency. counter incremented each time zero received, reset zero each time (mark) received. Depending operation mode, certain number consecutive zeros sets signal. recovered clock replaced MCLK RCLK output with minimum amount phase errors. (MCLK required receive operation.) When condition cleared, flag reset another transition replaces MCLK with recovered clock RCLK. RPOS/RNEG will high during entire detection period that port.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
8.3.2
Alarm Indication Signal (AIS)
Alarm Indication Signal reports one's signal received RTIP RRING pins. Once detected, port status flag "Alarm Status Page Register, 12h" page maskable processor interrupt controlled "Interrupt Enable Page Register, 11h" page available. Details about interrupt status reported "Interrupt Status Page Register, 13h" page Depending whether port configured service, will cleared appropriate zeros density after detection shown below.
Table
Service Condition Variations
T1/E1 Window Size msec. Spaces Window Clear Spaces Window Reset
(per: G.775) declared when less than three spaces (i.e., less zeroes) detected µsec period data (512 window). This condition should reliably detected presence 1.0E-03 Error Rate (BER), implying that framed all-ones pattern will mistaken AIS. (per: ANSI T1.231) (Blue Alarm) declared when less than five spaces detected msec. window data. This condition will reliably detected presence 1.0E-03 Error Rate (BER). When detected, appropriate status register microprocessor interrupt generated (unless masked).
8.3.3
NLOOP Status
With NLOOP detection enabled "Loopback Enable Page Register, 10h" page receiver looks NLOOP data patterns (00001 enable, disable) input data stream. When receiver detects NLOOP enable data pattern repeated minimum five seconds, device enables RLOOP port status flag "Alarm Status Page Register, 12h" page device responds both framed unframed NLOOP patterns. NLOOP cleared
Receiving pattern five seconds. Activating RLOOP "Loopback Enable Page Register, 10h" page ALOOP "Port
Master Control Page Register, 01h" page
Disabling NLOOP detection "Loopback Enable Page Register, 10h".
maskable processor interrupt NLOOP controlled "Interrupt Enable Page Register, 11h" page Details about NLOOP interrupt status reported "Interrupt Status Page Register, 13h" page
8.3.4
Line Coding Violations
line coding violations reported signal traffic received RTIP RRING pins. Once condition detected, port status flag "Alarm Status Page Register, 12h" page LXT3108 registers that form 16-bit counter each
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
port monitor BPVs Excess zeroes. counter mode bits through "Line Coding Control Page Register, 1Ch". counter enabled count both BPVs Excess Zeroes trouble-shooting purposes, count either BPVs Excess Zeroes only. These counters, "BPV Counter High Byte Page Register, 1Eh" "BPV Counter Byte Page Register, 1Fh", incremented when there valid code violation. counter shadow register that updated second intervals. count value stored shadow register read host. counter reset every second.
8.3.4.1
AMI/B8ZS BPV's
service, only type line coding violation used: Bipolar Violation (BPV) defined consecutive pulses (marks) same polarity with coded stream. When B8ZS encoded signal present B8ZS decoding active, BPV's will detected reported. LXT3108 actively monitors line signal this type coding violation increments counter performance monitoring purposes.
8.3.4.2
AMI/HDB3 BPV's
basic types line coding violations defined: G.703 BiPolar Violation (BPV) defined consecutive pulses (marks) same polarity with coded stream. O.161- HDB3 coding violation defined occurrence consecutive BPVs same polarity that part HDB3 zero substitution coding. LXT3108 actively monitors line signal both types coding violations increments counter performance monitoring purposes.
8.3.4.3
Excess Zeroes (EXZ)
definition depends upon line coding format, explained Table line signal monitored violations maximum space rule "Line Coding Control Page Register, 1Ch" page selected, occurrences increment counter performance monitoring purposes. Table Excess Zero (EXZ) Definitions
Coding Method HDB3 B8ZS Definition (ANSI) string greater than consecutive string greater than consecutive string greater than consecutive Definition (FCC) string with greater than consecutive zeroes string with greater than consecutive zeroes string with greater than consecutive zeroes
Host Interface
microprocessor interface used relay configuration, control, status, data information between LXT3108 external microprocessor micro controller.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
microprocessor interface supports MPC860/M68360 (memory like bus), M68302 (standard Motorola bus), I960/I486 processor bus, 8051 type microcontrollers. 8-bit address data buses supported. Non-multiplexed address data busses supported along with multiplexed address data mode 8051-type micro controller. user selects processor type tying MPI_TYPE pins appropriately. processor interface operate cycle 33Mhz. MPC860 requires cycle relaxed timing I960 requires wait state. Handshaking automatic wait state generation supported. latency processor access fixed wait state signal optional. LXT3108 provides extensive interrupt support. interrupts independently maskable. interrupt output provided. interrupt signal open-drain output.
Supported Processors Connections
LXT3108 supports direct connection MPC860, M68360, M68302 (M68000 family), I486, I960 processors. user selects type processor tying TYPEx pins appropriate connections. connections between processor pins MPI_TYPE programming defined below. Intel processor requires wait state, MPC860 requires relaxed timing.
9.1.1
MPC860/M68360
Motorola MPC860 M68360 supported this mode. Note LXT3108 host interface pins follow MPC860 data endian fashion. MPC860, though there need asynchronous wait states, relaxed write timing should used. LXT3108 requires write data valid prior falling edge write enable.
Table MPC860/M68360 Mode 8-Bit Mode
TYPE1 TYPE2 MPI_CLK R/W# R/W# DSACK1 MPC860 68360
9.1.2
M68302
M68302 M68000) supported this mode. This commonly referred Motorola bus.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table 68302 8-bit mode
TYPE1 TYPE2 MPI_CLK R/W# DTACK 68302
9.1.3
I960/I486
Intel i960/i486 family supported this mode. This synchronous interface with timing being derived from MPI_CLK input. Internally operations will performed next cycle after asserted. wait state required.
Table i960/i486 Mode
TYPE1 TYPE2
MPI_CLK W/R# CLKO1 READY
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
9.1.4
8051 Mode
Table 8051 Mode
TYPE1 TYPE2 MPI_CLK
Interrupts
There four interrupt sources: Status change Loss Signal, LOS, "Receiver Equalizer Status Page Register, 07h" LXT3108's analog/digital processor continuously monitors receiver signal updates specific status indicate presence absence condition. Status change (Alarm Indication Signal) "Alarm Status Page Register, 12h". LXT3108's receiver monitors incoming data stream updates specific status indicate presence absence condition. Status change NLOOP (Network Loop Code) "Alarm Status Page Register, 12h". Elastic Store overflow underflow, (DJA overflow underflow) bits "Alarm Status Page Register, 12h". LXT3108 jitter attenuator updates these based response jitter incoming signal.
9.2.1
Interrupt Enable
LXT3108 provides latched interrupt output (INT). interrupt occurs time there transition enabled status register. Writing logic into mask register will enable respective respective Interrupt status register generate interrupt. power-on default value zeroes. setting interrupt enable does affect operation status registers.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
When there transition enabled status register, associated interrupt status register interrupt generated already pending). When interrupt occurs, asserted Low. output stage consists only pull-down device; external pull-up resistor approximately required support wired-OR operation.
9.2.2
Interrupt Clearing
There three status registers: LOS, AIS, NLOOP. Reading either status register will clear corresponding interrupts with rising edge read data strobe. When there pending interrupts left will back high. Refer Figure "Interrupt Processing FlowChart" page details.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Figure Interrupt Processing FlowChart
Start-up Restart Interrupts enabled
Mask Interrupts
Does High Interrupt interrupt) Condition Exist (interrupt) Read ISR, 02h, read Port Interrupt Status register, each port Read ISR, 02h, port then read Port Interrupt Status, detect/clear interrupt status AIS, NLOOP, DJAx
Mask Which Interrupts
AIS, NLOOP, DJAx
AIS,etc. Write Reg. 11h, Mask Interrupt Write LOS, AIS, etc. bits Reg. Mask LOS, AIS, etc. Interrupts Write AIS, NLOOP, DJAx bits Reg. Mask AIS, NLOOP, DJAx Interrupt
What Interrupt Condition Exists
AIS,etc. Read Alarm Status Reg, Clear AIS, NLOOP, DJAx Interrupt
Read Status Reg, Clear Interrupt
Read Status Reg's, Clear LOS, AIS, etc. Interrupts
Both Interrupt Conditions Masked
goes HIGH
Read Interrupt Status Register, clear previous interrupts
Re-Enable Interrupts
AIS, Re-Enable NLOOP, Which DJAx Interrupt AIS, etc. Write AIS, NLOOP, Write Write"0" LOS, AIS, etc. bits DJAx bits Reg. Reg. 11h, Reg. Mask Mask AIS, NLOOP, Mask Interrupt LOS, AIS, etc. Interrupts DJAx Interrupt
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
10.0
Register Definitions
Since LXT3108 both global registers Port Page Registers (PPR's), first subsection covers global registers second subsection covers port page registers. global registers control parameters affecting operation entire device. registers controls parameters affecting operation single port. nine sets registers, there each eight ports there additional that controls eight ports same time. Because global registers programmed differently than PPR's, this section describes differences:
Access global register reading writing directly global register address. This
single operation read write global register.
Access port page registers writing global register, Port Page Select (PPS) address 00h,
with selected port number. Immediately following this action, access selected port reading writing chosen address. This double operation, write access with port number followed single read write PPR.
10.1
Global Registers
This subsection organized with summary global registers Table followed descriptive listing each global register starting Table Page ending Table Page Table includes global register names addresses LXT3108.
Table Global Register Addresses
Name Port Page Select Register Register Interrupt Port Register Symbol Parallel Port A7-A0 00000000 00000001 00000010 Address Mode
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Port Page Select Register, CPS,
Name Function Writing this register selects index page individual port control registers. used 0000 0001 0010 PS4-PS0 0011 0100 0101 0110 0111 1000 1001 Index/Page Selects Global Register Page Selects Page control registers Port Selects Page control registers Port Selects Page control registers Port Selects Page control registers Port Selects Page control registers Port Selects Page control registers Port Selects Page control registers Port Selects Page control registers Port Selects write page control registers time. Soft-reset, resets ports, entire device.
Note: When Register value equals Read disabled
Table Register,
Name ID7-ID0 Function This register contains unique revision code mask programmed.
Table Interrupt Status Register, ISR,
Name ICR7-ICR0 Function indicates that interrupt occurred respective port.
Table Register Names
Register Name Page select register Register Interrupt Port Register Soft_R PSR3 PSR2 PSR1 PSR0
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
10.2
Port Page Register Bank (PPRB)
Each eight ports LXT3108 independent register control available through Port Page Register Bank. Writing each bank registers two-step process:
Select port writing port number global register Port Page Select (PPS), address 00h.
register address global register across pages. Therefore, writing address time will switch register read/write access last specified value written address 00h.
Immediately after, access registers port reading writing chosen CPRB address.
There additional mode where eight ports set-up identical settings writing first address with 09h. Table Page gives overview CPRB structure each port's LIU. Each port LXT3108 individual CPRB. registers port bank structure descriptively listed range Table Page through Table Page Table Port Page Register Bank Addresses
Name Port Master Control Port Enable, Used Transmit Control Receiver Control Termination Control Equalizer Status0 Equalizer Status1 Equalizer Status2 Window Threshold Reset Threshold Loopback Enable Register Interrupt Enable Register Alarm Status Register Interrupt Status Register Control Register Control Register counter High Byte counter Byte Transmit Pulse Shape Coefficients Symbol MASTER RENEN TXCON RXCON TERM RXSTATUS0 RXSTATUS1 RXSTATUS2 LOSWINLEN LOSTHRES1 LOSTHRES2 BPVCTRHB BPVCTRLB TXCOEF Parallel Port A7-A0 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1011 0000 1100 0000 1101 0001 0000 0001 0001 0001 0010 0001 0011 0001 1100 0001 1101 0001 1110 0001 1111 Address 40h-6Fh Mode
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Port Master Control Page Register,
Address Description Name Status Port Master Control MASTER Note: Upon reset, restored default value Reserved TXPD, powers down transmitter section RXPD, powers down receiver section USR_LOS, enables programmable control digital window, set, clear conditions I431, enables programmable control analog levels clear Reserved ALOOP, enable analog loopback diagnostic mode T1E1, enables 1.544 operation, while enables 2.048 operation Description
Table Port Receive Enable Page Register,
Address Description Port Enable Name CHANEN Status Function high, port receiver starts
Note: Upon reset, restored default value
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Transmit Control Page Register,
Address Description Name Status [4.1] Transmit Control TXCON Note: Upon reset, restored default value Function Transmit ones enable (TAOS) Transmit output high impedance (OES) Transmit Clock Detect Enable Decode bits pre-programmed pulse shapes. short haul 0-133 short haul -266 short haul
short haul -533 short haul long haul long haul -7.5 long haul
long haul -22.5 short haul short haul long haul
long haul encoded pulse) used used ATWG_EN active high enables ATWG operation
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Receive Control Page Register,
Address Description Name RXSH MON_MOD Status [4.0] Receiver Control RXCON Function active high limits receiver short haul operation active high enables monitor mode used Decode bits selecting receive sensitivity E1-43; T1-36 E1-40; T1-34 E1-38; T1-32 E1-36; T1-30 E1-34; T1-28 E1-32; T1-26 E1-30; T1-24 E1-28; T1-22 E1-26; T1-20 E1-24; T1-18 E1-22; T1-16 E1-20; T1-14 E1-18; T1-12 E1-16; T1-10 E1-14; T1-8 E1-22; T1-6 E1-20; T1-4 E1-18; T1-2 E1-16; T1-0 E1-14; T1-36 E1-43; T1-36
Note: Upon reset, restored default value
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Termination Control Page Register,
Address Description Name Status [7.6] Termination Control TX/RX [5.2] TERM [1.0] Decode bits selecting receive termination control Ohms Ohms Ohms Ohms Function Decode bits selecting transmit termination control Ohms Ohms Ohms Ohms through assigned
Note: Upon reset, restored default value
Table Receiver Equalizer Status Zero Page Register,
Address Description Equalizer Status0 Name RXSTATUS0 Status [7.0] Function Reserved
Note: Upon reset, restored default value
Table Receiver Equalizer Status Page Register,
Address Description Name Status [7.4] Equalizer Status1 RXSTATUS1 [3.0] Function Reserved Decode bits selecting state settings Attenuation reading determines cable length this formula:
Note: Upon reset, restored default value
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Receiver Equalizer Status Page Register,
Address Description Name Status Equalizer Status2 RXSTATUS2 Reserved Reserved Function used Reserved
Note: Upon reset, restored default value
Table Window Page Register,
Address Description Name Status Function detector evaluation window. When USER Mode selected, this register must programmed length evaluation window. This number consecutive bits which condition must true before asserted, (e.g. 256, then consecutive will assert LOS).
Window
LOSWINLEN
Note: Upon reset, restored default value
Table Threshold Page Register,
Address Description Name Status Function This register controls functions: Threshold detection mode, treshold LOSTHRES1 detection mode, RSPACELIM
Note: Upon reset, restored default value
Table Reset Threshold Page Register,
Address Description Reset Threshold Name Status Function This register controls functions: LOSTHRES2 detection mode, threshold reset detection mode, RMARKCLR Note: Upon reset, restored default value
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Loopback Enable Page Register,
Address Description Name Status [7.5] Loopback Enable Register Function Bits used DLOOP, Digital loopback, Transmit network Loop Down code Transmit network Loop code NLOOP, Network loopback enabled `1', (Receive) RLOOP, Remote loopback,
Note: Upon reset, restored default value
Table Interrupt Enable Page Register,
Address Description Name Status [7.5] Interrupt Enable Register Function Bits used Underflow Interrupt Enable, Overflow Interrupt Enable, NLOOP Interrupt Enable, Interrupt Enable, Interrupt Enable,
Note: Upon reset, restored default value
Table Alarm Status Page Register,
Address Description Name Status [7.5] Status Register Function Bits used. status overflow status underflow status NLOOP status status
Note: Upon reset, restored default value
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Interrupt Status Page Register,
Address Description Name Status [7.5] Interrupt Status Register NLOOP interrupt status interrupt status Function Bits used. interrupt status overflow interrupt status underflow interrupt status
Note: Upon reset, restored default value
Table Line Coding Control Page Register,
Address Description Name Status [6.5] Control Register Function mode ANSI, Decode bits selecting Counter mode Enable counting both BPVs Excess Zero Enable counting BPVs only Enable counting Excess Zeroes only invalid code
Functions E1AIS_Sel, G.775, ETSI 300233 Transmit B8ZS/HDB3 enable, HDB3/B8ZS Receive B8ZS/HDB3 enable, HDB3/B8ZS Transmit Unipolar/Bipolar select, Bipolar Receive Unipolar/Bipolar select, Bipolar
Note: Upon reset, restored default value
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Control Page Register,
Address Description Name JARES JARST JAJC ES64 Control Register JABW1 JABW0 transmit receive path enable Note: Upon reset, restored default value Status Function reset DJA's elastic store completely reset 0=jamming enabled, 1=jamming disabled depth select, bits, bits JABW1 JABW0 receive path; transmit path enable
Table Counter High Byte Page Register,
Address Description counter high byte Name BPVCTRHB Status Function High byte 16-bit counter shadow register
Note: Upon reset, restored default value
Table Counter Byte Page Register,
Address Description counter byte Name BPVCTRLB Status Function byte 16-bit counter shadow register
Note: Upon reset, restored default value
Table Transmit Coefficient Page Register Range, 40h-6Fh
Address 40-6F Description Transmit Coefficients pulse shaping Name TXCOEF Status Function 16/48 8-bit filter coefficients
Note: Upon reset, restored default value
11.0
JTAG Boundary Scan
LXT3108 supports IEEE 1149.1 compliant JTAG boundary scan. Boundary scan allows easy access interface pins board testing purposes.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
11.1
Architecture
Figure represents LXT3108 basic JTAG architecture:
Figure LXT3108 JTAG Architecture
Boundry Scan Data Register Analog Port Scan Register Device Identification Register Bypass Register Instruction Register
TRST
Controller
LXT3108 JTAG architecture includes Test Access Port Controller, data registers instruction register. following paragraphs describe these blocks detail.
11.2
Controller
controller state synchronous state machine controlled input clocked (see Figure 25). controls whether LXT3108 reset mode, receiving instruction, receiving data, transmitting data idle state. Table describes detail each states represented Figure
Table State Description
State Test Logic Reset -Test/Idle Capture Shift Update Capture Shift Description this state test logic disabled. device normal operation mode. While this state, instruction register ICODE instruction. controller stays this state long low. Used perform tests. Boundary Scan Data Register (BSR) loaded with input data. Shifts selected test data registers stage toward serial output. Data latched into parallel output when selected. Used load instruction register with fixed instruction. Shifts instruction register stage.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table State Description
State Update Pause Pause Exit1 Exit1 Exit2 Exit2 Description Loads instruction into instruction register. Momentarily pauses shifting data through data/instruction registers.
Temporary states that used terminate scanning process.
Figure JTAG State Diagram
TEST-LOGIC RESET
TEST/IDLE
SELECT-DR
SELECT-IR
CAPTURE-DR SHIFT-DR
CAPTURE-IR SHIFT-IR
EXIT1-DR
EXIT1-IR
PAUSE-DR PAUSE-IR
EXIT2-DR
EXIT2-IR
UPDATE-DR
UPDATE-IR
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
11.3
JTAG Register Description
following paragraphs describe each registers represented Figure
11.3.1
Boundary Scan Register (BSR)
shift register that provides access digital pins. used apply read test patterns to/from board. Each associated with scan cell register. Bidirectional pins tristatable pins require more than position register. Data into shifted first.
11.3.2
Device Identification Register (IDR)
register provides access manufacturer number, part number LXT3108 revision. register arranged IEEE 1149.1 represented Table Data into shifted first.
Table Device Identification Register (IDR)
Comments Revision Number Part Number Manufacturer Number
11.3.3
Bypass Register (BYR)
Bypass Register register that allows direct connection between input output.
11.3.4
Instruction Register (IR)
shift register that loads instruction performed. instructions shifted first. Table shows valid instruction codes corresponding instruction description.
Table Instruction Register (IR)
Instruction EXTEST INTEST_ANALOG SAMPLE/PRELOAD IDCODE BYPASS Code Comments Connects TDO. Input pins values loaded into BSR. Output pins values loaded from BSR. Connects TDO. Allows voltage forcing/sensing through AT2. Connects TDO. normal path between LXT3108 logic pins maintained. loaded with signals pins. Connects pin. Serial data from input passed output through Bypass Register.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
12.0
Test Specifications
Table Absolute Maximum Ratings
Parameter supply (reference GND) Input voltage, RTIP/RRING
VCC, TvCC TSTG
-0.5 -6.0 GND-0.5
TVCC
Unit
Input voltage, digital Input current, Storage temperature Thermal Resistance, junction ambient, Thermal Resistance, junction ambient, PBGA voltage,
2000
Caution: Operation these limits permanently damage device. Normal operation these extremes guaranteed. TVCC must differ more than during operation. TGND must differ more than during operation. Transient currents will cause latch-up. TTIP TRING withstand continuous currents Human body model. This design target product specification.
Table Recommended Operating Conditions
Parameter supply
VCC, TVCC short haul
3.135
Typ1
Max5 3.465
Unit Ohms
Test Conditions 3.3V
Ambient operating temperature
100% mark density mark density 100% mark density mark density 100% mark density mark density
Total power dissipation3,
long haul short haul/ long haul
Recommended line load TTIP/ TRING
Typical figures design only; guaranteed subject production testing. TVCC must differ more than Power dissipation specifications TBD. Power dissipation values include shared circuit.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Electrical Characteristics (Over Recommended Operating Conditions)
Parameter High level input voltage1 level input voltage Output High voltage Output voltage Quiescent current Input leakage current Three-state leakage current (all outputs) TTIP/TRING leakage current Output driver rise time LXT3108 interface CMOS logic levels. Output drivers will output logic levels.
IDDQ
VCCIO
Unit
Test Conditions idle power down
idle power down load
Table Transmitter Analog Characteristics
Parameter Output pulse amplitude Peak voltage space Min. 2.14 -0.237 -0.3 Typ. 2.37 Max. 2.60 0.237 0.95 1.05 U.I. U.I. Disabled Unipolar mode Guaranteed design other correlation methods. U.I. path TCLK jitter free Unit consecutive pulses Note: nominal half amplitude Test Condition Tested line side Tested line side
Transmit amplitude variation with supply Difference between pulse sequences Pulse width ratio positive negative pulses 51kHz Transmit return loss coaxial cable1 2.048 2.048 3.072 Transmit return loss twisted pair cable1 51kHz 2.048 2.048 3.072
Transmit intrinsic jitter; 20Hz Bipolar mode Transmit path delay
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Receiver Analog Characteristics
Parameter Permissible cable attenuation Receiver sensitivity 1024 line loss) short haul/12 long haul/43 Consecutive zeros before loss signal 2048 reset delay time reset limit input jitter tolerance 0.05 12.5% marks U.I. U.I. Disabled Unipolar mode U.I. Wide band jitter 13.6 Min. Typ. Max. G.775 recommendation ETSI specification density Data recovery mode Data recovery mode G.823 recommendation Note Cable Attenuation @1.024 G.703, O.151 cable Attenuation Rel. peak input voltage Receiver sensitivity 1024 line loss) Unit Test Condition @1024
Receiver dynamic range Signal noise interference margin Data decision threshold Data slicer threshold (short haul) Loss signal threshold
Differential receiver input impedance Common mode input impedance ground Input termination resistor tolerance Input return loss1 2048 2048kHz 3072 Receive intrinsic jitter, RCLK output Receive path delay Bipolar mode
Guaranteed design other correlation methods.
Table Transmitter Analog Characteristics
Parameter Output pulse amplitude Peak voltage space Transmit amplitude variation with power supply Min. -0.15 Typ. Max. +0.15 Unit Test Condition Measured
Guaranteed design other correlation methods. Power measured bandwidth point signal arrives distribution frame pattern.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Transmitter Analog Characteristics (Continued)
Parameter Imbalance between positive negative pulse amplitude Difference between pulse sequences Pulse width variation half amplitude 10Hz Jitter added Transmitter1 8KHz 10Hz Wide Band Output power levels2 1544 77KHz Transmit Return Loss 1544 1544 2316KHz Bipolar mode Transmit path delay Unipolar mode U.I. Min. 0.95 12.6 Typ. Max. 1.05 0.05 17.9 17.9 Unit UIpk-pk UIpk-pk UIpk-pk UIpk-pk U.I. Disabled T1.102 1993 Referenced power AT&T 62411 TCLK jitter free Test Condition T1.102, isolated pulse consecutive pulses, GR-499-CORE
Guaranteed design other correlation methods. Power measured bandwidth point signal arrives distribution frame pattern.
Table Receiver Analog Characteristics
Parameter Permissible cable attenuation Receiver sensitivity line loss) short haul/12 long haul/36 Min. -16.5 U.I. AT&T Pub. 62411 Typ. 13.6 Max. T1.231 1993 ABAM cable Rel. peak input voltage Receiver sensitivity line loss) Unit Test Condition
Receiver dynamic range Signal noise interference margin Data decision threshold Data slicer threshold (Short Haul) Loss signal threshold hysteresis Consecutive zeros before loss signal limit input jitter tolerance 10Hz 300Hz 10KHz 100KHz
Differential receiver input impedance Common mode input impedance ground Input termination resistor tolerance
@772
Guaranteed design other correlation methods.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Receiver Analog Characteristics (Continued)
Parameter 77KHz Input return loss1 1544 1544 2316KHz Receive intrinsic jitter, RCLK output Receive path delay Bipolar mode Unipolar mode
Min.
Typ.
Max. 0.05
Unit U.I. U.I.
Test Condition
Wide band jitter Disabled
U.I.
Guaranteed design other correlation methods.
Table General Analog Performance
Parameter Internal transmitter impedance tolerance Pulse amplitude variation Pulse amplitude variation Squelch level short haul Un-squelch level long haul Squelch level short haul Un-squelch level long haul Interference conditions include longitudinal modulation, power related interference, sinusoidal jitter Gaussian/Single Tone NEXT specified T1.408. DSX-1, CEPT (ITU) Typ1 Unit Test Conditions Matching line load
Receiver performance with cable (T1.408-1992) (i.e. minimum signal-to-noise ratio)
Line side short circuit current (E1) Line side short circuit current (T1)
Typical figures design only; guaranteed subject production testing.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Master Transmit Clock Timing Characteristics
Parameter Master clock frequency Master clock tolerance Master clock duty cycle Transmit clock frequency Transmit clock frequency Transmit clock tolerance Transmit clock duty cycle TPOS/TNEG TCLK setup time TCLK TPOS/TNEG hold time MCLK MCLKt MCLKd TCLK TCLK TCLKt TCLKd Tsut Typ1 8.192 1.544 2.048 Unit Notes Must supplied
Typical figures design only; guaranteed subject production testing.
Figure Transmit Clock Timing Diagram
TCLK
TPOS TNEG
tSUT
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Jitter Attenuator Characteristics
Parameter 32bit FIFO JACF=0 64bit jitter attenuator corner frequency JACF=1 64bit FIFO 32bit FIFO JACF=0 64bit jitter attenuator corner frequency JACF=1 64bit FIFO Jitter attenuator corner frequency, 32bit FIFO Data latency delay 64bit FIFO 32bit Input jitter tolerance before FIFO overflow underflow FIFO 64bit FIFO jitter attenuation jitter attenuation Output Jitter remote loopback
Min. -0.5 -0.5 +19.5 +19.5 33.3
Typ. 0.11
Max.
Unit
Test Condition
FIFO 32bit FIFO
Sinusoidal jitter modulation
FIFO 32bit FIFO
Delay through Jitter attenuator only. total receive path delay total transmit path delay.
ITU-T G.736
AT&T Pub. 62411
ETSI CTR12/13 Output jitter
Guaranteed design other correlation methods.
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table Receive Timing Characteristics Operation
Parameter Receive clock duty cycle Receive clock pulse width
RLCKd tPWH tPWL tSUR
Typ1
Unit
Receive clock pulse width High Receive clock pulse width RPOS/RNEG RCLK rising time RCLK rising RPOS/RNEG hold time
Typical figures design only; guaranteed subject production testing. RCLK duty cycle widths will vary according extent received pulse jitter displacement. RCLK duty cycles worst case jitter conditions. Worst case conditions guaranteed design only.
Table Receive Timing Characteristics Operation
Parameter Receive clock duty cycle Receive clock pulse width Receive clock pulse width High Receive clock pulse width RPOS/RNEG RCLK rising time RCLK rising RPOS/RNEG hold time
RLCKd tPWH tPWL tSUR
Typ1
Unit
Typical figures design only; guaranteed subject production testing. RCLK duty cycle widths will vary according extent received pulse jitter displacement. RCLK duty cycles worst case jitter conditions. Worst case conditions guaranteed design only.
Figure Receive Clock Timing Diagram
RCLK
tPWH
tPWL
tSUR
RPOS RNEG
CLKE
tSUR
RPOS RNEG
CLKE
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Figure LXT3108 Output Jitter CTR12/13 Applications
Jitter Amplitude (Ulpp)
0.15
0.05
Frequency
Figure JTAG Timing
Table JTAG Timing Characteristics
Parameter Cycle time J-TMS/J-TDI J-TCK rising edge time J-CLK rising J-TMS/L-TDI hold time J-TCLK falling J-TDO valid Tcyc Tsut Tdod Unit Test Conditions
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Table G.703 2.048 Mbps Pulse Mask Specifications
Cable Parameter Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio positive negative pulse amplitudes center pulse Ratio positive negative pulse amplitudes nominal half amplitude ±0.30 95-105 95-105 Coax 2.37 ±0.237 95-105 95-105 Unit
Figure G.703 Mask Templates
(244+25)
100%
(244-
NOMINAL PULSE
(244-25)
(244+244)
Table T1.102 1.544 Mbps Pulse Mask Specifications
Cable Parameter Test load impedance Nominal peak mark voltage Nominal peak space voltage Nominal pulse width Ratio positive negative pulse amplitudes ±0.15 95-105 Unit
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Figure T1.102 Mask Templates
1.20 1.00 0.80 0.60 0.40 0.20 0.00 0.00 -0.20 -0.40 -0.60 Time [UI]
Normalized Amplitude -0.80
-0.60
-0.40
-0.20
0.20
0.40
0.60
0.80
1.00
1.20
Figure LXT3108 Jitter Tolerance Performance
1000
AT&T 62411, 1990 (T1)
Jitter
GR-499-CORE, 1995 (T1) G.823, 1993 (E1)
Frequency
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
Figure LXT3108 Jitter Transfer Performance
G.736 Template
40Hz
Gain
-19.5
-19.5
Frequency
AT&T 62411 GR-253-CORE TR-TSY-000009
Gain
-33.3 -33.7 2.5kHz
-49.2 15kHz
Frequency
LXT3108 Octal T1/E1/J1 Long Haul/Short Haul Line Interface Unit
12.1
Supported Microprocessors Connections
LXT3108 supports direct connection MPC860, M68360, M68302, I486, I960 8051 microprocessors. address data bus. user select

LXT3108

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