LTC2261-14 LTC2260-14 LTC2259-14
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marking 101 900MHz - marking 101 900MHz
LTC5527 - LTC5527
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LTC2260-14 - LTC2260-14
LTC2259-14 - LTC2259-14
LTC2261-14 LTC2260-14/LTC2259-14 14-Bit, 125/105/80Msps Ultralow Power 1.8V ADCs FEATURES
®2261-14/LTC2260-14/LTC2259-14 sampling 14-bit converters designed digitizing high frequency, wide dynamic range signals. They perfect demanding communications applications with performance that includes 73.4dB 85dB spurious free dynamic range (SFDR). Ultralow jitter 0.17psRMS allows undersampling frequencies with excellent noise performance. specs include ±1LSB (typical), ±0.3LSB (typical) missing codes over temperature. transition noise 1.2LSBRMS. digital outputs either full rate CMOS, double data rate CMOS, double data rate LVDS. separate output power supply allows CMOS output swing range from 1.2V 1.8V. ENC+ ENC- inputs driven differentially single ended with sine wave, PECL, LVDS, CMOS inputs. optional clock duty cycle stabilizer allows high performance full speed wide range clock duty cycles.
Lare registered trademarks Linear Technology Corporation. other trademarks property their respective owners.
73.4dB 85dB SFDR Power: 127mW/106mW/89mW Single 1.8V Supply CMOS, CMOS LVDS Outputs Selectable Input Ranges: 1VP-P 2VP-P 800MHz Full-Power Bandwidth Optional Data Output Randomizer Optional Clock Duty Cycle Stabilizer Shutdown Modes Serial Port Configuration Compatible 14-Bit 12-Bit Versions 40-Pin (6mm 6mm) Package
APPLICATIONS
Communications Cellular Base Stations Software Defined Radios Portable Medical Imaging Multi-Channel Data Acquisition Nondestructive Testing
TYPICAL APPLICATION
2-Tone FFT, 70MHz 75MHz
1.8V 1.2V 1.8V OVDD AMPLITUDE (dBFS)
ANALOG INPUT INPUT
14-BIT PIPELINED CORE
CORRECTION LOGIC
OUTPUT DRIVERS
CMOS LVDS OGND
CLOCK/DUTY CYCLE CONTROL
226114 TA01a
-100 -110 -120 FREQUENCY (MHz)
226114 TA01b
125MHz CLOCK
226114f
LTC2261-14 LTC2260-14/LTC2259-14 ABSOLUTE MAXIMUM RATINGS
(Notes
Supply Voltages (VDD, OVDD) -0.3V Analog Input Voltage (AIN+, AIN-, PAR/SER, SENSE) (Note .-0.3V (VDD 0.2V) Digital Input Voltage (ENC+, ENC-, SDI, SCK) (Note -0.3V 3.9V (Note -0.3V 3.9V
Digital Output Voltage -0.3V (OVDD 0.3V) Operating Temperature Range: LTC2261C, LTC2260C, LTC2259C. 70°C LTC2261I, LTC2260I, LTC2259I -40°C 85°C Storage Temperature Range. -65°C 150°C
CONFIGURATIONS
D12_13 D10_11 SENSE FULL-RATE CMOS OUTPUT MODE VIEW VREF DOUBLE DATA RATE CMOS OUTPUT MODE VIEW SENSE VREF D8_9 CLKOUT+ CLKOUT- OVDD OGND D6_7 D4_5 D0_1 D2_3 ENC+ ENC-
AIN+ AIN- REFH REFH REFL REFL PAR/SER ENC+ ENC- CLKOUT+ CLKOUT- OVDD OGND AIN+ AIN- REFH REFH REFL REFL PAR/SER
PACKAGE 40-LEAD (6mm 6mm) PLASTIC
PACKAGE 40-LEAD (6mm 6mm) PLASTIC
TJMAX 150°C, 32°C/W EXPOSED (PIN GND, MUST SOLDERED
TJMAX 150°C, 32°C/W EXPOSED (PIN GND, MUST SOLDERED
DOUBLE DATA RATE LVDS OUTPUT MODE VIEW D12_13+ D12_13- D10_11+ D2_3- D10_11- D8_9+ D8_9- CLKOUT+ CLKOUT- OVDD OGND D6_7+ D6_7- D4_5+ D4_5- ENC+ ENC- D0_1- D0_1+ D2_3+ SENSE VREF
AIN+ AIN- REFH REFH REFL REFL PAR/SER
PACKAGE 40-LEAD (6mm 6mm) PLASTIC
TJMAX 150°C, 32°C/W EXPOSED (PIN GND, MUST SOLDERED
226114f
LTC2261-14 LTC2260-14/LTC2259-14 ORDER INFORMATION
LEAD FREE FINISH LTC2261CUJ-14#PBF LTC2261IUJ-14#PBF LTC2260CUJ-14#PBF LTC2260IUJ-14#PBF LTC2259CUJ-14#PBF LTC2259IUJ-14#PBF TAPE REEL LTC2261CUJ-14#TRPBF LTC2261IUJ-14#TRPBF LTC2260CUJ-14#TRPBF LTC2260IUJ-14#TRPBF LTC2259CUJ-14#TRPBF LTC2259IUJ-14#TRPBF PART MARKING* LTC2261UJ-14 LTC2261UJ-14 LTC2260UJ-14 LTC2260UJ-14 LTC2259UJ-14 LTC2259UJ-14 PACKAGE DESCRIPTION 40-Lead (6mm 6mm) Plastic 40-Lead (6mm 6mm) Plastic 40-Lead (6mm 6mm) Plastic 40-Lead (6mm 6mm) Plastic 40-Lead (6mm 6mm) Plastic 40-Lead (6mm 6mm) Plastic TEMPERATURE RANGE 70°C -40°C 85°C 70°C -40°C 85°C 70°C -40°C 85°C
Consult Marketing parts specified with wider operating temperature ranges. *The temperature grade identified label shipping container. Consult Marketing information non-standard lead based finish parts. more information lead free part marking, http://www.linear.com/leadfree/ more information tape reel specifications,
CONVERTER CHARACTERISTICS denotes specifications which apply over full operating
temperature range, otherwise specifications 25°C. (Note
LTC2261-14 PARAMETER Resolution Missing Codes) Integral Linearity Error Differential Linearity Error Offset Error Gain Error Offset Drift Full-Scale Drift Transition Noise Internal Reference External Reference External Reference Differential Analog Input (Note Internal Reference External Reference CONDITIONS
LTC2260-14 -3.75 -0.9 -1.5 ±0.3 ±1.5 ±1.5 ±0.4 3.75
LTC2259-14 -3.5 -0.9 -1.5 ±0.3 ±1.5 ±1.5 ±0.4 UNITS Bits V/°C ppm/°C ppm/°C LSBRMS
±0.3 ±1.5 ±1.5 ±0.4
3.75
Differential Analog Input (Note -3.75 -0.9 -1.5
226114f
LTC2261-14 LTC2260-14/LTC2259-14 ANALOG INPUT
SYMBOL PARAMETER VIN(CM) VSENSE IINCM Analog Input Range (AIN+ AIN-) Analog Input Common Mode (AIN+ AIN-)/2 Analog Input Common Mode Current
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS 1.7V 1.9V Differential Analog Input (Note Pin, 125Msps Pin, 105Msps Pin, 80Msps AIN+, AIN- VDD, Encode PAR/SER 0.625 SENSE 1.3V
100mV 0.625
1.250
100mV 1.300
UNITS VP-P
External Voltage Reference Applied SENSE External Reference Mode
IIN1 IIN2 IIN3 tJITTER CMRR BW-3B
Analog Input Leakage Current PAR/SER Input Leakage Current SENSE Input Leakage Current Sample-and-Hold Acquisition Delay Time Sample-and-Hold Acquisition Delay Jitter Analog Input Common Mode Rejection Ratio Full-Power Bandwidth
0.17
psRMS
Figure Test Circuit
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. -1dBFS. (Note
LTC2261-14 SYMBOL PARAMETER Signal-to-Noise Ratio CONDITIONS 5MHz Input 70MHz Input 140MHz Input
DYNAMIC ACCURACY
LTC2260-14 71.3 73.4 73.2 72.7 72.6
LTC2259-14 70.9 73.1 72.9 72.4 72.9 72.6 UNITS
71.3
73.4 73.2 72.7 72.6
SFDR
Spurious Free Dynamic Range 5MHz Input Harmonic 70MHz Input 140MHz Input Spurious Free Dynamic Range 5MHz Input Harmonic Higher 70MHz Input 140MHz Input
S/(N+D)
Signal-to-Noise Plus Distortion Ratio
5MHz Input 70MHz Input 140MHz Input
70.2
70.2
70.4
INTERNAL REFERENCE CHARACTERISTICS
PARAMETER Output Voltage Output Temperature Drift Output Resistance VREF Output Voltage VREF Output Temperature Drift VREF Output Resistance VREF Line Regulation -400A IOUT 1.7V 1.9V -600A IOUT IOUT CONDITIONS IOUT
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
25mV 1.225 1.250 1.275 25mV UNITS ppm/°C ppm/°C mV/V
226114f
LTC2261-14 LTC2260-14/LTC2259-14 DIGITAL INPUTS OUTPUTS
SYMBOL PARAMETER ENCODE INPUTS (ENC+, ENC- Differential Encode Mode (ENC- Tied GND) VICM COUT Differential Input Voltage Common Mode Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Level Input Voltage Input Voltage Range Input Resistance Input Capacitance High Level Input Voltage Level Input Voltage Input Current Input Capacitance Logic Output Resistance Logic High Output Leakage Current Output Capacitance (Note Internally Externally (Note ENC+, ENC- (See Figure (Note 1.8V 1.8V ENC+ (See Figure (Note 1.8V 1.8V 3.6V (Note 1.8V, 3.6V (Note
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS UNITS
Single-Ended Encode Mode (ENC- Tied GND)
DIGITAL INPUTS (CS, SDI, SCK)
OUTPUT (Open-Drain Output. Requires Pull-Up Resistor Used)
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE DOUBLE DATA RATE) OVDD 1.8V RTERM High Level Output Voltage Level Output Voltage High Level Output Voltage Level Output Voltage High Level Output Voltage Level Output Voltage Differential Output Voltage Common Mode Output Voltage On-Chip Termination Resistance -500A 500A -500A 500A -500A 500A Differential Load, 3.5mA Mode Differential Load, 1.75mA Mode Differential Load, 3.5mA Mode Differential Load, 1.75mA Mode Termination Enabled, OVDD 1.8V
1.750
1.790 0.010 1.488 0.010 1.185 0.010 0.050
1.375
OVDD 1.5V
OVDD 1.2V
DIGITAL DATA OUTPUTS (LVDS MODE) 1.125 1.250 1.250
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LTC2261-14 LTC2260-14/LTC2259-14 POWER REQUIREMENTS
SYMBOL PARAMETER OVDD IVDD IOVDD PDISS Analog Supply Voltage Output Supply Voltage Analog Supply Current Digital Supply Current Power Dissipation CONDITIONS (Note (Note Input Sine Wave Input Sine Wave Input, OVDD=1.2V
Input Sine Wave Input, OVDD=1.2V
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
LTC2261-14 70.5 71.8 75.4 20.7 40.5 83.2 58.6 59.8 63.4 20.7 40.5 CMOS Output Modes: Full Data Rate Double Data Rate 69.1 49.2 50.2 53.8 20.7 40.5 58.1 LTC2260-14 LTC2259-14 UNITS
LVDS Output Mode OVDD IVDD IOVDD PDISS Analog Supply Voltage Output Supply Voltage Analog Supply Current Digital Supply Current (0VDD 1.8V) Power Dissipation (Note (Note Sine Wave Input Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode Sine Input, 1.75mA Mode Sine Input, 3.5mA Mode
47.8
74.8 47.8
63.5 47.8
Output Modes PSLEEP PNAP PDIFFCLK Sleep Mode Power Mode Power Power Increase with Differential Encode Mode Enabled increase Sleep Modes)
TIMING CHARACTERISTICS
SYMBOL PARAMETER Sampling Frequency Time (Note High Time (Note Sample-and-Hold Acquisition Delay Time PARAMETER Data Delay CLKOUT Delay DATA CLKOUT Skew Pipeline Latency CONDITIONS (Note
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
LTC2261-14
LTC2260-14 4.52 2.00 4.52 2.00 4.76 4.76 4.76 4.76
LTC2259-14 5.93 2.00 5.93 2.00 6.25 6.25 6.25 6.25 UNITS
Duty Cycle Stabilizer Duty Cycle Stabilizer Duty Cycle Stabilizer Duty Cycle Stabilizer
SYMBOL tSKEW
CONDITIONS (Note (Note (Note Full Data Rate Mode Double Data Rate Mode
UNITS Cycles Cycles
Digital Data Outputs (CMOS Modes: Full Data Rate Double Data Rate)
226114f
LTC2261-14 LTC2260-14/LTC2259-14 TIMING CHARACTERISTICS
SYMBOL tSKEW PARAMETER Data Delay CLKOUT Delay DATA CLKOUT Skew Pipeline Latency Port Timing (Note tSCK Period Setup Time Setup Time Setup Time Hold Time Falling Valid Readback Mode, CSDO 20pF RPULLUP Write Mode Readback Mode, CSDO 20pF RPULLUP
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS (Note (Note (Note
UNITS Cycles
Digital Data Outputs (LVDS Mode)
Note Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. Exposure Absolute Maximum Rating condition extended periods affect device reliability lifetime. Note voltage values with respect with OGND shorted (unless otherwise noted). Note When these voltages taken below above VDD, they will clamped internal diodes. This product handle input currents greater than 100mA below above without latchup. Note When these voltages taken below they will clamped internal diodes. When these voltages taken above they will clamped internal diodes. This product handle input currents greater than 100mA below without latchup. Note OVDD 1.8V, fSAMPLE 125MHz (LTC2261), 105MHz (LTC2260), 80MHz (LTC2259), LVDS outputs with internal
termination disabled, differential ENC+/ENC- 2VP-P sine wave, input range 2VP-P with differential drive, unless otherwise noted. Note Integral nonlinearity defined deviation code from best straight line transfer curve. deviation measured from center quantization band. Note Offset error offset voltage measured from -0.5 when output code flickers between 0000 0000 0000 1111 1111 1111 complement output mode. Note Guaranteed design, subject test. Note 1.8V, fSAMPLE 125MHz (LTC2261), 105MHz (LTC2260), 80MHz (LTC2259), ENC+ single-ended 1.8V square wave, ENC- input range 2VP-P with differential drive, load each digital output unless otherwise noted. Note Recommended operating conditions.
TIMING DIAGRAMS
Full-Rate CMOS Output Mode Timing Outputs Single-Ended Have CMOS Levels
ANALOG INPUT ENC- ENC+ D0-D13,
CLKOUT CLKOUT
226114 TD01
226114f
LTC2261-14 LTC2260-14/LTC2259-14 TIMING DIAGRAMS
Double Data Rate CMOS Output Mode Timing Outputs Single-Ended Have CMOS Levels
ANALOG INPUT ENC- ENC+ D0_1 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2
D12_13 D12N-5 D13N-5 D12N-4 D13N-4 D12N-3 D13N-3 D12N-2 D13N-2
OFN-5
OFN-4
OFN-3
OFN-2
CLKOUT+ CLKOUT
226114 TD02
Double Data Rate LVDS Output Mode Timing Outputs Differential Have LVDS Levels
ANALOG INPUT ENC- ENC+ D0_1+ D0_1- D12_13+ D12_13- CLKOUT+ CLKOUT OFN-5 OFN-4 OFN-3 OFN-3 D12N-5 D13N-5 D12N-4 D13N-4 D12N-3 D13N-3 D12N-2 D13N-2 D0N-5 D1N-5 D0N-4 D1N-4 D0N-3 D1N-3 D0N-2 D1N-2
226114 TD03
226114f
LTC2261-14 LTC2260-14/LTC2259-14 TIMING DIAGRAMS
Port Timing (Readback Mode)
HIGH IMPEDANCE tSCK
Port Timing (Write Mode)
HIGH IMPEDANCE
226114 TD04
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2261-14: Integral Non-Linearity (INL)
ERROR (LSB) ERROR (LSB) -0.5 -1.0 -1.5 -2.0 4096 8192 12288 OUTPUT CODE 16384
226114
LTC2261-14: Differential Non-Linearity (DNL)
AMPLITUDE (dBFS) -0.2 -0.4 -0.6 -0.8 -1.0 4096 8192 12288 OUTPUT CODE 16384
226114
LTC2261-14: Point FFT, 5MHz -1dBFS, 125Msps
-100 -110 -120 FREQUENCY (MHz)
226114
226114f
LTC2261-14 LTC2260-14/LTC2259-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2261-14: Point FFT, 30MHz -1dBFS, 125Msps
AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS) FREQUENCY (MHz)
226114
LTC2261-14: Point FFT, 70MHz -1dBFS, 125Msps
LTC2261-14: Point FFT, 140MHz -1dBFS, 125Msps
-100 -110 -120 FREQUENCY (MHz)
226114
-100 -110 -120
-100 -110 -120 FREQUENCY (MHz)
226114
LTC2261-14: Point 2-Tone FFT, 70MHz, 75MHz, -1dBFS, 125Msps
AMPLITUDE (dBFS) 4000 5000 6000
LTC2261-14: Shorted Input Histogram
(dBFS) 1000 8178 8180 8182 8184 OUTPUT CODE 8186
226114
LTC2261-14: Input Frequency, -1dB, Range, 125Msps
-100 -110 -120 FREQUENCY (MHz)
226114
COUNT
3000 2000
INPUT FREQUENCY (MHz)
226114
LTC2261-14: SFDR Input Frequency, -1dB, Range, 125Msps
SFDR (dBc dBFS) INPUT FREQUENCY (MHz)
LTC2261-14: SFDR Input Level, 70MHz, Range, 125Msps
dBFS
LTC2261-14: IVDD Sample Rate, 5MHz Sine Wave Input, -1dB
LVDS OUTPUTS IVDD (mA) CMOS OUTPUTS
SFDR (dBFS)
INPUT LEVEL (dBFS)
SAMPLE RATE (Msps)
226114
226114
226114
226114f
LTC2261-14 LTC2260-14/LTC2259-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2261-14: IOVDD Sample Rate, 5MHz Sine Wave Input, -1dB, Each Data Output
3.5mA LVDS IOVDD (mA) 1.8V CMOS 1.2V CMOS SAMPLE RATE (Msps)
226114
LTC2261-14: SENSE, 5MHz, -1dB
(dBFS) SENSE -100 -110 -120 -130
LTC2261-14: 128k Point Averaged FFT, 70MHz, -65dBFS, 125Msps, RAND
1.75mA LVDS
AMPLITUDE (dBFS)
FREQUENCY (MHz)
226114
226114
LTC2261-14: 128k Point Averaged FFT, 70MHz, -65dBFS, 125Msps, RAND
(dBFS)
LTC2261-14: Sample Rate Digital Output Mode, 30MHz Sine Wave Input, -1dB
LVDS CMOS ERROR (LSB)
226114
LTC2260-14: Integral Non-Linearity (INL)
AMPLITUDE (dBFS)
CMOS
-100 -110 -120 -130
-0.5 -1.0 -1.5
FREQUENCY (MHz)
226114
SAMPLE RATE (Msps)
-2.0
4096
8192 12288 OUTPUT CODE
16384
226114
LTC2260-14: Differential Non-Linearity (DNL)
ERROR (LSB) -0.2 -0.4 -0.6 -0.8 -1.0 4096 8192 12288 OUTPUT CODE 16384
226114
LTC2260-14: Point FFT, 5MHz -1dBFS, 105Msps
AMPLITUDE (dBFS) AMPLITUDE (dBFS)
LTC2260-14: Point FFT, 30MHz -1dBFS, 105Msps
-100 -110 -120 FREQUENCY (MHz)
226114
-100 -110 -120 FREQUENCY (MHz)
226114
226114f
LTC2261-14 LTC2260-14/LTC2259-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2260-14: Point FFT, 70MHz -1dBFS, 105Msps
AMPLITUDE (dBFS) AMPLITUDE (dBFS) AMPLITUDE (dBFS)
LTC2260-14: Point FFT, 140MHz -1dBFS, 105Msps
LTC2260-14: Point 2-Tone FFT, 70MHz, 75MHz, -1dBFS, 105Msps
-100 -110 -120 FREQUENCY (MHz)
226114
-100 -110 -120 FREQUENCY (MHz)
226114
-100 -110 -120 FREQUENCY (MHz)
226114
LTC2260-14: Shorted Input Histogram
6000 5000 4000 (dBFS) COUNT 3000 2000 1000 8195
LTC2260-14: Input Frequency, -1dB, Range, 105Msps
INPUT FREQUENCY (MHz)
LTC2260-14: SFDR Input Frequency, -1dB, Range, 105Msps
8197
8199 8201 OUTPUT CODE
8203
226114
SFDR (dBFS)
INPUT FREQUENCY (MHz)
226114
226114
LTC2260-14: SFDR Input Level, 70MHz, Range, 105Msps
SFDR (dBc dBFS) IVDD (mA) INPUT LEVEL (dBFS) dBFS
LTC2260-14: IVDD Sample Rate, 5MHz Sine Wave Input, -1dB
LVDS OUTPUTS IOVDD (mA) SAMPLE RATE (Msps)
226114
LTC2260-14: IOVDD Sample Rate, 5MHz Sine Wave Input, -1dB, Each Data Output
3.5mA LVDS
CMOS OUTPUTS
1.75mA LVDS
1.8V CMOS 1.2V CMOS SAMPLE RATE (Msps)
226114
226114
226114f
LTC2261-14 LTC2260-14/LTC2259-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2260-14: SENSE, 5MHz, -1dB
ERROR (LSB) (dBFS) SENSE -0.5 -1.0 -1.5 -2.0 4096 8192 12288 OUTPUT CODE 16384
226114
LTC2259-14: Integral Non-Linearity (INL)
ERROR (LSB) -0.2 -0.4 -0.6 -0.8 -1.0
LTC2259-14: Differential Non-Linearity (DNL)
4096
8192 12288 OUTPUT CODE
16384
226114
226114
LTC2259-14: Point FFT, 5MHz -1dBFS, 80Msps
AMPLITUDE (dBFS) AMPLITUDE (dBFS)
LTC2259-14: Point FFT, 30MHz -1dBFS, 80Msps
AMPLITUDE (dBFS) FREQUENCY (MHz)
226114
LTC2259-14: Point FFT, 70MHz -1dBFS, 80Msps
-100 -110 -120 FREQUENCY (MHz)
226114
-100 -110 -120
-100 -110 -120 FREQUENCY (MHz)
226114
LTC2259-14: Point FFT, 140MHz -1dBFS, 80Msps
AMPLITUDE (dBFS) AMPLITUDE (dBFS)
LTC2259-14: Point 2-Tone FFT, 70MHz, 75MHz, -1dBFS, 80Msps
6000 5000 4000 COUNT FREQUENCY (MHz)
226114
LTC2259-14: Shorted Input Histogram
3000 2000 1000 8184
-100 -110 -120 FREQUENCY (MHz)
226114
-100 -110 -120
8186
8188 8190 OUTPUT CODE
8192
226114
226114f
LTC2261-14 LTC2260-14/LTC2259-14 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2259-14: Input Frequency, -1dB, Range, 80Msps
(dBFS) INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz) SFDR (dBFS) SFDR (dBc dBFS)
LTC2259-14: SFDR Input Frequency, -1dB, Range, 80Msps
LTC2259-14: SFDR Input Level, 70MHz, Range, 80Msps
dBFS
INPUT LEVEL (dBFS)
226114
226114
226114
LTC2259-14: IVDD Sample Rate, 5MHz Sine Wave Input, -1dB
IVDD (mA) LVDS OUTPUTS IOVDD (mA) SAMPLE RATE (Msps)
226114
LTC2259-14: IOVDD Sample Rate, 5MHz Sine Wave Input, -1dB, Each Data Output
3.5mA LVDS (dBFS) 1.2V CMOS 1.8V CMOS SAMPLE RATE (Msps)
226114
LTC2259-14: SENSE, 5MHz, -1dB
CMOS OUTPUTS
1.75mA LVDS
SENSE
226114
FUNCTIONS
PINS THAT SAME DIGITAL OUTPUT MODES AIN+ (Pin Positive Differential Analog Input. AIN- (Pin Negative Differential Analog Input. (Pin Power Ground. REFH (Pins High Reference. Bypass Pins with 2.2F ceramic capacitor ground with 0.1F ceramic capacitor. REFL (Pins Reference. Bypass Pins with 2.2F ceramic capacitor ground with 0.1F ceramic capacitor. PAR/SER (Pin Programming Mode Selection Pin. Connect ground enable serial programming mode. SCK, SDI, become serial interface that control operating modes. Connect enable parallel programming mode where SCK, become parallel logic inputs that control reduced
226114f
LTC2261-14 LTC2260-14/LTC2259-14 FUNCTIONS
operating modes. PAR/SER should connected directly ground part driven logic signal. (Pins 40): 1.8V Analog Power Supply. Bypass ground with 0.1F ceramic capacitors. Pins share bypass capacitor. ENC+ (Pin 11): Encode Input. Conversion starts rising edge. (Pin 12): Encode Complement Input. Conversion starts falling edge. (Pin 13): serial programming mode, (PAR/SER 0V), serial interface chip select input. When low, enabled shifting data into mode control registers. parallel programming mode (PAR/SER VDD), controls clock duty cycle stabilizer. When low, clock duty cycle stabilizer turned off. When high, clock duty cycle stabilizer turned driven with 1.8V 3.3V logic. (Pin 14): serial programming mode, (PAR/SER 0V), serial interface clock input. parallel programming mode (PAR/SER VDD), controls digital output mode. When low, full-rate CMOS output mode enabled. When high, double data rate LVDS output mode (with 3.5mA output current) enabled. driven with 1.8V 3.3V logic. (Pin 15): serial programming mode, (PAR/SER 0V), serial interface data input. Data clocked into mode control registers rising edge SCK. parallel programming mode (PAR/SER VDD), used power down part. When low, part operates normally. When high, part enters sleep mode. driven with 1.8V 3.3V logic. (Pin 16): serial programming mode, (PAR/SER 0V), optional serial interface data output. Data read back from mode control registers latched falling edge SCK. open-drain NMOS output that requires external pull-up resistor 1.8V-3.3V. read back from mode control registers needed, pull-up resistor necessary left unconnected. parallel programming mode (PAR/SER VDD), used should connected. OGND (Pin 25): Output Driver Ground. OVDD (Pin 26): Output Driver Supply. Bypass ground with 0.1F ceramic capacitor. (Pin 37): Common Mode Bias Output, Nominally Equal VDD/2. should used bias common mode analog inputs. Bypass ground with 0.1F ceramic capacitor. VREF (Pin 38): Reference Voltage Output. Bypass ground with ceramic capacitor, nominally 1.25V. SENSE (Pin 39): Reference Programming Pin. Connecting SENSE selects internal reference input range. Connecting SENSE ground selects internal reference ±0.5V input range. external reference between 0.625V 1.3V applied SENSE selects input range ±0.8 VSENSE. FULL-RATE CMOS OUTPUT MODE Pins Below Have CMOS Output Levels (OGND OVDD) (Pins 17-24, 29-34): Digital Outputs. MSB. CLKOUT- (Pin 27): Inverted version CLKOUT+. CLKOUT+ (Pin 28): Data Output Clock. digital outputs normally transition same time falling edge CLKOUT+. phase CLKOUT+ also delayed relative digital outputs programming mode control registers. (Pin 35): connect this pin. (Pin 36): Over/Under Flow Digital Output. high when overflow underflow occurred. DOUBLE DATA RATE CMOS OUTPUT MODE Pins Below Have CMOS Output Levels (OGND OVDD) D0_1 D12_13 (Pins 34): Double Data Rate Digital Outputs. data bits multiplexed onto each output pin. even data bits (D0, D10,
226114f
LTC2261-14 LTC2260-14/LTC2259-14 FUNCTIONS
D12) appear when CLKOUT+ low. data bits (D1, D11, D13) appear when CLKOUT+ high. CLKOUT- (Pin 27): Inverted version CLKOUT+. CLKOUT+ (Pin 28): Data Output Clock. digital outputs normally transition same time falling rising edges CLKOUT+. phase CLKOUT+ also delayed relative digital outputs programming mode control registers. (Pins 35): connect these pins. (Pin 36): Over/Under Flow Digital Output. high when overflow underflow occurred. DOUBLE DATA RATE LVDS OUTPUT MODE Pins Below Have LVDS Output Levels. Output Current Level Programmable. There Optional Internal Termination Resistor Between Pins Each LVDS Output Pair. D0_1-/D0_1+ D12_13 -/D12_13+ (Pins 17/18, 19/20, 21/22, 23/24, 29/30, 31/32, 33/34): Double Data Rate Digital Outputs. data bits multiplexed onto each differential output pair. even data bits (D0, D10, D12) appear when CLKOUT+ low. data bits (D1, D11, D13) appear when CLKOUT+ high. CLKOUT-/CLKOUT+ (Pins 27/28): Data Output Clock. digital outputs normally transition same time falling rising edges CLKOUT+. phase CLKOUT+ also delayed relative digital outputs programming mode control registers. OF-/OF+ (Pins 35/36): Over/Under Flow Digital Output. high when overflow underflow occurred.
FUNCTIONAL BLOCK DIAGRAM
AIN+ INPUT FIRST PIPELINED STAGE SECOND PIPELINED STAGE THIRD PIPELINED STAGE FOURTH PIPELINED STAGE FIFTH PIPELINED STAGE
0.1F VREF
VDD/2
1.25V REFERENCE RANGE SELECT
SHIFT REGISTER CORRECTION
SENSE
REFH
REFL INTERNAL CLOCK SIGNALS OVDD
DIFF
CLOCK/DUTY CYCLE CONTROL
MODE CONTROL REGISTERS
OUTPUT DRIVERS
CLKOUT CLKOUT
REFH
0.1F
REFL ENC+ ENC- PAR/SER
OGND
226114
2.2F 0.1F 0.1F
Figure Functional Block Diagram
226114f
LTC2261-14 LTC2260-14/LTC2259-14 APPLICATIONS INFORMATION
CONVERTER OPERATION power 14-bit 125Msps/105Msps/80Msps converters that powered single 1.8V supply. analog inputs should driven differentially. encode input driven differentially, single ended lower power consumption. digital outputs CMOS, double data rate CMOS halve number output lines), double data rate LVDS reduce digital noise system.) Many additional features chosen programming mode control registers through serial port. Serial Programming Mode section. ANALOG INPUT analog input differential CMOS sample-and-hold circuit (Figure inputs should driven differentially around common mode voltage output pin, which nominally VDD/2. input range, inputs should swing from 0.5V 0.5V. There should 180° phase difference between inputs. INPUT DRIVE CIRCUITS Input filtering possible, there should lowpass filter right analog inputs. This lowpass filter isolates drive circuitry from sample-and-hold switching, also limits wideband noise from drive circuitry. Figure shows example input filter. component values should chosen based application's input frequency. Transformer Coupled Circuits Figure shows analog input being driven transformer with center-tapped secondary. center biased with VCM, setting input optimal
LTC2261-14 CPARASITIC 1.8pF CPARASITIC 1.8pF CSAMPLE 3.5pF
0.1F
0.1F CSAMPLE 3.5pF ANALOG INPUT
0.1F
AIN+ LTC2261-14 12pF
AIN+
AIN-
226114
AIN-
MA/COM MABAES0060 RESISTORS, CAPACITORS 0402 PACKAGE SIZE
Figure Analog Input Circuit Using Transformer. Recommended Input Frequencies from 5MHz
1.2V ENC+ ENC- 1.2V
226114
Figure Equivalent Input Circuit
226114f
LTC2261-14 LTC2260-14/LTC2259-14 APPLICATIONS INFORMATION
level. higher input frequencies transmission line balun transformer (Figures better balance, resulting lower distortion. Amplifier Circuits Figure shows analog input being driven high speed differential amplifier. output amplifier coupled amplifier's output common mode voltage optimally minimize distortion. very high frequencies gain block will often have lower distortion than differential amplifier. gain block single-ended, then transformer circuit (Figures should convert signal differential before driving A/D.
0.1F 0.1F ANALOG INPUT 0.1F 1.8pF 0.1F 0.1F ANALOG INPUT 0.1F 4.7pF 0.1F AIN-
226114 226114
AIN+ LTC2261-14
0.1F
AIN-
AIN+ LTC2261-14
MA/COM MABA-007159-000000 COILCRAFT WBC1-1LB RESISTORS, CAPACITORS 0402 PACKAGE SIZE
Figure Recommended Front-End Circuit Input Frequencies from 170MHz 270MHz
MA/COM MABA-007159-000000 MA/COM MABAES0060 RESISTORS, CAPACITORS 0402 PACKAGE SIZE 0.1F 0.1F ANALOG INPUT 0.1F 2.7nH AIN-
226114
Figure Recommended Front-End Circuit Input Frequencies from 70MHz 170MHz
2.7nH 0.1F
AIN+ LTC2261-14
MA/COM ETC1-1-13 RESISTORS, CAPACITORS 0402 PACKAGE SIZE
Figure Recommended Front-End Circuit Input Frequencies Above 270MHz
226114f
LTC2261-14 LTC2260-14/LTC2259-14 APPLICATIONS INFORMATION
Reference LTC2261-14/2260-14/2259-14 internal 1.25V voltage reference. input range using internal reference, connect SENSE VDD. input range using external reference, connect SENSE ground. input range with external reference, apply 1.25V reference voltage SENSE (Figure input range adjusted applying voltage SENSE that between 0.625V 1.30V. input range will then VSENSE.
RANGE; RANGE; RANGE VSENSE 0.65V VSENSE 1.300V 0.1F LTC2261-14 REFH
VREF REFH REFL pins should bypassed shown Figure 0.1F capacitor between REFH REFL should close pins possible (not back side circuit board).
LTC2261-14 1.25V VREF 0.625V RANGE DETECT CONTROL SENSE BUFFER INTERNAL HIGH REFERENCE 1.25V BANDGAP REFERENCE
HIGH SPEED DIFFERENTIAL 0.1F AMPLIFIER ANALOG INPUT 0.1F AIN+
12pF
0.1F
AIN-
2.2F
0.1F
0.8x DIFF
226114
0.1F REFL INTERNAL REFERENCE
226114
Figure Front-End Circuit Using High Speed Differential Amplifier
Figure Reference Circuit
VREF LTC2261-14 1.25V EXTERNAL REFERENCE SENSE
226114
Figure Using External 1.25V Reference
226114f
LTC2261-14 LTC2260-14/LTC2259-14 APPLICATIONS INFORMATION
Encode Input signal quality encode inputs strongly affects noise performance. encode inputs should treated analog signals-do route them next digital traces circuit board. There modes operation encode inputs: differential encode mode (Figure single-ended encode mode (Figure 11). differential encode mode recommended sinusoidal, PECL LVDS encode inputs (Figures 13). encode inputs internally biased 1.2V through equivalent resistance. encode inputs taken above 3.6V), common mode range from 1.1V 1.6V. differential encode mode, ENC- should stay least 200mV above ground avoid falsely triggering single-ended encode mode. good jitter performance ENC+ ENC- should have fast rise fall times. single-ended encode mode should used with CMOS encode inputs. select this mode, connected ground ENC+ driven with square wave encode input. ENC+ taken above 3.6V) 1.8V 3.3V CMOS logic levels used. ENC+ threshold 0.9V. good jitter performance ENC+ should have fast rise fall times. Clock Duty Cycle Stabilizer good performance encode signal should have 50%(±5%) duty cycle. optional clock duty cycle stabilizer circuit enabled, encode duty cycle vary from duty cycle stabilizer will maintain constant internal duty cycle. encode signal changes frequency turned off, duty cycle stabilizer circuit requires hundred clock cycles lock onto input clock. duty cycle stabilizer enabled mode control register (serial programming mode), (parallel programming mode).
DIFFERENTIAL COMPARATOR 0.1F ENC+ LTC2261-14 ENC+ ENC- COILCRAFT WBC4 AVAGO HSMS 2822 RESISTORS, CAPACITORS 0402 PACKAGE SIZE ENC- 0.1F
226114
LTC2261-14
226114
Figure Sinusoidal Encode Drive
Figure Equivalent Encode Input Circuit Differential Encode Mode
0.1F ENC+
LTC2261-14 1.8V 3.3V ENC+ ENC- CMOS LOGIC BUFFER
226114
PECL LVDS CLOCK
LTC2261-14 0.1F ENC-
226114
Figure PECL LVDS Encode Drive
Figure Equivalent Encode Input Circuit Single-Ended Encode Mode
226114f
LTC2261-14 LTC2260-14/LTC2259-14 APPLICATIONS INFORMATION
applications where sample rate needs changed quickly, clock duty cycle stabilizer disabled. duty cycle stabilizer disabled, care should taken make sampling clock have 50%(±5%) duty cycle. duty cycle stabilizer should used below 5Msps. DIGITAL OUTPUTS Digital Output Modes operate three digital output modes: full rate CMOS, double data rate CMOS halve number output lines), double data rate LVDS reduce digital noise system). output mode mode control register (serial programming mode), (parallel programming mode). Note that double data rate CMOS cannot selected parallel programming mode. Full-Rate CMOS Mode full-rate CMOS mode digital outputs (D0-D13), overflow (OF), data output clocks (CLKOUT+, CLKOUT-) have CMOS output levels. outputs powered OVDD OGND which isolated from core power ground. OVDD range from 1.1V 1.9V, allowing 1.2V through 1.8V CMOS logic outputs. good performance, digital outputs should drive minimal capacitive loads. load capacitance larger than 10pF digital buffer should used. Double Data Rate CMOS Mode double data rate CMOS mode, data bits multiplexed output each data pin. This reduces number data lines seven, simplifying board routing reducing number input pins needed receive data. digital outputs (D0_1, D2_3, D4_5, D6_7, D8_9, D10_11, D12_13), overflow (OF), data output clocks (CLKOUT+, CLKOUT-) have CMOS output levels. outputs powered OVDD OGND which isolated from core power ground. OVDD range from 1.1V 1.9V, allowing 1.2V through 1.8V CMOS logic outputs. good performance digital outputs should drive minimal capacitive loads. load capacitance larger than 10pF digital buffer should used. When using Double Data Rate CMOS high sample rates will degrade slightly (see Typical Performance Characteristics section). CMOS recommended sample frequencies above 100MHz. Double Data Rate LVDS Mode double data rate LVDS mode, data bits multiplexed output each differential output pair. There LVDS output pairs (D0_1+/D0_1- through D12_13+/D12_13-) digital output data. Overflow (OF+/OF data output clock (CLKOUT+/CLKOUT-) each have LVDS output pair. default outputs standard LVDS levels: 3.5mA output current 1.25V output common mode voltage. external differential termination resistor required each LVDS output pair. termination resistors should located close possible LVDS receiver. outputs powered OVDD OGND which isolated from core power ground. LVDS mode, OVDD must 1.8V. Programmable LVDS Output Current LVDS mode, default output driver current 3.5mA. This current adjusted serially programming mode control register Available current levels 1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4.5mA. Optional LVDS Driver Internal Termination most cases using just external termination resistor will give excellent LVDS signal integrity. addition, optional internal termination resistor enabled serially programming mode control register internal termination helps absorb reflections caused imperfect termination receiver. When internal termination enabled, output driver current increased 1.6x maintain about same output voltage swing. Overflow overflow output (OF) outputs logic high when analog input either overranged underranged. overflow same pipeline latency data bits. 226114f
LTC2261-14 LTC2260-14/LTC2259-14 APPLICATIONS INFORMATION
Phase Shifting Output Clock full-rate CMOS mode data output bits normally change same time falling edge CLKOUT+, rising edge CLKOUT+ used latch output data. double data rate CMOS LVDS modes data output bits normally change same time falling rising edges CLKOUT+. allow adequate setup-and-hold time when latching data, CLKOUT+ signal need phase shifted relative data output bits. Most FPGAs have this feature; this generally best place adjust timing. also phase shift CLKOUT+/CLKOUT- signals serially programming mode control register output clock shifted 45°, 135°. phase shifting feature clock duty cycle stabilizer must turned Another control register invert polarity CLKOUT+ CLKOUT-, independently phase shift. combination these features enables phase shifts 315° (Figure 14). DATA FORMAT Table shows relationship between analog input voltage, digital data output bits overflow bit. default output data format offset binary. complement format selected serially programming mode control register
Table Output Codes Input Voltage
AIN+ AIN- Range) >1.000000V +0.999878V +0.999756V +0.000122V +0.000000V -0.000122V -0.000244V -0.999878V -1.000000V -1.000000V D13-D0 (OFFSET BINARY) 1111 1111 1111 1111 1111 1111 1111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 0000 0000 0001 0000 0000 0000 0000 0000 0000 D13-D0 (2's COMPLEMENT) 1111 1111 1111 1111 1111 1111 1111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 0000 0000 0001 0000 0000 0000 0000 0000 0000
ENC+
D0-D13, PHASE SHIFT 135° CLKOUT+ 180° 225° 270° 315°
226114
MODE CONTROL BITS CLKINV CLKPHASE1 CLKPHASE0
Figure Phase Shifting CLKOUT
226114f
LTC2261-14 LTC2260-14/LTC2259-14 APPLICATIONS INFORMATION
Digital Output Randomizer Interference from digital outputs sometimes unavoidable. Digital interference from capacitive inductive coupling coupling through ground plane. Even tiny coupling factor cause unwanted tones output spectrum. randomizing digital output before transmitted chip, these unwanted tones randomized which reduces unwanted tone amplitude. digital output "randomized" applying exclusive-OR logic operation between other data output bits. decode, reverse operation applied-an exclusive-OR operation applied between other bits. LSB, CLKOUT outputs affected. output randomizer enabled serially programming mode control register Alternate Polarity Another feature that reduces digital feedback circuit board alternate polarity mode. When this mode enabled, bits (D1, D11, D13) inverted before output buffers. even bits (D0, D10, D12), CLKOUT affected. This reduce digital currents circuit board ground plane reduce digital noise, particularly very small analog input signals. When there very small signal input that centered around midscale, digital outputs toggle between mostly mostly This simultaneous switching most bits will cause large currents ground plane. inverting every other bit, alternate polarity mode makes half bits transition high while half bits transition low. first order, this cancels current flow ground plane, reducing digital noise.
BOARD CLKOUT FPGA
CLKOUT
CLKOUT
D13/D0
D12/D0
D13/D0 D12/D0
RANDOMIZER
D2/D0 LTC2261-14
D2/D0
D1/D0
D1/D0
116114
Figure Functional Equivalent Digital Output Randomizer
116114
Figure Unrandomizing Randomized Digital Output Signal
226114f
LTC2261-14 LTC2260-14/LTC2259-14 APPLICATIONS INFORMATION
digital output decoded receiver inverting bits (D1, D11, D13.) alternate polarity mode independent digital output randomizer-either, both neither function same time. When alternate polarity mode data format offset binary complement control effect. alternate polarity mode enabled serially programming mode control register Digital Output Test Patterns allow in-circuit testing digital interface A/D, there several test modes that force data outputs (OF, D13-D0) known values: outputs outputs Alternating: Outputs change from alternating samples Checkerboard: Outputs change from 101010101010101 010101010101010 alternating samples digital output test patterns enabled serially programming mode control register When enabled, test patterns override other formatting modes: complement, randomizer, alternate-bit-polarity. Output Disable digital outputs disabled serially programming mode control register digital outputs including CLKOUT disabled. high impedance disabled state intended long periods inactivity-it slow multiplex data between multiple converters full speed. Sleep Modes placed sleep modes conserve power. sleep mode entire converter powered down, resulting 0.5mW power consumption. Sleep mode enabled mode control register (serial programming mode), (parallel programming mode). amount time required recover from sleep mode depends size bypass capacitors VREF REFH, REFL. suggested values Figure will stabilize after 2ms. mode core powered down while internal reference circuits stay active, allowing faster wake-up than from sleep mode. Recovering from mode requires least clock cycles. application demands very accurate settling then additional should allowed on-chip references settle from slight temperature shift caused change supply current leaves mode. mode enabled mode control register serial programming mode. DEVICE PROGRAMMING MODES operating modes LTC2261-14 programmed either parallel interface simple serial interface. serial interface more flexibility program available modes. parallel interface more limited only program some more commonly used modes. Parallel Programming Mode parallel programming mode, PAR/SER should tied VDD. pins binary logic inputs that certain operating modes. These pins tied ground, driven 1.8V, 2.5V 3.3V CMOS logic. Table shows modes SDI.
Table Parallel Programming Mode Control Bits (PAR/SER VDD)
DESCRIPTION Clock Duty Cycle Stabilizer Control Clock Duty Cycle Stabilizer Clock Duty Cycle Stabilizer Digital Output Mode Control Full-Rate CMOS Output Mode Double Data Rate LVDS Output Mode (3.5mA LVDS Current, Internal Termination Off) Power Down Control Normal Operation Sleep Mode
226114f
LTC2261-14 LTC2260-14/LTC2259-14 APPLICATIONS INFORMATION
Serial Programming Mode serial programming mode, PAR/SER should tied ground. SCK, pins become serial interface that program mode control registers. Data written register with 16-bit serial word. Data also read back from register verify contents. Serial data transfer starts when taken low. data latched first rising edges SCK. rising edges after first ignored. data transfer ends when taken high again. first 16-bit input word bit. next seven bits address register (A6:A0). final eight bits register data (D7:D0). low, serial data (D7:D0) will written register address bits (A6:A0). high, data register address bits (A6:A0) will read back (see timing diagrams). During read back command register updated data ignored.
Table Serial Programming Mode Register
REGISTER RESET REGISTER (ADDRESS 00h) RESET RESET Software Reset
open-drain output that pulls ground with impedance. register data read back through SDO, external pull-up resistor required. serial data only written read back needed, then left floating pull-up resistor needed. Table shows mode control registers. Software Reset serial programming used, mode control registers should programmed soon possible after power supplies turn stable. first serial command must software reset which will reset register data bits logic perform software reset, reset register written with logic After reset complete, automatically back zero.
Used Software Reset. Mode Control Registers Reset 00h. This Automatically Back Zero After Reset Complete Bits Unused, Don't Care Bits.
REGISTER POWER-DOWN REGISTER (ADDRESS 01h) Bits Bits Unused, Don't Care Bits. PWROFF1:PWROFF0 Normal Operation Mode Used Sleep Mode Power Down Control Bits PWROFF1 PWROFF0
226114f
LTC2261-14 LTC2260-14/LTC2259-14 APPLICATIONS INFORMATION
REGISTER TIMING REGISTER (ADDRESS 02h) Bits Unused, Don't Care Bits. CLKINV Output Clock Invert Normal CLKOUT Polarity Shown Timing Diagrams) Inverted CLKOUT Polarity CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits CLKOUT Delay Shown Timing Diagrams) CLKOUT+/CLKOUT- Delayed (Clock Period 1/8) CLKOUT+/CLKOUT- Delayed (Clock Period 1/4) CLKOUT+/CLKOUT- Delayed 135° (Clock Period 3/8) Note: CLKOUT Phase Delay Feature Used, Clock Duty Cycle Stabilizer Must Also Turned Clock Duty Cycle Stabilizer Clock Duty Cycle Stabilizer Clock Duty Cycle Stabilizer CLKINV CLKPHASE1 CLKPHASE0
Bits
REGISTER OUTPUT MODE REGISTER (ADDRESS 03h) Bits ILVDS2 Unused, Don't Care Bit. ILVDS2:ILVDS0 LVDS Output Current Bits 3.5mA LVDS Output Driver Current 4.0mA LVDS Output Driver Current 4.5mA LVDS Output Driver Current Used 3.0mA LVDS Output Driver Current 2.5mA LVDS Output Driver Current 2.1mA LVDS Output Driver Current 1.75mA LVDS Output Driver Current TERMON LVDS Internal Termination Internal Termination Internal Termination LVDS Output Driver Current Current ILVDS2:ILVDS0 OUTOFF Output Disable Digital Outputs Enabled Digital Outputs Disabled Have High Output Impedance OUTMODE1:OUTMODE0 Digital Output Mode Control Bits Full-Rate CMOS Output Mode Double Data Rate LVDS Output Mode Double Data Rate CMOS Output Mode Used ILVDS1 ILVDS0 TERMON OUTOFF OUTMODE1 OUTMODE0
Bits
226114f
LTC2261-14 LTC2260-14/LTC2259-14 APPLICATIONS INFORMATION
REGISTER DATA FORMAT REGISTER (ADDRESS 04h) Bits Unused, Don't Care Bits. OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits Digital Output Test Patterns Digital Outputs Digital Outputs Checkerboard Output Pattern. D13-D0 Alternate Between 0101 1010 0101 1010 0101 1010 Alternating Output Pattern. D13-D0 Alternate Between 0000 0000 0000 1111 1111 1111 Note: Other Combinations Used Alternate Polarity Mode Control Alternate Polarity Mode Alternate Polarity Mode RAND Data Output Randomizer Mode Control Data Output Randomizer Mode Data Output Randomizer Mode TWOSCOMP Two's Complement Mode Control Offset Binary Data Format Two's Complement Data Format Note: Forces Output Format Offset Binary OUTTEST2 OUTTEST1 OUTTEST0 RAND TWOSCOMP
GROUNDING BYPASSING LTC2261-14 requires printed circuit board with clean unbroken ground plane. multilayer board with internal ground plane recommended. Layout printed circuit board should ensure that digital analog signal lines separated much possible. particular, care should taken digital track alongside analog signal track underneath ADC. High quality ceramic bypass capacitors should used VDD, OVDD, VCM, VREF, REFH REFL pins. Bypass capacitors must located close pins possible. particular importance 0.1F capacitor between REFH REFL. This capacitor should same side circuit board A/D, close device possible (1.5mm less). Size 0402 ceramic capacitors recommended. larger 2.2F capacitor between REFH REFL somewhat further away.
capacitor should located close possible. make space this capacitor VREF further away back board. traces connecting pins bypass capacitors must kept short should made wide possible. analog inputs, encode signals, digital outputs should routed next each other. Ground fill grounded vias should used barriers isolate these signals from each other. HEAT TRANSFER Most heat generated LTC2261-14 transferred from through bottom-side exposed package leads onto printed circuit board. good electrical thermal performance, exposed must soldered large grounded board.
226114f
LTC2261-14 LTC2260-14/LTC2259-14 TYPICAL APPLICATIONS
LTC2261 Schematic
MABAES0060
33.2 33.2
ANALOG INPUT
SENSE 4.7pF
0.1F
0.1F SENSE VREF 0.1F 2.2F 0.1F PAR/SER 0.1F AIN+ AIN- REFH REFH REFL REFL PAR/SER ENC+ ENC- LTC2261CUJ
DIGITAL OUTPUTS
CLKOUT+ CLKOUT- OVDD OGND
0VDD 0.1F
DIGITAL OUTPUTS
ENCODE CLOCK
226114 TA02
226114f
LTC2261-14 LTC2260-14/LTC2259-14 TYPICAL APPLICATIONS
Silkscreen Side
226114 TA04
226114 TA03
Inner Layer
Inner Layer
226114 TA04
226114 TA06
226114f
LTC2261-14 LTC2260-14/LTC2259-14 TYPICAL APPLICATIONS
Inner Layer Inner Layer Power
226114 TA07
226114 TA08
Bottom Side
226114 TA09
226114f
LTC2261-14 LTC2260-14/LTC2259-14 PACKAGE Package 40-Lead Plastic (6mm 6mm)
(Reference 05-08-1728
0.70 ±0.05
6.50 ±0.05 5.10 ±0.05 4.42 ±0.05 4.50 ±0.05 SIDES)
4.42 ±0.05
PACKAGE OUTLINE 0.25 ±0.05 0.50 RECOMMENDED SOLDER PITCH DIMENSIONS APPLY SOLDER MASK AREAS THAT SOLDERED
6.00 0.10 SIDES)
0.75 0.05 0.10
0.115
0.40 0.10 NOTCH 0.45 0.35 CHAMFER
MARK (SEE NOTE
4.50 (4-SIDES)
4.42 ±0.10
4.42 ±0.10
(UJ40) 0406
0.200 0.00 0.05 NOTE: DRAWING JEDEC PACKAGE OUTLINE VARIATION (WJJD-2) DRAWING SCALE DIMENSIONS MILLIMETERS DIMENSIONS EXPOSED BOTTOM PACKAGE INCLUDE MOLD FLASH. MOLD FLASH, PRESENT, SHALL EXCEED 0.20mm SIDE, PRESENT EXPOSED SHALL SOLDER PLATED SHADED AREA ONLY REFERENCE LOCATION BOTTOM PACKAGE
0.25 0.05 0.50 BOTTOM VIEW-EXPOSED
226114f
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LTC2261-14 LTC2260-14/LTC2259-14 RELATED PARTS
PART NUMBER LTC1993-2 LTC1994 LTC2215 LTC2216 LTC2217 LTC2202 LTC2203 LTC2204 LTC2205 LTC2206 LTC2207 LTC2208 LTC2209 LTC2220 LTC2220-1 LTC2224 LTC2249 LTC2250 LTC2251 LTC2252 LTC2253 LTC2254 LTC2255 LTC2259-12/ LTC2260-12/ LTC2261-12 LTC2284 LTC2299 LTC5517 LTC5527 LTC5557 LTC5575 LTC6400-20 LTC6604-2.5/ LTC6604 LTC6604-10/ LTC6604-15 DESCRIPTION High Speed Differential Noise, Distortion Fully Differential Input/ Output Amplifier/Driver 16-Bit, 65Msps, Noise 16-Bit, 80Msps, Noise 16-Bit, 105Msps, Noise 16-Bit, 10Msps, 3.3V ADC, Lowest Noise 16-Bit, 25Msps, 3.3V ADC, Lowest Noise 16-Bit, 40Msps, 3.3V 16-Bit, 65Msps, 3.3V 16-Bit, 80Msps, 3.3V 16-Bit, 105Msps, 3.3V 16-Bit, 130Msps, 3.3V ADC, LVDS Outputs 16-Bit, 160Msps, 3.3V ADC, LVDS Outputs 12-Bit, 170Msps 12-Bit, 185Msps, 3.3V ADC, LVDS Outputs 12-Bit, 135Msps, 3.3V ADC, High Sampling 14-Bit, 80Msps 10-Bit, 105Msps 10-Bit, 125Msps 12-Bit, 105Msps 12-Bit, 125Msps 14-Bit, 105Msps 14-Bit, 125Msps, ADC, Lowest Power 12-Bit, 80/105/125Msps 1.8V ADCs, Ultralow Power 14-Bit, Dual, 105Msps, ADC, Crosstalk Dual 14-Bit, 80Msps 40MHz 900MHz Direct Conversion Quadrature Demodulator 400MHz 3.7GHz High Linearity Downconverting Mixer 400MHz 3.8GHz High Linearity Downconverting Mixer 800MHz 2.7GHz Direct Conversion Quadrature Demodulator 1.8GHz Noise, Distortion Differential Driver 300MHz Dual Matched 2.5MHz, 5MHz, 10MHz, 15MHz Filter with Driver COMMENTS 800MHz 70dBc Distortion 70MHz, Gain Distortion: -94dBc 1MHz 700mW, 81.5dB SNR, 100dB SFDR, 64-Pin 970mW, 81.3dB SNR, 100dB SFDR, 64-Pin 1190mW, 81.2dB SNR, 100dB SFDR, 64-Pin 140mW, 81.6dB SNR, 100dB SFDR, 48-Pin 220mW, 81.6dB SNR, 100dB SFDR, 48-Pin 480mW, 79dB SNR, 100dB SFDR, 48-Pin 590mW, 79dB SNR, 100dB SFDR, 48-Pin 725mW, 77.9dB SNR, 100dB SFDR, 48-Pin 900mW, 77.9dB SNR, 100dB SFDR, 48-Pin 1250mW, 77.7dB SNR, 100dB SFDR, 64-Pin 1450mW, 77.1dB SNR, 100dB SFDR, 64-Pin 890mW, 67.5dB SNR, Package 910mW, 67.7dB SNR, 80dB SFDR, 64-Pin 630mW, 67.6dB SNR, 84dB SFDR, 48-Pin 230mW, 73dB SNR, Package 320mW, 61.6dB SNR, Package 395mW, 61.6dB SNR, Package 320mW, 70.2dB SNR, Package 395mW, 70.2dB SNR, Package 320mW, 72.5dB SNR, Package 395mW, 72.5dB SNR, 88dB SFDR, 32-Pin 87mW/103mW/124mW, 70.8dB SNR, 85dB SFDR, LVDS/DDR CMOS/ CMOS Outputs, Package 540mW, 72.4dB SNR, 88dB SFDR, 64-Pin 230mW, 71.6dB SNR, Package High IIP3: 21dBm 800MHz, Integrated Quadrature Generator 24.5dBm IIP3 900MHz, 23.5dBm IIP3 3.5GHz, 12.5dB, Single-Ended Ports 23.7dBm IIP3 2.6GHz, 23.5dBm IIP3 3.5GHz, 13.2dB, 3.3V Supply Operation, Integrated Transformer High IIP3: 28dBm 900MHz, Integrated Quadrature Generator Integrated Transformer Fixed Gain 10V/V, 2.1nVHz Total Input Noise, QFN-16 Package Dual Matched Order Filters with Differential Drivers. Noise, Distortion Amplifiers
226114f
Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1208 PRINTED
1630 McCarthy Blvd., Milpitas, 95035-7417
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2008
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