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AN10950
LPC24XX external memory example
Rev. July 2010 Application note
Document information Info Content Keywords Abstract LPC24XX, EMC, memory, SDRAM, SRAM, flash This application note will detail example design illustrating connect asynchronous dynamic memory elements external memory LPC24XX. This note also includes suggested design rules which apply both schematic capture layout phases design.
Semiconductors
AN10950
LPC24XX external memory example
Revision history Date 20100706
Description Initial version
Contact information
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Application note
Rev. July 2010
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AN10950
LPC24XX external memory example
Introduction
LPC24XX provides multiple static dynamic memory chip select outputs enable designers work with large memory topologies. Designers must take care ensure that their satisfies electrical timing characteristics external memory their embedded systems able operate reliably maximum frequency. Consult with "Dynamic characteristics: Dynamic external memory interface" "Dynamic characteristics: Static external memory interface" sections LPC24XX Data Sheet detailed list specifications. ability memory with multiple devices operate properly dependent several factors: electrical characteristics memory devices, operating frequency memory transactions, length traces between LPC24XX memory device, well voltage levels being used.
Suggestions achieving peak performance
Several factors affect performance embedded system using LPC24XX. Signal integrity external memory important order achieve robust operation MHz. Operating performance also negatively impacted choice memory topologies design. need evaluate whether single dual memory device design preferred. order reduce size PCB, designer choose single 16-bit memory device their system. This would meet loading requirements external memory operate reliably MHz, because data constricted performance will degraded. order improve performance, might simply additional 16-bit memory. Without proper consideration signal integrity, however, this additional 16-bit device result marginal design. care taken properly memory memory elements, become improperly loaded. This mitigated using buffer circuitry case static memories, additional parts increase board costs. case dynamic memories this overcome using lower clock frequency, price reducing performance. seen Table design used AM29LV64 flash memory combination 16-bit HYB39S128 SDRAM, pins would have loading 18.0 (without taking parasitic capacitances into account). This appear have large safety margin when compared LPC24XX's maximum rating 30.0 Many designs this simplistic, however, design required additional SRAM peripheral device using SRAM interface) loading data could increase beyond rated limit. recommended topology consists single 32-bit wide SDRAM memory device. This loading excessive, additional data transfers required achieve maximum throughput. Always remember properly configure software match memory topology given design. Each channel's EMCDynamicConfig register should configured Table LPC24XX User Manual ensure proper functionality. Also note that LPC24XX supports maximum memory range.
AN10950
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B.V. 2010. rights reserved.
Application note
Rev. July 2010
Semiconductors
AN10950
LPC24XX external memory example
Table Loading characteristics Maximum loading various memory Part Clock HYB39S128 MT48LC4M32B2 M29EW AM29LV64 CY62256VN
Data width bits bits bits bits bits
Native input, wide input 14.0 15.0 24.0
Input/output 12.0
Suggested design rules
following rules collection guidelines, which properly followed will reduce risk design failing. However, some instances possible meet these requirements; proper signal integrity analysis design conducted, depending results simulation possible build robust design which does utilize every these recommendations.
General rules
Because Dynamic memories rely heavily their clocks, important minimize latency jitter clock output signals relation rest external memory bus. layer with power planes recommended high performance designs. Ensure that both LPC24XX memory elements properly decoupled from their power supplies with low-ESR capacitors (MLCC Tantalum). Consult chosen memory device documentation recommended decoupling capacitors arrangements. analysis cannot done, general recommendation least single bulk capacitor device combination with supply should work reliably most cases. When using mixture dynamic static memories shown following example) recommended that signals being used static memory buffered prior arriving memory devices. signals which arrive connector taken board should also buffered. recommended that entire bus, including control address signals (rather than simply data lines) buffered ensure signals arrive downstream with minimal jitter skew. Dynamic memories typically buffered their synchronous nature. Ensure that selected memory devices exceed electrical characteristics CLKOUT signals. order reduce reflections dynamic memory bus, recommended that data LPC24XX dynamic memory devices properly terminated.
Schematic
When using multiple banks dynamic memory, evenly distribute CLKOUT[1:0] amongst memory banks, rather than disproportionately loading individual clock. sure that connectivity BA[1:0] memory devices connected their multi-function pins A[14:13] LPC24XX (even when using lower density memories with fewer address lines).
AN10950
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B.V. 2010. rights reserved.
Application note
Rev. July 2010
Semiconductors
AN10950
LPC24XX external memory example
Placement
Memory elements should placed close possible LPC24XX. interconnecting memory cannot accomplished without vias, care should taken ensure that unnecessary vias added traces. While strict requirement, stripline transmission lines preferred.
Routing
Non-buffered interconnecting traces should short possible, recommended exceed When branched, ensure that stub connection lengths within ±5.0 each other. Orthogonal connections should using tapers smooth curves, rather than corners. recommended physical placement devices.
Example: Embedded uCLinux (no-MMU support)
common LPC24XX involves device running embedded distribution Linux operating system without support, such uCLinux. Typically these designs will non-volatile memory (such parallel flash) store root file system compressed kernel image, which copied boot loader into high speed memory (such SDRAM) execution. This application note will cover design analysis simple embedded system using LPC24XX with flash SDRAM while insuring that will operate maximum frequency. non-volatile memory usually accessed only during system startup boot loader during field updates. Because this limited designer will typically accept tradeoff between performance penalty incurred 16-bit wide device reduced cost decreased part count.
Design details
design this application note follows: single 32-bit wide SDRAM will connected external memory controller without external buffering circuitry. critical that memory connected with traces which excessive capacitance bus. thorough design analysis should always conducted ensure that electrical specifications LPC24XX met. LPC24XX will boot from single 16-bit wide FLASH memory with buffered data, address control signals. This example design meant primarily illustrate buffer asynchronous LPC24XX, assumed that real user design require additional asynchronous memory devices addition FLASH. Notice that memory structure MT48LC4M32B2 compatible with external high-performance address mapping" seen Table LPC24XX User Manual. Also note that MT48LC4M32B2 only operate frequencies above with latencies When using LPC2420/60/70 parts care must taken ensure boot memory connected proper chip select lines that BOOT[1:0] pins properly reflect width attached memory when they sampled startup. Section "LPC2420/60/70 boot control" LPC24XX User Manual details startup behavior requirements.
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B.V. 2010. rights reserved.
Application note
Rev. July 2010
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AN10950
LPC24XX external memory example
Example bill materials
Table Bill materials Designator U3,U4,U5 C13,C18,C23,C28 R11-R12 R5,R7,R13-R16 R1-4,R6,R8-R10 Manufacturer Micron Spansion Murata Kemet Unspecified Unspecified Part Number LPC2478FBD208 MT48LC4M32B2 74ABT162245A AM29LV641DH101REI GRM155R61A104KA01D C0603C475K8PACTU Generic Generic 500-1500 742C163220JPTR 0603 Debug jumper Pull up/down 20.0 array Description ARM7 32-bit microcontroller SDRAM Mbit 16-bit transceiver flash memory 0.100 0603
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Application note
Rev. July 2010
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LPC24XX external memory example
Schematics
Please aware that following schematics lacking many application specific connections, such input power conversion, connectivity, additional LPC24XX peripherals, etc. While care been taken demonstrate full performance example using external memory bus, included schematics alone sufficient fabrication.
Simplified block diagram
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B.V. 2010. rights reserved.
Application note
Rev. July 2010
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AN10950
LPC24XX external memory example
LPC24XX external memory controller interface: control signals
AN10950
information provided this document subject legal disclaimers.
B.V. 2010. rights reserved.
Application note
Rev. July 2010
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AN10950
LPC24XX external memory example
LPC24XX external memory controller interface: data signals
AN10950
information provided this document subject legal disclaimers.
B.V. 2010. rights reserved.
Application note
Rev. July 2010
Semiconductors
AN10950
LPC24XX external memory example
LPC24XX external memory controller interface: address, control signals
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B.V. 2010. rights reserved.
Application note
Rev. July 2010
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AN10950
LPC24XX external memory example
SDRAM interface
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B.V. 2010. rights reserved.
Application note
Rev. July 2010
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LPC24XX external memory example
Data[15:0] buffering, BLS[1:0] control output enable
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B.V. 2010. rights reserved.
Application note
Rev. July 2010
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AN10950
LPC24XX external memory example
Address[23:0] buffering, static control buffering
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B.V. 2010. rights reserved.
Application note
Rev. July 2010
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AN10950
LPC24XX external memory example
flash memory, CS#1 primary boot memory source
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information provided this document subject legal disclaimers.
B.V. 2010. rights reserved.
Application note
Rev. July 2010
Semiconductors
AN10950
LPC24XX external memory example
Recommended physical placement
Conclusion
This example project should illustrate properly design making LPC24XX's external memory bus. aware that design this application note relatively simplistic, more complicated designs will warrant thorough design analysis, with focus signal integrity. Always take care carefully read data sheets devices memory bus, including LPC24XX's electrical timing specifications. following design rules included application note, designers avoid many common (and easily corrected) pitfalls which might have otherwise prevented their systems from operating maximum system speed.
AN10950
information provided this document subject legal disclaimers.
B.V. 2010. rights reserved.
Application note
Rev. July 2010
Semiconductors
AN10950
LPC24XX external memory example
Legal information
Definitions
Draft document draft version only. content still under internal review subject formal approval, which result modifications additions. Semiconductors does give representations warranties accuracy completeness information included herein shall have liability consequences such information. Semiconductors products such equipment applications therefore such inclusion and/or customer's risk. Applications Applications that described herein these products illustrative purposes only. Semiconductors makes representation warranty that such applications will suitable specified without further testing modification. Customers responsible design operation their applications products using Semiconductors products, Semiconductors accepts liability assistance with applications customer product design. customer's sole responsibility determine whether Semiconductors product suitable customer's applications products planned, well planned application customer's third party customer(s). Customers should provide appropriate design operating safeguards minimize risks associated with their applications products. Semiconductors does accept liability related default, damage, costs problem which based weakness default customer's applications products, application customer's third party customer(s). Customer responsible doing necessary testing customer's applications products using Semiconductors products order avoid default applications products application customer's third party customer(s). does accept liability this respect. Export control This document well item(s) described herein subject export control regulations. Export might require prior authorization from national authorities.
Disclaimers
Limited warranty liability Information this document believed accurate reliable. However, Semiconductors does give representations warranties, expressed implied, accuracy completeness such information shall have liability consequences such information. event shall Semiconductors liable indirect, incidental, punitive, special consequential damages (including without limitation lost profits, lost savings, business interruption, costs related removal replacement products rework charges) whether such damages based tort (including negligence), warranty, breach contract other legal theory. Notwithstanding damages that customer might incur reason whatsoever, Semiconductors' aggregate cumulative liability towards customer products described herein shall limited accordance with Terms conditions commercial sale Semiconductors. Right make changes Semiconductors reserves right make changes information published this document, including without limitation specifications product descriptions, time without notice. This document supersedes replaces information supplied prior publication hereof. Suitability Semiconductors products designed, authorized warranted suitable life support, life-critical safety-critical systems equipment, applications where failure malfunction Semiconductors product reasonably expected result personal injury, death severe property environmental damage. Semiconductors accepts liability inclusion and/or
Trademarks
Notice: referenced brands, product names, service names trademarks property their respective owners.
AN10950
information provided this document subject legal disclaimers.
B.V. 2010. rights reserved.
Application note
Rev. July 2010
Semiconductors
AN10950
LPC24XX external memory example
Contents
Introduction Suggestions achieving peak performance.3 Suggested design rules General rules.4 Schematic Placement Routing.5 Example: Embedded uCLinux (no-MMU support).5 Design details Example bill materials.6 Schematics Conclusion.15 Legal information Definitions Disclaimers.16 Trademarks Contents.17
Please aware that important notices concerning this document product(s) described herein, have been included section 'Legal information'.
B.V. 2010.
rights reserved.
more information, please visit: http://www.nxp.com sales office addresses, please send please send email salesaddresses@nxp.com Date release: July 2010 Document identifier: AN10950
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