LP3923
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LP3923 Cellular Phone Power Management Unit
April 2010
LP3923 Cellular Phone Power Management Unit
LP3923 fully Integrated Power Management Unit (PMU) designed CDMA cellular phones. LP3923 contains fully integrated Li-Ion battery charger with power over-voltage-protection (OVP), Buck regulator, low-noise low-dropout (LDO) voltage regulators, high-speed serial interface program conditions output voltages individual regulators, read status information PMU. LILO (low-input, low-output) type LDOs with separate power input provide application option pre-regulated high efficient power management longer battery life. Li-Ion charger safely charge maintain single cell Li-Ion battery operating from adapter. charger integrates power FET, reverse current blocking diode, sense resistor with current monitor output, requires only external components. Charging thermally regulated obtain most efficient charging rate given ambient temperature. built-in Over-Voltage Protection (OVP) circuit charger inputs protects from input voltages +28V, eliminating need external protection circuitry. Buck regulator automatic switch mode load conditions providing very good efficiency output currents. external divider circuitry provides user defined buck output voltage. A-type regulators provide excellent PSRR very noise, typ., ideally suited supplying voltage other analog sections.
Features
Integrated Li-Ion battery charger with power FET, thermal
regulation Low-Noise LDOs, LILO LDOs high efficiency Synchronous Magnetic Buck Regulators, IOUT High efficiency mode @low IOUT Auto Mode PFM/PWM switch inductance clock I2C-compatible interface controlling outputs charger operation Thermal Shutdown with Early Warning Alarm Under-Voltage Lockout 30-bump micro package
Specifications
1200 Charging Current 3.0V 5.5V Input Voltage Range typ. Dropout Voltage LDOs
(typ.) Output Voltage accuracy LDOs
(typ.) buck regulator
Applications
Cellular Handsets
System Diagram
30058601
2010 National Semiconductor Corporation
300586
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LP3923
Typical Application Diagram
30058639
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LP3923
Device Diagram
30058603
Package Marking Information
30058604
Ordering Information
Order Number PWR_ON Level Sensitive Level Sensitive Level Sensitive Level Sensitive Level Sensitive Level Sensitive HF_PWR Standby Level Sensitive Level Sensitive Level Sensitive Level Sensitive Level Sensitive Level Sensitive VFULL_
RATE
Default Charging Current 400mA 400mA 100mA 100mA 100mA 100mA
Charger Mode Disabled Disabled Disabled Disabled Disabled Disabled
PS_HOLD Startup
LDO2 Startup condition with SEL=GND default 3.0V default 3.0V defaul 3.0V default 3.0V default 3.0V default 3.0V
Product
Supplied
LP3923TL LP3923TLX LP3923TL-VI LP3923TLX-VI LP3923TL-VB LP3923TLX-VB
2.8V 2.8V 2.8V 2.8V 2.8V 2.8V
3923 3923 V017 V017 V020 V020
Tape Reel 3000 Tape Reel Tape Reel 3000 Tape Reel Tape Reel 3000 Tape Reel
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LP3923
Order Number
PWR_ON Level Sensitive Level Sensitive
HF_PWR Standby Level Sensitive Level Sensitive
VFULL_
RATE
Default Charging Current 100mA 100mA
Charger Mode Disabled Disabled
PS_HOLD Startup
LDO2 Startup condition with SEL=GND default 3.0V default 3.0V
Product
Supplied
LP3923TL-VC LP3923TLX-VC
3.0V 3.0V
V026 V026
Tape Reel 3000 Tape Reel
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LP3923
LP3923 Descriptions
Number Name LDO4 LDO5 LDO6 VIN2 LDO7 LDO2 TCXO_EN RX_EN TX_EN LDO3 VIN1 PS_HOLD RESET_N IMON LDO8 LDO1 PON_N HF_PWR PWR_ON BATT Type DI/O Description LDO4 Output LDO5 Output LDO6 Output Input LDO3 -LDO8 LDO7 Output LDO2 Output Enable control input LDO4. HIGH Enable, Disable (SLEEP Mode). Enable control input LDO5. HIGH Enable, Disable. Enable control input LDO6. HIGH Enable, Disable. LDO3 Output Input LDO1 LDO2 Power Supply Hold Input Reset Output. stays during power sequence Charging current monitor output. This presents analog voltage representation charging current. LDO8 Output LDO1 Output LDO1 LDO2 default voltage selection. State PWR_ON inverted. Digital output referred LDO3. Serial Interface, Data Input/Output Open Drain output, external pull resistor needed, typ. Ground Buck Output Power sequence starts when this HIGH. Internal pulldown resistor. Power sequence starts when this HIGH. Internal pull-down resistor. Serial Interface Clock input. External pull resistor needed, typ. Main battery connection. Used both power connection current delivery battery voltage sense connection monitor battery charge level. Input Buck Power Ground Buck Buck Feedback Adapter indicator, when VCHG_IN above trip point power input charger block from adapter
DI/O
VINB GNDB ACOK_N CHG_IN Analog Digital Input Digital Input/Output Ground Output Power Connection
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LP3923
Device Description
LP3923 Charge Management Regulator Unit designed supply charger voltage output capabilities mobile systems, e.g. CDMA handsets. device provides Li-Ion charging function regulated outputs. Communication with device compatible serial interface that allows function control status read-back. battery charge management section provides programmable CC/CV linear charge capability charging current threshold. Following normal charge cycle maintenance mode utilizing programmable restart voltage levels enables battery voltage maintained correct level. Power dissipation thermally regulated obtain optimum charge levels over ambient temperature range. CHARGER FEATURES Pre-charge, Maintenance modes Integrated Integrated Reverse Current Blocking Diode Integrated Sense Resistor Thermal Regulation Charging Current Monitor Output Programmable charging current 1200 with steps
Default mode current Pre-charging current fixed Termination voltage 4.1V, 4.2V (default), 4.3V 4.4V Restart level (default), below Termination voltage Charge 0,05C, 0.1C, 0.15C (default) 0.2C Input voltage operating range 6.8V
REGULATORS Eight dropout linear regulators provide programmable voltage outputs with current capabilities given table below. LDO1 LDO2 supplied either VBATT (SEL=GND) buck regulator's output (SEL=VBATT). supply voltage (supply from buck), then LDO1 LDO2 going lowinput low-output (LILO) LDOs. Buck regulator provide (typ.) current. buck used supplying LDO1 LDO2 won't able supply external devices. LDO1 LDO2 supplied VBATT, then buck used output power channel digital loading with default output voltage value 1.8V Under voltage lockout oversees device start with preset level 3.0V( typ.).
LDOs Buck Default Voltages (for options LP3923TL/X LP3923TL/X-VI) Device Type Current Enable (mA) control LILO LILO TCXO_EN RX_EN TX_EN Input SEL=BATT Buck LDO1 LDO2 LDO3 LDO4 LDO5 LDO6 LDO7 LDO8 VINB=BATT VIN1=VBUCK VIN1=VBUCK VIN2=BATT VIN2=BATT VIN2=BATT VIN2=BATT VIN2=BATT VIN2=BATT 2.0* Output(V) Startup default Input SEL=GND VINB=BATT VIN1=BATT VIN1=BATT VIN2=BATT VIN2=BATT VIN2=BATT VIN2=BATT VIN2=BATT VIN2=BATT 1.8* Output(V) Startup default
Voltage external resistors.
LDOs Buck Default Voltages (for option LP3923TL/X-VB) Device Type Current Enable (mA) control LILO LILO TCXO_EN RX_EN TX_EN Input SEL=BATT Buck LDO1 LDO2 LDO3 LDO4 LDO5 LDO6 LDO7 LDO8 VINB=BATT VIN1=VBUCK VIN1=VBUCK VIN2=BATT VIN2=BATT VIN2=BATT VIN2=BATT VIN2=BATT VIN2=BATT 2.0* Output(V) Startup default Input SEL=GND VINB=BATT VIN1=BATT VIN1=BATT VIN2=BATT VIN2=BATT VIN2=BATT VIN2=BATT VIN2=BATT VIN2=BATT 1.8* Output(V) Startup default
Voltage external resistors.
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LP3923
Absolute Maximum Ratings (Note Note
Military/Aerospace specified devices required, please contact National Semiconductor Sales Office/ Distributors availability specifications. CHG_IN (VBATT=2.8-5.5V) VBATT=VIN1-2, BATT, HF_PWR, VINB other inputs Junction Temperature (TJ-MAX) Storage Temperature Continuous Power Dissipation PD-MAX (Note (Note BATT, VIN1, VIN2, HF_PWR, CHG_IN, PWR_ON, VINB -0.3V +28V -0.3V +6.0V -0.3V VBATT+0.3V, 6.0V 150°C -40°C +150°C Internally Limited
Operating Ratings
(Note Note 6.8V 3.0V 5.5V 5.5V
CHG_IN (Note VBATT VIN1-2, BATT, VINB HF_PWR, PWR_ON ACOK_N, SDA, SCL, RX_EN, TX_EN, TCXO_EN, PS_HOLD, RESET_N other pins Junction Temperature (TJ) Ambient Temperature (TA) (Note
(VLDO 0.3V) VBATT 0.3V) -40°C +125°C -40°C +85°C
Thermal Properties
Junction-to-Ambient Thermal Resistance (JA) (Jedec Standard Thermal PCB) Micro
(Note
39°C/W
General Electrical Characteristics
Unless otherwise noted, VIN1 VIN2 VINB BATT) 3.6V, CVIN1-2 CVINB CLDOx Typical values limits appearing normal type apply 25°C. Limits appearing boldface type apply over entire junction temperature range operation, -40°C +125°C. (Note Symbol IQ(STANDBY) IQ(SLEEP) Parameter Standby Supply Current Sleep Mode Current load Conditions 3.6V, UVLO internal logic circuit other circuits off. Buck, LDO1, LDO2, LDO3 LDO7 enabled Limit Units
POWER MONITOR FUNCTIONS Battery Under-Voltage Lockout VUVLO-R VUVLO-F Under Voltage Lockout Rising Under Voltage Lockout Falling Higher Threshold LOGIC CONTROL INPUTS Input Level PS_HOLD, SDA, SCL, RX_EN, TCXO_EN, TX_EN PWR_ON, HF_PWR, Input High Level PS_HOLD, SDA, SCL, RX_EN, TCXO_EN, TX_EN PWR_ON, HF_PWR, Logic Input Current Input Resistance logic inputs except PWR_ON, HF_PWR. VINPUT VBATT PWR_ON HF_PWR Pull-Down resistance (Note 0.75* VLDO3 0.75* VBATT 0.25* VLDO3 0.25* VBATT Rising Falling (LP3923-VC) 3.00 2.80 2.85 2.65 3.15 2.95
THERMAL SHUTDOWN (Note
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LP3923
Symbol
Parameter
Conditions
Limit 0.25* VLDO3 0.75* VLDO3
Units
LOGIC CONTROL OUTPUTS Output Level Output High Level PON_N, RESET_N, SDA, ACOK_N IOUT PON_N, RESET_N, ACOK_N IOUT (Not applicable Open Drain Output SDA)
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LP3923
LDO1, LDO2 (LILO) Electrical Characteristics
Unless otherwise noted, SEL=GND, then VIN=VIN1=BATT=3.6V, SEL=BATT, then VIN=VIN1=VBUCK, CV!N1-2 CLDOx= Note VINMIN greater 3.0V VOUT +0.5V. Typical values limits appearing normal type apply 25°C. Limits appearing boldface type apply over entire junction temperature range operation, -40°C +125°C.(Note Symbol VOUT Parameter Output Voltage Accuracy Default Output Voltage IOUT VOUT Output Current Conditions IOUT VOUT 3.0V BATT VINMIN 5.5V IOUT =300 (Note Note VINMIN 5.5V IOUT IOUT Typical Limit Units
Output Current Limit VOUT Dropout Voltage Line Regulation Load Regulation PSRR tSTART-UP TTransient
Power Supply Ripple kHz, COUT Rejection Ratio VOUT 3.0V, IOUT (Note Start-Up Time from Shut-down Start-Up Transient Overshoot COUT IOUT (Note COUT IOUT (Note
LDO3 (D-Type) Electrical Characteristics
Unless otherwise noted, VIN=VIN2=BATT=3.6V, CV!N1-2 CLDOx= Note VINMIN greater 3.0V VOUT +0.5V. Typical values limits appearing normal type apply 25°C. Limits appearing boldface type apply over entire junction temperature range operation, -40°C +125°C. (Note Symbol VOUT Parameter Output Voltage Accuracy Default Output Voltage IOUT VOUT Output Current Output Current Limit Dropout Voltage Line Regulation Load Regulation PSRR Output Noise Voltage Power Supply Ripple Rejection Ratio Start-Up Time from Shut-down Start-Up Transient Overshoot VINMIN 5.5V VOUT IOUT (Note Note VINMIN 5.5V IOUT IOUT kHz, COUT (Note kHz, COUT IOUT (Note COUT IOUT (Note COUT IOUT (Note µVRMS Conditions IOUT VOUT 3.0V Typical Limit Units
tSTART-UP TTransient
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LP3923
LDO4 (A-Type) Electrical Characteristics
Unless otherwise noted, VIN=VIN2=BATT=3.6V, CV!N1-2 CLDOx= TCXO_EN high. Note VINMIN greater 3.0V VOUT +0.5V. Typical values limits appearing normal type apply 25°C. Limits appearing boldface type apply over entire junction temperature range operation, -40°C +125°C. (Note Symbol VOUT Parameter Output Voltage Accuracy Default Output Voltage IOUT VOUT PSRR tSTART-UP TTransient Output Current Output Current Limit Dropout Voltage Line Regulation Load Regulation Output Noise Voltage Power Supply Ripple Rejection Ratio Start-Up Time from Shut-down Start-Up Transient Overshoot VINMIN 5.5V VOUT IOUT (Note Note VINMIN 5.5V, IOUT IOUT kHz, COUT (Note kHz, COUT IOUT (Note COUT IOUT (Note COUT IOUT (Note Conditions IOUT VOUT 3.0V Typical Limit Units µVRMS
LDO5, LDO6, LDO7 (A-Type) Electrical Characteristics
Unless otherwise noted, VIN=VIN2=BATT=3.6V, CV!N1-2 CLDOx= RX_EN, TX_EN high. Note VINMIN greater 3.0V VOUT +0.5V. Typical values limits appearing normal type apply 25°C. Limits appearing boldface type apply over entire junction temperature range operation, -40°C +125°C. (Note Symbol VOUT Parameter Output Voltage Accuracy Default Output Voltage IOUT VOUT Output Current Output Current Limit Dropout Voltage Line Regulation Load Regulation PSRR tSTART-UP TTransient Output Noise Voltage Power Supply Ripple Rejection Ratio Start-Up Time from Shut-down Start-Up Transient Overshoot VINMIN 5.5V VOUT IOUT (Note Note VINMIN 5.5V IOUT IOUT kHz, COUT (Note kHz, COUT IOUT (Note COUT IOUT (Note COUT IOUT (Note µVRMS Conditions IOUT VOUT 3.0V Typical Limit Units
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LP3923
LDO8 (D-Type) Electrical Characteristics
Unless otherwise noted, VIN=VIN2=BATT=3.6V, CV!N1-2 CLDOx= Note VINMIN greater 3.0V VOUT +0.5V. Typical values limits appearing normal type apply 25°C. Limits appearing boldface type apply over entire junction temperature range operation, -40°C +125°C. (Note Symbol VOUT Parameter Output Voltage Accuracy Default Output Voltage IOUT VOUT PSRR tSTART-UP TTransient Output Current Output Current Limit Dropout Voltage Line Regulation Load Regulation Output Noise Voltage Power Supply Ripple Rejection Ratio Start-Up Time from Shut-down Start-Up Transient Overshoot VINMIN 5.5V VOUT IOUT (Note Note VINMIN 5.5V, IOUT IOUT kHz, COUT (Note kHz, COUT IOUT (Note COUT IOUT (Note COUT IOUT (Note Conditions IOUT VOUT 3.0V µVRMS Typical Limit Units
Buck Converter Electrical Characteristics
Unless otherwise noted, VINB 3.6V, CVINB Typical values limits appearing normal type apply 25°C. Limits appearing boldface type apply over entire junction temperature range operation, -40°C +125°C. (Note Note Symbol VOUT,PWM Parameter Feedback Voltage (BUCK) Output Voltage Conditions 3.0V 5.5V 3.0V 5.5V, IOUT 150mA External resistor divider accuracy considered. RFB1=390k RFB2=150k (Note Limit 0.485 0.515 Units
1.746
1.854
VOUT,PFM
Output Voltage regulation (Note mode relative regulation mode Line Regulation 3.0V 5.5V, IOUT IOUT Mode Load Regulation Switch Peak Current Limit Channel Resistance Internal Oscillator Frequency
0.14 0.0013 1150 1500
%/mA
VOUT ILIM_PWM RDSON(P) RDSON(N) fOSC Efficiency
3.6V Channel Resistance Mode IOUT Mode VOUT 1.8V (Note IOUT Mode VOUT 1.8V (Note
TSTUP
Start Time
IOUT (Note VOUT 1.8V
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LP3923
Charger Electrical Characteristics
Unless otherwise noted, VCHG_IN VIN= BATT 3.6V, CCHG_IN VBATT Typical values limits appearing normal type apply 25°C. Limits appearing boldface type apply over entire junction temperature range operation, -25°C +85°C. (Note Note Symbol VCHG_IN Parameter wall adapter input voltage operating range CHG_IN trip-point. Battery charging termination voltage tolerance CHG_IN programmable full-rate charging current VCHG_IN VBATT (Rising) VCHG_IN VBATT (Falling) VTERM 4.2V, ICHG VTERM measured programmed ICHG current 6.8V VCHG_IN 4.5V VBATT VCHG_IN VOK_CHG VFULL_RATE VBATT VTERM (Note -0.35 +0.35 Conditions Typical Limit Units
VOK_CHG
VTERM ICHG
-100 0.247 0.988 0.840
1200
Full rate charging current ICHG tolerance IPREEQUAL VFULL_RATE Pre-charging current Full-rate qualification threshold 2.2V VBATT VFULL_RATE VBATT rising, transition from pre-charging fullrate charging VBATT rising, transition from pre-charging fullrate charging (LP3923-VC) IEOC VRESTART IMON CBATT TREG End-of-charging current, full-rate current 0.1C option selected
-130
Restart threshold voltage From VTERM voltage (4.2V, -100 options selected) IMON Voltage IMON Voltage Capacitance BATT Regulated junction temperature Power deglitch time Deglitch time Charge timer ICHG ICHG (Note (Note
1.127 1000
Detection Timing (one combined timer) TPOK TPC_FULL TCHG VCHG VBATT VOK_CHG From pre-charging full-rate charging Pre-charge mode disabled mode/CV mode (combined timer) TEOC Deglitch time end- ofcharge transition
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LP3923
Serial Interface
Unless otherwise noted, BATT 3.6V, CVIN1-2 CLDOx VLDO3 3.0V. Typical values limits appearing normal type apply 25°C. Limits appearing boldface type apply over entire junction temperature range operation, -40°C +125°C. (Note Note Symbol fCLK tHOLD tCLK-LP tCLK-HP tDATA-HOLD tDATA-SU tTRANS Parameter Clock Frequency Bus-Free Time between START STOP Hold Time Repeated START Condition Period High Period Set-Up Time Repeated START Condition Data Hold Time Data Set-Up Time Set-Up Time STOP Condition Maximum Pulse Width Spikes that Must Suppressed Input Filter Both DATA Signals Conditions Limit Units
Note Absolute Maximum Ratings limits beyond which damage device occur. Operating Ratings conditions under which operation device guaranteed. Operating Ratings imply guaranteed performance limits. guaranteed performance limits associated test conditions, Electrical Characteristics tables. Note voltages with respect potential pin. Note Internal Thermal Shutdown circuitry protects device from permanent damage. Note human-body model discharged through machine model capacitor discharged directly into each pin, MIL-STD-883 3015.7. Note Care must exercised where high power dissipation likely. maximum ambient temperature have derated. Maximum ambient temperature (TA-MAX) dependant maximum operating junction temperature (TJ-MAX-OP), maximum power dissipation device application (PD-MAX), junction ambient thermal resistance package application (JA). This relationship given following equation: TA-MAX TJ-MAX-OP PD-MAX) Note limits guaranteed. electrical characteristics having room-temperature limits tested during production with 25°C. cold limits guaranteed correlating electrical characteristics process temperature variations applying statistical process control. Note Guaranteed design. Note Dropout voltage input-to-output voltage difference which output voltage below nominal value. This specification does apply cases implies operation with input voltage below 2.5V minimum appearing under Operating Ratings. example, this specification does apply devices having 1.5V outputs because specification would imply operation with input voltage about 1.5V. Note Junction-to-ambient thermal resistance highly application board-layout dependent. applications where high maximum power dissipation exists, special care must paid thermal dissipation issues board design. Note Full charging current guaranteed CHG_IN 6.8V, particularly higher input voltages. Increased power dissipation cause thermal regulation limit current safe level, resulting longer charging time. Note Buck output voltage accuracy depends accuracy external feedback resistors. Resistor values should chosen divider network ensure that desired output voltage specified value 0.5V. Buck Converter Application Information.
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LP3923
Power Power Down Sequences
30058638
Note CHG_IN edge sensitive HF_PWR level sensitive startup STANDBY mode level sensitive POWER-ON-RESET mode. Note PWR_ON level sensitive startup. PS_HOLD must asserted before PWR_ON goes keep powered. PWR_ON input monitored after powered (PS_HOLD asserted). Note PON_N direct inversion PWR_ON input when LDO3 powered power-on switch debouncing PON_N output). Note input signal which activates Power sequence (either PWR_ON CHG_IN HF_PWR) must when PS_HOLD asserted. Note Time delay between PS_HOLD going start Power Down sequence depends PS_HOLD_DELAY setting (0=35ms, 1=350ms) (typ.).
FIGURE Power Power Down Timing Diagram
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LP3923
LP3923 Serial Port Communication: Slave Address Code: 7h'7E
Control Registers Addr 8h'00 Register (Default value)* OP_EN1 (01000111) LDO1PGM SEL=BATT (00001100) SEL=GND (00011011) LDO2 Program SEL=BATT (00001100) SEL=GND (00011011) LDO3 (00011011) LDO4 (00011011) LDO5 (00011011) LDO6 (00011011) LDO7 (00011011) LDO8 (00011011) Status1 Trig.-PWR_ON (10000010) Trig.-HF_PWR (01000010) Trig.-CHG_IN (00100010) CHARGER Control (00010 001) CHARGER Control (00000111) CHARGER Control (00011001) BUCK_ BUCK EN_LDO8 EN_LDO7 EN_LDO2 EN_LDO1
8h'01
LDO1_ V1_OP[4]
LDO1_ V1_OP[3]
LDO1_ V1_OP[2]
LDO1_ V1_OP[1]
LDO1_ V1_OP[0]
8h'02
LDO2_ V2_OP[4]
LDO2_ V2_OP[3]
LDO2_ V2_OP[2]
LDO2_ V2_OP[1]
LDO2_ V2_OP[0]
8h'03 8h'04 8h'05 8h'06 8h'07 8h'08
LDO3_ V3_OP[4] LDO4_ V4_OP[4] LDO5_ V5_OP[4] LDO6_ V6_OP[4] LDO7_ V7_OP[4] LDO8_ V8_OP[4]
LDO3_ V3_OP[3] LDO4_ V4_OP[3] LDO5_ V5_OP[3] LDO6_ V6_OP[3] LDO7_ V7_OP[3] LDO8_ V8_OP[3]
LDO3_ V3_OP[2] LDO4_ V4_OP[2] LDO5_ V5_OP[2] LDO6_ V6_OP[2] LDO7_ V7_OP[2] LDO8_ V8_OP[2]
LDO3_ V3_OP[1] LDO4_ V4_OP[1] LDO5_ V5_OP[1] LDO6_ V6_OP[1] LDO7_ V7_OP[1] LDO8_ V8_OP[1]
LDO3_ V3_OP[0] LDO4_ V4_OP[0] LDO5_ V5_OP[0] LDO6_ V6_OP[0] LDO7_ V7_OP[0] LDO8_ V8_OP[0]
8h'0C
PWR_ON TRIG
HF_PWR TRIG
CHG_IN TRIG
TSD_H
TSD_L
8h'10
Force_ VTERM
PROG_ CHGTIME PROG_ ICHG[4] VTERM[0] TOUT_ FULLRATE
PROG_ CHGTIME PROG_ ICHG[3] PROG_ EOC[1] TOUT_ PRECHG
EN_EOC PROG_ ICHG[2] PROG_ EOC[0]
PROG_ ICHG[1] PROG_ VSTRT[1] FULLRATE TOUT_ CONSTV APU_TSD
EN_CHG PROG_ ICHG[0] PROG_ VSTART[0] PRECHG BAD_BATT PS_HOLD_ DELAY
8h'11 8h'12 8h'13 8h'14 8h'1C
CHARGER Status BATT_ CHGIN_ (0000 0000) OVER_OUT OK_OUT CHARGER Status (00000000) MISC Control1 (00000000)
used. BOLD locations Read Only type. NOTE: Control registers apart from Charger Control registers (h'10 h'12) reset default every Power Down sequence.
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LP3923
Register 0x00 OP_EN1 BUCK_PWM EN_BUCK EN_LDO8 EN_LDO7 EN_LDO2 EN_LDO1 Auto mode PFM/PWM Buck forced mode disable Buck enable Buck disable LDO8 enable LDO8 disable LDO7 enable LDO7 disable LDO2 LP3923TL/X -VI; enable LP3923TL/X-VB enable LDO2 LP3923TL/X -VI; disable LP3923TL/X-VB disable LDO1 LP3923TL/X -VI; enable LP3923TL/X-VB enable LDO1 LP3923TL/X -VI; disable LP3923TL/X-VB
Register 0x0C (Read Only) Status PWR_ON_TRIG HF_PWR_TRIG CHG_IN_TRIG TSD_H TSD_L system powered PWR_ON input system powered PWR_ON input system powered HF_PWR input system powered HF_PWR input system powered connecting adapter system powered connecting adapter Thermal Shutdown threshold exceeded Thermal Shutdown threshold exceeded (cause Power Down sequence) chip temperature been over early warning threshold chip temperature been over early warning threshold Buck output voltage range Buck output voltage within range
Register 0x13 (Read Only) CHARGER Status BATT_OVER_OUT CHGIN_OK_OUT TOUT_FULLRATE TOUT_PRECHG FULLRATE PRECHG battery voltage normal range battery voltage over critical limit voltage connected adapter input voltage connected adapter input charging current above current level charging current below current level time occurred Constant Current mode time occurred Constant Current mode time occurred pre-charge mode time occurred pre-charge mode charger mode charger mode charger pre-charge mode charger pre-charge mode
Register 0x14 (Read Only) CHARGER Status TOUT_CONSTV BAD_BATT time occurred Constant Voltage mode time occurred Constant Voltage mode charger detected battery charger detected battery
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LP3923
Register 0x1C MISC Control EN_APU_TSD PS_HOLD_DELAY start automatically after event start automatically after event powerdown after PS_HOLD been powerdown after PS_HOLD been
OUTPUT VOLTAGE PROGRAMMING following table summarizes supported output voltages LP3923. Default voltages after start-up sequences have been highlighted bold. Data Code LDO_Vx_OP[x] 8h'00 8h'01 8h'02 8h'03 8h'04 8h'05 8h'06 8h'07 8h08 8h'09 8h'0A 8h'0B 8h'0C 8h'0D 8h'0E 8h'0F table page CHARGING CURRENT PROGRAMMING following table summarizes supported currents LP3923. PROG_ ICHG[4] PROG_ ICHG[3] PROG_ ICHG[2]
LDOx 1.20 1.25 1.30 1.35 1.40 1.45 1.50 1.55 1.60 1.65 1.70 1.75 1.80* 1.85 1.90 2.00
Data Code LDO_Vx_OP[x] 8h'10 8h'11 8h'12 8h'13 8h'14 8h'15 8h'16 8h'17 8h'18 8h'19 8h'1A 8h'1B 8h'1C 8h'1D 8h'1E 8h'1F
LDOx 2.20 2.40 2.50 2.60 2.65 2.70 2.75 2.80 2.85 2.90 2.95 3.00* 3.05 3.10 3.20
PROG_ ICHG[1]
PROG_ ICHG[0]
ICHG (mA) (Default)
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LP3923
PROG_ ICHG[4]
PROG_ ICHG[3]
PROG_ ICHG[2]
PROG_ ICHG[1]
PROG_ ICHG[0]
ICHG (mA) 1000 1050 1100 1150 1200
Charging Termination Voltage Programming VTERM[1] VTERM[0] Charging Current Programming PROG_EOC[1]
Note: programmed charging current.
VTERM (Default)
PROG_EOC[0]
IEOC 0.05C 0.1C 0.15C (Default) 0.2C
Charging Restart Voltage Programming PROG_VRSTRT[1] PROG_VRSTRT[0] Charge Timer Programming PROG_CHGTIME[1] PROG_CHGTIME[0] Charging Timer (Hrs) Disabled (Default) Restart Voltage VTERM VTERM -100 (Default) VTERM -150 VTERM -200
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LP3923
BATTERY CHARGE MANAGEMENT charge management system allowing safe charge maintenance Li-Ion battery implemented LP3923. CC/CV linear charge capability with programmable battery regulation voltage charging current threshold. maintenance mode utilizing programmable restart voltage levels enables battery voltage maintained correct level. charging current constant voltage mode programmable from 1.2A steps. started without battery, battery attached later, charging current should programmed once more; otherwise, charging current will same without battery. battery deeply depleted overdischarge protection circuit active, during startup charger detect that battery present. This cause charger select non-default charging current (LDO mode default charging current). CHARGER FUNCTION Following correct detection input voltage charger charger enters pre-charge mode. this mode constant current available charge battery 2.8V. this voltage level charge management applies full rate constant current raise battery voltage termination voltage level (default 4.2V). fullrate charging current programmed different level this stage. When termination voltage (VTERM) reached, charger constant voltage mode constant voltage 4.2V maintained. This mode complete when charging current (default 0.15C) detected charge management enters maintenance mode. maintenance mode battery voltage monitored restart level (default VTERM charge cycle reinitiated re-establish termination voltage level. THERMAL SHUTDOWN Thermal Shutdown (TSD) function monitors chip temperature protect chip from temperature damage
caused, example, excessive power dissipation. temperature exceeds higher threshold value +160°C, TSD_H Register 0x0C set, chip will automatically Power Down sequence. restart operation after Thermal Shutdown initiated only after chip cooled down threshold. APU_TSD_EN Register 0x1C controlling restart. this cleared (default) then Power sequence initiated normally through PWR_ON, CHG_IN VBUS. APU_TSD_EN written logic then automatic Power sequence initiated. register settings preserved such case. Power activated only junction temperature less than early warning lower threshold +90°C. temperature monitoring function charger threshold values that result protective actions. When lower threshold +105°C exceeded, TSD_L Register 0x0C will set, will reset temperature decreased lower than below threshold. When upper charger threshold exceeded, charger will reduce charging current protect chip. Parameter Higher Threshold Charger Early Warning Early Warning Hysteresis Charger Thermal Regulation Guaranteed design. TERMINATION RESTART termination restart voltage levels determined data VTERM[1:0] PROG_VSTRT[1:0] bits control register. restart voltage programmed relative selected termination voltage. Unit
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LP3923
30058634
Simplified Charger Functional State Diagram (when enabled)
30058607
Charging Cycle Diagram
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LP3923
IMON CHARGING CURRENT MONITOR Charging current monitored within charger section proportional voltage representation charging current presented IMON output pin. output voltage relationship actual charging current represented following graph equation: VIMON(mV) (2.47 ICHG(mA))
Note that this function available there input CHG_IN charger input CHG_IN being less than compliance voltage.
30058606
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LP3923
Buck Converter Application Information
BUCK OUTPUT VOLTAGE SELECTION Buck output voltage programmed selection external feedback resistor network forming output feedback between output voltage side inductor GND.
VOUT will adjusted make voltage equal 0.5V. resistor from ground (RFB2) should around keep current drawn through resistor network minimum large enough that susceptible noise. with 0.5V, current through resistor feedback network will formula output voltage selection
VOUT RFB1 RFB2
output voltage feedback voltage (0.5V) feedback resistor from VOUT feedback resistor from
recommended value
30058618
Buck Converter Components Component Configurations Various Output Voltage Values VOUT RFB1 RFB2 [pF] [pF] [µH] COUT [µF]
INDUCTOR SELECTION There main considerations when choosing inductor; inductor should saturate, inductor current ripple small enough achieve desired output voltage ripple. Different saturation current rating specs followed different manufacturers attention must given details. Saturation current ratings typically given 25°C ratings application maximum ambient temperature should requested from manufacturer. There methods choose inductor saturation current rating. Method total current load inductor ripple current. This written
inductor inductance switching frequency
Method more conservative approach choose inductor that handle maximum current limit 1500 Given peak-to-peak current ripple (IPP) inductor needs least:
ILOAD IRIPPLE
load current average peak inductor current input voltage
inductor with saturation current rating least 1500 recommended most applications. inductor's resistance should less than good efficiency. below table suggests inductors suppliers. low-cost applications, unshielded bobbin inductor suggested. noise critical applications, toroidal shielded-bobbin inductor should used. good practice board with overlapping footprints both types design flexibility. This allows substitution low-noise toroidal inductor, event that noise from low-cost bobbin models unacceptable.
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LP3923
Suggested Inductors Their Suppliers (Preliminary Untested) Model DO3314-222MXC LPO3310-222MX ELL5GM2R2N CDRH2D142R2 Vendor Coilcraft Coilcraft Panasonic Sumida Dimensions (mm) 1.55 R(max)
INPUT CAPACITOR SELECTION ceramic input capacitor sufficient most applications. larger value used improved input voltage filtering. type capacitors, Y5V. bias characteristics ceramic capacitors must considered when selecting case sizes 0805 smaller application. Smaller case sizes many cases exhibit large drop capacitance value bias increases. input filter capacitor supplies current PFET switch converter first half each cycle reduces voltage ripple imposed input power source. ceramic capacitor's provides best noise filtering input voltage spikes this rapidly changing current. Select input filter capacitor with surge current rating sufficient power-up surge from input power source. power-up surge current approximately capacitor's value (µF) times voltage rise rate (V/µs). input current ripple calculated
considered when selecting case sizes 0805 smaller application. Smaller case sizes many cases exhibit large drop capacitance value bias increases. bias characteristics vary from manufacturer manufacturer bias curves should requested from them part capacitor selection process. output filter capacitor smooths current flow from inductor load, helps maintain steady output voltage during transient load changes reduces output voltage ripple. These capacitors must selected with sufficient capacitance sufficiently perform these functions. output voltage ripple caused charging discharging output capacitor also ESR. calculated Voltage peak peak ripple capacitance
Voltage peak peak ripple VPP-ESR IPP*RESR Voltage peak peak ripple, root mean squared worst case IRMS
OUTPUT CAPACITOR SELECTION capacitor recommended output buck converter. type capacitors; Y5V. bias characteristics ceramic capacitors must
Note that output ripple dependent inductor current ripple equivalent series resistance output capacitor (RESR). Because these components phase value used. RESR frequency dependent well temperature dependent); make sure frequency RESR given same order magnitude switching frequency.
Suggested Capacitors Their Suppliers Model (CIN COUT) GRM21BR60J106k JMK212BJ106K C2012X5R0J106K Ceramic, Ceramic, Ceramic, MURATA TAIYO YUDEN 6.3V 6.3V 6.3V 0805 0805 0805 Type Vendor Voltage Rating Case Size
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LP3923
Information
OPERATIONAL INFORMATION LP3923 eight LDOs which enabled default powered during power sequence, LDOs powered during power sequence. LDOs separately externally enabled will follow LDO3 start their respective enable pulled high. LDO1, LDO2, LDO7 LDO8 enabled/disabled Serial Interface LDO3 must remain regulation otherwise device will power down. LILO-type optimized output voltage good dynamic performance supply different fast charging (digital) pads. INPUT VOLTAGES There input voltage pins used power eight LDOs LP3923. VIN1 supply LDO1 LDO2. VIN2 supply LDO3, LDO4, LDO5, LDO6, LDO7, LDO8. EXTERNAL CAPACITORS Drop Linear Voltage regulators LP3923 require external capacitors ensure stable outputs. LDOs LP3923 specifically designed small surface mount ceramic capacitors which require minimum board space. These capacitors must correctly selected good performance. INPUT CAPACITOR Input capacitors required correct operation. recommended that capacitor connected between each voltage input pins ground (this capacitance value increased without limit). This capacitor must located distance more than from input returned clean analogue ground. ceramic capacitor recommended although good quality tantalum film capacitor used input. Important: Tantalum capacitors suffer catastrophic failures surge current when connected lowimpedance source power (like battery very large capacitor). tantalum capacitor used input, must guaranteed manufacturer have surge current rating sufficient application. There requirements (Equivalent Series Resistance) input capacitor, tolerance temperature coefficient must considered when selecting capacitor ensure capacitance will remain within operational range over entire operating temperature range conditions. OUTPUT CAPACITOR Correct selection output capacitor critical ensure stable operation intended application. output capacitor must meet requirements specified recommended capacitor table over conditions application. These conditions include DC-bias, frequency temperature. Unstable operation will result capacitance drops below minimum specified value. LP3923 designed specifically work with very small ceramic output capacitors. LDOs LP3923 specifically designed used with type capacitors. With these capacitors, selection capacitor
application dependant range operating conditions temperature range that application. (See section Capacitor Characteristics). also recommended that output capacitor placed within from output returned clean ground line. CAPACITOR CHARACTERISTICS LDOs LP3923 designed work with ceramic capacitors input output take advantage benefits they offer. capacitance values around 1µF, ceramic capacitors give circuit designer best design options terms cost minimal area. both input output capacitors careful interpretation capacitor specification required ensure correct device operation. capacitor value change greatly dependant conditions operation capacitor type. particular, ensure stability, output capacitor selection should take account capacitor parameters ensure that specification within application. Capacitance value vary with bias conditions well temperature frequency operation. Capacitor values will also show some decrease over time aging. capacitor parameters also dependant particular case size with smaller sizes giving poorer performance figures general. example shows typical graph showing comparison capacitor case sizes Capacitance Bias plot. shown graph, result Bias condition capacitance value drop below minimum capacitance value given recommended capacitor table (0.7 this case). Note that graph shows capacitance spec 0402 case size capacitor higher bias voltages. therefore recommended that capacitor manufacturers' specifications nominal value capacitor consulted conditions some capacitor sizes (e.g. 0402) suitable actual application.
30058616
FIGURE Graph Showing Typical Variation Capacitance Bias Ceramic capacitors have lowest values, thus making them best eliminating high frequency noise. typical ceramic capacitor range also meets requirement stability. temperature performance ceramic capacitors varies type. Capacitor type specified with tolerance ±15%
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LP3923
over temperature range -55°C +125°C. similar tolerance over reduced temperature range 55°C +85°C. Most large value ceramic capacitors manufactured with temperature characteristics, which results capacitance dropping more than temperature goes from +25°C +85°C. Therefore recommended over these other capacitor Output Capacitors, Recommended Specification Symbol CO(LDO1) CO(LDO2) CO(LDO3) CO(LDO4) CO(LDO5) CO(LDO6) CO(LDO7) CO(LDO8) Parameter Capacitance Capacitance Capacitance Capacitance Capacitance Capacitance Capacitance Capacitance
types applications where temperature will change significantly above below +25°C. No-Load Stability LDOs LP3923 will remain stable regulation with external load.
Type X5R, X5R, X5R, X5R, X5R, X5R, X5R, X5R,
Units
Note: Note: capacitor tolerance should better over full temperature range. X7R, capacitors should used. These specifications given ensure stability supply outputs care must taken ensure that capacitance remains within these values over conditions within application. Capacitor Characteristics section Application Information.
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LP3923
30058602
FIGURE Typical Application Circuit (Buck Output used input LILOs)
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LP3923
Compatible Serial Interface
INTERFACE OVERVIEW compatible synchronous serial interface provides access programmable functions registers device. This protocol uses two-wire interface bi-directional communications between IC's connected bus. interface lines Serial Data Line (SDA), Serial Clock Line (SCL). These lines should connected positive supply, pull-up resistor remain HIGH even when idle. Every device assigned unique address acts either Master Slave depending whether generates receives serial clock (SCL). DATA TRANSACTIONS data transferred during each clock pulse. Data sampled during high state serial clock (SCL). Consequently, throughout clock's high period, data should remain stable. changes line during high state middle transaction, aborts current transaction. data should sent during state. This protocol permits single data line transfer both command/control information data using synchronous serial clock.
Condition terminate transaction. Every byte written must bits long transferred with most significant first. After each byte, Acknowledge signal must follow. following sections provide further details this process. START STOP Master device always generates Start Stop Conditions (control codes). After Start Condition generated, considered busy retains this status until certain time after Stop Condition generated. high-to-low transition data line (SDA) while clock (SCL) high indicates Start Condition. low-to-high transition line while high indicates Stop Condition.
30058610
FIGURE Start Stop Conditions addition first Start Condition, repeated Start Condition generated middle transaction. This allows another device accessed, register read cycle. ACKNOWLEDGE CYCLE Acknowledge Cycle consists signals: acknowledge clock pulse master sends with each byte transferred, acknowledge signal sent receiving device. master generates acknowledge clock pulse ninth clock pulse byte transfer. transmitter releases line (permits high) allow receiver send acknowledge signal. receiver must pull down line during acknowledge clock pulse ensure that remains during high period clock pulse, thus signaling correct reception last data byte readiness receive next byte.
30058627
FIGURE Transfer Each data transaction composed Start Condition, number byte transfers (set software) Stop
30058628
FIGURE Acknowledge Cycle
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LP3923
"ACKNOWLEDGE AFTER EVERY BYTE" RULE master generates acknowledge clock pulse after each byte transfer. receiver sends acknowledge signal after every byte received. There exception "acknowledge after every byte" rule. When master receiver, must indicate transmitter data not-acknowledging ("negative acknowledge") last byte clocked slave. This "negative acknowledge" still includes acknowledge clock pulse (generated master), line pulled down. ADDRESSING TRANSFER FORMATS Each device unique slave address. LP3923 operates slave device with address 7h'7E (binary nnnnnnnn). Before data transmitted, master transmits address slave being addressed. slave device should send acknowledge signal line, once recognizes address. slave address first seven bits after Start Condition. direction data transfer (R/W) depends sent after slave address eighth bit. When slave address sent, each device system compares this slave address with own. there match, device considers itself addressed sends acknowledge signal. Depending upon state (1:read, 0:write), device acts transmitter receiver. CONTROL REGISTER WRITE CYCLE Master device generates start condition. Master device sends slave address bits) data direction (r/w '0'). Address Mode Data Read
Slave device sends acknowledge signal slave address correct. Master sends control register address bits). Slave sends acknowledge signal. Master sends data byte written addressed register. Slave sends acknowledge signal. master will send further data bytes control register address will incremented after acknowledge signal. Write cycle ends when master creates stop condition.
CONTROL REGISTER READ CYCLE Master device generates start condition. Master device sends slave address bits) data direction (r/w '0'). Slave device sends acknowledge signal slave address correct. Master sends control register address bits). Slave sends acknowledge signal. Master device generates repeated start condition. Master sends slave address bits) data direction (r/w "1"). Slave sends acknowledge signal slave address correct. Slave sends data byte from addressed register. master device sends acknowledge signal, control register address will incremented one. Slave device sends data byte from addressed register. Read cycle ends when master does generate acknowledge signal after data byte generates stop condition.
<Start Condition> <Slave Address><r/w `0'>[Ack] <Register Addr.>[Ack] <Repeated Start Condition> <Slave Address><r/w `1'>[Ack] [Register Data]<Ack NAck> additional reads from subsequent register address possible <Stop Condition> <Start Condition> <Slave Address><r/w `0'>[Ack] <Register Addr.>[Ack] <Register Data>[Ack] additional writes subsequent register address possible <Stop Condition>
Data Write
Data from master Data from slave
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LP3923
REGISTER READ WRITE DETAIL
30058629
FIGURE Register Write Format
30058630
FIGURE Register Read Format
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LP3923
Physical Dimensions inches (millimeters) unless otherwise noted
Thin Micro 30Package Package Number MKT-TLA3011A 2.466 ±0.030 2.974 ±0.030 0.600 ±0.075
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LP3923
Notes
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LP3923 Cellular Phone Power Management Unit
Notes
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