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LH79531
LH79531 Universal Microcontroller
SHARP reserves right make changes specifications described herein time without notice order improve design reliability. SHARP does assume responsibility circuitry described; circuit patent licenses implied. SHARP assumes responsibility damage caused misuse improper devices.
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LH79531 Universal Microcontroller Data Sheet 2000-2001 Copyright SHARP CORPORATION. Revision ICG000017 Released July 2003
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LH79531 Universal Microcontroller
Table Contents
Introduction Features. Application Flexibility Functional Descriptions ARM7TDMICore Memory Interface Architecture Memory Map. Operation. System Priorities. Memory Region Supervisor Access Internal Memory-Mapped Objects Locked Instruction Sequences Error Handling Memory Segmentation. Memory Protection Unit Register Summary. Register Descriptions SegxStart Segment Start Register SegxSize Segment Size Register SegxCfg Memory Segment Configuration Registers SegDefCfg: Default Segment Configuration Register Chip Enables Cache Local SRAM Cache Configurations Write Buffer Bufferable Write Reset. Invalidate. Flush Abort. Local SRAM. Register Summary. Register Descriptions SRAMTag: Local SRAM Start Address Register SRAMWait: Local SRAM Wait Register Main MAINASBCTRL: Local SRAM Start Address Register Main LCDASBCTRL: Local SRAM Start Address Register CacheControlReg: Cache Control Register. External Interface (EBI). Features. Page Mode Support. External Interface Memory Registers. Register Summary. Register Descriptions RAM_SEG_REGx Registers Segment Register RAM_CTL_REGx Registers Control Register EXTBIFCtrl: External Interface Control Register Synchronous Dynamic Controller (SDRAMC) Features. Register Summary. Register Descriptions SDRAM_SEGx_REG SDRAM Segment Register SDRAM_SDRx_REG SDRAM Segment Descriptor Register. SDRAM_CNTROL: SDRAM Control Register SDRAM_STATUS: SDRAM Status Register Data Sheet Page
LH79531 Universal Microcontroller
SDRAM_TIMING0: SDRAM Timing0 Register SDRAM_TIMING1: SDRAM Timing1 Register SDRAM_TIMING2: SDRAM Timing2 Register ASBBridgeCtrl: Bridge Control Register Address Mapping. Page Management SDRAM Controller Operations Write Mode Register Auto Refresh Mode Self Refresh Mode (Power Down Mode) Power Save Mode. Initialization Sequence External Data Width Internal Access Size Conversions. Controller (DMAC). Overview. Register Summary. Register Descriptions DMACModeCtrlRegChx DMAC Mode Control Register DMACSrc(Dst)CtrlRegChx DMAC Source(Destination) Address Control Register DMACStatusRegChx DMAC Status Register DMACSrc(Dst)AddrRegChx DMAC Source(Destination) Address Register. DMACCounterRegChx DMAC Transfer Count Register DMACControlReg: DMAC Control Register DMACRequestSource: DMAC Request Source Register DMACIntSourceChx DMAC Interrupt Source Register DMACAckSelect: DMAC Acknowledge Select Register. Real Time Clock (RTC). Overview. Functional Description Timer, Alarm Calendar Setting Reading Current Time Date Operation Modes Register Summary. Register Descriptions Second, Minute: Second, Minute Register Hour: Hour Register DayM: Month Register. DayW: Week Register Month: Month Register. Year: Year Register Century: Century Register MinD, HourD: Alarm Min, Alarm Hour Register Check: Check Register RCSR: Control Status Register. Reset Values Reset Power Controller (RPC) Features. Overview. Power Mode Operation. Active Mode Standby Mode Sleep Mode Stop Mode. Stop2 Mode. XCLKEN Output Port Register Summary. Register Descriptions Data Sheet Page
LH79531 Universal Microcontroller
PowerMode: Power Mode Register Identification: Register. MemoryMap: Memory Control Register. ResetStatus: Reset Status Register ResetStatusClear: Reset Status Clear Register CPUClockCtrl: Clock Control Register MacroClockCtrl: Macro Clock Control Register MacroClockSel: Macro Clock Select Register SoftReset: Soft Reset Register Arbitration: Arbitration Register. DecodeMode: Decode Mode Register. ASBBridgeCtrl: Bridge Control Register Controller Overview. Register Summary. Register Description PLL_CTL: Control Register PLL_FREQ: Frequency Divide Count Register PLL_PSR: Prescale Count Register. PLL_WUC: Warm-Up Count Register Controller. Features. Overview. Palette Direct Color Gray Scale Timing Generation Interrupts Pixel Data Storage Format. Register Summary. Register Descriptions (STN Format). LCDTiming0: Timing0 Register LCDTiming1: Timing1 Register LCDTiming2: Timing2 Register LCDTiming3: Timing3 Register LCDUP(LP)BASE: Upper(Lower) Panel Frame Base Address Register LCDINTREnable: Interrupt Enable Register. LCDControl: Control Register LCDStatus: Interrupt Status Register LCDInterrupt: Masked Interrupt Status Register LCDUP(LP)CURR: Upper(Lower) Panel Current Address Register LCDPalette: Palette Register. Register Descriptions (DMTN HR-TFT Interface Conversion) Register. LCDICPSetup: Interface Peripheral Setup Register. LCDICPControl: Interface Peripheral Control Register LCDICPTiming1: HR-TFT Timing1 Register. LCDICPTiming2: HR-TFT Timing2 Register. Panel Output Signal Controller. Features. Register Summary. Register Descriptions USBINTRDA: Interrupt Read Bank Register USBINTRSTA: Interrupt Write Bank Register. USBINTRDB: Interrupt Read Bank Register USBINTRSTB: Interrupt Write Bank Register. USBFRML: Lower Frame Number Register. Data Sheet Page
LH79531 Universal Microcontroller
USBPRMDATA: Parameter Register USBFRMH: Higher Frame Number Register USBEPT0I: FIFO Data Write Register USBREQDATA: Device Request Data Register USBEPT1I: FIFO Data Write Register USBEPT3I: FIFO Data Write Register USBEPTSTR: Endpoint Status Read Register USBEPTSTW: Endpoint Status Write Register. USBCTRL1: Control Register. USBCTRL2: Control Register. USBFIFOST: FIFO Status Register USBEPT0RES: FIFO Reset Register FIFO Response Register USBEPT0O: FIFO Data Read Register USBEPT1RES: FIFO Response Register. USBEPT2O: FIFO Data Read Register USBEPT3RES: FIFO Response Register. USBWNUM: Wait Number Register USBSRST: Software Reset Register Synchronous Serial Interface Features. Register Summary. Register Descriptions SSPCR0: Control Register SSPCR1: Control Register SSPDR: Data Register SSPSR: Status Register SSPCPSR: Clock Prescale Register SSPIIR: Interrupt Identification Register. SSPICR: Interrupt Clear Register. Universal Asynchronous Receiver Transmitter (UART) Features. Register Summary. Register Descriptions UARTxDR UART Data Register UARTxRXSTAT UART Receive Status Register UARTxMSEOI UART Clear Modem Status Change Interrupt L_UxBRLCR UART Baud Rate Line Control Register H_UxBRLCR UART High Byte Baud Rate Line Control Register. M_UxBRLCR UART Middle byte Baud Rate Line Control Register L_UxBRLCR UART byte Baud Rate Line Control Register. UARTxCON UART Control Register UARTxFLG UART Flag Register. UARTxMCR UART MODEM Control Register UARTxINTMSK UART Interrupt Mask Register UARTxSTAT UART Interrupt Status Register UARTxINTR UART Interrupt Status Register. Pulse Width Modulators (PWM) Features. Overview. Normal Mode Synchronization Mode Power Management. Frequency Duty Cycle. Register Summary. Register Descriptions PWMx_TC Terminal Count Register PWMx_DC Duty Cycle Register Data Sheet Page
LH79531 Universal Microcontroller
PWMx_ENB Enable Register PWMx_DIV Clock Divider Register PWMx_SYNC Synchronous Mode Register PWMx_INV Output Inversion Register Programming Rules Programming Examples. Infrared Controller. Overview. Register Summary. Register Descriptions IrDA Interface Register IrDAWCNT: IrDA Wait Count Register IrDAMCLKSEL: IrDA MCLK Frequency Select Register IrDA Control Register CR0: IrDA Reset Register. CR1: IrDA Transmit Receive Mode Register CR2: IrDA Interrupt Mask Register CR3: IrDA Transmit Receive Control Register CR4: IrDA Transmit Data Length Setup Register (Lower byte). CR5: IrDA Transmit Data Length Setup Register (Upper byte). CR6: IrDA Transmit Data Register (Lower byte) CR7: IrDA Transmit Data Write (Upper byte) CR8: IrDA Local Address Register CR9: IrDA System Control Register CR10: IrDA Modem Select Register CR11: IrDA System Control CR12: IrDA Timer Initial Value Register (Lower byte) CR13: IrDA Timer Initial Value Register (Upper byte) CR15: System Control Register. IrDA Status Register SR0: IrDA Transmit Receive Status Register SR1: IrDA Receive Status Register :IrDA Interrupt Mask Status Register SR3: IrDA Interrupt Cause Register SR4: IrDA Actual Data Length Counter Register (Lower byte) SR5: IrDA Actual Data Length Counter Register (Upper byte) SR6: IrDA Receive Data Register (Lower byte) SR7: IrDA Receive Data Register (Upper byte) SR8: IrDA Controller Version Register SR9: IrDA System Status Register SR10: IrDA Modem Select Status Register SR11: IrDA System Status Register SR12: IrDA Timer Counter Register (Lower byte) SR13: IrDA Timer Counter Register (Upper byte) SR15: IrDA System Status Register External Interface Signals. Counter Timer. Counter Timer Operation. Register Summary. Register Descriptions CTxLoad Counter Timer Load Register CTxValue Counter Timer Value Register CTxControl Counter Timer Control Register CTxClear Counter Timer Clear Register Watchdog Timer (WDT) Features. Overview. Data Sheet Page
LH79531 Universal Microcontroller
Register Summary. Register Descriptions WDTCTRL: Control Register WDCNTR: Counter Reset Register Programmable (PIO). Features. Register Summary. Register Descriptions PIO[A-E]Data: Data Register PIO[A-E]Ctrl: Control Register PIO[A-E]DataSet: Data Register PIO[A-E]DataReset: Data Reset Register PIO[A-F]MuxControl(1-2): Multiplex Control Register Multiplexed I/O. Interrupt Controller (INTC) Features. Register Summary. Register Descriptions IRQStatus FIQStatus: Interrupt Status Register IRQRawStatus FIQRawStatus: Interrupt Status Register IRQEnable FIQEnable: Interrupt Enable Register IRQEnableSet FIQEnableSet: Interrupt Enable Register. IRQEnableClear FIQEnableClear: Interrupt Enable Clear Register INTConfig0 INTConfig1: External Interrupt Configuration Register. INTClear: Interrupt Clear Register Interrupt Channel Assignments Electrical Characteristics Absolute Maximum Ratings. Recommended Operating Conditions Specifications Test Conditions. Specifications Descriptions Mechanical Dimensions Appendix Interface Waveforms Timings Memory Read Write Operation Timing. SDRAM Cycle Waveforms Transfer Timing Interface Waveforms Power Sequence Reset Timing.
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LH79531 Universal Microcontroller
Introduction
LH79531, powered ARM7TDMITM, complete `System-On-Chip' with high level integration satisfy wide range requirements expectations. LH79531 combines 32-bit ARM7TDMIRISC, color controller, Cache, Local SRAM, number essential peripherals such Direct Memory Access Controller (DMAC), Serial Parallel Interfaces, Counter/Timers, Real Time Clock, Watch Timer, Pulse Width Modulators, on-chip Phase Lock Loop (PLL). Debug made simple JTAG support. This high level integration lowers overall system costs, reduces development cycle time accelerates product introduction. LH79531's fully static design, power management unit, voltage operation (2.5 Core, I/O), on-chip PLL, fast interrupt response time, on-chip cache/SRAM, powerful instruction set, very power RISC core provide high performance current draw. needs mobile lifestyle require advanced processing capability portable devices. This capability must come with increased performance display system peripherals, demand less power from batteries. LH79531 integrated solution these needs.
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LH79531 Universal Microcontroller
Features
Highly Integrated Single Chip High Performance MHz) Driven, External Clock Power Modes Active, Standby, Sleep, Stop, Stop2 32-bit ARM7TDMIRISC Core Dual Architecture SDRAM 32-bit Data SRAM 16-bit Data On-Chip Memory Cache SRAM Cache SRAM Cache SRAM On-Chip Cache Unified Instruction Data Supports Bytes, Half-words, Words Write-back Write-through Write Buffer On-chip Programmable (32.768kHz) Clock Power Management On-chip Programmable Interrupt Controller External Interrupts Programmable Active High Edge Level Trigger Three UARTs 16C550-class Support Real-Time Clock (RTC) Full Calendar Separate Power Clock Four 16-bit Pulse Width Modulators Synchronous Serial Interface Compatible with SPI, µWire, Synchronous Serial Standard Programmable Color Controller 1024 Resolution 18-bit Video Direct Interface HR-TFT panels Supports STN, Color STN, HR-TFT, TFT, DMTN STN: Supports Gray Shades Color STN: 3375 Direct Colors Supports Colors Selected from palette 3375 Colors TFT: Supports Direct Colors Colors Selected from Palette Colors Flexible Programmable Memory Interface SRAM Flash Controller 26-bit External Address 8-bit External Data Segments each) SDRAM Controller 15-bit External Address 16-bit External Data Segments (256 Mbytes each) Supports Self Auto Refresh Programmable Parallel Signals Three 16-bit Counter Timer Channels Modes Operation Interrupt Terminal Count Rate Generator Square Wave Generator Cascadable (32-bit 48-bit) Hardware Watchdog Timer Programmable Time-out Intervals Protection Mechanism System Reset Interrupt Options channels Internal External Transfers Single Burst Buffered 8-bit, 16-bit, 32-bit Transfers Controller (Compatible with USB1.1 Standard) Universal Communication Controller IrDA-1.0 (115.2 kbps) IrDA-1.1 Mbps) DASK Interface JTAG Debug Support Little Endian Package: 216-pin TQFP Operating Conditions Core: 2.35V 2.75 I/O: 70°C
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LH79531 Universal Microcontroller
DEBUG/ BOUNDARY SCAN
CONTROLS
DISPLAY
CONTROLS DATA ADDRESS
JTAG
ARM7TDMI CACHE
CONTROLLER
ADDRESS DATA CONTROLS IrDA
EXTBIF (x8, x16) MAIN MAIN LCDC SDRAMC BRIDGE SDRAM CONTROLLER (x16 x32)
IrDA Mbps
BRIDGE
RESET
DEVICE
PERIPHERAL
PERIPHERAL
(74)
GENERAL
UART
INTC
TIMER
ASYNCHROUS SERIAL INTERFACE SYNCHRONOUS SERIAL INTERFACES
OSCILLATOR
CHANNELS CLK/XTAL
INTERRUPTS
CHANNELS
77791-11A
Figure Block Diagram LH79531
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LH79531 Universal Microcontroller
Application Flexibility
LH79531's flexibility simplifies creation innovative products. Figure LH79531 forms basis advanced Internet appliance. many available functions allow touch screen, plus power consumption makes excellent choice portable applications.
ARM7TDMI@50MHz with cache perform functions required simple audio output
TOUCH SCREEN Panel
Frame Buffer
Controller
Touch Screen Interface
System Memory Memory Expansion Flash
SOUND POTS
A/D,
AUDIO LH79531 MODEM KEYPAD Timer, GPIO, PWM, SPI, IrDA, PLL, DMA,
Controller IrDA Controller
RS-232C Application Specific Module
LH79531 Component
Real Time Clock
BATTERY MGT.
Figure Sample Application Using LH79531
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LH79531 Universal Microcontroller
Functional Descriptions
ARM7TDMICore
LH79531 built around ARM7TDMIcore. ARM7TDMIis comprised Thumb-aware ARM7T processor, with Debugging (D), Enhanced Multiplier (M), In-Circuit-Emulation (I), JTAG-style port ease development application software, operating systems, hardware. Thumb Aware Core Supports Powerful Standard 32-bit Architecture/Instructions Supports Code Efficient 16-bit Thumb Architecture/Instructions Transparent, Real Time Decompression Thumb Instructions 64-bit Enhanced Multiplier with Accumulator Excellent Code Density Fully Static Design Power Sensitive Applications Power Consumption High Performance Fast Interrupt Response with Minimal Context Switching Endian Little Endian Mode Built-in Debug Support JTAG-style Port Based IEEE Standard 1149.1-1990
NOTE: Refer ARM7TDMIData Sheet additional information, including: Programmer's model, instruction set, Thumb instruction set, instruction cycle operation, JTAG debug interface. LH79531 have restriction ARM7TDMI debug interface. hardware breakpoint using ICEBreaker cachable region cache enabled state, possible break. avoid this, software breakpoint.
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LH79531 Universal Microcontroller
Memory Interface Architecture
LH79531 provides following data-path-management resources chip: Three 32-bit high-bandwidth internal data busses zero-wait-state instruction/data cache, configurable write-back write-through zero-wait-state scratch-pad (Local SRAM) (Shared resource with instruction/data cache) 8-word posted-write buffer that accumulates forwards outgoing data slow memory Chip Select External Controller ROM/SRAM Synchronous DRAM controller 32-bit interface common program graphics memory External Interface with address bi-directional data pins high-resolution controller with built-in HR-TFT timing logic 2-channel general purpose controller
Memory
system resources accessible LH79531 memory mapped. These include external resources (e.g. ROM, PROM, SRAM, SDRAM, External Peripherals) internal resources (system configuration registers, peripheral configuration registers, Local SRAM). Allocation address ranges each physical resource accomplished programming number segments start size registers, allowing wide flexibility partitioning memory space. These configurable partitions will called `segments' throughout this document. They programmed means several segment registers contained within LH79531. broadest partitioning memory space subdivision into four `regions'. address range each these regions fixed, according highest-order address bits. These regions define broad type resource being addressed. Some regions only contain external SDRAM. Others only contain external devices connected External Interface. region address space reserved accessing system configuration registers themselves, well many peripheral control registers. Figure narrowest level partitioning memory space defined programming eight separate memory segments, plus default segment. these, used describe address range configure features different External Interface peripherals; used describe address range features external SDRAM devices; (the default segment) used after system reboot immediately access boot ROM; describe Local SRAM. segment's segment-descriptor registers carry information about communicate with corresponding external devices, such number system clock cycles, type SDRAM, etc., access protection information such cache-ability CPU, queuing through write-buffers. storage such information distributed through several blocks within LH79531, thus must programmed into each affected resource's segment descriptor registers before corresponding resource used. following sections describe each resource category must programmed proper resource-access configuration address-range selection. some cases, same segment's address range must defined consistently several system resources, same address mapping should programmed into each affected peripheral's segment registers. other cases, segment's address range fixed hardware, that access common resource depend upon perspective requesting master. three separate busses provide bi-directional address/control data transport between system resources, allowing transactions originated concurrently ARM7TDMITM, controller, controller. Memory partitioned into segments, each which associates type peripheral designated address-range controls over access permissions configuration: segment activates System-level peripherals (e.g. memory registers, cache configuration) segment activates Local SRAM segments define ROM/SRAM configurations segments distinguish between SDRAM configurations segment activates User-level peripherals such UART ports
decoders block selection, privilege information, configuration information such latency memory lookup tables. Their principal function decode addresses select appropriate peripheral destinations routing Data Sheet Page
LH79531 Universal Microcontroller
data. program these lookup-tables, they appear 32-bit registers that permanently mapped into peripherals region memory. Mapping information must made available each controller.
Operation
Separating optimizes latency bandwidth between Controller external SDRAM (graphics memory region) with little disruption local processor peripheral activity. LCD, cache, controllers perform majority their data transfers 4-word sequential bursts within single memory segment, maximizing throughput. This supports high pixel-rate bandwidth since ARM7TDMI, cache, Local SRAM have their bus. high rate cache and/or Local SRAM provides good processor throughput with little interference graphics updates peripheral DMA. Code, Data Graphics memory reside either SRAM SDRAM. high performance, graphics memory should reside SDRAM, Code/Data SRAM. following types transactions require data traffic traverse more than busses. Depending system application, code should optimized keep these transactions infrequent possible, since their interaction reduces achievable system throughput: Cache misses causing line-fills Load/stores with cache disabled Stores while cache write-through mode Transfers between processor peripherals into Local SRAM into SDRAM
System Priorities
LH79531 provides three independent operating busses. This provides large degree concurrency among tasks, such CPU/Cache transactions, transactions, refreshes. However, programmer must take care issue inter-dependent tasks proper sequence. busy high-priority master monopolize control bus, obstructing lower-priority requestors. When programming concurrent tasks (such DMA), care must taken make high-priority task dependent completion competing, lower-priority task, this could hang system. SDRAM maintenance (for example, refresh) affect latency SDRAM access. Refer SDRAM section more details. Setting ARBPR (Arbitration Priority Control) Reset Power Controller's Arbitration register sets priorities follows: Master Device Access Main LCDC Channel Channel NOTES: Priority Highest, Lowest) Default setting ARBPR bit. (`0') Peripheral
Alternatively, setting ARBPR (Arbitration Priority Control) RPC's Arbitration register change priorities channel Master Device Access LCDC Channel Channel Main Peripheral
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LH79531 Universal Microcontroller
LH79531 optimized have frame buffer SDRAM. system also support graphics memory SRAM addition Code Data) Code Data SDRAM addition Graphics memory). presence bridges allows busses operate independently.
Memory Region
system memory LH79531 views, based RPC_MAP (MemoryMap: Memory Control Register; Reset Power Controller Section):
0xFFFFFFFF Region3 0xC0000000 Region2 0x80000000 Region1 0x40000000 Region0 0x00000000
0xFFFFFFFF SYSTEM INTERNAL PERIPHERALS ROM/RAM EXTERNAL CONTROLLER Region3 0xC0000000 Region2 0x80000000 SDRAM SDRAM CONTROLLER Region1 0x40000000 ROM/RAM EXTERNAL CONTROLLER Region0 0x00000000 RPC_MAP RPC_MAP SDRAM SDRAM CONTROLLER SDRAM SDRAM CONTROLLER SYSTEM INTERNAL PERIPHERALS ROM/RAM EXTERNAL CONTROLLER
Figure Memory NOTES: RPC_MAP initialized upon reset. Local SRAM mapped only regions 0,1,and Cache section more details. Right after reset when RPC_MAP `0', ROM/RAM mapped regions: 0x00000000-0x3FFFFFFF 0x80000000-0xBFFFFFFF This means same physical ROM/RAM memory accessed from both locations. Programming RPC_MAP will extend SDRAM lower memory. This will SDRAM 0x00000000-0x3FFFFFFF 0x40000000-0x7FFFFFFF This means that user only access ROM/RAM from 0x80000000-0xBFFFFFFF. segments have overlapping areas then lower numbered segment activated (Segment_0 higher priority than Segment_1).
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LH79531 Universal Microcontroller
Supervisor Access Internal Memory-Mapped Objects
Table Table Table show addresses, Remap functions, Class various devices within LH79531. Table Main Memory Mapping REMAP Ext. ROM/RAM IrDA MainASB EXTBIF Cache Ctrl Class
Address REMAP 0x80000000 Ext. ROM/RAM 0xC0000000 0xFFFF0000 IrDA 0xFFFF0400 0xFFFF0800 0xFFFFA000 MainASB 0xFFFFA400 EXTBIF 0xFFFFAC00 Cache Ctrl 0xFFFFB000 0xFFFFE400 NOTE: Reserved.
Int. Int. Int. Sys. Sys. Sys.
Table
Memory Mapping REMAP SDRAM LCDC LCDMUX SDRAMC LCDASB Class
Address REMAP 0x40000000 SDRAM 0xC0000000 0xFFFF2000 LCDC 0xFFFF2400 0xFFFF2800 LCDMUX 0xFFFFC000 SDRAMC 0xFFFFC400 LCDASB NOTE: Reserved.
Int. Sys. Sys.
Table
Peripheral Memory Mapping Device Class Internal Internal Internal Internal Internal Internal Internal System System System System System
Address MACRO 0xFFFF4000 UART0 0xFFFF4400 UART1 0xFFFF4800 UART2 0xFFFF4C00 0xFFFF5000 0xFFFF5400 0xFFFF5800 Counter/Timer 0xFFFF5C00 0xFFFF7000 0xFFFF7400 INTC 0xFFFF7800 0xFFFF7C00 0xFFFF8000 0xFFFF8400 0xFFFF8800 NOTE: Reserved.
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LH79531 Universal Microcontroller
Locked Instruction Sequences
ARM7 instructions SWPB supported LH79531 use. Users should restrict external-semaphore targets non-bufferable memory space assure memory coherency. External cycles, however, atomic system includes multiple competing masters sharing external interface.
Error Handling
decoders responsible flagging memory protection faults (during memory lookup) attempts access unassigned areas memory. selected slaves responsible flagging other types access faults, such configuration addressing problems. errors generate BERROR interrupt.
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LH79531 Universal Microcontroller
Memory Segmentation
Memory Protection Unit
system supports eight programmable memory segments default segment. user must define these segments consistently decoders. EBI(External Interface) SDRAM blocks descriptions these registers. When address outside area specified least these segments, interface will respond with SDRAM error. start (SegxStart) size (SegxSize) registers determine boundaries segment. (Where describes numerical registers.) configuration (SegxCfg) registers contain information about system/user write/read privileges, cache-ability, buffer-ability each eight segments default segment. default segment used after Reset access boot ROM. configuration register SegDefCfg. (See SegDefCfg, RAM_SEG_REG Configuration.)
Register Summary
Table Memory Protection Unit Registers (Base Address: 0xFFFFAC00) Offset Register Name Size Reset Value 0x00 Seg0Start Segment Start Register 0x000000 0x04 Seg1Start Segment Start Register 0x000000 0x08 Seg2Start Segment Start Register 0x000000 0x0C Seg3Start Segment Start Register 0x000000 0x10 Seg4Start Segment Start Register 0x000000 0x14 Seg5Start Segment Start Register 0x000000 0x18 Seg6Start Segment Start Register 0x000000 0x1C Seg7Start Segment Start Register 0x000000 0x20 Seg0Size Segment Size Register 0x00 0x24 Seg1Size Segment Size Register 0x00 0x28 Seg2Size Segment Size Register 0x00 0x2C Seg3Size Segment Size Register 0x00 0x30 Seg4Size Segment Size Register 0x00 0x34 Seg5Size Segment Size Register 0x00 0x38 Seg6Size Segment Size Register 0x00 0x3C Seg7Size Segment Size Register 0x00 0x40 Seg0Cfg Segment Configuration Register 0x3C 0x44 Seg1Cfg Segment Configuration Register 0x3C 0x48 Seg2Cfg Segment Configuration Register 0x3C 0x4C Seg3Cfg Segment Configuration Register 0x3C 0x50 Seg4Cfg Segment Configuration Register 0x3C 0x54 Seg5Cfg Segment Configuration Register 0x3C 0x58 Seg6Cfg Segment Configuration Register 0x3C 0x5C Seg7Cfg Segment Configuration Register 0x3C 0x60 SegDefCfg Default Segment Configuration Register 0x3C NOTES: important that these registers programmed compatibly with those SDRAM External controllers. Those controllers also contain configuration registers that must programmed compatibly with these registers. segments default reset privileges (Supervisor), privileges (User), non-bufferable, non-cacheable.
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LH79531 Universal Microcontroller
Register Descriptions
SegxStart Segment Start Register
Offset 0x00 0x1C Position 3322222222221111111111 109876543210987654321098765 3210 Seg0Start Seg7Start 0x00000000 START Reserved Register Size Reset Value
memory address belongs segment SegxStart [31:10] Memory Address [31:10] SegxStart [31:10] Size (Where describes numerical registers) registers 32-bits wide. However, 32-bits address value used; some bits reserved. Reserved bits must written `0'. These reserved bits undefined when read. start address must start address boundary consistent with segment size. instance, segment must start boundary; segment must start boundary.
SegxSize Segment Size Register
Offset 0x20 0x3C Register Seg0Size Seg7Size Size Position Reset 3322222222221111111111 Value 0x00 Reserved SIZE SegSize Description
Table
SIZE [4:0] Segment Size 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 Others NOTE: areas will wrap occupy address range. Upon reset, size register defaults size (non-area).
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LH79531 Universal Microcontroller
SegxCfg Memory Segment Configuration Registers
Offset 0x40 0x5C Register Seg0Cfg Seg7Cfg Size Position Reset 3322222222221111111111 Value 0x3C Reserved
This registers provide access privileges, cacheability, bufferability information corresponding memory segments. device placed Supervisor, and/or User modes; each these carrying privileges read write. Note that SDRAM External Interface controllers also contain configuration registers that must programmed compatibly with configuration registers Memory Protection Unit. register segments region configuration must non-bufferable non-cacheable. Table Name SegCfg Description
Description Supervisor mode privileges privilege Read only privilege Write only privilege Read/Write privilege User mode privileges privilege Read only privilege Write only privilege Read/Write privilege Bufferability (Supervisor User modes) bufferable Bufferable Cacheability (Supervisor User modes) cacheable Cacheable
Each segment overlapped. Lower numbered memory segments have higher priority. Example: Segment0 Segment Segment Default Segment. Here, `Segment Segment signifies that priority Segment higher than that Segment
SegDefCfg: Default Segment Configuration Register
Offset 0x60 Register SegDefCfg Size Position Reset Value 0x3C Reserved
Upon reset, default segment used. Default Segment Configuration Register same format Segment Configuration Register, except that applies unmapped space SDRAM. Unmapped SDRAM access attempts generate abort. (See Memory Protection Unit.)
Chip Enables
Each segment that defines external memory device associated with unique external chip enable pin. Addresses that fall within range that segment will cause corresponding chip enable activated. Therefore, address-ranges properties these segments must programmed consistently between Memory Protection Unit, segment registers associated with External Interface SDRAM controllers. Data Sheet Page
LH79531 Universal Microcontroller
Cache Local SRAM
combined instruction data cache configured cache, cache SRAM, SRAM. When configured cache mode, cache 4-way set-associative. cache designed supply with data higher average bandwidth shorter latency than main memory, while greatly reducing traffic load main, LCD, external busses. cache write-coherency policy configured either write-back (also known copy-back) write-through. Whenever cache fills, cache controller must evict line (four words). uses modified, least-recently-used (LRU) algorithm select victim line. write-through mode, data from write-hits written into cache write buffer, forwarded external memory.
Cache Configurations
bytes on-chip data SRAM shared between cache local SRAM. Three possible operating modes give system designer high degree flexibility. three modes shown Table Table Mode Cache Mode SRAM Mode Split Mode Memory Combinations Cache SRAM
Write Buffer
write buffer provided improve system performance. buffer eight words data, four independent addresses. write buffer enabled disabled (bit register named CacheControlReg buffer disabled reset. write write buffer, both CacheControlReg, appropriate SegCfg register protection unit must set. WRBUF Bridge Control Register also must when Controller using main access. "ASBBridgeCtrl: Bridge Control Register" RPC.
Bufferable Write
write buffer enabled processor performs write bufferable area, data placed write buffer BClk speeds continues execution. write buffer then performs external write parallel. however, write buffer full (either because there already eight words data buffer, because there slot address), processor stalled until there sufficient space buffer.
Reset
This initiated hardware power-on reset. cache invalidated(emptied). control register bits initialized `0'.
Invalidate
This operation marks cache empty, automatically clearing valid bits cache tags simultaneously. After Invalidate operation completed, Invalidate automatically cleared. Invalidate triggered writing invalidate-mode CacheControlReg, which clears itself next cycle without changing rest register.
Flush
Flush causes every valid, modified (dirty-tagged) cache entry automatically written external memory. This occurs line-by-line bursts where possible, beginning with first modified word each line. purpose bring external memory date with modified values still stored cache. After Flush been accomplished, Flush automatically cleared. Data Sheet Page
LH79531 Universal Microcontroller
When write-back mode, user should flush-invalidate cache before changing cache configuration, usage policy, cache-ability parameters. Flush self-timed multi-cycle operation that cause large block sequential writes external memory, holding until completion. flush sequence triggered writing flush-mode CacheControlReg; which clears itself. This operation only pertinent when cache been write-back mode. NOTE: Disable cache (i.e. `0') don't change SRAM Mode (SM) before enabling Flush.
Abort
Buffered write aborts cause unrecoverable errors. abort handler handles others.
Local SRAM
bytes on-chip data SRAM shared between cache local SRAM. fast wait state) local scratchpad-memory made available. size either organized according bits CacheControlReg. data contents Local SRAM undefined after reset. This memory uses cache data-memory array, total amount Cache Local SRAM exactly partitioned either cache, Local SRAM, cache Local SRAM according bits CacheControlReg. user must change Local SRAM configuration while live data resides while live data resides region external memory where Local SRAM will overlaid. SRAMTag register contains start address Local SRAM area. system/user privileges local SRAM under control Segment Configuration Register associated with address range local SRAM, default segment configuration register SegxCfg associated with local SRAM address.
Register Summary
Table Address 0xFFFFAC84 0xFFFFAC88 0xFFFFA000 0xFFFFC400 Register SRAMTag SRAMWait MAINASBCTRL LCDASBCTRL Local SRAM Configuration Registers Size Reset Value 0xFFFE0000 0x00000000 0x00000000 Name Local SRAM Start Address Register Local SRAM Wait Register Main Local SRAM Start Address Register Main Local SRAM Start Address Register
Table Address 0xFFFFAC80 Register CacheControlReg
Cache Contorol Register Size Reset Value
Name Cache Control Register
NOTE: Upon reset, CacheControl register initialized 0x00000011 (bigend 0x00000111 (bigend depending input bigend. This gives cache controller following properties: lock External endian mode upon reset. Write buffer disabled Cache disabled Local SRAM enabled Flush disabled Invalidate disabled SRAM Mode (SRAM Data Sheet Page
LH79531 Universal Microcontroller
Register Descriptions
SRAMTag: Local SRAM Start Address Register
Address 0xFFFFAC84 Register Size Position Reset Value 0xFFFE0000 START Reserved
SRAMTag
location on-chip SRAM within 32-bit address range defined SRAMTag register. Split mode, SRAMTag register defines start address (low address) local SRAM. SRAM mode, SRAMTag register defines start address (low address) local SRAM. Cache mode SRAMTag register ignored. NOTE: Mapping system register region prohibited. safe operation SRAMTag register should SRAM appropriate portion memory space before either Split mode SRAM mode enabled.
SRAMWait: Local SRAM Wait Register Main
Address 0xFFFFAC88 Position Size Reset Value 1098765432109876543210987654321 SRAMWait Reserved Wait Register
wait count on-chip SRAM access from Main defined SRAMWait register. Table SRAMWait Description Description SRAM Wait Control SRAM wait SRAM wait
Name Wait
MAINASBCTRL: Local SRAM Start Address Register Main
Address 0xFFFFA000 Position Size Reset Value 1098765432109876543210987654321 MAINASBCTRL 0x00000000 START Reserved Register
location on-chip SRAM within 32-bit address range Main defined MAINASBCTRL register. NOTE: Mapping system register region prohibited. Table 31:12 11:2 Name START MAINASBCTRL Description Description Local SRAM Start Address Main Reserved SRAM Mode SRAM used SRAM mode SRAM mode Page
LH79531 Universal Microcontroller
LCDASBCTRL: Local SRAM Start Address Register
Address 0xFFFFC400 Register Position Size Reset Value 1098765432109876543210987654321 0x00000000 START Reserved
LCDASBCTRL
location on-chip SRAM within 32-bit address range defined LCDASBCTRL register. NOTE: Mapping system register region prohibited. Table 31:12 11:2 Name START LCDASBCTRL Description Description Local SRAM Start Address Reserved SRAM Mode SRAM used SRAM mode SRAM mode
CacheControlReg: Cache Control Register
Address Register Size Position Reset 3322222222221111111111 Value 1098765432109876543210 Reserved
3210
0xFFFFAC80 CacheControlReg
NOTE: Upon reset, CacheControl register initialized 0x00000011 (bigend 0x00000111 (bigend depending input bigend. Table Name 31:11 10:9
CacheControlReg Description
Description Reserved. Lock signal control bits lock Locked during Line fetch Locked during Write back Locked during Line fetch Write back endian Little endian endian Write buffer enable Write buffer disable Write buffer enable Cache mode Write back mode Write through mode Cache enable Cache disable Cache enable Local SRAM enable Local SRAM disable Local SRAM enable Page
LH79531 Universal Microcontroller Flush mode Flush disable Flush enable Invalidate mode Invalidate disable Invalidate enable SRAM Mode SRAM used SRAM mode Cache mode Split mode
NOTES:
Lock prevents other masters from interrupting associated operations, thereby maintaining pipeline operation that process. should changed. When writing this register, care should taken match existing value bigend state. LH79531 have restriction ARM7TDMI debug interface. hardware breakpoint using ICEBreaker cachable region cache enabled state, possible break. avoid this, software breakpoint.
Example: Sequence Flush Step1: Disable Cache (CE=0, F=0, SM=10) Step2: Enable Flush (CE=0, F=1, SM=10) Step3: Check (F=0 (Read)) Step4: Change (set SRAM-mode) (CE=0, F=0, SM=01) sequence Invalidate same sequence Flush.
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LH79531 Universal Microcontroller
External Interface (EBI)
External Interface (EBI) supports standard SRAM, ROM, Flash, memory-mapped peripherals bi-directional data bus.
Features
Flexible programmable memory interface Supports SRAM, Normal Page Mode Flash 26-bit External Address 16-bit External Data x16) nWE0, nWE1 support Byte/Halfword Writes Reads Eight Banks (64MB) selected through dedicated Chip Enables (nCE7:nCE0) Programmable Address Setup time Programmable Setup Hold times Programmable memory cycle turnaround times (Inserts internal Wait states Idle states) Selectable boot-up from Static Memory Endian Control Supports external WAIT requests Programmable power-down state data (Three-state Output)
Page Mode Support
External Interface supports word page memory devices. first cycle access non-sequential (N-cycle) timing. Subsequent sequential accesses have sequential (S-cycle) timing until page boundary reached, which time N-cycle timing resumed. This page mode function only affects Read cycle.
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LH79531 Universal Microcontroller
LH79531 External Main
Segment Register
External-Bus Timing External ROM, SRAM, Devices
External Interface Controller
Figure External Interface Block Diagram
RA[21:1] RA[25:0] A[20:0] From External Interface D[15:0] RD[15:0]
RA[21:1]
RA[21:1]
RA[20:0]
A[20:0] SRAM (LSB)
A[20:0] SRAM (MSB)
A[20:0]
D[7:0]
D[7:0]
D[7:0]
Figure Example External Connections
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LH79531 Universal Microcontroller
External Interface Memory Registers
user must define these segments consistently decoders. Memory Protection Unit SDRAM Memory sections descriptions additional registers. External Interface segment registers must programmed with start size values that define identical areas segments defined Memory Protection Unit. Note that start values size values must consistent. (The External Interface does support segment sizes.)
Register Summary
Table Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C Register RAM_SEG_REG0 RAM_SEG_REG1 RAM_SEG_REG2 RAM_SEG_REG3 RAM_SEG_REG4 RAM_SEG_REG5 RAM_SEG_REG6 RAM_SEG_REG7 Segment Registers (Base address: 0xFFFFA400) Position START START START START START START START START
Size Reset Value 0x8000000D 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000
SIZE SIZE SIZE SIZE SIZE SIZE SIZE SIZE
Table Offset Register Size
Control Registers (Base Address: 0xFFFFA400) Reset Value
Position 0x20 RAM_CTL_REG0 IDLE 0x24 RAM_CTL_REG1 0x000000 IDLE 0x28 RAM_CTL_REG2 0x000000 IDLE 0x2C RAM_CTL_REG3 0x000000 IDLE 0x30 RAM_CTL_REG4 0x000000 IDLE 0x34 RAM_CTL_REG5 0x000000 IDLE 0x38 RAM_CTL_REG6 0x000000 IDLE 0x3C RAM_CTL_REG7 0x000000 IDLE 0x40 EXTBIFCtrl 0x000000 NOTE: S-bit (bit 10): Reset value RAM_CTL_REG0 same value BOOT signal. RAM_CTL_REG0 initialized 0x000000(BOOT=0) 0x000400(BOOT=1). N-speed S-Speed, then Page Mode disabled.
N-speed N-speed N-speed N-speed N-speed N-speed N-speed N-speed S-speed S-speed S-speed S-speed S-speed S-speed S-speed S-speed
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LH79531 Universal Microcontroller
Register Descriptions
RAM_SEG_REGx Registers Segment Register
Position Reset Value 0x00 RAM_SEG_REG0 0x8000000D START SIZE 0x04 0x1C RAM_SEG_REGn (n=1 0x00000000 START SIZE Offset Register RAM_SEG_REG registers store desired START Address SIZE each segment. Together, these define valid range addresses each eight segments. Each segment controls external nCEx chip select signals. When address falls within segment's valid START SIZE range, that segment's corresponding nCEx asserted uniquely. Therefore, RAM_SEG_REG0 controls nCE0, Table START SIZE RAM_SEG_REGx Description Description Reserved. Segment Enable Segment disabled Segment enabled START address each segment SIZE each segment
SIZE represents segment size (valid address range), which must between user choose from among following sizes: SIZE [3:0] Segment Size 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 NOTE: user sets reserved value, treated setting. START indicates starting boundary each segment memory map. valid START each RAM_SEG_REGx[29:13]** compared bits BA[29:13]** main internal address bus. LH79531 will assert external chip select corresponding lowest segment number whose allocated START+SIZE address range contains current address. This mechanism used select appropriate external memory peripheral, since only lower bits bits address vector available external pins RA[25:0]. NOTE: granularity segment boundary (the number address bits that used determine which segment being addressed) depends segment size.
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LH79531 Universal Microcontroller
bits stored START address value used. Reserved bits must `0'. example, SIZE (segment granularity) programmed 64MB, then this segment, only bits used segment-selection. this case START bits should programmed `0'. SIZE another segment then START address bits valid segment selection. Valid address bits shown Table Table Valid Address Bits Segment Size Valid START Bits Reserved START Bits [29:13] reserved bits [29:14] [13] reserved [29:15] [14:13] reserved [29:16] [15:13] reserved [29:17] [16:13] reserved [29:18] [17:13] reserved [29:19] [18:13] reserved [29:20] [19:13] reserved [29:21] [20:13] reserved [29:22] [21:13] reserved [29:23] [22:13] reserved [29:24] [23:13] reserved [29:25] [24:13] reserved [29:26] [25:13] reserved more address regions programmed have overlapping areas, lowest numbered segment will take precedence. Thus, segment-0 will always selected when segment START addresses `0'. When address outside areas specified segment registers, responds with error. Examples: Segment2 Start address 0x11000000 Size Segment3 Start address 0x10000000 Size When access address 0x10000000, Chip select asserted. When access address 0x11000000, Chip select asserted. When access address 0x12000000, Chip select asserted. Reserved bits must written `0'. These will read undefined.
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LH79531 Universal Microcontroller
RAM_CTL_REGx Registers Control Register
Offset 0x20 Register Reset Value Position 3322222222221 1098765432109 2109876543210 IDLE N-speed S-speed
RAM_CTL_REG0 RAM_CTL_REGn 0x24 0x3C 0x000000 IDLE N-speed S-speed (n=1 NOTE: RAM_CTL_REG0 initialized 0x000000(BOOT=0) 0x000400(BOOT=1).
RAM_CTL_REGx registers used define operation each segment. They provide wait count, page mode support, setup hold control. Each RAM_CTL_REGx register number controls corresponding numbered segment's nCEx chip select. (E.g. RAM_CTL_REG0 register controls nCE0, on.) RAM_CTL_REGx Description Name Reset Value Description 0000: idle cycle after High 0001: idle cycle after High 22:19 IDLE Idle cycle 0000 0010: idle cycles after High 1111: idle cycles after High `0': active cycle after activate control `1': active same time `0': de-active cycle before High de-activate control `1': de-active same time High `0': active cycle after activate control `1': active same time `0': de-active cycle before High de-activate control `1': de-active same time High `0': active cycle after Address valid activate control `1': active same time Address valid `0': de-active cycle before Address invalid de-activate control `1': de-active same time Address invalid `0': sequential addresses page Page size control `1': sequential addresses page Reserved `0': data Memory data size control `1': data 00000: cycles memory access number clock cycles N-speed 00000 11101: cycles memory access non-sequential access 11110: cycles memory access 11111: Reserved 00000: cycles memory access number clock cycles S-speed 00000 11101: cycles memory access sequential access 11110: cycles memory access 11111: cycle memory access NOTES: RAM_CTL_REG0 only, initial value after reset depends upon level Boot pin. (Boot `1'; Boot `0') proper operation non-page mode memory devices, N-speed S-speed must same value. page mode memory devices, value S-speed must less than N-speed. values must compatible with number clock cycles memory access. When write cycle starts with non-sequential address, always activates cycle after nCE. Reserved. reserved bits must written zero. These will read undefined. Table Function
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LH79531 Universal Microcontroller
EXTBIFCtrl: External Interface Control Register
Offset Position Reset Value 0x40 EXTBIFCtrl Reserved Register
EXTBIFCtrl register sets mode external data-bus drivers. (Also "ASBBridgeCtrl: Bridge Control Register" RPC) Table Name Function EXTBIFCtrl Description
Description Data remains 'Output' mode when 'HIGH' Data Control Data enters 'High-Z' mode when 'HIGH' NOTES: Reserved bits must written zero. These will read undefined.
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LH79531 Universal Microcontroller
Synchronous Dynamic Controller (SDRAMC)
Features
external address (256 SDRAM support) Programmable address multiplexing external data access Little Endian block, banks block (A13 used bank select signal) Compatible with SDRAMs Programmable timing latency, Refresh rate, tRC, tRAS, tRP, tRCD, tXSR Full page burst access Page Mode accesses with open pages Supports Self refresh Auto refresh Programmable Refresh Rate
SLAVE INTERFACE
CONTROL STATUS REGISTERS
MAIN CONTROL
AUTO REFRESH CONTROL INITIALIZE CONTROL SELF REFRESH CONTROL POWER SAVE CONTROL
SLAVE INTERFACE
SDRAM ACCESS CONTROL
SDRAM TIMING CONTROL
SDRAM CONTROL ADDRESS DATA
Figure SDRAM Control Block Diagram
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LH79531 Universal Microcontroller
Register Summary
SDRAMC Registers (Base address: 0xFFFFC000) Position Offset Register Size Reset Value 109876543210987 543210 0x00 SDRAM_SEG0_REG 0x000000C0 Start_Addr Size 0x04 SDRAM_SDR0_REG 0x003 0x08 SDRAM_SEG1_REG 0x000000C0 Start_Addr Size 0x0C SDRAM_SDR1_REG 0x003 0x10 SDRAM_CNTROL 0x00 0x14 SDRAM_STATUS 0x18 SDRAM_TIMING0 0x000 0x1C SDRAM_TIMING1 0x0000000 tRCD tRAS 0x20 SDRAM_TIMING2 0x00000 tXSR Table
Register Descriptions
SDRAM_SEGx_REG SDRAM Segment Register
Offset 0x00 0x08 Size Reset Value SDRAM_SEG0_REG 0x000000C0 SDRAM_SEG1_REG 0x000000C0 Register Position 3222222222211111111 0987654321098765432 Start_Addr Start_Addr 09876543210 Size Size
[31]: Segment Enable segment enable defines whether access into segment SDRAM allowed. Description Access SDRAM Segment Disabled Access SDRAM Segment Enabled
When this (disable), access this segment will produce error there valid overlapping segment memory. address specified outside areas delineated SDRAM segment register would also cause SDRAM controller respond with error. Start_Addr [29:13]: Start Address This used conjunction with Size field describe logical address ranges into which physical SDRAM devices mapped. Internal addresses within either these ranges will cause SDRAM-x corresponding segment-x selected. boundaries segment-x are: Lower boundary: [Start_Addr] Upper boundary: [Start_Addr Segment Size (decimal, inclusive)]
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LH79531 Universal Microcontroller
Where Start_Addr[29:13]= internal_addr[29:13]. Since segments have minimum size granularity least order bits internal address affect segment selection. Size [3:0]: Segment Size Each segment's size (memory address range) programmed from using Size [3:0] shown Table Table Size [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Segment Size Segment Size
Segment Selection Mechanism bits Start_Addr field (SDRAM_SEGx_REG[29:13]) significant determining segment boundary. granularity segment boundary finer than segment's Size. Table used determine which Start_Addr bits significant. Invalid bits must programmed `0'. Table Valid Start_Addr Segment Size Valid Start_Addr [29:13] [29:14] [29:15] [29:16] [29:17] [29:18] [29:19] [29:20] [29:21] [29:22] [29:23] [29:24] [29:25] [29:26] [29:27] [29:28]
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LH79531 Universal Microcontroller SDRAM_SEG0_REG programmed 0xBE40000D: Start_Addr bits) Size 1110 0100 0000 0000 0000 1101 Size: 1101 (See SDRAM_SEGxREG[3:0] Size[3:0].) Start_Addr: 1110 0100 0000 1100 0000 0x3c000000 indicated table above segment size/granularity 64MB, only four most significant bits Start_Addr (Bits [29:26] SDRAM_SEG0_REG) will used compare logic determine internal address programmed range not. this case, offset range segment 0x3C000000 0x3FFFFFFF. 0x7C000000 0x7FFFFFFF Region1 Memory Map.)
Example1:
Example2:
SDRAM_SEG0_REG programmed 0xBE40000F: Start Address bits) Size 1110 0100 0000 0000 0000 1111 Size: 1111 (See SDRAM_SEGxREG[3:0] Size[3:0].) Start_Addr: 1110 0100 0000 0000 0000 0000 0x30000000 Only most significant bits Start_Addr (Bits [29:28] SDRAM_SEG0_REG) will used compare logic determine internal address programmed range not. this case, offset range segment 0x30000000 0x3FFFFFFF. 0x70000000 0x7FFFFFFF Region1 Memory Map.)
Overlapping Segments SDRAM segments have overlapping areas, then Chip Select associated with lower numbered segment activated (Segment0 higher priority than Segment1). Example: Segment0 Starting address 0x51000000 Size Segment0 range [0x51000000-0x51FFFFFF] Segment1 Starting address 0x50000000 Size Segment1 range [0x50000000-0x53FFFFFF] When internal address 0x50000000, nDCS1 asserted because address belongs only Segment1. When internal address 0x51000000, nDCS0 asserted because address belongs both segments, lower segment (Segment0) chip select activated. When physical address 0x52000000, nDCS1 asserted because address belongs only Segment1. 0x53FFFFFF 0x52000000 0x51000000 0x50000000 Figure Overlapping Segments Segment0 Segment1
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LH79531 Universal Microcontroller
SDRAM_SDRx_REG SDRAM Segment Descriptor Register
Offset Register Size Position Reset Value 0x003 0x003
0x04 0x0C
SDRAM_SDR0_REG SDRAM_SDR1_REG
[9:8]: Column Address Width Specifies Column Address Width [5:4]: Address Width Specifies Address Width [1]: Bank Width Specifies Number Banks [0]: External Width Specifies External Width External Width Number Banks banks banks Address Width Reserved COLUMN Address Width
NOTE: When mode, keep following conditions; Bridge's write buffer shoud enable, LCDC frame buffer shoud placed SDRAM. Refer "ASBBridgeCtrl: Bridge Control Register" RPC. Cashe should writeback mode, SDRAM area shuld cacheable.
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LH79531 Universal Microcontroller
SDRAM_CNTROL: SDRAM Control Register
Offset Register Size Position Reset Value 0x00
0x10
SDRAM_CNTROL
[4]: Data Mode Control SDRAM Data remains 'Output' mode during 'HIGH' this `0'. SDRAM Data enters 'High-Z' modes during 'HIGH' this `1'. This function prevents long time `High-Z' during LH79531 power save mode (ex. Sleep Stop mode etc.). Data Mode Output Hi-Z
[3]: Page Mode Enable This enables Page mode access. Refer Page Management section description this mode. Page Mode Disable Enable
[2]: Power Save Mode Enable This causes SDRAM enter exit Power Save mode. Refer Power Save mode section description this mode. Power Save Mode Disable Enable
[1]: Self Refresh Enable This causes SDRAM enter exit Self-refresh mode. Refer Self Refresh mode section description this mode. Self Refresh Mode Disable Enable
[0]: SDRAM Controller Enable SDRAM Controller initially disabled system reset. appropriate configuration timing parameters must programmed into SDRAM_SEG_REG, SDRAM_SDR_REG, SDRAM_TIMING registers before enabling SDRAM Controller. Also, various SDRAM specs require wait interval after power before beginning their initialization. After waiting specified time, SDRAM Controller then enabled writing SDRAM_CNTROL register. This allows SDRAM Controller begin automatic setup command sequence, which initializes SDRAM. SDRAM Controller disabled writing bit. This will initiate orderly shutdown sequence. SDRAM Controller should re-enabled again until after waiting SDRAM_STATUS register become zeros.
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LH79531 Universal Microcontroller
SDRAM_STATUS: SDRAM Status Register
Offset Register Size Position Reset Value
0x14
SDRAM_STATUS
[2]: Power Save Mode Status Whenever SDRAM controller sensed sufficiently long period inactivity automatically entered power save state, this goes `1'. power save state, SDRAM temporarily self-refresh mode. soon SDRAM access requested, SDRAM controller automatically exits power save state, re-activates SDRAM, this goes `0'. Please refer refresh mode section more details. Power Save Mode Status Inactive Active
[1]: Self Refresh Mode Status While SDRAM self-refresh mode, this `1'. system cannot access SDRAM while self-refresh mode. Self-Refresh Mode Status Inactive Active
[0]: SDRAM Controller Status While SDRAM Controller active, this `1'. system only access SDRAM SDRAM Controller active Self-refresh mode (see bit). SDRAM Controller Status Inactive Active
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LH79531 Universal Microcontroller
SDRAM_TIMING0: SDRAM Timing0 Register
Offset 0x18 Register SDRAM_TIMING0 Size Position Reset Value 0x000
[9:8]: Refresh Clock Cycle Factor This specifies clock rate, which drives auto refresh counter. Refresh Clock Cycle System clock cycle System clock cycle System clock cycle System clock cycle
[6:0]: Refresh Interval Factor This specifies auto refresh counter value. Refresh cycle timing specified using RCC. 0000000 0000001 1111111 Refresh cycle settings calculated follows: Refresh cycle (Refresh counter value) (Refresh clock cycle) range counter value range 128, refresh clock cycle range times. refresh cycle programmed from 4096 system clock ticks. Example: typical SDRAM require 4096 refreshes refresh cycle takes: 4096 times) 15,625 system clock frequency period),then refresh cycle required intervals less than system clock ticks: 15,625 max. 781.25 max. Since largest available count 128, minimum required cycles times Start choosing nearest value greater than 6.1: (0b01) times. This requires that (781 cycles max. 97.7 max. choose nearest value less than 97.7 (0b1100001) This produces refresh cycle length clock ticks refresh cycle. This product effectively satisfies SDRAM refresh cycle requirement less than equal clock ticks. Counter Value
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LH79531 Universal Microcontroller
SDRAM_TIMING1: SDRAM Timing1 Register
Offset Register Size Position 0x0000000 tRCD tRAS Reset Value
0x1C SDRAM_TIMING1
Register SDRAM_Timing1 designates timing parameters specific SDRAM controlled SDRAM Controller. These timing parameters specified appropriate SDRAM data sheet. value converted from physical value (usually nano-seconds) integral number System clock cycles. [27:24]: SDRAM Ref/Act-to-Act/Ref time specifies SDRAM `Refresh/Active' `Active/Refresh' command period (RAS-cycle time). 0000 0001 1111 Number Clock Cycles cycle cycles cycles
tRCD [17:16]: SDRAM Act-to-R/W time tRCD specifies SDRAM `Active R/W' command delay time (RAS-to-CAS Delay). tRCD Number Clock Cycles cycle cycles cycles cycles
tRAS [10:8]: SDRAM Act-to-Pre time tRAS specifies SDRAM `Active Precharge' command period (RAS-active time). tRAS Number Clock Cycles cycle cycles cycles
tRP[1:0]: SDRAM Pre-to-Act time specifies SDRAM `Precharge Active' command period (RAS-recovery precharge time). Number Clock Cycles cycle cycles cycles cycles
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LH79531 Universal Microcontroller
SDRAM_TIMING2: SDRAM Timing2 Register
Offset 0x20 Register Size Position 332222222222111 111111 109876543210987 543210 7654321 0x00000 tXSR Reset Value
SDRAM_TIMING2
Register SDRAM_Timing2 designates additional timing parameters specific SDRAM controlled SDRAM Controller. These timing parameters specified vendor's SDRAM data sheet. value converted from physical value (usually nanoseconds) integral number System clock cycles. [16]: SDRAM Write Recovery time specifies SDRAM write recovery time. [9:8]: SDRAM Latency specifies SDRAM Latency. Number Clock Cycles cycle cycles cycles cycles Number Clock Cycles cycle cycles
tXSR [3:0]: SDRAM Self-Refresh Act-to-Exit time tXSR specifies SDRAM `Active Exit' command time exit self-refresh period. tXSR 0000 0001 1111 Number Clock Cycles cycle cycles cycles
ASBBridgeCtrl: Bridge Control Register
This register used control SDRAM Write buffer. Refer "ASBBridgeCtrl: Bridge Control Register" details this register.
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LH79531 Universal Microcontroller
Address Mapping
Table Table show supported configurations SDRAM relationship between external SDRAM multiplexed address internal address bus. Table Total Size 16MB 32MB 64MB 128MB 64MB 128MB 256MB Chip Size 128M 128M 128M 256M 256M 256M Address Multiplexing External Data Mode) Addr-MUX Bits [7:0] 18:11 17:10 17:10 17:10 18:11 19:12 20:13 18:11 19:12 20:13
Configuration Words Bits Banks Chips 0.5M 0.5M
Table Total Size Chip Size 16MB 32MB 64MB 32MB 64MB 128MB 128M 128M 128M 256M 256M 256M
Address Multiplexing External Data Mode) [7:1] 17:11 16:10 16:10 17:11 18:12 19:13 17:11 18:12 19:13
Configuration Addr-MUX Bits Words Bits Banks Chips 0.5M
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LH79531 Universal Microcontroller
NOTES:
refer external pins named SDRA[0] SDRA[13]. refers multiplexed function named SDRA[14]. Figures table refer Main address locations. Shaded entries `bank select'. `Col' addresses) refers optional bank select. Null entries `don't care', stable. generated SDRAM Controller when word (32-bit) access. Otherwise Main address `1'.
High Address High Address
Bank Bank
Bank Bank Address
Bank Bank
Address
Banks
Four Banks
NOTE: Each bank SDRAM located contiguously memory map. each bank, pages located contiguously. Figure Memory
Page Management
When Page mode disabled, each transfer always starts with ACTIVE command, then READ WRITE command issued SDRAM. When PAGE mode enabled, transfer accesses same address (same page) that previous transfer accessed, then this transfer accesses SDRAM without PRECH ACTIVE commands. data accessed contiguous local area, overhead SDRAM access minimized. SDRAM transfer accesses different address (different page) than previous transfer, then this transfer needs PRECH ACTIVE commands before READ WRITE command executed. Page Mode disabled: ACTIVE READ WRITE PRECH Page Mode enabled, on-page access: READ WRITE Page Mode enabled, off-page access: PRECH ACTIVE READ WRITE following address bits determine whether access on-page off-page: COLUMN Addr Width 32bit A24-A10 A25-A11 A26-A12 A27-A13 16bit A23-A9 A24-A10 A25-A11 A26-A12
Page Open mode, Refresh operation closes open pages.
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LH79531 Universal Microcontroller
SDRAM Controller Operations
Write Mode Register
soon SDRAM Controller enabled, automatically performs required SDRAM initialization sequence. This transfers following values into SDRAM's mode registers: Access Action 00000 (set mode register) latency Value LTMODE (sequential) (full page) Mode
Auto Refresh Mode
this mode SDRAM Controller inserts auto-refresh cycles into SDRAM transaction stream periodically, intervals specified SDRAM_TIMING0 register. avoid interrupting burst sequential SDRAM accesses, these refresh requests stored queue issued whenever spare (non-sequential) SDRAM cycle becomes available. maximum depth this refresh request queue seven. prevent overflowing this queue dropping refresh cycles, maximum sequential-burst length must exceed (auto refresh cycle).
Self Refresh Mode (Power Down Mode)
When SDRAM_CNTROL register `1', SDRAM Controller goes into self-refresh mode. this mode, controller instructs SDRAMs enter Self-Refresh state, then stops SDRAM clock. Once this state, necessary supply SDRAMs with signals except (Chip/Clock Enable). SDRAMs continue retain their memory contents with minimal power consumption. However, SDRAMs cannot accessed while they Self-Refresh state. exit Self-Refresh Mode, should written into SDRAM_CNTROL register. controller will then instruct SDRAMs exit their Self-Refresh state into Idle state, from which they begin accept access requests. controller will indicate status register when this completed. However, SDRAM access attempted while SDRAM Self-Refresh state, SDRAM controller will respond with error. NOTE: While SDRAM Controller self-refresh mode, access SDRAMs prohibited. this situation, access SDRAMs cause System freeze state.
Power Save Mode
Power Save Mode enabled when SDRAM_CNTROL register `1'. this mode, there have been SDRAM accesses during past more auto-refresh cycles, SDRAM Controller puts SDRAM into Self-Refresh state (low power `sleeping' state). controller will automatically wake SDRAM from Self-Refresh state into Active state when next SDRAM access attempted. controller's status register will reflect these events. Writing into SDRAM_CNTROL register will wake SDRAM Self-Refresh state into IDLE state.
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LH79531 Universal Microcontroller
Initialization Sequence
SDRAM Controller SDRAM must initialized before SDRAM accessed. SDRAM access attempted before during Initialization Sequence, SDRAM controller will respond with error. initialization should accomplished performing following steps: After powering SDRAMs, wait startup time specified SDRAM spec. SDRAM_SEGx_REG, SDRAM_SDRx_REG, SDRAM_CNTROL SDRAM_TIMING registers. This done during step SDRAM _CNTROL register `1'. This causes SDRAM Controller perform following operations automatically: Precharge banks Wait eight cycles Write mode register Perform eight refresh cycles When last initialization step completed, SDRAM Controller will change status SDRAM_STATUS register from `1'.
External Data Width Internal Access Size Conversions
SDRAM Controller supports External Data widths. converts these from (Byte), (Half word), (Word) internal transactions needed. Four data mask outputs [3:0] indicate SDRAMs which byte(s) outgoing data word active.
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LH79531 Universal Microcontroller
Controller (DMAC)
Overview
controller (DMAC) LH79531 handles data transfers between memory peripherals; from memory memory, without intervention ARM7TDMICore. This controller provides independent channels (Channel Channel that operate autonomously (subject priority conflict resolution). transfer consists multiple cycles. Each cycle either single cycle burst cycle. single cycle consists read cycle followed write cycle. burst Cycle consists four read cycles followed four write cycles. transfers hardware software triggered. transfer software triggered writing value appropriate DMACModeCtrlReg, which disables hardware triggers sets software trigger bit. transfer hardware triggered when hardware triggers enabled appropriate DMACModeCtrlReg peripheral that enabled appropriate field DMACRequestSource requests transfer. Each cycle buffered; data read from source stored internally before being written destination. DMACCounterReg registers control number items transferred. size each item bits controlled DMACModeCtrlReg. item size must same source destination. Transfers between external devices memory; between internal devices memory; between internal external memory device. source address DMACSrcAddrReg registers destination address DMACDstAddrReg registers each either fixed increment with each cycle. Status current transfer stored DMACStatusReg. This status reflects whether request been made, transfer progress, error occurred. DMAC configured DMACControlReg enable interrupt suspend transfers generate interrupts upon completion transfer (`end transfer interrupt') controller reports error during cycle (`transfer error interrupt'). Regardless whether transfer interrupt masked will assert appropriate DMACStatusReg: bit, bit, then stop current transaction. source destination address registers placed double buffer mode support hardware requests re-triggering. event conflict shared resources between channels, channel higher priority. channel cycle suspended this manner, will continue when channel cycle terminates. Setting ARBPR Arbitration register decide priority between channel Default setting priority than channel more details, information about other control registers, `Register Descriptions' this section.
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LH79531 Universal Microcontroller
Register Summary
Table Offset Register DMAC Registers (Base Address: 0xFFFF0800) Reset Size Description Value Controls triggers, transfer mode, width type, lock release channel Controls whether source address channel increments frozen. Controls whether destination address channel increments frozen. Reflects status transfers channel Current source address channel (See also buffering modes under DMACControlReg) Current destination address channel (See also buffering modes under DMACControlReg) number items that remain moved transfer currently ongoing Channel (See also buffering modes under DMACControlReg) Controls triggers, transfer mode, width type, lock release channel Controls whether source address channel increments frozen. Controls whether destination address channel increments frozen. Reflects status transfers channel Current source address channel (See also buffering modes under DMACControlReg) Current destination address channel (See also buffering modes under DMACControlReg) number items that remain moved transfer currently ongoing Channel (See also buffering modes under DMACControlReg) Controls interrupt buffer modes flags both channels Enables controls polarity hardware DREQ signals. Enables individual interrupt sources suspend active transfer channel Enables individual interrupt sources suspend active transfer channel DACK select control each peripheral
0x00 DMACModeCtrlRegCh0 0x04 DMACSrcCtrlRegCh0 0x08 DMACDstCtrlRegCh0 0x0C DMACStatusRegCh0 0x10 DMACSrcAddrRegCh0 0x14 DMACDstAddrRegCh0 0x18 DMACCounterRegCh0
0x20 DMACModeCtrlRegCh1 0x24 DMACSrcCtrlRegCh1 0x28 DMACDstCtrlRegCh1 0x2C DMACStatusRegCh1 0x30 DMACSrcAddrRegCh1 0x34 DMACDstAddrRegCh1 0x38 DMACCounterRegCh1 0x40 DMACControlReg 0x80 DMACRequestSource 0x84 DMACIntSourceCh0 0x88 DMACIntSourceCh1 0x8C DMACAckSelect
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LH79531 Universal Microcontroller
Register Descriptions
DMACModeCtrlRegChx DMAC Mode Control Register
Offset 0x00 0x20 Register Size DMACModeCtrlRegCh0 DMACModeCtrlRegCh1 Reset Value 0x000 0x000 Reserved Reserved Position Brel TrType TrSize Lock Brel TrType TrSize Lock
Table Name
DMACModeCtrlRegChx Description Description
Brel
TrType
TrSize
Lock
Release Release Released When Brel `1', transfers will continue until transfer counter `0', without releasing bus. DMAC will only burst transfers this mode. This mode used only memory-to-memory transfers. Transfer Type: this used generate appropriate nDACK signal Memory (Generate Aligned with Read cycle) Memory (Generate Aligned with Write cycle) Memory Memory (does Generate nDACK) Reserved Transfer Size Byte Half Word Word Reserved Lock (links read write phases indivisibly) Unlock Lock Single/Burst Transfer Single: item data transferred cycle Burst: four items data transferred cycle. Hardware Trigger Disable Enable Note: automatically ignored. Software Trigger Disable Enable
NOTES:
When transfers External Memory whose IDLE cycle none-zero value External Interface, Brel must
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LH79531 Universal Microcontroller
DMACSrc(Dst)CtrlRegChx DMAC Source(Destination) Address Control Register
Offset 0x04 0x08 0x24 0x28 Register DMACSrcCtrlRegCh0 DMACDstCtrlRegCh0 DMACSrcCtrlRegCh1 DMACDstCtrlRegCh1 Table Name Size Reset Value Position Reserved Reserved Reserved Reserved
DMACSrc(Dst)CtrlRegChx Description Description
Increment Freeze Increment: relevant address register increments value appropriate DMACModeCrtlReg: TrSize after each cycle. Freeze: relevant address register does increment after each transfer.
DMACStatusRegChx DMAC Status Register
Offset 0x0C 0x2C Register DMACStatusRegCh0 DMACStatsuRegCh1 Table Name Size Reset Value 0x000 0x000 Undefined Undefined Position
DMACStatusRegChx Description Description
Transfer Error Status Transfer-Error Occurred. only error that detected DMAC when controller reports error during cycle. Transfer Status Transfer Progress Transfer Ended Request Request Transfer been made completed. Request since last Transfer completed.
DMACSrc(Dst)AddrRegChx DMAC Source(Destination) Address Register
Offset 0x10 0x14 0x30 0x34 Register DMACSrcAddrRegCh0 DMACDstAddrRegCh0 DMACSrcAddrRegCh1 DMACDstAddrRegCh1 Table 31:0 31:0 Size Reset Value 0x00000000 0x00000000 0x00000000 0x00000000 Position SrcAddr DstAddr SrcAddr DstAddr
DMACSrc(Dst)AddrRegChx Description Name SrcAddr DstAddr Description Current source address Current destination address
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LH79531 Universal Microcontroller
DMACCounterRegChx DMAC Transfer Count Register
Offset 0x18 0x38 Register DMACCounterRegCh0 DMACCounterRegCh1 Size Reset Value 0x000000 0x000000 Position Reserved Transfer_Count Reserved Transfer_Cunnt
Table 23:0 Name Transfer_Count
DMACCounterRegChx Description
Description Transfer Count: number items that remain moved.
Specifies number items that remain moved Operation, where `item' specified appropriate DMACModeCtrlReg. count zero implies that more items transferred. Transfer counter decremented every write cycle. also `buffering modes' under DMACControlReg.
DMACControlReg: DMAC Control Register
Offset Position Reset Value 0x40 DMACControlReg 0x000 BIGE ERC1 ERC0 ENC1 ENC0 ERM1 ERM0 ENM1 ENM0 Register Size Table Name BIGE ERC1 ERC0 ENC1 ENC0 ERM1 ERM0 ENM1 ENM0 DMACControlReg Description
Description Little/Big Endian Little Endian Endian Double/Single Buffer Single Buffer Double Buffer (see Buffering Modes below) Double/Single Buffer Single Buffer Double Buffer (see Buffering Modes below) Clear flag Clear flag DMACStatusRegCh1 This automatically cleared once hardware cleared flag. Clear flag Clear flag DMACStatusRegCh0 This automatically cleared once hardware cleared flag. Clear flag Clear flag DMACStatusRegCh1 This automatically cleared once hardware cleared flag. Clear flag Clear flag DMACStatusRegCh0 This automatically cleared once hardware cleared flag. Transfer-Error Interrupt Mask CH1. Mask Transfer Error Interrupt Transfer-Error Interrupt Mask CH0. Mask Transfer Error Interrupt End-of-Transfer Interrupt Mask CH1. Mask Transfer Interrupt End-of-Transfer Interrupt Mask CH0. Mask Transfer Interrupt
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LH79531 Universal Microcontroller
Buffering Modes DMACSrcAddrReg, DMADstAddrReg, DMACCounterReg registers used single double-buffered register modes. These modes enabling re-trigger mechanism. When single-buffer mode, reading register results current value appropriate transfer which ongoing which just completed. Writing register while transfer ongoing will change nature transfer cause undesirable results. When double-buffer mode there internal copy each register each registers involved, preventing glitches errors. Reading registers while transfer ongoing will result values appropriate current transfer. Writing registers during transfer will have immediate effect; however value will stored internal copy register. transfer, registers will updated with values from internal copies. These values from internal copies registers will values used initiate next transfer unless these were over-written during that transfer.
DMACRequestSource: DMAC Request Source Register
Offset 0x80 Register DMACRequestSource Size Reset Value 0x000 Position CFGCH1 CFGCH0
Table Name
DMACRequestSource Description
CFGCHx
Description This controls DREQ signal polarity. Note that signals given channel will have same polarity. Active Active HIGH This enables hardware Request signals, (DREQ) only corresponding DMACModeCtrlReg: set. decoding specifically listed below reserved. 0000 Request from dmareq0 0001 Request from dmareq1 0010 UART0 Receive FIFO Interrupt 0011 UART0 Transmit FIFO Interrupt 0100 UART1 Receive FIFO Interrupt 0101 UART1 Transmit FIFO Interrupt 0110 UART2 Receive FIFO Interrupt 0111 UART2 Transmit FIFO Interrupt 1000 Receive FIFO Interrupt 1001 Transmit FIFO Interrupt 1010 Request from IrDA 1011 Request from
NOTE: When user uses external device which need DEOT signal, DMACRequestSource cannot following settings: CFGCH0 0001 CFGCH1 0000. When user uses DEOT0 DREQ0 nDACK0) signal, CFGCH0 must "0000" value (This means only this case, CFGCH0 "0001" setting cannot use). when user DEOT1 DREQ1 nDACK1) signal, CFGCH1 must "0001" value (This means only this case, CFGCH1 "0000" setting cannot use). transfer without DEOT, DREQ selected from (DREQ0, DREQ1), nDACK selected from (nDACK0, nDACK1) both channel channel
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LH79531 Universal Microcontroller
DMACIntSourceChx DMAC Interrupt Source Register
Offset 0x84 0x88 Register DMACIntSourceCh0 DMACIntSourceCh1 Size Reset Value 0x0000000 0x0000000 Position Reserved Reserved Interrupt_Mask Interrupt_Mask
Each interrupt mask enables corresponding interrupt source suspend transfer appropriate channel. When this happens, will cease transferring after finishing current write cycle. When interrupt source cleared, will resume transferring from next read access. Each independently. Table Name INT0 INT1 INT2 INT3 INT4 INT5 URT0 URT1 URT2 IrDA LCDC PWM0 PWM1 PWM2 PWM3 RTIR Interrupt_Mask
Description External Interrupt0 (INTR0) External Interrupt1 (INTR1) External Interrupt2 (INTR2) External Interrupt3 (INTR3) External Interrupt4 (INTR4) External Interrupt5 (INTR5) Counter/Timer0 Counter/Timer1 Counter/Timer2 UART UART UART IrDA LCDC Synchronous Serial Interface Reserved Reserved ALARM IRQF Reserved Lock Lost
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LH79531 Universal Microcontroller
DMACAckSelect: DMAC Acknowledge Select Register
Offset 0x8C Register DMACAckSelect Size Reset Value 0x00 Reserved Position IrDA nDACK1 nDACK0
Each field connects DMAC acknowledge signals corresponding peripheral external I/O. Pattern Description Connect nDACK Connect nDACK Connect `VDD' i.e. signal connected. Reserved
NOTE: DMAC samples DREQ signal External Request transfer when each falling edge CLKOUT, during IDLE state. each falling edge CLKOUT, during last transfer writing last data destination. Dreq signal must deassert before last transfer begins. (When nDACK signal deasserted, DREQ signal would deasserted. Please refer Figure
Signal Interfaces External Request transfer Aside from internal data interface, there logical signals channel: DEOT Signal which assert transfer (DMACCounterReg nDACK signal external memory access flow control, DREQ signals hardware trigger.
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LH79531 Universal Microcontroller
Real Time Clock (RTC)
Overview
real time clock with programmable timer calendar. clock input comes from either recommended internal 32.768 crystal oscillator external 32.768 clock source. features digital clock with alarm function well auto-calendar function. Other functions include: Input clock conversion real time clock. Settable timer, alarm calendar. Current time date output. Control operation modes using RCSR (RTC control status register). Backup Power Operation
32.768
Divider
1sec Pulse
Seconds Counter
Minutes Counter
Hours, Days, etc.
Figure Divider Block Diagram
Functional Description
8-bit registers store count real time second, minutes, hour, day, week, month, year century. auto-calendar function operates from January 1901 00:00:00 December 2099 23:59:59. important note that connected same power supply PLL, reset nRESETi.
Timer, Alarm Calendar Setting
Writing desired value each register sets clock, alarm calendar. alarm function, addition setting alarm time, alarm enable RCSR register order activate alarm. signal will activate minute when real time clock alarm setting time match.
Reading Current Time Date
timer register read time without affecting timer. hold mode hold counting clock while reading timer register. hold mode CHLD RCSR register. enters hold mode within will still capture incoming second pulse arrived during hold mode, releases this pulse after CHLD returns zero. Only pulse captured hold mode.
Operation Modes
operation modes controlled RCSR register.
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LH79531 Universal Microcontroller
Register Summary
Table Offset Register 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 Second Minute Hour Month Year Century MinD HourD Value Registers (Base Address: 0xFFFF7000) Position `0': AM/PM `1': AM/PM EALM ALM*
Century
0x28 Check 0x2C RCSR NOTES: Unused bit. Reserved. Read-only bit. address values above table hexadecimal.
CLKSEL CLKEN CHLD
Register Descriptions
Second, Minute: Second, Minute Register
Both registers count from reset Each increment lower bits (bit bit0) represents unit, each increment upper bits (bit represent units. lower bits count from reset upper bits only count from reset
Hour: Hour Register
Hour register supports 12-hour clock 24-hour clock format. Setting selects which hour format. setting bit7 `0', hour register will counting 12-hour clock will used indicate (`0') (`1'). lower bits count from reset same time toggles. When `1', 24-hour clock format used. lower bits count from reset
DayM: Month Register
This register represents month. counts from last month (28, resets last month determined auto-calendar function.
DayW: Week Register
This register counts from reset represents week.
Month: Month Register
month register represents month year. counts from (January) (December) resets
Year: Year Register
year register represents last digits year. counts from 00-99 resets Data Sheet Page
LH79531 Universal Microcontroller
Century: Century Register
bit0 Century register indicates century, represents 1900s represents 2000s.
MinD, HourD: Alarm Min, Alarm Hour Register
These registers alarm time. format these registers same Minute Hour registers. Bit5 indicates AM/PM Hour depending state Bit7 Hour register. alarm only activated deactivated EALM RCSR register.
Check: Check Register
lower bits control clock source 32.768 clock input. Name CLKEN Function Clock Enable Description Enable clock Disable clock Select 32.768kHz clock from Crystal clock Select external clock
CLKSEL Clock Select
RCSR: Control Status Register
Name Description will HIGH when alarm setting time real time clock match, EALM Enable Alarm this `1'. resetting EALM `0', will return immediately. Reserved Alarm Alarm signal. Read Only. control frequency IRQF output signal. pulse sent IRQF IRQF Output Frequency period IRQF minute period IRQF second period IRQF 1/16 second When this `1', will enter Modify mode within Modify mode internal clock divider will reset auto-calendar function Modify mode will stopped. timer registers modified without affecting next stage counter. will start counting after returned `0'. When Modify mode entered, timekeeping stops. When this `1', will enter hold mode within 60µs. Hold mode will freeze auto-calendar function. incoming clock during this period will still CHLD Hold mode captured released after CHLD returns `0'. hold mode internal clock divider circuit still dividing incoming input clock source. When this `1', value second register equal greater than second register will reset minute register advances otherwise Adjust mode second register will reset adjust mode, internal clock divider will reset. (Reset When Adjust mode entered, timekeeping stops. Function
Reset Values
Since these registers define clock function, they undefined power However, possible that these bits could power `enabled' with alarm Reset does affect RTC. Keep mind that when Modify Adjust mode entered, internal sub-second counter reset, timekeeping stops.
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LH79531 Universal Microcontroller
Reset Power Controller (RPC)
Features
provides following power modes: Active mode Standby mode Sleep mode Stop mode Stop2 mode generates following signals: Reset output (nRESETO) System clock with selectable source from either: External clock (XCLKIN) Clock generated controller UART clock with selectable source from either: System clock External clock (UCLK) clock, internally/externally selectable USB/FIR clock with selectable source from either: System clock External clock (USB_FIR_CLK: MHz/ MHz/ MHz) Internal clock Divided system clock
Overview
Reset Power Controller (RPC) used control peripheral clocks, system reset power. system clock chosen from external clock (XCLKIN) clock generated from crystal output.
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LH79531 Universal Microcontroller
Power Mode Operation
manages system power. Table summarizes state operation various peripherals. Table Function ARM7TDMITM, Cache, SDRAM Controller, DMA, PIO, SDRAM Self-Refresh UART0, UART1, UART2 CT0, CT1, LCDC IrDA, Crystal Oscillator Running Clocks Clock Source SYSCLK SYSCLK XTLCLK RTC_CLKIN* SYSCLK UCLK* XCLK SYSCLK MCLK SYSCLK USB_FIR_CLK* SYSCLK XCLK XTLCLK Power Mode Active On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off SYSCLK* XCLK* XTLCLK* Power Mode Standby Sleep Halt Halt On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off On/Off SYSCLK* XCLK* XCLK* XTLCLK* XTLCLK* Stop Halt On/Off On/Off XTLCLK*
Stop2* Halt On/Off
NOTES: Disabling these modules' clocks will lower total system power without disabling peripheral. XCLK either PLLCLK (PLL-driven clock) when CLKSEL XCLKIN (External clock input) when CLKSEL `1'. SYSCLK system clock. same XCLK halted sleep mode. XTLCLK crystal oscillator clock. turned while XCLKIN selected. Stop2 mode only selected PLLCLK selected.
Active Mode
This mode normal operation. System clock (SYSCLK) active Clock Speed controlled setting CPUClockCtrl register. Each peripheral clock controlled setting MacroClockCtrl register. SDRAM refresh controlled software through SDRAM control register. After system reset, system active mode.
Standby Mode
While this mode, both (ARM7TDMITM, Cache, Write Buffer) watch timer (WDT) halted. rest system active. Each peripheral clock controlled setting MacroClockCtrl register. However, must before entering standby mode. Switching from standby mode active mode occurs when there interrupt request system reset. that point, restart from halted state.
Sleep Mode
While this mode, SYSCLK halted XCLK active. When SYSCLK halted, peripherals using this clock halted. When interrupt request system reset occurs, SYSCLK activated system resumes operation active mode.
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LH79531 Universal Microcontroller
Stop Mode
While this mode, SYSCLK XCLK both halted only XTLCLK active. also halts this mode. peripherals except real-time clock (RTC) halted. peripheral configured external clock, halted. When interrupt request system reset occurs, SYSCLK XCLK reactivated system resumes operation active mode. NOTE: When switching Stop Stop2 mode, "Divider Value" PLL_PSR must 8-32.
Stop2 Mode
This mode available only when PLLCLK selected (CLKSEL `0'). clocks, including XTLCLK, halted. XTAL oscillator also halt this mode. Peripherals that external clock affected. When interrupt request system reset occurs, clocks reactivated system resumes operation active mode. NOTE: When switching Stop Stop2 mode, "Divider Value" PLL_PSR must 8-32.
XCLKEN Output Port
XCLKEN used control external clock oscillator reduce power consumption. This signal HIGH while active, standby, sleep modes. while Stop Stop2 modes. When external clock selected system clock, external clock should stable. case XCLKEN signal controls external clock oscillator, external clock should suspended after oscillator stably operated.
Register Summary
Table Offset 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C Register PowerMode Identification MemoryMap ResetStatus ResetStatusClear CPUClockCtrl MacroClockCtrl MacroClockSel SoftReset Arbitration DecodeMode ASBBridgeCtrl Registers (Base Address: 0xFFFF7800) Size Reset Value code 0x0000 0x00 Name Power Mode Register Register Memory Control Register Reset Status Register Reset Status Clear Register Clock Control Register Macro Clock Control Register Macro Clock Select Register Soft Reset Register Arbitration Register Decode Mode Register Bridge Control Register
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LH79531 Universal Microcontroller
Register Descriptions
PowerMode: Power Mode Register
Offset 0x00 Register PowerMode Size Reset Value Reserved Position POWERMODE
This register used control system power mode. system clock source PLLCLK, five power modes (Active, Standby, Sleep, Stop, Stop2) selectable. system clock XCLKIN, four power modes (Active, Standby Sleep, Stop) selectable. relationship between register value power mode shown table labeled Power Mode Register. details about each power mode, please refer each respective section. When power mode non-Active mode, system enters `Wait Interrupt' state. only exit this state issuing interrupt request system reset. Table PowerMode Description System Clock Source PLLCLK XCLKIN Active Mode Active Mode Standby Mode Standby Mode Sleep Mode Sleep Mode Stop Mode Stop Mode Stop2 Mode
POWERMODE [2:0] Others
NOTE: When system clock source PLL-base power mode become Stop Stop2 mode, process following steps. Store register value PLL_PSR (PLL register) memory. PLL_PSR more. Change power mode Stop Stop2. After return Active mode, restore register value stored memory PLL_PSR.
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LH79531 Universal Microcontroller
Identification: Register
Offset 0x04 Register Identification Size Reset Value code Position Undefined CORE
Reading register provides identification information about this chip. This register fifteen bits wide read-only. Table Bits 15:13 Name Identification Description Description Family Name General Purpose Handheld Others Future Member Name LH79531 LH79532 LH79533 Others Future Reserved Core 00xxx ARM7 Core 00000 ARM7 00001 ARM7T 01xxx ARM9 Core 10xxx ARM10 Core 11xxx Future Cores Reserved Silicon Revision Number Revision Revision Revision Value
12:10
CORE
00001
MemoryMap: Memory Control Register
Offset 0x08 Register MemoryMap Size Reset Value Position Reserved RPC_MAP
This register controls memory map. Please refer "Memory Region" section more details.
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LH79531 Universal Microcontroller
ResetStatus: Reset Status Register
Offset 0x0C Register ResetStatus Size Reset Value Position Undefined WDTO
Reading Reset Status register provides reset status device. This register contains Power-On Reset status timeout reset status. power reset (from nRESETi), WDTO cleared. timeout, only WDTO set. These bits remain until they cleared Reset Status Clear operation. Table Name WDTO ResetStatus Description Description Timeout WDTO since flag last cleared WDTO occurred Power Reset since flag last cleared occurred
ResetStatusClear: Reset Status Clear Register
Offset 0x10 Register ResetStatusClear Size Reset Value Position Reserved WCLR PCLR
This register used clear Reset Status flags. When writing this register, each HIGH data will cause corresponding ResetStatus register cleared. data bits have effect their corresponding ResetStatus register.
CPUClockCtrl: Clock Control Register
Offset 0x14 Register CPUClockCtrl Size Reset Value Position Reserved BUSCLK
This register used control system clock. After reset, value this register cleared. When interrupt occurred, value this register cleared. Table CPUClockCtrl Description Clock Frequency XCLK XCLK XCLK XCLK
BUSCLK
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LH79531 Universal Microcontroller
MacroClockCtrl: Macro Clock Control Register
Offset Register Size Reset Value Reserved Position
0x18
MacroClockCtrl
0x0000
This register used control several peripheral clocks. When writing this register, setting data stops clock corresponding peripheral. After reset, values this register cleared.
MacroClockSel: Macro Clock Select Register
Offset 0x1C Register MacroClockSel Size Reset Value 0x00 Reserved Position UART2 UART1 UART0 IrDA
This register used select clock source IrDA, USB, UART peripherals. Table 31:5 Clock UART0 IrDA MacroClockSel Description Description Reserved System clock External clock (UCLK) System clock External clock (USB_FIR_CLK) System clock External clock (USB_FIR_CLK)
SoftReset: Soft Reset Register
Offset 0x20 Register SoftReset Size Reset Value Position Reserved SWRST
This register provides mechanism software activate/deactivate nRESETO. Table Name SoftReset Description
Description Software Reset SWRST nRESETO driven HIGH nRESETO driven LOW. will remain until logical written into SWRST.
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LH79531 Universal Microcontroller
Arbitration: Arbitration Register
Offset 0x24 Register Arbitration Size Reset Value Position Reserved APBPR
This register used control master priority system arbiter. `System Priorities' Memory Interface Architecture section more information. Table Name Arbitration Description
Description Arbitration Priority Control APBPR priority than priority than
DecodeMode: Decode Mode Register
Offset 0x28 Register DecodeMode Size Reset Value Position Reserved DecCycle
This register used control decoder which inserts decode cycle. Table Name DecodeMode Description
Description Decoder Decode Cycle DecCycle Insert decode cycle Without Decode cycle
ASBBridgeCtrl: Bridge Control Register
Offset 0x2C Register ASBBridgeCtrl Size Reset Value Position Reserved WRBUF
This register used control SDRAM write buffer. When WRBUF `1', write request from Main LCDC buffered. When `0', write buffer disabled. This must Controller configured access graphics data from some other source other than SDRAM. Table Name WRBUF ASBBridgeCtrl Description Description SDRAM Write Buffer Control Write buffer disabled Write buffer enabled
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LH79531 Universal Microcontroller
Controller
Overview
Figure shows block diagram controller circuit interfacing crystal oscillator. controller disables different power-down modes controls varying frequency. also controls disabling on-chip crystal oscillator. controller also provides orderly start-up until crystal oscillator stabilizes acquires lock. desired change operating frequency during normal operation, controller will ensure smooth glitch-free transition between frequencies. controller alter PLL-based system clock frequency ways. first method requires reprogramming clock divider with value. This causes clocks halt until resynchronizes frequency. With this method, frequency 4096 times crystal oscillator frequency integer increments with restriction that frequency must kept within limits operation. second method altering PLL-based system clock frequency reprogram prescaler with value. There interruption clock activity with this method. prescaler divide clock controller provides `Loss Lock' interrupt interrupt controller. This interrupt asserted when lost lock reasons other than startup, halt modes, frequency change. deasserted when lock reacquired. controller contains `warm-up' counter that prevents crystal oscillator output from being until crystal oscillator becomes stable following reactivation. counter driven crystal oscillator output bits wide. defaults maximum count 65535 crystal oscillator cycles reprogrammed smaller value PLL_WUC register. Reprogramming count zero turns warm-up counter. warm-up counter effect after exiting STOP2 mode. power expected that nRESETi held asserted until crystal oscillator stabilizes. controller keeps disabled while nRESETi remains asserted. power-up, multiplier frequency (PLL_FREQ) 0x400 (1024) Prescaler (PLL_PSR) 0b100000 (32). This yields power-up frequency 1.0496 MHz.
XTAL_IN XTAL_OUT
Crystal Oscillator
Lock Detector
Clock Divider XTAL-driven Clock
PLLEN
OSCEN Control from Lock Detector Lock State Controller HALTCLK Prescaler Internal Clock PLL-driven System Clock Figure Controller block diagram CLKOUT
Loss-of-Lock Interrupt
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LH79531 Universal Microcontroller
Register Summary
Offset 0x08 0x0C 0x10 0x20 Register PLL_CTL PLL_FREQ PLL_PSR PLL_WUC Registers (Base Address: 0xFFFF7C00) Name Size Reset Value CLKSEL `0': 0b0000100011 Control Register CLKSEL `1': 0b0001100010 Frequency Divide Count Register 0x400 Prescale Count Register 0b100000 Warm-Up Count Register 0xFFFF Table
Register Description
PLL_CTL: Control Register
Offset Register Size Reset Value 0x08 PLL_CTL CLKSEL='0': 0x23, CLKSEL='1': 0x52 LOCK [9]: Write lock WRT_LOCK Description registers write protected registers write enabled LOST LOCK HALT [7]: Halt System Clock During Loss Lock this have system clock halt when loses lock reason other than during frequency change, halt mode, startup. system clock will become active again once regains lock. CLKSEL [6]: System Clock Source Select Status CLKSEL reflects status CLKSEL pin. This read only cannot changed writing CLKSEL Description System clock source PLL-based System Clock System clock source external clock Reserved Position WRT_LOCK LOST_LOCK_HALT CLKSEL OUTSEL
OUTSEL Bits [5:3]: CLKOUT Source Select This selects source CLKOUT. OUTSEL Other Source On-chip crystal oscillator output output clock Halt-able clock PLL-based System Clock Internal clock Internal clock
[1]: Enable on-chip Crystal Oscillator this enable on-chip crystal oscillator. This function provided test purposes only. When CLKSEL `0', setting this effect crystal oscillator operation. [0]: Enable this enable PLL. This function provided test purposes only. When CLKSEL `0', setting this effect operation.
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LH79531 Universal Microcontroller
PLL_FREQ: Frequency Divide Count Register
Offset 0x0C Register PLL_FREQ Size Reset Value 0x400 Reserved Position FREQ
PLL_FREQ 12-bit value that holds divide count frequency divider. value between 4095 valid. PLL_FREQ will cause frequency divider malfunction. PLL_FREQ determines clock frequency follows: (PLL clock) (PLL_FREQ (crystal oscillator) NOTE: PLL_FREQ that clock frequency within maximum 50MHz.
PLL_PSR: Prescale Count Register
Offset 0x10 Register PLL_PSR Size Reset Value 0x20 Position Reserved
PLL_PSR 6-bit value that holds prescale count prescaler. PLL_PSR divides down clock frequency follows: (System Clock) (PLL clock) PLL_PSR following table indicates valid values PLL_PSR resulting internal clock frequency. other PLL_PSR values invalid. PLL_PSR Divider Value (System Clock) 000000 (PLL clock) 000001 (PLL clock) 000010 (PLL clock) 000100 (PLL clock) 001000 (PLL clock) 010000 (PLL clock) 100000 (PLL clock) NOTE: When switching Stop Stop2 mode, "Divider Value" must 8-32.
PLL_WUC: Warm-Up Count Register
Offset 0x20 Register PLL_WUC Size Reset Value 0xFFFF Reserved Position
PLL_WUC 16-bit value that determines number internal crystal oscillator cycles that counted before enabled following activation crystal oscillator. Programming PLL_WUC zero turns warm-up counter.
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LH79531 Universal Microcontroller
Controller
Features
Maximum Frame Rate Internal External Clock Source 16-bit Palette Memory Interface 32-bit wide access external frame buffer Double Buffering support animation Dual Programmable 32-bit FIFO buffers Little Endian, Endian WinCE pixel data formats Interrupt event generation Interface Programmable resolution 1,024 pixels Programmable sync timing Single Dual Scan panels Produces frame line syncs, pixel-clock, control, enable AC-bias signals 18-bit wide Panel Data Power Down Modes Power Sequencing Monochrome/Gray format: shades synthesized gray scale bits pixel 8-bit wide Panel Data DMTN Gray-scale format: levels gray scale monochrome Transflective DMTN-LCD Panel Passive Color format: Palletized Colors 3,375 Direct Colors 16-bit Panel Data Active Color format: 16-bits pixel un-palletized over Direct Colors Color palette accepts bits pixel providing colors 18-bit Panel Data HR-TFT Active Color format: Direct Interface HR-TFT bits pixel driving 18-bit-wide panel Normal Reverse Scan horizontal vertical directions High-Reflectivity Panel
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LH79531 Universal Microcontroller
Overview
LH79531 Color Liquid Crystal Display Controller translates bit-mapped graphics image `frame' residing memory into specialized sequences required active, passive, color, monochrome panel drivers. Image data periodically refresh display automatically downloaded from graphics memory through dedicated 32-bit internal directly from SDRAM port, achieving high display bandwidth good resolution refresh rates. programmable FIFOs buffer incoming pixel-data stream single dual-panel displays. built-in Palette also provided. This enhance storage density bandwidth mapping gray-scale panel data bits color plus intensity bit) from fewer bits pixel data. Thin Film Transistor (TFT) color displays, pixel data directly displayed, providing direct simultaneous colors. when used address palette, palletized colors selected. Super Twisted Nematic (STN) displays, algorithmic gray-scale pattern generator synthesize gray shades, saturation levels color component 3,375 hues. Timings configurations programmed interface variety panels. Control signals generated pixel clocking, horizontal synchronization vertical sync pulses, bias (for panels), enable data capture panel power control. software synchronization, interrupts generated specific base-address update opportunities, vertical frame regions, FIFO underflows, errors. Peripheral Interfaces provide with read/write access setting querying mode-control, timing, status registers. parameters controlling basic panels accessed through Slave interface. parameters controlling DMTN HR-TFT panel formats accessed through Peripheral interface. Once programmed, Master (LCD-DMA interface) automatically fetches graphics data from designated frame buffer region external memory. These activities synchronized LH79531 system clock. After translating this data stream desired panel format, panel-timing signals generated panel data streamed through dedicated 18-bit panel-data cyclically refresh display. These output signals synchronized either external MCLK input, gated version SYSCLK controlled block. FIFO buffers provided inputs outputs this pipeline wide range clock rates.
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INTERFACE REGISTERS
SLAVE INTERFACE
CONTROL STATUS REGISTERS PANEL CLOCK GENERATOR
HR-TFT CONVERTER
PANEL CLOCKS DMTN CONVERTER
TIMING CONTROLLER UPPER PANEL FIFO UPPER PANEL FORMATTER
PANEL CONTROL UPPER PANEL OUTPUT FIFO
BYPASS PANEL DATA
Figure Controller Block Diagram
INPUT FIFO CONTROL PIXEL SERIALIZER PALETTE (128 GRAY SCALER LOWER PANEL FIFO LOWER PANEL FORMATTER LOWER PANEL OUTPUT FIFO
MASTER INTERFACE
LH79531 Universal Microcontroller
77791-61
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LH79531 Universal Microcontroller
Palette
built-in 256-entry 16-bit color palette available expanding 8-bit-per-pixel encoded data words into bits gray-scale color panel data. 16-bit-per-pixel mode palette automatically bypassed, serialized pixel data directly output panel. palette programmed through 128-word bank 32-bit read/write registers. must loaded prior use. palette will used whenever 8-bit pixel mode selected. When palette enabled, contents each data pixel interpreted address into palette RAM. least significant each pixel selects upper lower half-word palette register, while remaining bits binary-decoded address palette registers. little-endian byte order (LB), lowest position pixel selects upper half-word palette entry, while big-endian mode (BB) lowest pixel selects lower half-word. contents lower upper half-word palette register that addressed pixel then output panel produce color shade that pixel. monochrome panels, only palette bits [4:1] (and [20:17]) used, representing gray shades. monochrome DMTN panels, only palette bits [4:2] (and [20:18]) used, representing gray shades. panel, bits [4:0] (and [20:16]) represent panel data; bits [9:5] (and [25:21]) represent Green panel data; bits [14:10] (and [30:26]) represent Blue panel data. [15] (and [31]) used brightness modifier: applied least significant three color-components panel, thereby doubles available output shades. Blue field designations swapped using control register, support either color order.
Direct Color
When bits-per-pixel mode selected, palette will used. Each 16-bit input data word must contain actual binary intensity values each pixel's three color components, following formats. color order selected, Blue field swapped. Table Panel Format (passive) (active) NOTE: Reserved. Intensity bits-per-pixel format (RGB mode) Pixel Bit-Position Blue Green Blue Green
Gray Scale
gray-scaler synthesizes intermediate pixel intensities (gray pastel shades) panels, whose pixels must fully driven times. Each pixel's on/off duty cycle algorithmically modulated over many drive periods, allowing each 4-bit nibble panel data (each color component) encode appearance pixel intensity levels. This produces gray shades monochrome panels 3,375 hues color panels (0b1111 same 0x1110). DMTN panels, upper bits each 4-bit nibble palette data output directly panel, which interprets gray shades. Groups four such pixels output panel data simultaneously.
Timing Generation
provide flexible means driving several different display types, output signals produced Controller synchronized divided-down version input clock whose source division ratio programmable. clock source either LH79531 system clock external clock source (MCLK). division ratio clock programmed from produce compatible bits-per-pixel data rate, required panel. Controller produces shift clock, horizontal (line start end) vertical (frame) synchronization, AC-bias, data-enable signals suitable variety STN, DMTN, TFT, HR-TFT types panels. timing these outputs programmed through Timing registers.
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LH79531 Universal Microcontroller
Interrupts
Controller sends internal interrupt signal interrupt-controller block LH79531 when following four maskable interrupt events occurs: AMBA ERROR Interrupt (MBE) asserted when Controller receives ERROR response request data from memory. This interrupt remains asserted until cleared, writing LCDStatus register. This removes ERROR status, allows Controller resume fetching data beginning with start fresh frame. errors associated with attempts access data from regions memory that exist read-protected. Possible causes include inconsistency between frame base addresses contained LCDUPBASE LCDLPBASE, memory segment start address size allocated frame buffer region LH79531 memory map. frame buffer should reside SDRAM best performance. cannot reside on-chip cache. FIFO Underflow event generates interrupt Controller runs data with which refresh display, either input FIFOs becoming empty. This could caused improperly (FIFO Watermark) LCDControl register, inadequate bandwidth response time from frame buffer memory. This indicate that user allowed excessively long burst starve controller's input FIFO. Vertical Compare event triggers interrupt when specified region vertical frame interval reached, selected contents LCDControl register. interrupt triggered start vertical sync, back porch, active video, front porch. cleared writing VCOM LCDStatus register. Next Base Address Update event generates interrupt when becomes safe change contents LCDUPBASE LCDLPBASE registers, because their present value been copied into internal buffer. This provides double-buffered interlock function changing frames fly. (unmasked) status each these interrupt event flags read cleared through LCDStatus register. Each interrupt source either masked off, cause ignored, enabled, cause propagated interrupt controller, according setting LCDINTR-Enable register. effect pending unmasked interrupts read from LCDInterrupt register.
Pixel Data Storage Format
Pixel data stored 32-bit words graphics region memory. Each word fetched needed from memory ascending sequential order, stored temporarily 32-bit FIFO buffers awaiting serialization. Memory page boundaries managed built-in controller. pixel data packed into memory words available formats based byte-order, pixel-order, panel-number. dual-panel mode, input FIFO configured 16-word 32-bit buffers corresponding upper lower panel halves, into which alternating 32-bit words placed. Pixel data alternating panels word-interleaved into graphics memory. single-panel applications, FI
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