LC895196
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LC895196 - LC895196
Ordering number *5737A
LC895196
ATA-PI Compatible CD-ROM Decoder
Preliminary Overview
LC895196 large scale integrated circuit equipped with CD-ROM functions internal ATA-PI (IDE) interface. multitransmit function function that automatically transmits multiple blocks once.) Built-in CAV-audio functions Built-in intelligent functions (auto buffering, auto decoding, CD-R compatibility) Built subcode buffering function (NO-ECC) CD-TEXT compatibility
Functions
CD-ROM functions, SUB-CODE read function, ATA-PI (IDE) interface (Registers, etc.), CAVaudio function.
Package Dimensions
unit: 3214-SQFP144
[LC895196]
Features
Built-in ATA-PI (IDE) interface. speed supported Uses EDO-DRAM 16.6 Mbyte/s (with IORDY) Operating frequency: 27.5 speed supported Uses EDO-DRAM 16.6 Mbyte/s (without IORDY) Operating frequency: speed supported Uses DRAM Supports between Mbit Mbit buffer when DRAM used user flexibly main channel, flags, subcode regions buffer Built-in batch transfer function. (Where batch transfer function function that transmit main channel, flags, subcodes, etc. once.) Built-in multitransmit function. (Where
SANYO: SQFP144
Specifications
Absolute Maximum Ratings
Parameter Maximum supply voltage voltage Allowable power dissipation Operating temperatures Storage temperatures Soldering temperature (terminals only) current Note: basic cell Symbol Topr Tstg seconds 25°C 25°C 70°C Condition Ratings -0.3 +7.0 -0.3 +125 ±20* Unit
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, Chome, Ueno, Taito-ku, TOKYO, JAPAN
D3097HA (OT) 5737-1/12
LC895196 Allowable Operating Ranges +70°C,
Parameter Supply voltage Input voltage range Symbol Conditions Ratings Unit
Characteristics +70°C
Parameter Input high level voltage Input level input Input high level voltage Input level input Input high level voltage Input level input Output high level voltage Output level voltage Output high level voltage Output: level voltage Output high level voltage Output level voltage Output level voltage Output level voltage Input leakage current Output leakage current Pull-up resistor Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 VOL4 VOL5 (4), (10) (4), (10) (8), (11) (8), (11) (6), VSS, VDD: (1), (2), (3), (11) When high impedance output: (6), (8), (9), (11) (7), (10) compatible Schmitt: (2), (3), (11) compatible with pull-up resistor: (10) Conditions Applicable pins (see below) compatible Ratings Unit
Note: applicable pins correspond following names. [INPUT] .ATPINSEL, CSCTRL, SUA0 SUA6, BCK, C2PO, LRCK, SDATA, SBSO, SCOR, WFCK, TEST0, TEST1 .ZRESET, ZCS, ZRD, ZWR, CSEL .DA0 DA2, ZCS1FX, ZCS3FX, ZDIOR, ZDIOW, ZDMACK, ZHRST [OUTPUT] .RA0 RA9, ZCAS0, ZCAS1, ZLWE, ZOE, ZRAS0, ZRAS1, ZUWE, DBCK, DLRCK, DSDATA, EXCK .MCK, MCK2, MCK3 .ZRSTCPU, ZRSTIC .ZINT, ZINT1, ZSWAIT .DMARQ, HINTRQ .IORDY, ZIOCS16 [INPUT] (10) IO15 (11) .DD0 DD15, ZDASP, ZPDIAG XTAL0, XTALCK0, XTAL1, XTALCK1 pins included characteristics.
Recommended Example Oscillator Circuit
Ceramic oscillator frequency 33.8688 MHz. 33.8688 recommended example overtone. Ceramic oscillator frequency (XTALCK0) Because specific values influenced circuit board, confer with oscillator manufacturer.
5737-2/12
LC895196 Block Diagram
CD-DSP SYNC detector
Each block control signal External
Each block register R118
arbiter DRAM controller
buffer
DRAM
WFCK, SBSO, SCOR BCK, SDATA, LRCK, C2PO DD15, ZDASP, ZPDIAG ZCS1FX, ZCS3FX, DA2, ZDIOR, ZDIOW, ZDMACK, CSEL DMARQ, HINTRQ, ZIOCS16, IORDY, ZHRST ZRD, ZWR, SUA0 SUA6, ZCS, CSCTRL IO15 RA9, ZRAS0, ZRAS1, ZCAS0, ZCAS1, ZOE, ZUWE, ZLWE DBCK, DLRCK, DSDATA HISIDE (WD25C32) made WESTERN DIGITAL
5737-3/12
LC895196 Functions LC895196 opposite ATAPI layout using setting ATPINSEL
Input Bi-directional connected Output Power supply VSS0 VSS0 VSS0 Symbol VSS0 ZRAS0 ZRAS1 ZCAS0 ZCAS1 ZUWE ZLWE VSS0 VSS0 ATPINSEL IO10 IO11 IO12 VSS0 IO13 IO14 IO15 Type Data data buffer DRAM. Built-in pull-up resistor. Data data buffer DRAM. Built-in pull-up resistor. ATAPI assignment select pin. Connect VSS0. Data data buffer DRAM. Built-in pull-up resistor. Address signal output pins data buffer DRAM Address signal output pins data buffer DRAM signal output buffer DRAM (Normally uses signal output buffer DRAM signal output buffer DRAM (Normally uses signal output buffer DRAM Buffer DRAM output enable Buffer DRAM upper write enable Buffer DRAM lower write enable Function
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5737-4/12
LC895196
Continued from preceding page.
XTALCK0 XTAL0 VSS0 ZRESET VSS0 SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 VSS0 ZINT0 ZINT1 ZSWAIT ZRSTCPU XTALCK1 Symbol C2PO SDATA LRCK EXCK WFCK SBSO VSS0 SCOR DSDATA DLRCK DBCK TEST0 TEST1 CSEL ZRSTIC CSCTRL MCK2 MCK3 VSS0 Type Output interrupt request signal microcontroller (set ECC-side registers) Output interrupt request signal microcontroller (set ATAPI-side registers) Wait signal microcontroller Reset signal X'tal oscillator circuit input Microcontroller data signals. Built-in pull-up resistors. Microcontroller data signals. Built-in pull-up resistors. Microcontroller register select signals reset Microcontroller data read signal input Microcontroller data write signal input Input register chip select signal from microcontroller X'tal oscillator circuit input X'tal oscillator circuit input XTALCK1 1/1, STOP output Test input pin. Connect VSS. ATAPI control signal Reset signal drive reset Microcontroller-side active low/high select XTALCK0 1/1, 1/2, 1/5, 1/512 STOP output XTALCK0 1/1, 1/5, 2/5, 1/512 STOP output output Subcode Subcode CD-DSP interface Function
Continued next page.
5737-5/12
LC895196
Continued from preceding page.
Symbol XTAL1 VSS0 ZHRST ZDASP ZCS3FX ZCS1FX VSS0 ZPDIAG ZIOCS16 INTRQ ZDMACK VSS1 IORDY ZDIOR ZDIOW DMARQ DD15 VSS1 DD14 VSS1 DD13 DD12 VSS1 DD11 DD10 VSS1 VSS1 Type ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI data ATAPI control signals ATAPI control signals ATAPI control signals X'tal oscillator circuit output Function
Leave pins OPEN. Those names starting with letter indicate negative logic. VSS0 logic system ground, VSS1 interface driver ground.
5737-6/12
LC895196 ATPINSEL
Input Bi-directional connected Output Power supply VSS0 VSS0 VSS0 Symbol VSS0 ZRAS0 ZRAS1 ZCAS0 ZCAS1 ZUWE ZLWE VSS0 VSS0 ATPINSEL IO10 IO11 IO12 VSS0 IO13 IO14 IO15 Type Data data buffer DRAM. Built-in pull-up resistor. Data data buffer DRAM. Built-in pull-up resistor ATAPI assignment select pin. Connect VSS0. Data data buffer DRAM. Built-in pull-up resistor. Address signal output data buffer DRAM Address signal output data buffer DRAM signal output buffer DRAM (Normally uses signal output buffer DRAM signal output buffer DRAM (Normally uses signal output buffer DRAM Buffer DRAM output enable Buffer DRAM upper write enable Buffer DRAM lower write enable Function
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5737-7/12
LC895196
Continued from preceding page.
XTALCK0 XTAL0 VSS0 ZRESET VSS0 SUA0 SUA1 SUA2 SUA3 SUA4 SUA5 SUA6 VSS0 ZINT0 ZINT1 ZSWAIT ZRSTCPU XTALCK1 Symbol C2PO SDATA LRCK EXCK WFCK SBSO VSS0 SCOR DSDATA DLRCK DBCK TEST0 TEST1 CSEL ZRSTIC CSCTRL MCK2 MCK3 VSS0 Type Output interrupt request signal microcontroller (set ECC-side registers) Output interrupt request signal microcontroller (set ATAPI-side registers) Wait signal microcontroller Reset signal X'tal oscillator circuit input Microcontroller data signals Built-in pull-up resistors. Microcontroller data signals. Built-in pull-up resistors. Microcontroller register select signals reset Microcontroller data read signal input Microcontroller data write signal input Input register chip select signal from microcontroller X'tal oscillator circuit input X'tal oscillator circuit input XTALCK1 1/1, STOP output Test input pin. Connect VSS. ATAPI control signal Reset signal drive reset Microcontroller-side active low/high select XTALCK0 1/1, 1/2, 1/5, 1/512 STOP output XTALCK0 1/1, 1/5, 2/5, 1/512 STOP output output Subcode Subcode CD-DSP interface Function
Continued next page.
5737-8/12
LC895196
Continued from preceding page.
Symbol XTAL1 VSS0 VSS1 DD10 DD11 DD12 VSS1 DD13 DD14 DD15 VSS1 DMARQ ZDIOW ZDIOR VSS1 IORDY ZDMACK INTRQ ZIOCS16 VSS1 ZPDIAG VSS1 ZCS1FX ZCS3FX VSS1 ZDASP ZHRST Type ATAPI control signals ATAPI control signals ATAPI control signals ATAPI control signals ATAPI control signals ATAPI data ATAPI data ATAPI data X'tal oscillator circuit output Function
Leave pins OPEN. Those names starting with letter indicate negative logic. VSS0 logic system ground, VSS1 interface driver ground.
5737-9/12
LC895196 Descriptions ATAPI ZCS1FX (input) Chip select signal selecting command block register. ZCS3FX (input) Chip select signal selecting control block register. (input) Addresses accessing various ATAPI addresses. ZDASP (input/output) Drive output drive input. Signal indicating existence drive drive Attach external pull-up resistors. DD15 (input/output) 16-bit data bus. used transferring data. ZDIOR (input) Read strobe signal from host. ZDIOW (input) Write strobe signal from host. ZDMACK (input) During transmission, this acknowledged signal from host responding DMARQ drive request signal. There built-in pull-up resistor. DMARQ (output) This drive request signal during transmission. HINTRQ (output) Drive interrupt signal host. ZIOCS16 (output) This signal asserted depending drive when drive support 16-bit transfers. This signal asserted during transfers. IORDY (output) This signal indicates that drive ready respond during data transfer. This signal drive ready. Attach external pull-up resistor. ZPDIAG (input/output) This signal asserted drive inform drive that diagnostics complete. Attach external pull-up resistor. ZHRST (input) This reset signal from host. Applying signal this causes ZRSTIC resets drive. There built-in pull-up resistor. ZINT1 (output) This interrupt request signal from block CSEL (input) This cable select signal that determines master/slave. Attach external pull-up resistor. Microcontroller Interface (input) This MC-side chip select. CSCTRL (input) This signal selects MC-side chip select logic. High: active Low: active high ZRD, ZWR, SUA0 SUA6 (inputs) These interface control signals. Addressing uses SUA0 SUA6. ZSWAIT (output) When microcontroller accesses RAM, SUB-CPU must wait while this low.
5737-10/12
LC895196 (input/output) This MC-side data bus. Built-in pull-up resistor. ZINT (output) This interrupt signal microcontroller. Buffer IO15 (input/output) This buffer DRAM data bus. Built-in pull-up resistors. (output) These address pins buffer RAM. ZRAS0 ZRAS1 (output) These output pins buffer DRAM. Normally ZRAS0 used; however, when (64K )DRAMS used, connect pins each DRAM ZRAS0 ZRAS1. ZCAS0 ZCAS1 (output) This output buffer DRAM. Normally ZCAS0 used. When (64K bit) DRAMS used, connect ZCAS0 output each DRAM. When 2CAS types used, connect ZCAS0 UCAS connect ZCAS1 LCAS. (output) read output signal buffer DRAM. ZUWE, ZLWE (output) This write output signal buffer DRAM. This connects various DRAM pins. When 2CAS type used, connect ZLWE write enable signal. Subcode Interface EXCK, WFCK, SBSO, SCOR (input output) These subcode interface pins. connecting these CD-DSP subcode data accepted LC895196 transferred host. CD-DSP Data BCK, SDATA, LRCK, C2PO (input) When connected CD-DSP, CD-ROM data acquired. C2PO flag. Converter Interface DLRCK, DBCK (output) These pins made XTALCK0 XTALCK1. DSDATA (output) This outputs serial data DAC. Other Pins ZRESET (input) This LC895196 reset pin. LC895196 reset when this signal low. This signal must kept least period after power XTALCK0, XTAL0 These cause oscillation MHz. Multiples these respective clocks also input. Frequencies from outside also input into XTALCK0. XTALCK1, XTAL1 These specialty pins DLRCK, DBCK, IDE, which output DAC. They cause 33.8688 oscillation. frequency input into XTALCK1 from outside. (output) This outputs XTALCK1 XTALCK1/2 frequencies. output also turned off.
5737-11/12
LC895196 MCK2 (output) This outputs XTALCK0, XTALCK0/2, XTALCK0/5 XTALCK0/512 frequencies. output also turned off. MCK3 (output) This outputs XTALCK0, XTALCK0*2/5, XTALCK0/5 XTALCK0/512 frequencies. output also turned off. ZRSTIC (output) ZRSTIC output goes when microcontroller register R46-bit7 (ZSYSRES) ZHRST low. When both ZSYSRES ZHRST pins high, ZRSTIC enters high impedance state. Attach external pull-up resistor. ZRSTCPU (output) When ATAPI soft reset command (08h) received, pulse generated approximately (when XTALCK1 MHz). When this happens, interrupt sent microcontroller. When ZRESET become active, ZRESET signal output directly ZRSTCPU. Attach external pull-up resistor. ATPINSEL (input) changing input this pin, ATAPI-side layout reversed.
products described contained herein intended surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment like, failure which directly indirectly cause injury, death property loss. Anyone purchasing products described contained herein above-mentioned shall: Accept full responsibility indemnify defend SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees, jointly severally, against claims litigation damages, cost expenses associated with such use: impose responsibility fault negligence which cited such claim litigation SANYO ELECTRIC CO., LTD., affiliates, subsidiaries distributors their officers employees jointly severally. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information December, 1997. Specifications information herein subject change without notice. 5737-12/12
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