KS88C4116
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KS88C4116
8-Bit CMOS Microcontroller
Product Specification
OVERVIEW
KS88C4116 single-chip 8-bit microcontroller fabricated using highly advanced CMOS process. fast reliable based Zilog's Super8® architecture. With 8-bit ports, full-duplex serial port, 8-bit 16-bit timer/counters, with data capture, converter, KS88C4116 offers excellent design solution wide range general-purpose electronics applications.
FEATURES
SAM8 core General 8-bit general ports 8-bit n-channel, opendrain output port (port 8-bit input port (ADC input port Converter Eight analog input pins 8-bit resolution 16-µs conversion speed with 12-MHz clock End-of-conversion (EOC) signal output
Memory 1040-byte internal register file 16-Kbyte internal program memory
Timer Module External Interface 64-Kbyte external data memory area 64-Kbyte external program memory (ROM-less mode) 8-bit timers with interval mode Timer output pins (TA,
Backup Timer 28-bit backup timer 20°C 85°C
Operating Temperature Range Timer Module 16-bit timer/counters with four selectable modes
Instruction instructions, including IDLE STOP instructions power-down modes
Operating Voltage Range
Serial Port synchronous operating mode three full-duplex asynchronous UART modes
Package Type 80-pin
Instruction Execution Time fOSC (min.)
PWM/Capture Module outputs (PWM0, PWM1) 8-bit resolution, 2-bit prescaler Frequency: 46.87 with 12-MHz clock Capture module with input
Interrupts interrupt sources with vectors eight levels Fast interrupt processing (levels only)
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
EXTERNAL ADDRESS/DATA P0.0-P0.7 (A8-A15) P1.0-P1.7 (AD0-AD7) P2.0-P2.7
RESET
PORT
PORT
PORT
SAM8 XOUT XTOUT MAIN BACKUP TIMER
PORT
P3.0-P3.7
PORT INTERRUPT CONTROL
PORT P4.0-P4.7
TCCK TDCK
TIMERS
SAM8
PORT
P5.0-P5.3 P5.4-P5.7
TIMERS
SERIAL PORT
16-KB
1040-BYTE REGISTER FILE
PORT
P6.0-P6.7
SAM8 AVSS AVREF (P2.5) PWM/ CAPTURE MODULE
CONVERTER
VDD1 (INTERNAL) VSS1 (INTERNAL) VDD2 (EXTERNAL) VSS2 (EXTERNAL)
CAPTURE (P3.6)
ADC0 /P7.0 ADC7 /P7.7
PWM0
PWM1
Figure KS88C 4116 Block Diagram
MSUN
June 1996
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 VDD1 (int.)
P0.7 P0.6 P0.5 P0.4 P0.3 P0.2
P0.1 P0.0 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 VDD2 (ext.) P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 PWM1 PWM0 P3.0 TCCK INT0
KS88C4116
80-QFP
(TOP VIEW)
RESET
VSS1 (int.) XOUT P6.0 P6.1 P6.2 P6.3 P6.4 P6.5 P6.6 P6.7 P7.7 ADC7 P7.6 ADC6 P7.5 ADC5 P7.4 ADC4 P7.3 ADC3 AVSS P7.2 ADC2 P7.1 ADC1 AVREF P7.0 ADC0
Figure KS88C4116 Assignments (80-Pin QFP)
P3.7 WAIT P3.6 P3.5 P3.4 P3.3 INT3 P3.2 INT2 P3.1 TDCK INT1
P4.7 INT11 P4.6 INT10 P4.5 INT9 P4.4 INT8 P4.3 INT7 P4.2 INT6 P4.1 INT5 P4.0 INT4 VSS2 (ext.)
MSUN
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
Table KS88C4116 Descriptions Name P0.0-P0.7 Type Description Nibble programmable port; input output mode selected software; Schmitt trigger input push-pull, open-drain output with software assignable pull-ups; alternately configurable external interface address lines A8-A15 Same general characteristics port alternately configurable external interface address/data lines AD0-AD7; high current drive capability (15-mA typical value) General port with Schmitt trigger input push-pull output; programmable: P2.0 address strobe (AS) P2.1 data strobe (DS) P2.2 read/write (R/W) P2.3 data memory select (DM) P2.5 comparator output P2.6 timer output P2.7 timer output General port with programmable pins; Schmitt trigger input push-pull output with software assignable pull-ups; input/output mode selectable software; P3.0-P3.3 alternately used external interrupt input (noise filters, interrupt enable pending control); P3.0 timer clock input (TCCK) INT0 P3.1 timer clock input (TDCK) INT1 P3.2 timer gate input (TCG) INT2 P3.3 timer gate input (TDG) INT3 P3.6 Capture data input (CAP) P3.7 WAIT slow memory interface General port with programmable pins; Schmitt trigger input push-pull, open-drain output; software assignable pullups; input/output mode selectable software; P4.0-P4.7 alternately used inputs external interrupts INT4- INT11; noise filters, interrupt control General port with nibble programmable pins; Schmitt trigger input push-pull, open-drain output; software assignable pullups; input/output mode selectable software; high current drive capability (15-mA typical value) Circuit Type Number 80-75 Share Pins A8-A15
P1.0-P1.7
73-66
AD0-AD7
P2.0-P2.7
19-12
R/W;
EOC;
P3.0-P3.7
24-31
TCCK INT0, TDCK INT1, INT2, INT3, CAP,
WAIT
P4.0-P4.7
33-40
INT4 INT11
P5.0-P5.7
10-3
MSUN
June 1996
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
Table KS88C4116 Descriptions (Continued) Name P6.0-P6.7 ADC0-ADC7 Type Description Output port; n-channel, open-drain output pins; 9-volt capacity Analog input pins converter module; alternately, general-purpose input port System reset (pull-up resistor: External access (EA) with three modes: Normal operation (connect VSS) ROM-less operation (external interface) 9-10 input: Factory test mode Serial data pin; receive input, transmit output (mode Serial data pin; transmit output, shift clock (mode Pulse width modulation output pins Power input pins operation (internal) Power input pins port output (external) Main oscillator pins Suboscillator pins backup timer converter reference voltage ground Circuit Type Number 58-51 43-44, 46-50 Share Pins P7.0-P7.7
RESET
PWM0, PWM1 DD1, VSS1 DD2, VSS2 XOUT XTIN, XTOUT AVREF, AVSS
Table Circuit Assignments KS88C4116 Circuit Number Circuit Type Input Input KS88C4116 Assignments
RESET
converter input pins ADC0-ADC7 Ports Ports TCCK, TDCK, TCG, TDG, CAP, WAIT, INT0-INT11 Port
R/W,
Serial port Serial port pin, PWM0, PWM1 Port n-channel, open-drain output with high current capability
MSUN
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PULL-UP RESISTOR (Typical
INPUT BUFFER
LOGIC
INPUT
Figure Circuit Type (RESET)
Figure Circuit Type (ADC0-ADC7)
PULL-UP RESISTOR (Typical PULL-UP ENABLE
DATA
OPENDRAIN OUTPUT DISABLE
INPUT
Figure Circuit Type (Ports
MSUN
June 1996
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PULL-UP RESISTOR (Typical PULL-UP ENABLE
DATA
OUTPUT DISABLE INPUT EXTERNAL INTERRUPT INPUT
NOISE FILTER
Figure Circuit Type (Ports TCCK, TDCK, TCG, TDG, CAP, WAIT, INT0-INT11)
SELECTION BITS PORTS OTHER FUNCTIONS
DATA
OPENDRAIN OUTPUT DISABLE
INPUT OTHER FUNCTION
Figure Circuit Type (Port
R/W,
MSUN
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
EDGE DETECTION
DATA
OUTPUT DISABLE
INPUT NOISE FILTER
Figure Circuit Type (Serial Port Pin)
OUTPUT
DATA
DATA OUTPUT
NOTE: Circuit type withstand volts.
Figure Circuit Type (Serial Port Pin, PWM0, PWM1)
Figure Circuit Type (Port
MSUN
June 1996
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
ADDRESS SPACES
OVERVIEW KS88C4116 supports three types address space: Program memory (internal and/or external) Internal register file External data memory 16-bit address 8-bit data supports program memory data memory operations. separate 8-bit address 8-bit data carryaddresses data between register file. architecture therefore supports bytes program memory (ROM). KS88C4116 bytes mask-programmable internal program memory. There configuration options: normal mode ROMless mode. normal mode, only internal 16-Kbyte program memory used. ROM-less mode, internal 16-Kbyte area used. Instead, entire program memory space accessed externally. Using external interface, bytes program memory bytes data memory space accessed. These spaces combined they kept separate. separate program data memory areas configured, selective access controlled (data memory) signal line. KS88C4116 microcontroller 1040 registers internal register file. Most registers serve source destination address, accumulators data memory operations. Thirteen bytes register file contain system peripheral control registers. PROGRAM MEMORY (ROM) Normal Operating Mode (Masked ROM) Program memory (ROM) stores program code table data. Instructions fetched, data read, from ROM. KS88C4116 bytes (locations 0H-3FFFH) internal mask-programmable program memory (ROM). KS88 interrupt structure supports vector addresses. total twenty vectors used KS88C4116 interrupt structure. first bytes (0H-FFH) reserved maximum number vectors. Unused locations this address range used normal program memory. reset address 0020H. vector address area store normal program data, careful avoid overwriting vector addresses stored these locations.
MSUN
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
ROM-Less Operating Mode (External ROM) applications that require more than bytes program memory, ROM-less operating mode used configure 64-Kbyte area externally. Access internal 16-Kbyte program memory area disabled ROM-less mode. normal operating mode, also possible access bytes program memory externally over external memory interface. 16-Kbyte on-chip accessed when program memory locations 0H3FFFH addressed external interface used
whenever locations 4000HFFFFH addressed. This configuration not, however, practical cost-effective. Mode selection (internal ROM-less) depends voltage applied during reset operation: When applied pin, KS88C4116's internal configured normally 16-Kbyte space (0H- 3FFFH) addressed. When applied pin, KS88C0116 operates ROM-less mode. External memory locations 0000H-
FFFFH accessed over 16-bit address/data bus. When applied during power-on reset, external peripheral interface automatically configured follows: Port port control registers cleared their initial value (00H), corresponding address data lines configured. lower-nibble pins port (P2CONL) '11B', configuring interface signals (DM, R/W, P2.0- P2.3.
(DECIMAL) 65,535
(HEX) FFFFH
(DECIMAL) 65,535 (HEX) FFFFH
EXTERNAL MEMORY AREA
EXTERNAL MEMORY AREA
16,383 INTERNAL PROGRAM MEMORY AREA INTERRUPT VECTOR AREA
4000H 3FFFH
INTERRUPT VECTOR AREA
Figure Program Memory Normal Operating Mode "0")
Figure Program Memory ROM-less Operating Mode "1")
MSUN
June 1996 5-10
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
REGISTER ARCHITECTURE
INTERNAL REGISTER FILE physical 256-byte space logically extended into four 256-byte pages, giving total 1024 general-purpose registers. upper 64-byte area register file extended into sets called further divided into 32-byte register banks, called bank bank1, 32-byte common area. total register file space 1120 bytes (256 bytes pages set1 bytes bytes). However, because only locations FFH-F9H mapped bank KS88C4116 register file total 1095 8-bit registers. these 1095 registers, bytes system control registers, 42bytes peripheral control data registers. There 1040 generalpurpose registers. REGISTER PAGE POINTER (PP) total addressable area register file expanded means register page implementation. Page addressing controlled page pointer (PP, DFH). Figure shows settings used select specific register pages. reset clears register page pointer '000B', selecting page0. select another page, manipulate page pointer bits0-3. When select page, entire 256-byte address range page (00H-FFH) swapped with that page. Stack operations handled independently register page pointer using page only.
REGISTER PAGE POINTER (PP) DFH,
used
Page selection control bits: Page Page Page Page selected selected selected selected
('x' means don't care.)
Figure Register Page Pointer (PP)
MSUN
5-11
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
REGISTER term refers upper bytes register file, locations C0H-FFH. these bytes, upper bytes divided into register banks. lower 32-byte area banked. This non-banked area called common area because accessed times, regardless which page currently selected. upper bytes (E0H-FFH) divided into 32-byte register banks called bank bank Banks addressed using register bank instructions, SB1. reset automatically selects bank0 addressing. non-banked 32-byte area register contains bytes mapped system registers (D0H-DFH) 16-byte working register common area (C0H-CFH). locations 16-byte working
register area temporary buffers transferring register data between locations same page between different pages. registers banked non-banked areas directly accessible times using Register addressing mode. 16-byte working register area only accessed using working register addressing. REGISTER same 64-byte physical space that used register locations C0H-FFH logically duplicated bytes register space. This logically expanded area register file called KS88C4116, upper 64-byte area pages 0-3. logical division maintained means addressing mode restrictions: While only accessed using Register addressing mode,
accessed only using Register Indirect addressing mode Indexed addressing mode. 192-BYTE PRIME REGISTER SPACE lower bytes each 256-byte page (00H-BFH) called prime register area. access prime registers using addressing mode, either direct indirect. Prime register locations used accumulators, working registers, data buffers, user-defined stacks. KS88C4116 register file, prime areas pages available generalpurpose data registers. Page always selected after reset, prime registers page0 immediately addressable. address prime register locations page must register page pointer (PP) appropriate value.
MSUN
June 1996 5-12
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
BYTES BANK
PAGE PAGE PAGE PAGE
BANK SYSTEM PERIPHERAL CONTROL REGISTERS
(REGISTER ADDRESSING MODE)
BYTES
INDEXED, STACK (INDIRECT REGISTER, ADDRESSING ONLY) INDEXED, STACK
DATA REGISTERS (INDIRECT REGISTER, DATA REGISTERS
REGISTERS
SYSTEM REGISTERS
(REGISTER ADDRESSING MODE)
ADDRESSING ONLY) (INDIRECT REGISTER, INDEXED MODE, STACK OPERATIONS)
WORKING REGISTERS (WORKING REGISTER
ADDRESSING ONLY) PAGE
PAGE PAGE
BYTES
DATA REGISTERS
(INDIRECT REGISTER, DATA REGISTERS INDEXED, STACK (INDIRECT REGISTER, PRIME ADDRESSING ONLY) INDEXED, STACK
BYTES
DATA REGISTERS
ADDRESSING ONLY) (ALL ADDRESSING MODES)
Figure KS88C4116 Register File
MSUN
5-13
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
CONTROL REGISTERS
Table KS88C4116 Registers Control Register Name Timer Counter Register (High Byte) Timer Counter Register (Low Byte) Timer Counter Register (High Byte) Timer Counter Register (Low Byte) Port Interrupt Pending Register System Flags Register Register Pointer Register Pointer Stack Pointer (High Byte) Stack Pointer (Low Byte) Instruction Pointer (High Byte) Instruction Pointer (Low Byte) Interrupt Request Register Interrupt Mask Register System Mode Register Register Page Pointer Mnemonic P4PND FLAGS Decimal
Table KS88C4116 Bank Registers Control Register Name Port Data Register Port Data Register Port Data Register Port Data Register Port Data Register Port Data Register Port Data Register Backup Timer Control Register Backup Timer Counter Extension Register Serial Port Shift Register Serial Port Control Register Serial Port Interrupt Pending Register Mnemonic BTCON BTEXT SIOCON SIOPND Decimal
MSUN
June 1996 5-14
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
Table KS88C4116 Bank Registers (Continued) Control Register Name Timer Data Register Timer Data Register Timer Module Control Register Timer Control Register Port Control Register Port Control Register Port Control Register (High Byte) Port Control Register (Low Byte) Port Control Register (High Byte) Port Control Register (Low Byte) Port Control Register (High Byte) Port Control Register (Low Byte) Port Control Register Port Interrupt Enable Register Timer Module Control Register Timer Module Mode Register Port Interrupt Enable Register Port Interrupt Pending Register External Memory Timing Register Interrupt Priority Register Mnemonic TADATA TBDATA T0CON TBCON P0CON P1CON P2CONH P2CONL P3CONH P3CONL P4CONH P4CONL P5CON P4INT T1CON T1MOD P3INT P3PND Decimal
NOTES: timer interrupt pending (TAIP, T0CON register read. timer operating mode selection (EBPWM, TBCON register write-only.
Table KS88C4116 Bank Registers Register Name Converter Input Register Converter Output Register Converter Control Register Module Control Register PWM1 Data Register PWM0 Data Register Capture Register Mnemonic ADIN ADOUT ADCON PWMCON PWM1 PWM0 PWMCAP Decimal (Note)
NOTE: converter end-of-conversion (EOC, ADCON register read-only.
MSUN
5-15
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PROGRAMMING Using Load Instructions Read-Only Write-Only Registers
instructions (Logical OR), (Logical AND), (Compare), (Load Bit) access write-only read-only registers. Load instructions instead (except LDB). Here some examples: Example T0CON,#04H Invalid logical instruction!
instruction instead manipulate T0CON register: BITS Example
ST0CON.2 T0CON,ST0CON
ST0CON shadow register T0CON T0CON register
T0CON,#3CH EQ,AAA
Invalid instruction!
shadow register instead manipulate T0CON register:
ST0CON,#3CH EQ,AAA
ST0CON shadow register T0CON
MSUN
June 1996 5-16
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
INTERRUPT STRUCTURE
OVERVIEW KS88C4116 microcontroller interrupt sources, Twenty different vector addresses used support these interrupt sources. reason there vectors (the total number sources) that P3.3 P3.2 external interrupt sources (IRQ4) share same vector address: ECH. eight interrupt levels used interrupt structure. (see Figure 16). When multiple interrupt levels active, interrupt priority register (IPR) determines order which contending interrupts serviced. multiple interrupts occur within same interrupt level, interrupt with lowest vector address processed first. relative priorities multiple interrupts within single level hardware factory. When interrupt request granted, interrupt machine cycle entered. This disables subsequent interrupts, saves program counter status flags, branches program memory vector location reserved that interrupt. This memory location, together with next memory byte, constitutes 16-bit address interrupt
(DECIMAL) 16,383 (HEX) 3FFFH
16-KBYTE
PROGRAM MEMORY (ROM) AREA
PERIPHERAL REGISTERS PORTS
INTERRUPT VECTOR ADDRESS AREA
RESET
ADDRESS
Figure Vector Address Area service routine that particular interrupt request. Interrupt sources external internal. Internal sources hardwired particular vector level, while external sources freely defined control external events. External interrupts triggered rising falling signal edges, determined source's control register settings. INTERRUPT VECTOR ADDRESSES Interrupt vector addresses KS88C4116 stored first bytes ROM. reset address 0020H. Unused locations range 00H-FFH used program memory locations. Care must taken, however, overwrite interrupt vector addresses stored this area.
MSUN
5-17
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
LEVEL IRQ0
VECTOR
SOURCE Timer Interrupt Counter Interrupt Capture Data Interrupt Timer Interrupt Backup Timer Interrupt
RESET CLEAR
IRQ1
IRQ2
Serial Data Receive Interrupt Serial Data Transmit Interrupt Timer Interrupt Timer Interrupt P3.0 External Interrupt P3.1 External Interrupt P3.2 External Interrupt P3.3 External Interrupt
IRQ3 IRQ4
IRQ5
P4.0 External Interrupt P4.1 External Interrupt P4.2 External Interrupt P4.3 External Interrupt P4.4 External Interrupt P4.5 External Interrupt P4.6 External Interrupt P4.7 External Interrupt
IRQ6
IRQ7
NOTES: Within given interrupt level, lower vector address higher priority. example, higher priority than within IRQ7. These priorities factory. External interrupts triggered rising falling edge, based corresponding control register setting.
Figure KS88C4116 Interrupt Structure
MSUN
June 1996 5-18
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
Table KS88C4116 Interrupt Vectors Vector Address Decimal Value Value Timer overflow Timer overflow Timer overflow Serial data transmit Serial data receive P3.3 external interrupt P3.2 external interrupt P3.1 external interrupt P3.0 external interrupt P4.7 external interrupt P4.6 external interrupt P4.5 external interrupt P4.4 external interrupt P4.3 external interrupt P4.2 external interrupt P4.1 external interrupt P4.0 external interrupt Timer overflow Backup timer overflow Capture data input counter overflow Interrupt Source Request Interrupt Level IRQ0 IRQ3 Priority Level Reset/Clear
IRQ4
IRQ7
IRQ6
IRQ5 IRQ1 IRQ2 IRQ1
NOTES: Interrupt priorities identified inverse order: highest priority, next highest, more interrupts within same level contend, interrupt with lowest vector address priority over with higher vector address. priorities within level preset factory. example, interrupt level IRQ3 highest-priority interrupt vector serial data receive interrupt, vector F0H; lowest-priority interrupt within that level timer interrupt, vector F6H. P3.3 P3.2 interrupt sources share same interrupt vector: (decimal 236).
MSUN
5-19
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
ENABLE/DISABLE INTERRUPT INSTRUCTIONS (EI, Enable Interrupts (EI) instruction globally enables KS88 interrupt structure. When executed, interrupts serviced when they occur, based interrupt priority logic.
interrupt pending condition existed prior instruction, this request serviced when global enable goes into effect. instruction must always executed part system initialization routine that follows reset. (Disable Interrupt)
instruction executed time globally disable interrupt processing. During normal operation, system mode register (SYM.0) manipulated dynamically enable disable interrupt processing.
Table System Level Interrupt Control Registers Control Register System mode register Interrupt mask register Interrupt priority register Function Description Dynamic global interrupt processing enable disable, fast interrupt processing, tri-state external interface control. settings register enable disable interrupt processing each eight interrupt levels, IRQ0-IRQ7. Controls relative processing priorities interrupt levels. eight levels organized into three groups: Group includes IRQ0 IRQ1, group IRQ2-IRQ4, group IRQ5-IRQ7. This register contains request pending each eight interrupt levels, IRQ0-IRQ7.
Interrupt request register
MSUN
June 1996 5-20
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
SYSTEM MODE REGISTER (SYM) system mode register, (DEH, used dynamically enable disable interrupt processing level control fast interrupt processing. Enable Interrupt (EI) instruction must always included system
initialization routine enable global interrupt processing. During normal operation, manipulate SYM.0 dynamically enable disable interrupts. Fast interrupt processing configured only those interrupt levels whose pending bits cleared software. KS88C4116 interrupt structure, cannot fast interrupt processing IRQ1 IRQ2
because pending conditions these interrupts cleared automatically hardware. Timer interrupt (IRQ1) pending conditions must cleared software. Level IRQ1 "mixed" interrupt pending types that pending bits that software hardware. this case, none interrupts "mixed" level executed fast interrupt.
SYSTEM MODE REGISTER (SYM) DEH,
Tri-state external interface enable bit: used Normal operation (Tri-state disabled) Fast interrupt level High impedance selection bits: (Tri-state enabled)
Global interrupt enable bit: Disable interrupts Enable interrupts
Fast interrupt enable bit: Disable fast interrupts Enable fast interrupts
NOTE: Fast interrupt processing supported levels KS88C4116 microcontroller.
Figure System Mode Register (SYM)
MSUN
5-21
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
INTERRUPT MASK REGISTER (IMR) interrupt mask register (IMR) used enable disable interrupt processing each
eight interrupt levels, IRQ0- IRQ7. Each corresponds specific interrupt level: IRQ7, IRQ6, When interrupt level cleared "0", interrupt
processing that level disabled (masked). When level's "1", interrupt processing level enabled (not masked).
INTERRUPT MASK REGISTER (IMR) DDH,
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Interrupt level enable/disable bits: Disable interrupt processing Enable interrupt processing
Figure Interrupt Mask Register (IMR) INTERRUPT PRIORITY REGISTER (IPR) interrupt priority register (IPR) used relative priorities eight interrupt levels. order define these priorities, interrupt levels organized into groups subgroups interrupt logic. (These groups subgroups used only register priority definitions.) Three interrupt groups defined logic: Group Group Group IRQ0, IRQ1 IRQ2, IRQ3, IRQ4 IRQ5, IRQ6, IRQ7 first globally disabled clearing system mode register, SYM. After reset, register values undetermined. more than interrupt source active, source with highest priority level serviced first. both sources have same interrupt level, source with lowest vector address priority. When interrupt occurs, software automatically vectored service routines. more than active source shares that vector, software must poll individual sources connected that vector order identify interrupting source sources. controls relative priority IRQ0 IRQ1 interrupts. controls interrupt group register controls relative priorities group interrupts. Interrupt groups have subgroups provide additional priority relationship between interrupt levels. register controls subgroup relationships. Additional priority logic provided bits register. This 3-bit setting controls relative priority interrupt groups setting '001B' would select group relationship '101B' would select
Before register written, interrupt processing must
MSUN
June 1996 5-22
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
INTERRUPT PRIORITY REGISTER (IPR) FFH,
GROUP PRIORITY: UNDEFINED B>C>A A>B>C B>A>C C>A>B C>B>A A>C>B UNDEFINED
GROUP IRQ0 IRQ1 IRQ1 IRQ0
GROUP IRQ2 (IRQ3, IRQ4) (IRQ3, IRQ4) IRQ2 SUBGROUP IRQ3 IRQ4 IRQ4 IRQ4 GROUP IRQ5 (IRQ6, IRQ7) (IRQ6, IRQ7) IRQ5 SUBGROUP IRQ6 IRQ7 IRQ7 IRQ6
Figure Interrupt Priority Register (IPR)
PROGRAMMING Setting Interrupt Priorities Register
Writing value '01101011B' register would following KS88C4116 interrupt priorities: Highest Priority IRQ2 IRQ4 IRQ3 IRQ7 IRQ6 IRQ5 Lowest Priority IRQ1 IRQ0 Group
Group
Group
MSUN
5-23
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
INTERRUPT REQUEST REGISTER (IRQ) interrupt request register (IRQ) contains interrupt pending each eight interrupt levels, IRQ0-IRQ7. indicates that interrupt request pending; indicates that interrupt request pending. read (test) contents register time determine current request status specific interrupt levels.
register mapped register location values read-only addressable using Register addressing mode. After reset, register value 00H. This clears existing pending conditions interrupt levels. External interrupts disabled RESET. must execute instruction enable external interrupts. This must done before bits port port interrupt pending registers
external interrupt occurs. Application software polls register detect interrupts that controlled hardware that have been masked settings register. When polling interrupt request bits, software must clear pending when source's interrupt serviced. Writing effect because interrupt request must acknowledged source.
INTERRUPT REQUEST REGISTER (IRQ) DCH, Read-only
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 Interrupt level request pending bits: Interrupt level pending Interrupt level pending
Figure Interrupt Request Register (IRQ)
MSUN
June 1996 5-24
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
EXTERNAL INTERRUPT CONTROL REGISTERS Port Interrupt Control Register (P3CONL) 8-bit control register P3CONL (F5H, bank used enable disable external interrupts low-byte port pins, P3.0-P3.3. four bit-pairs port low-byte control register have functions: configure port3 pins input output, when input mode selected, configure interrupt signal edge detection mode that pin. Incoming signals trigger interrupt request rising falling signal edges. addition, pull-ups optionally configured software port input circuit.
Port Interrupt Enable Pending Registers (P3INT, P3PND) port interrupt control register (P3INT, FCH, bank0) used selectively enable disable interrupts each low-byte port pins. Only bits this 8-bit register used KS88C4116. poll P3PND bits software detect incoming external interrupts port interrupt pins P3.0-P3.3. Port Interrupt Control Registers (P4CONH, P4CONL) 8-bit control registers used configure port pins: P4CONH (F6H, bank high byte pins P4.4-P4.7 P4CONL (F7H, bank low-byte pins P4.0-P4.3.
addition basic input/output configuration, P4CONH P4CONL control external interrupt detection individual pins rising falling edges, with without pull-up resistors. Port Interrupt Enable Pending Registers (P4INT, P4PND) port interrupt control register (P4INT, F9H, bank0) used selectively enable disable interrupts each port pin, P4.0-P4.7. P4PND polled software detect incoming external interrupts. When interrupt acknowledged, pending must cleared software. clear pending bit, interrupt service routine must write pending location.
P3CONL, P4CONH, P4CONL SETTINGS
PORT PORT INTERRUPT INPUT
RISING EDGE TRIGGER
IRQ4 IRQ5 IRQ6 IRQ7
FALLING EDGE TRIGGER
Figure Port External Interrupt Function Diagram
MSUN
5-25
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
CLEARING INTERRUPT PENDING BITS Internally, interrupt requests represented levels. This levelactivated system requires routine that services interrupt disable interrupting source before re-enabling that interrupt. Each interrupt source (peripheral) requires pending register hold interrupt request level CPU's polling operation. Pending conditions interrupt sources cleared ways: Automatically, hardware. acknowledges interrupt level with highest priority clears interrupt source's pending bit. multiple sources multiple vectors share same interrupt level, peripheral's task break deadlock determining which highest priority, then clearing appropriate pending bit. application software. peripheral's pending register must cleared software during interrupt service routine. this, must written appropriate pending register bit.
order provide short timing delay, recommend adding least instruction immediately after instruction that clears pending bit. external interrupt inputs port port edge-triggered "interrupt pending" flip-flops used convert edge-triggered input level-activated interrupt. service routine must reset interrupt pending flip-flop order clear interrupt request. this, must written port3 port pending bit. automatically clears interrupt pending condition overflow interrupt, capture interrupt, backup timer interrupt when interrupt request serviced. remaining interrupts (timerA, timer serial data receive, serial data transmit, timerC, timer must write interrupt pending corresponding mode control register order clear interrupt source. INSTRUCTION POINTER (IP) instruction pointer (IP) used control optional high-speed
interrupt processing called fast interrupts consists register pair DBH. contains most significant (high) byte memory address least significant (low) byte. registers called (high byte, IP15-IP8) (low byte, IP7-IP0). FAST INTERRUPT PROCESSING feature called fast interrupt processing lets specific interrupt service routines completed approximately clock cycles instead usual cycles. NOTE KS88C4116, fast interrupt processing supported interrupt levels system mode register, SYM, enables fast interrupt processing. other system registers support fast interrupts: instruction pointer (IP) holds starting address service routine saves values, dedicated register, FLAGS', saves contents FLAGS register when fast interrupt occurs.
MSUN
June 1996 5-26
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PROGRAMMING Setting Interrupt Control Structure
This example shows enable interrupts select interrupt sources, disable interrupt other sources, interrupt priorities KS88C4116. sample program does following: Enable interrupts port pins P4.4-P4.7, timer timer overflow Disable timer timer UART, backup timer, P3.0-P3.3, P4.0-P4.3, PWM, capture interrupts interrupt priorities P4.4-P4.7 timer timer START
TBINT,#02H IMR,#8AH IPR,#82H TADATA,#0FH T0CON,#86H TCH,#0H TCL,#0H T1CON,#35H T1MOD,#31H P4CONH,#55H P4PND,#0FFH P4INT,#0F0H
Disable interrupts Disable timer interrupt IRQ1, IRQ3, IRQ7 selected IRQ7 IRQ1 IRQ3 Timer interrupt enable Normal baud rate, timer interrupt enable Timer disable, 16-bit timer mode timer Input, rising edge interrupt selection Reset port pending registers Enable interrupts port pins P4.4-P4.7 (All other interrupts disabled automatically reset)
Enable interrupts
MSUN
5-27
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PROGRAMMING Setting Interrupt Control Structure (Continued)
Assuming interrupt sources priorities have been above instruction sequence, could select interrupt level fast interrupt processing. following instructions enable fast interrupts level (IRQ7) only: IPH,#3000H SYM,#1EH Disable interrupts Load service routine address IRQ7 Enable fast interrupt processing Enable interrupts
PROGRAMMING Using Load Instructions Manipulate Interrupt Pending Registers
recommend using only load (LD) instructions, except LDB, manipulate interrupt pending registers. example, clear only port interrupt pending register, P4INT, following AND, instructions would invalid: P4PND,#0FDH P4PND,#02H P4PND.1,R0 Invalid logical instruction! Invalid logical instruction! Invalid (Load Bit) instruction!
instruction instead manipulate pending register bit: P4PND,#02H Only reset because writing effect; writing clears pending bit.
MSUN
June 1996 5-28
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
OSCILLATOR CIRCUITS
OVERVIEW external crystal produces maximum 12-MHz clock. XOUT pins connect external oscillation source on-chip clock circuit. MAIN OSCILLATOR CIRCUIT main oscillator circuit generates clock signal. increase processing speed reduce noise levels, nondivided logic implemented main clock circuit. SUBOSCILLATOR CIRCUIT BACKUP TIMER on-chip suboscillator circuit runs backup timer during normal operation Stop mode, event power outage. requires separate external oscillation source with typical operating frequency 32768 Very power consumption required time backup applications. this reason, suboscillator circuit much slower than main oscillator circuit. primary function provide high-resolution (accurate second) clock signal backup timer module. program real-time timing counting event power failure would following: Clear backup timer start counting; enters Stop mode. When power restored, "wakes checks backup timer count value long been "asleep." count value then added "frozen" main clock value give current time.
XOUT
KS88C4116
Figure Main Oscillator Circuit (With External Crystal Resonator) CLOCK STATUS DURING POWER-DOWN MODES power-down modes, Stop mode Idle mode, affect system clock oscillation follows: During Stop mode, main oscillator halted; contents internal register file special function registers retained. Stop mode released reset operation. Idle mode, internal clock signal gated CPU, interrupts, timers, serial port functions. status preserved, including stack pointer, program counter, flags, data contained internal register file retained. Idle mode released interrupt reset.
RESET
reset overrides other operating conditions puts KS88C4116 into known state. reset initiated holding signal RESET level least clocks. RESET signal input through Schmitt trigger circuit then synchronized with clock. following events occur during reset operation: interrupts disabled. Ports input. Peripheral control data registers disabled reset their original values. program counter loaded with ROM's reset address, 0020H. Eight clocks after RESET returns high, instruction fetched from location 0020H executed.
MSUN
5-29
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
RESET (Continued)
power-up, RESET input must held about after power supply comes within tolerance. This allows enough time internal clock oscillation stabilize. KS88C4116 Reset Operation (Masked ROM) normal (masked ROM) operating mode, tied VSS. While reset operation does enable access 16-Kbyte on-chip ROM, does automatically configure external interface. plan external interface
normal mode, must include instructions configuring interface initialization routine. Then execute reset. this case, RESET forces output while signal pulses every four clock cycles. signal remains high level. KS88C4116 Reset Operation (ROM-Less Mode) KS88C4116 microcontroller configured ROM-less device applying constant current pin. held high level (5-volt input) prior reset, ROM-less mode initiated
external interface automatically configured hardware, follows: Port control registers cleared their normal initialization values (00H); corresponding port address data lines configured external interface. low-nibble pins port (P2CONL) automatically '11B', configuring external interface signals (DM, R/W, P2.0-P2.3.
RESET
ADDRESS
0020H 0021H
DATA
OPND
Figure
RESET Timing External Interface (Masked
RESET
ADDRESS
0020H
DATA
Figure
RESET Timing External Interface (ROM-less Mode)
MSUN
June 1996
5-30
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
Table Register Values After RESET
Register Name Timer Data Register (High Byte) Timer Data Register (Low Byte) Timer Data Register (High Byte) Timer Data Register (Low Byte) Port Interrupt Pending Register System Flags Register Register Pointer Register Pointer Stack Pointer (High Byte) Stack Pointer (Low Byte) Instruction Pointer (High Byte) Instruction Pointer (Low Byte) Interrupt Request Register Interrupt Mask Register System Mode Register Register Page Pointer Mnemonic P4PND FLAGS Address Values After RESET
Table Bank Register Values After RESET
Register Name Port Data Register Port Data Register Port Data Register Port Data Register Port Data Register Port Data Register Port Data Register Backup Timer Control Register Backup Timer Extension Counter Serial Shift Register Serial Control Register Serial Interrupt Pending Register Timer Data Register Timer Data Register Timer Module Control Register Timer Control Register Mnemonic BTCON BTEXT SIOCON SIOPND TADATA TBDATA T0CON TBCON Address Values After RESET
MSUN
5-31
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
Table Bank Register Values After RESET (Continued)
Register Name Port Control Register Port Control Register Port Control Register (High Byte) Port Control Register (Low Byte) Port Control Register (High Byte) Port Control Register (Low Byte) Port Control Register (High Byte) Port Control Register (Low Byte) Port Control Register Port Interrupt Enable Register Timer Module Control Register Timer Module Mode Register Port Interrupt Enable Register Port Interrupt Pending Register External Memory Timing Register Interrupt Priority Register Mnemonic P0CON P1CON P2CONH P2CONL P3CONH P3CONL P4CONH P4CONL P5CON P4INT T1CON T1MOD P3INT P3PND Address Values After RESET
Table Bank Register Values After RESET
Register Name Converter Input Register Converter Output Register Converter Control Register Module Control Register PWM1 Data Register PWM0 Data Register Capture Register Mnemonic ADIN ADOUT ADCON PWMCON PWM1 PWM0 PWMCAP Address Values After RESET
Table External Interface Control Register Values After RESET (ROM-Less Mode)
Register Name Mnemonic Address Port Control Register (Low Byte) P2CONL Values After RESET High)
NOTE: RESET values P2CONL valid only KS88C4116 ROM-less operating mode (that when continuously applied pin).
MSUN
June 1996 5-32
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
POWER-DOWN MODES
IDLE MODE instruction IDLE (opcode 6FH) invokes Idle mode. Idle mode, "sleeps" while select peripherals remain active: KS88C4116, these peripherals module, serial port, timers timers backup timer, external interrupt logic. During Idle mode, contents system registers, control registers, data registers retained. Port pins retain mode (input output) they time Idle mode entered. There ways release Idle mode: Activate enabled interrupt, causing hardware release Idle mode. interrupt then serviced. When service routine completed, instruction immediately following that initiated Idle mode executed. Execute external reset. Because clock oscillator continues operate, reset completed hardware. interrupts masked, reset only release Idle mode. STOP MODE instruction STOP (opcode 7FH) invokes Stop mode. Stop mode, peripherals "put sleep" (that on-chip main oscillator halted). data stored internal register file current values peripheral control data registers retained. only release Stop mode executing reset. RESET must held least clock cycles. reset operation resets system peripheral control registers their default values, data register file remains unchanged. When RESET released goes high, processor restarts program from vector address 0020H. suboscillator connected backup timer module, backup timer remains active during Stop mode, assuming that connected separate oscillation source.
XTAL
MAIN OSCILLATOR
TIMERS SERIAL PORT
CLOCK DISABLE STOP IDLE
Figure Stop Idle Mode Function Diagram
MSUN
5-33
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PROGRAMMING Sample KS88C4116 Initialization Routine
following sample program shows initial program settings KS88C4116 address space, interrupt vectors, peripheral functions: Chip Definition CHIP 88C4116.DEF
User Equation Define INCLUDE EQU.TBL
Reference label vector area: 000H-00FFH 0000H
Reset Vector 0020H t,INITIAL
0023H-00B7H: Reserved
Interrupt Vector Addresses VECTOR VECTOR VECTOR VECTOR 00B8H PWMOV_int PWMCAP_int BACKUP_int TA_int IRQ1 IRQ1 IRQ2 IRQ1
00C0H-00D7H: Reserved VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR VECTOR 00D8H EXT40_int EXT41_int EXT42_int EXT43_int EXT44_int EXT45_int EXT46_int EXT47_int 00E8H EXT30_int EXT31_int EXT32_33_int IRQ5 IRQ6 IRQ6 IRQ6 IRQ7 IRQ7 IRQ7 IRQ7
IRQ4 IRQ4 IRQ4
(Continued next page)
MSUN
June 1996 5-34
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PROGRAMMING Sample KS88C4116 Initialization Routine (Continued)
VECTOR VECTOR VECTOR VECTOR 00F0H SIOINT_R SIOINT_T TC_int TD_int IRQ3 IRQ3 IRQ3 IRQ3
00F8H-00FDH: Reserved VECTOR 00FEH TB_int IRQ0
System Peripheral Initialization INITIAL: 0100H PP,#00 Disable interrupts Clear page pointer register Select bank
System register setting Interrupt settings INI_PERI_SET: Port setting Port setting Port setting P2CONL,#01100101B P2.0 input mode P2.1 input mode P2.2 output mode, push-pull P2.3 input mode P2.4 input mode P2.5, P2.6 output mode P2.7 input mode P1CON,#11H Output, push-pull P0CON,#11H Output, push-pull IPR,#16H IMR,#00001101B Interrupt priorities: IRQ3 levels enable SYM,#00000000B EMT,#00000000B SPL,#00H Fast, global interrupt disable wait internal stack area select Stack pointer byte zero
P2CONH,#01101001B
(Continued next page)
MSUN
5-35
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PROGRAMMING Sample KS88C4116 Initialization Routine (Continued)
Port setting Port setting Port setting P5CON,#11H Output, push-pull P4CONL,#00000000B P4CONH,#11111111B P4INT,#00H P4.0-P4.3 input mode P4.4-P4.7 output, push-pull interrupts disabled P3CONL,#10101010B P3CONH,#10101010B P3INT,#00H P3.0-P3.7 input mode with pull-up Disable port interrupts
Port always n-channel, open-drain, output mode Timer TADATA,#17H T0CON,#00000110B clock divided clock 11.0592 clock /1024 1.66 Interval mode Interrupt enable
Timer Timer Timer TDL,#0FAH TDH,#0FAH T1CON,#00110011B TBINT,#02H Disable timer interrupt 16-bit free-running timer, interrupt baud rate generator 9600 clock 11.0592 Start value Auto-reload value 9600 4800 Normal baud rate Timer pending clear Timer interrupt disable Timer enable Timer gate function disable Timer clock clock Timer 16-bit timer mode Timer Auto-reload mode
T1MOD,#00100000B
(Continued next page)
MSUN
June 1996 5-36
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PROGRAMMING Sample KS88C4116 Initialization Routine (Continued)
SIO(UART) SIOCON,#01010010B Mode 8-bit UART, variable baud rate Multiple-bit clear Receive enable Receive interrupt enable Transmit interrupt disable Pending clear
SIOPND,#03
Register Initialization #0C0H
Clear data registers 00H-0FFH page RAMCLR: DJNZ
R0,#0FFH R0,RAMCLR
Initialize other registers
Must executed this position before external interrupt executed
Main Loop MAIN:
Start main loop
CALL
KEY_SCAN
CALL
LED_DISPLAY
CALL
t,MAIN
(Continued next page)
MSUN
5-37
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PROGRAMMING Sample KS88C4116 Initialization Routine (Continued)
Subroutine KEY_SCAN:
Subroutine LED_DISPLAY:
Subroutine JOB:
Interrupt Service Routine TA_int: PUSH PUSH
#TA_REG
TA_REG
IRET
T0CON,#00000110B
Pending clear
(Continued next page)
MSUN
June 1996 5-38
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PROGRAMMING Sample KS88C4116 Initialization Routine (Concluded)
Other Interrupt Vectors EXT30_int: EXT31_int: EXT32_33_int: IRET EXT40_int: EXT41_int: EXT42_int: EXT43_int: EXT44_int: EXT45_int: EXT46_int: EXT47_int: IRET SIOint_R: SIOint_T: IRET TC_int: TD_int: IRET BACKUP_int: IRET TB_int: IRET PWMOV_int: PWMCAPint: IRET TBINT,#02H T1CON,#00110011B SIOPND,#03H P4PND,#0FFH P3PND,#0FH
MSUN
5-39
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PORTS
OVERVIEW pins KS88C4116 package, pins used I/O. There eight ports (see Table 13). Each port configured software meet varied system configuration design requirements. accesses port directly writing reading port's data register. this reason, special instructions required. Ports alternatively configured address data lines signal lines external peripheral interface. 8-bit input port receive analog data converter module, serve general input port (port
Table KS88C4116 Port Configuration Overview Port Configuration Options General port; configured external address lines A8-A15 external interface. General port; configured multiplexed address/data lines AD0-AD7 external interface. General port; lower nibble pins (P2.0-P2.3) used alternately signal lines external interface; P2.4 general only; P2.5 used end-of-conversion output signal (EOC) converter; P2.6 P2.7 configured timer module (timer timer outputs. Programmability Nibble programmable Nibble programmable programmable
General port; lower nibble pins (P3.0-P3.3) programmable used alternately inputs timer module external interrupt inputs INT0-INT3; upper nibble pins P3.4 P3.5 general only; P3.6 configured capture input module; P3.7 used external device WAIT signal input. General port; alternately serve external interrupt inputs INT4-INT11. General port with high current capability. N-channel, open-drain output with high current capability. Analog input channels ADC0-ADC7; alternately used general input port. programmable Nibble programmable Output mode only programmable
MSUN
June 1996 5-40
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PORT Port pins P0.0-P0.7 configured nibble basis general data input output. When configured outputs, pins each nibble optionally open-drain. Port0 alternatively configured additional address lines (A8-A15) external peripheral interface. possible configure lower nibble external interface address lines
A8-A11, upper nibble pins general I/O. access port write read port data register, (E0H) bank port data register cannot written port bits configured address lines external interface: write operations have effect read operations only return state pin. normal operating mode (that when state
low) reset operation clears P0CON register values "0". ROM-less operating mode, reset automatically configures P0.0-P0.7 address lines external interface. Physically, P0CON reset normal initialization value, 00H. Logically, reset automatically configures port external interface mode (assuming that being input pin).
PORT CONTROL REGISTER (P0CON) F0H, Bank
Upper nibble port configuration
Lower nibble port configuration Port Mode Selection Input, Schmitt trigger Input, Schmitt trigger, pull-up Output, push-pull Output, open-drain Output, open-drain, pull-up External interface (A8-A15)
('x' means don't care.)
Figure Port Control Register (P0CON)
MSUN
5-41
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PORT Port identical port except that alternately used address data lines external interface. (Port alternately configured address lines A8-A15.)
access port write read port data register, (E1H), bank port data register cannot written, however, when port bits normal operating mode, reset clears P0CON 00H. ROM-less operating mode, reset operation automatically
configures high-nibble lownibble lines port (P1.0-P1.7) address/data lines AD0-AD7 external interface. Physically, P1CON reset normal initialization value, 00H. Logically, reset automatically configures port external interface mode.
PORT CONTROL REGISTER (P1CON) F1H, Bank
Upper nibble port configuration
Lower nibble port configuration Port Mode Selection Input, Schmitt trigger Input, Schmitt trigger, pull-up Output, push-pull Output, open-drain Output, open-drain, pull-up External interface (AD0-AD7)
('x' means don't care.)
Figure Port Control Register (P1CON)
MSUN
June 1996 5-42
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PORT Port 8-bit port with individually configurable pins. accessed directly writing reading port2 data register, (E2H), bank P2CONH control register (F2H, bank configures pins P2.4-P2.7, P2CONL (F3H, bank configures pins P2.0-P2.3. port general I/O, following alternative functions: nibble pins P.0-P2.3 configured external interface control lines (data memory), (read/write), (data strobe), (address strobe) signals. P2.4 general only. P2.5 configured end-of-conversion signal
output (EOC) converter. P2.6 P2.7 configured, respectively, timer timer output. that special functions programmed using port high-byte control register (the converter timers must also enabled associated peripheral device. Please also remember that when port2 pins functions other than general I/O, must still corresponding port control register value configure each input output mode. PORT OPERATION NORMAL ROM-LESS MODES normal operating mode, reset clears P2CONL P2CONH register settings "0". This
configures port pins normal input mode. ROM-less operating mode, reset sets P2CONL P2CONH values, follows: P2CONH (P2.4-P2.7) cleared '00H', configuring high-byte pins Schmitt trigger input mode. P2CONL (P2.0-P2.3) automatically 'FFH', configuring low-byte pins control signal lines external interface. When using ROM-less mode, control P2CONL values automatically passed external interface control logic after reset. should modify these values.
PORT CONTROL REGISTER, HIGH BYTE (P2CONH) F2H, Bank
/EOC P2CONH Bit-Pair Configuration Settings: Schmitt trigger input Push-pull output Select alternate function (except P2.4)
('x' means don't care.)
Figure Port High-Byte Control Register (P2CONH)
MSUN
5-43
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PORT CONTROL REGISTER, BYTE (P2CONL) F3H, Bank
P2CONL Bit-Pair Configuration Settings: Schmitt trigger input Push-pull output External memory interface line
('x' means don't care.)
Figure Port Low-Byte Control Register (P2CONL)
MSUN
June 1996 5-44
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PORT Port 8-bit port with individually configurable pins. Port3 used general I/O, following alternative input mode functions (except P3.4 P3.5, which general only): Pins P3.0 P3.1 used clock inputs timer/counters share names TCCK TDCK, respectively. Pins P3.2 P3.3 configured gate signal inputs timer timer (TCG TDG, respectively) lower nibble port pins (P3.0-P3.3) also serve
external interrupt inputs INT0- INT3, respectively P3.6 used capture data input module (CAP) P3.7 used WAIT signal input line external interface (WAIT) Port accessed directly writing reading port data register, (E3H) bank0. Each configured Schmitt trigger input push-pull output. configure port input mode, alternative input function also configured. special functions
configure using port control registers WAIT, CAP, TDG, TCG, TDCK TCCK must also enabled associated peripheral control register. When port pins functions other than general I/O, remember that port control registers must still programmed specify which pins input mode which output mode. 8-bit control registers used configure port pins: P3CONH P3CONL. Figures show control settings port interrupt enable register P3INT port interrupt pending register P3PND.
PORT CONTROL REGISTER, HIGH BYTE (P3CONH) F4H, Bank
/CAP /WAIT P3CONH Bit-Pair Configuration Settings: Schmitt trigger input Schmitt trigger input, pull-up Push-pull output
('x' means don't care.)
NOTES: alternate function P3.6 P3.7 automatically configured when input mode. enable WAIT input function, must first make appropriate settings PWMCON registers, respectively.
Figure Port High-Byte Control Register (P3CONH)
MSUN
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June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PORT CONTROL REGISTER, BYTE (P3CONL) F5H, Bank
/TCCK /TDCK /TCG /TDG P3CONL Bit-Pair Configuration Settings: Schmitt trigger input, falling-edge interrupt Schmitt trigger input, rising-edge interrupt Schmitt trigger input, falling-edge interrupt, pull-up Push-pull output
NOTES alternate function pins P3.3-P3.0 configured three input mode selections. enable alternate timer module input function, must first make appropriate settings T1MOD register.
Figure Port Low-Byte Control Register (P3CONL)
PORT INTERRUPT ENABLE REGISTER (P3INT) FCH, Bank
mapped KS88C4116 P3.3 /INT3
P3.2 /INT2
P3.1 /INT1
P3.0 /INT0
Port interrupt control settings: Disable interrupt P3.n Enable interrupt P3.n
Figure Port Interrupt Enable Register (P3INT)
PORT INTERRUPT PENDING REGISTER (P3PND) FDH, Bank
mapped KS88C4116 P3.3 /INT3 P3.2 /INT2
P3.1 /INT1
P3.0 /INT0
Port interrupt request pending bits: Interrupt request pending Interrupt request pending
Figure Port Interrupt Pending Register (P3PND)
MSUN
June 1996 5-46
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PORT Port serve generalpurpose 8-bit port pins configured individually external interrupt inputs. inputs Schmitt-triggered. Port accessed directly writing reading port data register, (E4H) bank Port Control Registers direction each port configured bit-pair settings control registers: P4CONH (high byte, F6H, bank P4CONL (low byte, F7H,
set1, bank P4CONH controls pins P4.0-P4.3 P4CONL controls pins P4.4-P4.7. Port Interrupt Enable Pending Registers (P4INT, P4PND) process external interrupts, additional control registers provided: port interrupt enable register, P4INT (F9H, set1, bank port interrupt pending register, P4PND (D4H, port interrupt pending register P4PND lets check
interrupt pending conditions clear pending condition when interrupt request been serviced. Incoming interrupt requests detected polling P4PND values. When interrupt enable port "1", rising falling signal edge that generates interrupt request. (When port interrupt request serviced, interrupt pending must cleared software writing corresponding P4PND bit.
PORT CONTROL REGISTER, HIGH BYTE (P4CONH) F6H, Bank
/INT8 /INT9 /INT10 /INT11 P4CONH Bit-Pair Configuration Settings: Schmitt trigger input, falling-edge interrupt Schmitt trigger input, rising-edge interrupt Schmitt trigger input, falling-edge interrupt, pull-up Push-pull output
Figure Port High-Byte Control Register (P4CONH)
MSUN
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June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PORT CONTROL REGISTER, BYTE (P4CONL) F7H, Bank
/INT4 /INT5 /INT6 /INT7 P4CONL Bit-Pair Configuration Settings: Schmitt trigger input, falling-edge interrupt Schmitt trigger input, rising-edge interrupt Schmitt trigger input, falling-edge interrupt, pull-up Push-pull output
Figure Port Low-Byte Control Register (P4CONL)
PORT INTERRUPT ENABLE REGISTER (P4INT) F9H, Bank
P4.6 P4.7 /INT10 /INT11
P4.5 /INT9
P4.4 /INT8
P4.3 /INT7
P4.2 /INT6
P4.1 /INT5
P4.0 /INT4
Port interrupt control settings: Disable interrupt P4.n Enable interrupt P4.n
Figure Port Interrupt Enable Register (P4INT)
PORT INTERRUPT PENDING REGISTER (P4PND) D4H,
P4.7 /INT11
P4.6 /INT10
P4.5 /INT9
P4.4 /INT8
P4.3 /INT7
P4.2 /INT6
P4.1 /INT5
P4.0 /INT4
Port interrupt request pending bits: Interrupt request pending Interrupt request pending
Figure Port Interrupt Pending Register (P4PND)
MSUN
June 1996 5-48
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PORT Port general-purpose 8-bit port with nibble-programmable pins. Port accessed directly writing reading port data register, (E5H) bank PORT Port n-channel, open-drain output port. designed high-
voltage applications withstand loads 9volts. access port directly addressing data register bank Because port configuration options, does have control register. PORT 8-bit input port (pins 46-50) used either
analog inputs converter module (ADC0-ADC7) general input port pins P7.0-P7.7. Incoming port data values read directly from converter's 8-bit digital input register ADIN, located bank address F9H.
PORT CONTROL REGISTER (P5CON) F8H, Bank
Upper nibble port configuration (P5.4-P5.7)
Lower nibble port configuration (P5.0-P5.3) Port Mode Selection Schmitt trigger input Schmitt trigger input, pull-up Output, push-pull Output, open-drain Output, open-drain, pull-up
('x' means don't care.)
Figure Port Control Register (P5CON)
MSUN
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June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PROGRAMMING Configuring KS88C4116 Port Pins Specification
This example shows configure KS88C4116 ports according sample specifications. program configures port through port follows: P0.0-P0.3 open-drain output mode P0.4-P0.7 input mode with pull-up P1.0-P1.7 push-pull output mode P2.0-P2.7 input mode P3.0 input mode P3.1-P3.7 push-pull output mode P4.0-P4.4 push-pull output mode P4.5 input mode with rising-edge interrupts P4.6 input mode with falling-edge interrupts P4.7 input mode, falling-edge interrupts, push-pull P5.0-P5.7 open-drain output mode with pull-up Port automatically output mode, open-drain type (there port control register)
P0CON,#43H P1CON,#11H P2CONH,#00H P2CONL,#00H P3CONH,#0FFH P3CONL,#0FEH P3INT,#00H P4CONH,#087H P4CONL,#0FFH P5CON,#77H P4PND,#0FFH P4INT,#0E0H
P0.0-P0.3 output, open-drain P0.4-P0.7 input, pull-up resistor P1.0-P1.7 output, push-pull P2.4-2.7 input mode P2.0-P2.3 input mode P3.1-P3.7 output, push-pull P3.0 input, timer clock input enable Disable interrupts INT0-INT3 P4.7 input, falling edge interrupt, pull-ups P4.6 input, falling edge interrupt P4.5 input, rising edge interrupt P4.0-P4.4 output, push-pull P5.0-P5.7 output, open-drain, pull-ups Reset pending register bits port interrupts Enable port interrupts
MSUN
June 1996 5-50
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
TIMER MODULE
OVERVIEW KS88C4116 timer module (T0) 8-bit timer/counters, called timer timer Each timer 8-bit counter register, 8-bit data register, 8-bit comparator, corresponding output pin. control registers, T0CON TBCON, control timer module operation. Timers continuously. Counter values cannot modified reset because they have mapped register addresses. TIMER OPERATING MODES Timers operate either interval mode pulse width modulation (PWM) mode. T0CON register controls timer operating mode, TBCON register controls operating mode timer TIMER CLOCK INPUT Timers driven same clock input. There options timer clock input: non-scaled clock clock divided 1024 (decimal). When (bit T0CON register "0", module runs divided-by1024 clock. When "1", runs non-scaled clock pulse. clock frequency scaled using 4-bit prescaler bits T0CON register (TPS3-TPS0). TIMER TIMER INTERRUPT CONTROL interval mode, both timers generate match signal when count value referenced data value TADATA TBDATA register same. When interrupt enable timer timer interrupt generated when match detected. corresponding count register cleared counting resumes. enable timer interrupt, ETAI (bit T0CON register. enable timer interrupt, ETBI (bit TBCON register. timer interrupt pending bits, TAIP TBIP, located T0CON TBCON registers, respectively. These bits polled software detect interrupt pending conditions. When timer timer pending read operation shows value, interrupt pending; when "1", interrupt request pending. When request acknowledged service routine starts, pending must cleared software. this, write TAIP TBIP bit.
ETAI TIMER INTERRUPT (IRQ1, BEH) P2.6
COUNT
8-BIT
TAIP
(T0CON)
COMPARATOR
MATCH 8-BIT
FORMAT
EAPWM TADATA 1024 4-BIT PRESCALER
ETBI TIMER INTERRUPT (IRQ0, FEH) P2.7
COUNT
8-BIT
TBIP
COMPARATOR
MATCH 8-BIT
FORMAT
EBPWM TBDATA
Figure Timer Function Block Diagram
MSUN
5-51
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
TIMER MODULE CONTROL REGISTER (T0CON) EEH, (TAIP R/W)
TPS3 TPS2 TPS1 TPS0 ETAI TAIP
EAPWM
4-bit prescaler timer clock input Timer clock source select bit: clock divided 1024 clock (non-scaled frequency) Timer interrupt enable: Timer interrupt disabled Timer interrupt enabled
NOTES:
Ttimer mode selection bit: Select interval mode Select mode
Timer interrupt pending bit: Timer interrupt pending Timer interrupt pending
avoid possible programming errors, recommend using Load instructions (except LDB) manipulate T0CON register values. TAIP (bit only readable T0CON register. must write TAIP reset (clear) timer interrupt pending condition. Writing effect.
Figure Timer Module Control Register (T0CON) TIMER MODULE FUNCTION DESCRIPTION Timer timer operate interval mode pulse width modulation mode, selected EAPWM (T0CON.0) EBPWM (TBINT.0). Timer functions exactly same timer Interval Mode interval mode, level toggles during high period timer clock cycle each match timer's count value TADATA register value. remains high level other times. With each match, timer reset zero. interval mode, pulse width fixed. interval which pulse occurs determined combination timer frequency value written data register. Pulse Width Modulation Mode mode, timer data register written CPU. This value then used modulate pulse width output pin. toggles frequency equal selected timer input clock, divided (that prescaler output). However, duty cycle ranging from 99.6%, based value TADATA register. contents TADATA register compared 8-bit count value. toggles whenever TADATA value greater than value. example, assume input clock timer MHz. toggles high every 64µs (4MHz divided 256). timer data register value (128 decimal), will remain cycles (32µs), cycles, producing duty cycle (128/256). value timer data register (true after reset), results constant from pin. value would therefore generate 99.6% duty cycle (255/256).
MSUN
June 1996 5-52
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
CLOCK:
TIMER DATA REGISTER VALUES:
NOTES: generate timer clock, 4-bit prescaler value '0010B' used. Note that timer uses divided-by-1024 clock source, addition 4-bit prescaler value.
Figure Timer Waveforms Interval Mode
TIMER CLOCK: TIMER DATA REGISTER VALUES:
100H
200H
TIMER CYCLE:
NOTE: 4-MHz timer clock value prescaler value assumed.
Figure Timer Waveforms Pulse Width Modulation Mode
MSUN
5-53
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
TIMER CONTROL REGISTER (TBCON) timer clock source controlled T0CON register. Timer also separate control register called TBCON, located bank TBCON register three functions:
Select timer operating mode (interval PWM) Enable timer interrupt Control timer interrupt pending condition least significant TBCON register called EBPWM bit. When "0", timerB operates interval timer mode; when "1", timer operates mode.
TBCON (ETBI) timer interrupt enable bit. (TBIP) timer interrupt pending bit. Application software poll TBIP detect timer interrupt pending conditions. When interrupt acknowledged service routine started, TBIP must cleared software. this, write position (writing effect).
TIMER CONTROL REGISTER (TBCON) EFH, Bank (EBPWM write-only)
ETBI TBIP EBPWM
used KS88C4116 Timer interrupt enable bit: Disable timer interrupt Enable timer interrupt Timer interrupt pending bit: pending (when read) Pending (when read) Timer mode select bit: Select normal interval timer mode Select mode
NOTES: timer mode select bit, EBPWM, write-only. clear timer interrupt pending condition, write logic ("1") TBIP bit. Writing effect. avoid errors, recommend using Load instructions (except LDB) modify TBCON register values.
Figure Timer Control Register (TBCON)
MSUN
June 1996 5-54
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PROGRAMMING Configuring Timer Timer
This example sets timer normal interval mode, disables timer sets oscillation frequency timer clock, determines execution sequence that follows timer interrupt. program parameters are: Timer used interval mode; timer interval approximately milliseconds Timer disabled Oscillation frequency executed after timer interrupt VECTOR VECTOR
0020H T,START 00BEH TA_int 00FEH TB_int 0100H
Reset address Timer interrupt vector Timer interrupt vector
START
PP,#00H T0CON,#56H
TADATA,#01H TBCON,#02H
page pointer (for divide-by-6) clock /1024 selected timer Enable timer interrupt, reset timer pending register Select interval mode timer TADATA (divided two) /1024 Disable timer interrupt Enable interrupts
TA_int
PUSH SRP0 IRET
#90H R0,R1 R0,R2 R0,R3 R0,R4 T0CON,#56H
Save stack Reset timer pending register Restore register pointer value Return from interrupt service routine
TB_int
IRET
TBCON,#02H
MSUN
5-55
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
TIMER MODULE
OVERVIEW KS88C4116 16-bit timer/counters, called timer timer Both configured operate either timers event counters. functional components timer module summarized follows: Timer module control register (T1CON) Timer module mode register (T1MOD) Timer high-byte count registers (TCH, TDH) Timer low-byte count registers (TCL, TDL) Timer gate (TCG /P3.2) Timer gate (TDG /P3.3) Timer external clock input (TCCK /P3.0) Timer external clock input (TDCK /P3.1) Timer module operate four different modes: Mode Mode Mode Mode 13-bit timer/counter 16-bit timer/counter 8-bit auto-reload timer/counter 8-bit timer/counters TDCK timer external input sampled every fifth clock pulse. When high-level sample immediately followed lowlevel sample (that when 1-to-0 transition occurs), count register incremented one. (Note that count value written count register five clocks after which 1-to-0 transition detected.) therefore takes complete sampling cycles clocks) recognize 1-to-0 transition. There restrictions duty cycle external signal input, ensure that given level sampled least once before changes, should held least clocks. TIMER MODULE MODE REGISTER (T1MOD) timer mode register T1MOD (FBH, bank controls following functions: Clock source selection timer/counter operation Gate function enable/disable Operating mode selection (four available modes) lower nibble bits (0-3) correspond timer upper nibble bits (4-7) correspond timer After reset, T1MOD values cleared zero. This '00H' setting selects clock (divided six) clock source, disables gate function, configures timers 13-bit timer/counter mode. Clock Source Selection Options Timers both have clock source selection options: internal clock pulse, divided external clock source. divided-by-6 clock selected timerC timer clock (TxC "0"), timer acts interval timer. external clock selected (TxC "1"), functions event counter external device. clock source selection bits T1MOD timer (TCC) timer (TDC). external clock source used, corresponding input must configured: timer clock input TCCK (P3.0, 25); timer external clock input TDCK (P3.1, 24). port low-byte control register P3CONL configure clock input pins this function. Gate Function Enable Timers have gate function enable bits T1MOD register: (GCE) timer (GDE) timer After reset, bits cleared gate function turned off. timers enabled four timer module1 operating modes, independently gate control function. Timer Module Operating Modes bit-pairs T1MOD (bit-pair timer bit-pair timer used select four available operating modes timer module Operating modes functionally identical both timers. Mode however, operates differently timer
When used interval timer, corresponding count register incremented based internal timer clock rate. timer clock selected either external clock source, divided-by-six clock. When used event counter, timer's count register incremented response 1-to-0 transitions external input (TCCK timer
MSUN
June 1996 5-56
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
TIMER MODULE MODE REGISTER (T1MOD) FBH, TDM1 TDM0 TCM1 TCM0
Timer gate enable bit: Disable gate function Enable gate function Timer clock input selection bit: clock (interval timer function) External clock input; (event counter function, max. input freq.:
Timer mode select bits (see table below) Timer clock input selection bit: clock (interval timer function) External clock input (event counter function, max. input freq.:
Timer gate enable bit: Timer mode select bits Disable gate function (see table below) Enable gate function
Operating Mode Description 13-bit timer/counter mode. 16-bit timer/counter; cascaded. 8-bit auto-reload timer/counter; holds value reloaded into count register each time overflows. Timer operates 8-bit timer/counter controlled standard timer control bits; 8-bit timer only that controlled using timer control settings. Timer Timer/counter disabled.
TxM1 TxM0
NOTES: When enable gate function timer timer (GxE "1"), timer incremented only when held high, corresponding timer enable T1CON register. When "0", corresponding timer enabled whenever set. means timer timer
Figure Timer Module Mode Register (T1MOD) TIMER MODULE CONTROL REGISTER (T1CON) timer control register T1CON (FAH, bank0) controls timer functions: Timer/counter enable bits Interrupt enable interrupt pending bits Baud rate selection (for UART baud rate generation) reset clears T1CON values zero (00H). This setting disables timers disables timer module interrupt processing, selects normal baud rate setting UART baud rate generator function. T1CON.6 mapped. avoid possible program errors, recommend using Load instructions only (except LDB) manipulate T1CON values. Timer/Counter Control Bits T1CON.0 T1CON.1 (TCE TDE, respectively) timer timer control bits. timer/counters started stopped independently each other. Before enabling timer setting "1", first make necessary T1MOD settings clock source, operating mode, gate function.
MSUN
5-57
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
Interrupt Control Function External interrupts gated timer module through pins (pin respectively). gate function enabled externally when these pins input appropriate P4CONL control settings. When using gate function, external interrupt INT4 gated timer INT5 gated timer This lets timer event counter external device. timer interrupt enable bits (TCIE) timer (TDIE) timer Each timer interrupt pending that serves flag
gated external interrupts. These flags polled software: (TCIP) pending timer (TDIP) pending timer interrupt. When appropriate interrupt enable enabled, interrupt request will branch that timer's interrupt vector location whenever pending flag "1". (The branch occurs, however, only after current instruction executed, other interrupts with higher priority being serviced.) pending flag cleared hardware when branch occurs; must clear writing appropriate pending
T1CON register (writing effect). Baud Rate Generator Function timer module baud rate generator UART module. T1CON register (BSEL) baud rate selection bit. setting selects normal baud rate based timer module clock source (either clock/6 external clock source). setting doubles frequency normal baud rate selection. select double baud rate, must also UART module operate mode (mode operation allowed).
TIMER MODULE CONTROL REGISTER (T1CON) FAH, Bank
BSEL TDIP TCIP TDIE TCIE
Baud rate selection bit: Normal baud rate Double baud rate used Timer interrupt pending flag: interrupt pending Interrupt pending Timer interrupt pending flag: interrupt pending Interrupt pending
NOTES:
Timer enable bit: stop; Timer enable bit: stop; Timer interrupt enable bit: Disable timer interrupt Enable timer interrupt Timer interrupt enable bit: Disable timer interrupt Enable timer interrupt
complex read/write characteristics T1CON register, avoid possible program errors, recommend using Load instructions only (except LDB) manipulate T1CON register values. BSEL double baud rate generation, UART module must operate mode (that UART mode valid selection).
Figure Timer Module Control Register (T1CON)
MSUN
June 1996 5-58
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
clk/6 TxCK
(TxL) 5-bit Up-counter 3-bit TxM0 TxM1 TxIP IRQ5
TxM0 TxM1 TxM0
TxM1
8-bit Up-counter (TxH)
Figure Timer Block Diagram
MSUN
5-59
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
TIMER MODULE GATE FUNCTION DESCRIPTION port pins (P3.0 P3.1) available interrupt input gate pins timers These pins normally serve input ports external interrupts INT0 INT1, respectively. P3.0 /INT0 used timer gate TCG, P3.1 /INT1 used timer gate, TDG. enable gate function:
corresponding timer T1CON register (TCE TDE) must "1". corresponding external interrupt must configured input mode must high level. gate function lets timer measure duration pulses applied external interrupt relative timer's count source.
pin's interrupt function enabled, will continue trigger corresponding external interrupt. interrupt service routine then read counter value that accumulated while signal high level. this way, timer module event counter external device.
CLOCK TIMER/COUNTER EXTERNAL CLOCK INPUT (TCCK, TDCK) TIMER ENABLE (TxE) GATE ENABLE (GxE) GATE (TxG) NOTES: clock same fOSC configuration count registers determined mode selection T1MOD register. CONTROL TxIP BITS) TxIE
BITS)
TIMER INTERRUPT
Figure Timer Module Gate Function Block Diagram
MSUN
June 1996 5-60
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
GATE (TxG)
COUNTER VALUE
INCREASING
INCREASING
INCREASING INT0 INT1 ISSUED
INT0 INT1 ISSUED
Figure Count Value Incrementing With Gate Function Enabled TIMER MODULE MODE OPERATION Mode operation functionally identical timers mode corresponding count registers (TxH, TxL) configured 13-bit timer/ counter with divide-by-32 prescaler. reset automatically selects mode Eight bits high-byte count register (TxH) used 8-bit counter; five lower bits low-byte count register (TxL) used 5-bit counter. value upper three bits undetermined should ignored. Both registers read write addressable. value 8-bit counter (TxH) undetermined after reset. Enabling timer setting does automatically clear count value; must clear software. When count overflows, timer's interrupt pending flag TxIP (T1CON bits "1". interrupt pending flags polled software control timer interrupt processing.
13-BIT TIMER/COUNTER
TxIE
EXTERNAL CLOCK INPUT (TCCK, TDCK) TIMER ENABLE (TxE) GATE ENABLE (GxE) GATE (TxG)
CONTROL
BITS)
BITS)
TxIP
TIMER INTERRUPT
Figure Timer Module Mode Function Diagram
MSUN
5-61
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
TIMER MODULE MODE OPERATION Mode same mode except that 8-bit timer counters (TxH TxL) operate together 16-bit event counter. TIMER MODULE MODE OPERATION Mode establishes timer registers 8-bit counter
(TxL) that automatically reloaded with 8-bit value stored register when counter overflows. When counter overflow occurs, corresponding interrupt pending flag (TxIP) T1CON register "1", counter reloaded with value stored TxH, counting resumes.
reload value that stored must preset software. reload value unchanged reload operation. Assuming that appropriate interrupt enable (TxIE) T1CON register set, timer's interrupt pending flag then polled generate timer timer interrupt request.
16-BIT TIMER/COUNTER
TxIE
EXTERNAL CLOCK INPUT (TCCK, TDCK) TIMER ENABLE (TxE) GATE ENABLE (GxE) GATE (TxG)
CONTROL
BITS)
BITS)
TxIP
TIMER INTERRUPT
Figure Timer Module Mode Function Diagram
TIMER/COUNTER
TxIE
EXTERNAL CLOCK INPUT (TCCK, TDCK) TIMER ENABLE (TxE) GATE ENABLE (GxE) GATE (TxG)
CONTROL
BITS) RELOAD TxIP BITS)
TIMER INTERRUPT
Figure Timer Module Mode Function Diagram
MSUN
June 1996 5-62
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
TIMER MODULE MODE OPERATION Unlike modes mode3, timer functions separate 8-bit counters while timer does operate. select mode TCM1/M0 bit-pairs T1MOD register '11B.' This setting establishes timer count registers, TCH, separate counters with difference: 8-bit
(fOSC
timer/counter 8-bit timer only (that external input). program mode operation, must also write appropriate values timer mode control bits T1MOD register. With locked into timer function counting internal clocks, assumes control timer interrupt control bits. "timer interrupt" thereby generated timer counter.
When timer operate mode timer turned switching mode operating status, used serial port baud rate generator. Timer used mode during timer mode application that does require generate interrupt.
TIMER/COUNTER
TCIE
EXTERNAL CLOCK INPUT (TCCK) TIMER ENABLE (TCE) GATE ENABLE (GCE) GATE (TCG)
CONTROL
BITS)
TCIP
TIMER INTERRUPT
TDIE TIMER ONLY (fOSC CONTROL TIMER ENABLE (TDE) TDIP (8-BIT)
TIMER INTERRUPT
Figure Timer Module Mode Function Diagram
MSUN
5-63
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PROGRAMMING Timer Module Operating Mode
This example shows program timer module (timers operate 13-bit timer/counter mode (that mode parameters sample program are: Only timer used this example; timer disabled clock frequency Timer input clock Timer interrupts occur 2-ms intervals Each timer interrupt toggles P0.0
START
TIMER INTERRUPT
SYSTEM INITIALIZATION; TIMER MODE SETTINGS
1830H
TOGGLE P3.0; CLEAR TIMER PENDING MAIN
IRET
Figure Timer Module Mode Programming Flowchart START
Disable interrupts System initialization settings P0CON,#11H TCH,#0C1H TCL,#10H T1MOD,#30H T1CON,#35H Port output push-pull mode select 07D0H counter value equal 2000H 07D0H 1830H (TCH, TCL) 1830H bits 1830H '10H' Bits 5-12 1830H 'C1H' Timer disable, timer 13-bit timer mode select, timer clock clock Timer interrupt enable; timer enable Enable interrupts
MAIN
(Continued next page)
MSUN
June 1996 5-64
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PROGRAMMING Timer Module Operating Mode (Continued)
CALL
other
T,MAIN
Then, timer overflow interrupt service routine (TC_INT): TC_INT: IRET TCH,#0C1H TCL,#10H TCH,#00H P0,#01H T1CON,#35H 1830H just 5-bit counter Toggle P0.0 Clear timer pending Return from interrupt
PROGRAMMING Timer Module Operating Mode
This example shows program timer module (timers operate 16-bit timer/counter mode (that mode parameters sample program are: clock frequency Clock input pulse TCCK unknown frequency Clock input pulse timer gate (TCG) equal 62.5 (50% duty) Interrupt INT2 occurs with each falling edge Program Function Description Timer operates frequency counter. unknown frequency being input through timer clock input (TCCK). Suppose, however, that frequency range TCCK less than kHz. Using reference pulse timer gate input (TCG), count unknown clock pulses TCCK during 8-ms interval (1/62.5 timer count value saved into B_TC0 B_TC1 hexadecimal format. values B_TC0 B_TC1 actual frequency value kHz.
(62.5 TCCK
SAMPLING TIME
Figure Timer Module Mode Timing Diagram
MSUN
5-65
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
START
EXTERNAL INTERRUPT INT2
SYSTEM INITIALIZATION; TIMER MODE SETTINGS
B_TC0 B_TC1
MAIN
(B_TC0, B_TC1)
(B_TC0, B_TC1)
CLEAR TIMER CLEAR P3.2 INT2 PENDING
IRET
Figure Timer Module Mode Programming Flowchart B_TC0 B_TC1 START
Timer data buffer register Disable interrupts System initialization settings
P3CONL,#00H P3INT,#04H P3PND,#0FH TCH,#0000H T1MOD,#3DH T1CON,#31H
TCCK input mode select (INT2) falling-edge input select P3.2 /TCG interrupt enable Clear pending Initialize timer counter Disable timer enable input, timer clock external clock input select, 16-bit counter mode select Disable timer interrupt, timer enable Enable interrupts
MAIN
CALL
other
T,MAIN
MSUN
June 1996 5-66
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PROGRAMMING Timer Module Operating Mode (Concluded)
external interrupt occurs P3.2 /TCG 16-ms intervals (falling edges): EXTINT_TCG: IRET B_TC0,TCH B_TC0 B_TC1 B_TC0 B_TC1 B_TC0 B_TC1 TCH,#0000H P3PND,#04H Count value detection (two bytes) (B_TC0, B_TC1) (B_TC0, B_TC1) (B_TC0, B_TC1) (B_TC0, B_TC1)
(B_TC0, B_TC1) (B_TC0, B_TC1) value B_TC0, B_TC1 indicates clock frequency TCCK kHz) Clear P3.2 (INT2) pending
PROGRAMMING Timer Module Operating Mode
This example shows program timer module (timers operate auto-reload timer/counter mode (that mode parameters sample program are: clock frequency Clock input pulse TCCK (square wave) Timer operates auto-reload mode using external clock input Timer interrupt occurs 0.5-second intervals level P3.4 toggles whenever interrupt occurs
START TIMER INTERRUPT SYSTEM INITIALIZATION; TIMER MODE SETTINGS
TOGGLE P3.4; CLEAR TIMER PENDING
MAIN
IRET
Figure Timer Module Mode Programming Flowchart
MSUN
5-67
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PROGRAMMING Timer Module Operating Mode (Continued)
START
Disable interrupts System initialization settings P3CONH,#11H P3CONL,#00H TCL,#(0FFH-1EH) TCH,#(0FFH-1EH) T1MOD,#36H P3.4-P3.7 output, push-pull mode P3.0 (TCCK), P3.1 (TDCK) clock input select Initial value timer byte 1/60 (decimal) automatically reload value Disable timer Select timer auto-reload operating mode Select external clock source timer Disable timer gate function Enable timer interrupt Timer enable Enable interrupts
T1CON,#35H
MAIN
CALL
other
T,MAIN
TMRC_INT: IRET P3,#10H T1CON,#35H P3.4 toggle Clear timer pending
MSUN
June 1996 5-68
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PROGRAMMING Timer Module Operating Mode
This example shows program timer module operate 8-bit timer/counters (that mode parameters sample program are: Main oscillator frequency 11.0592 (CPU clock 11.0592 MHz) Clock input pulse TCCK (square wave) Timer operates mode 8-bit timer/counters) Timer operates auto-reload mode with interrupt function Program Function Description Timer low-byte count register (TCL) counts interrupts that occur 0.5-second intervals. These interrupts generated external 60-Hz clock input through TCCK pin. high-byte count register (TCH) counts interrupts generated 278-µs intervals. timer interrupt generated count register overflow frequency clock divided Timer serves baud rate generator UART module. baud rate 9600 BPS. Timer does generate interrupt. state P0.0 P0.1 pins toggles each time interrupt service routine starts.
START TIMER INTERRUPT SYSTEM INITIALIZATION; TIMER MODE SETTINGS TIMER INTERRUPT
0E1H TOGGLE PORT P3.0 CLEAR PENDING
TOGGLE PORT P3.1 CLEAR PENDING
MAIN IRET IRET
Figure Timer Module Mode Programming Flowchart
MSUN
5-69
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PROGRAMMING Timer Module Operating Mode (Continued)
START
Disable interrupts System initialization settings P0CON,#11H P3CONL,#00H TCL,#0E1H TCH,#00H TDH,0FAH TDL,#0FAH T1MOD,#27H Select port output mode Select TCCK input mode External 60-Hz clock gives 0.5-second interval value clock divided gives 278-µs value Baud rate 9600 with divided-by-6 clock Timer auto-reload mode (CPU clock Disable gate function Select timer 8-bit timer/counter mode Low-byte clock source external High-byte clock source clock Disable gate function Enable timer interrupts Enable baud rate generator function Timer enable Enable interrupts
T1CON,#3FH
MAIN
CALL
other
T,MAIN
timer interrupt generated timer byte counter (TCL) overflow (0.5-second intervals): TMRC_INT: IRET TCL,#0E1H P0,#01H T1CON,#1FH 0E1H (0.5 seconds) P0.0 toggle Clear pending (bit
timer interrupt generated timer high-byte counter (TCH) overflow. count value range 00H- 0FFH completed resulting 278-µs interrupt interval: TMRD_INT: IRET P0,#02H T1CON,#2FH P0.1 toggle Clear pending (bit
MSUN
June 1996 5-70
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
SERIAL PORT (UART)
OVERVIEW KS88C4116 full-duplex serial port with four programmable operating modes: There synchronous mode three UART (Universal Asynchronous Receiver/Transmitter) modes: Serial with baud rate clock 8-bit UART mode; variable baud rate 9-bit UART mode; clock/32 9-bit UART mode, variable baud rate Serial port receive transmit buffers both accessed through shift register, (E9H). Writing shift register loads transmit buffer; reading shift register accesses physically separate receive buffer. serial port receive-buffered. Using receive data buffer, reception next byte start before previously received byte been read from receive register. however, first byte been read time next byte been completely received, bytes will lost. four operating modes, data transmission starts when instruction uses register destination address. mode reception serial data starts when receive interrupt pending (RIP) SIOPND register cleared receive enable (RE) "1". modes reception starts when incoming start ("0") received receive enable (RE) "1". SERIAL PORT CONTROL REGISTER (SIOCON) control register serial port called SIOCON (EAH). following control functions: Operating mode selection. data location transmit receive operations (TB8, RB8). Multiple processor communications interrupt control. SERIAL PORT INTERRUPT PENDING REGISTER (SIOPND) serial interrupt pending register, SIOPND (EBH, set1, bank contains serial data transmit interrupt pending (TIP) receive interrupt pending (RIP) positions SIOPND.0 SIOPND.1, respectively. mode receive interrupt pending flag, RIP, when receive data been shifted. mode halfway point stop bit's shift time. When acknowledged receive interrupt pending condition, flag must then cleared software. mode transmit interrupt pending flag when transmit data been shifted. mode start stop bit. When acknowledged transmit interrupt pending condition, flag must then cleared software.
MSUN
5-71
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
SERIAL PORT CONTROL REGISTER (SIOCON) EAH, Bank
Operating mode baud rate selection bits (see table below) Multiprocessor communication enable (for modes only): disable; enable Serial data receive enable bit: disable; enable Mode
Transmit interrupt enable bit: disable; enable Receive interrupt enable bit: disable; enable Location data that received mode ("0" "1") Location data transmitted mode ("0" "1")
Description Shift register 8-bit UART 9-bit UART 9-bit UART
Baud Rate clock variable clock variable
NOTES: mode then receive interrupt will activated received data "0". mode then receive interrupt will activated valid stop received. mode should "0". descriptions 8-bit 9-bit UART mode include start stop bits serial data receive transmit.
Figure Serial Port Control Register (SIOCON)
SERIAL PORT INTERRUPT PENDING REGISTER (SIOPND) EBH, Bank
used
NOTES: order clear data transmit receive interrupt pending flag, must write appropriate pending bit. effect. avoid possible program errors, recommend using Load instructions only (except LDB) manipulate SIOPND register.
Serial data transmit interrupt pending flag: pending Pending Serial data receive interrupt pending flag: pending Pending
Figure Serial Port Interrupt Pending Register (SIOPND)
MSUN
June 1996 5-72
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
SAM8 INTERNAL DATA BSEL
SBUF
TIMER CLOCK
BAUD RATE GENERATOR WRITE SBUF
ZERO DETECTOR START SHIFT
CONTROL
CLOCK CLOCK
SEND
SHIFT CLOCK RECEIVE SHIFT SHIFT VALUE SHIFT REGISTER
IRQ2 INTERRUPT
1-TO-0 TRANSITION DETECTOR
CONTROL
START
DETECTOR
SBUF
SAM8 INTERNAL DATA
Figure Serial Port (UART) Function Diagram
MSUN
5-73
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
SERIAL PORT MODE FUNCTION DESCRIPTION mode serial data input output through (pin 20). (pin outputs shift clock. Data transmitted received 8-bit units only. 8-bit value transmitted received) first. baud rate mode equal clock frequency divided six. Mode Transmit Procedure Select mode setting SIOCON bits '00B'.
Write transmission data shift register (E9H) start transmit operation. Mode Receive Procedure Select mode (shift register; clock setting SIOCON bits '00B'. Clear receive interrupt pending (RIP, SIOPND.1) writing "1". serial data receive enable (RE, SIOCON.4) "1". shift clock will output (pin will read data (pin20). Interrupt requests generated SIOCON register "1".
WRITE SHIFT REGISTER (SIO)
SHIFT (DATA OUT) (SHIFT CLOCK)
WRITE SIOPND (Clear RIP) WRITE SIOCON (Set
RECEIVE
SHIFT (DATA
(SHIFT CLOCK)
Figure Timing Diagram Serial Port Mode Operation
MSUN
June 1996 5-74
TRANSMIT
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
SERIAL PORT MODE FUNCTION DESCRIPTION mode bits transmitted (through pin) received (through pin). Each data frame three components: Start ("0") data bits (LSB first) Stop ("1") When receiving, stop written SIOCON register. baud rate mode variable. Mode Transmit Procedure Select baud rate generated timer/counter using timer module control register, T1CON.
baud selection (BSEL, T1CON.7) offers choice normal double baud rate generation UART module. Select mode (8-bit UART) setting SIOCON bits '01B'. Write transmission data shift register (E9H). (The start stop bits will generated automatically hardware.) Mode Receive Procedure Select baud rate generated timer/counter Select mode (Receive Enable) SIOCON register "1". start ("0") condition will start serial data receive operation.
SHIF
STAR
SAMPLE
Figure Timing Diagram Serial Port Mode Operation
MSUN
5-75
June 1996
ECEIVE
TRANSM
WRIT REGIST (SIO)
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
SERIAL PORT MODE FUNCTION DESCRIPTION mode eleven bits transmitted (through pin) received (through pin). Each data frame four components: Start ("0") data bits (LSB first) Programmable data Stop ("1") data transmitted assigned value writing (bit SIOCON register. When receiving, data that received written (SIOCON.2) while stop ignored. baud rate mode programmable either 1/16 1/32 clock frequency.
Mode Transmit Procedure Select mode (9-bit UART) setting SIOCON bits '10B'. Also, select data transmitted writing SIOCON.3 (TB8) "1". Select baud rate setting BSEL T1CON register normal baud double baud rate generation. Write transmission data shift register, (E9H) start transmit operation. Mode Receive Procedure Select baud rate setting clearing BSEL T1CON register. Select mode (Receive Enable) SIOCON register "1". receive operation will start when signal goes level.
WRIT REGIST (SIO) NSMIT
STAR
CLOC
SAMPLE IMES SHIF
Figure Timing Diagram Serial Port Mode Operation
MSUN
June 1996 5-76
EIVE
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
SERIAL PORT MODE FUNCTION DESCRIPTION mode eleven bits transmitted (through pin) received (through pin). Mode identical mode respects except baud rate, which variable. Each data frame four components: Start ("0") data bits (LSB first) Programmable data Stop ("1") Mode Transmit Procedure Select baud rate setting BSEL T1CON register normal baud double baud rate generation, then enable
timer setting T1CON register "1". Select mode operation (9-bit UART) setting SIOCON bits '11B'. Also, select data transmitted writing SIOCON (TB8) "1". Write transmission data shift register, (E9H) start transmit operation. Mode Receive Procedure Select baud rate generated timer/ counter setting clearing BSEL T1CON register. Select mode (Receive Enable) SIOCON register "1". receive operation will start when signal goes level.
SHIF
SAMPL TIMES
Figure Timing Diagram Serial Port Mode Operation
MSUN
5-77
June 1996
EIVE
SMIT
SHIF EGISTER (SIO)
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
BAUD RATE CALCULATIONS Mode Baud Rate Calculation baud rate mode fixed clock frequency, divided Baud rate CPUclock
Baud rate
2BSEL
should disable timer interrupt enable (TDIE, T1CON.3) baud generator applications. timer itself configured either "timer" "counter" operation three operating modes selected. most applications, timer configured "timer" operation 8-bit auto-reload mode (high nibble T1MOD 0010B), where baud rate calculated following formula: Baud rate BSEL
Mode Baud Rate Calculation mode baud rate depends value double baud rate selection bit, BSEL (T1CON.7). BSEL (its default value after reset), mode baud rate 1/32 clock frequency. BSEL= "1", baud rate 1/16 clock frequency. Baud rate BSEL
timer achieve very baud rates, follow these steps: Leave timer interrupt enabled, Configure timer 16-bit timer (high nibble T1MOD 0001B), timer interrupt perform 16-bit software reload.
Modes Baud Rate Calculation When timer/counter used baud rate generator modes baud rate determined timer/counter overflow rate value BSEL (T1CON.7), follows.
Table Commonly Used Baud Rates Generated Timer Baud Rate Mode max. Mode 187.5 Mode Modes 62.5 19.2 11.0592 11.0592 11.0592 11.0592 11.0592 FEE3H Clock BSEL Timer Values Mode Reload Value
NOTE: clock same fOSC.
MSUN
June 1996 5-78
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
SERIAL COMMUNICATION MULTIPROCESSOR CONFIGURATIONS multiprocessor communication feature lets "master" KS88C4116 send multiple-frame serial message "slave" device multipleKS88C4116 configuration. does this without interrupting other slaves that same serial line. This feature used only UART modes most commonly used with mode which runs 250kHz without using timer (Mode also BSEL T1CON register "1", selecting double baud rate.) modes nine data bits received. value written (SIOCON.2). stop follows. program this function that when stop received, serial interrupt will activated only "1". enable this feature, multiprocessor communication enable SIOCON register (MCE). When "1",
serial data frames received which generate interrupt, simply separate address from serial data. Sample Protocol Master/Slave Interaction When master processor wants transmit block data slave device, first sends address byte that identifies target slave. address byte differs from data byte that address byte, data byte, "0". address byte interrupts slaves that each slave then examine received byte being addressed. addressed slave then clears prepares receive incoming data bytes. slaves that were addressed leave their bits continue operating normally while ignoring incoming data bytes. While setting effect mode used mode check validity stop bit.
mode reception, "1", receive interrupt activated until valid stop received. Setup Procedure Multiprocessor Communications following steps provide general guideline configuring multiprocessor communications: KS88C4116 devices (masters slaves) mode Write bits slave devices "1". master's transmission protocol follows: First byte: Address identifying target slave device (9th "1") Next bytes: Data (9th "0") When targeted slave device receives first byte, slaves interrupted, data "1". Each slave compares address byte address; addressed slave then clears bit.
FULL-DUPLEX MULTI-KS88C4116 INTERCONNECT
MASTER KS88C4116
SLAVE KS88C4116
SLAVE KS88C4116
SLAVE KS88C4116
Figure Connection Example Multiprocessor Serial Data Communications
MSUN
5-79
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PROGRAMMING Programming Serial Port Mode Operation
This example shows program KS88C4116 serial port operate synchronous mode (mode program parameters are: clock frequency Device enabled P0.0 (P0.0 level) Device enabled P0.1 (P0.1 level) Program Function Description One-byte data transmitted device one-byte data received from device baud rate clock/6 MHz) selected. other words, (BSEL) timer module control register T1CON "0". Assume following conditions: Transmit data register labeled 'TRANS'. Data that received from device loaded register 'RECEIVE'. subroutine SIO_T_R called every
START
SIO_T_R
SIOINT_R
SYSTEM INITIALIZATION; INITIAL SETTINGS
Enable output port; Select (enable) device Transmit/receive 1-byte data; Delay Disable device
RECEIVE SIO; Disable receive mode; Disable receive interrupt; Disable device Clear pending
MAIN JOB: CALL SIO_T_R
input mode; Select (enable) device Enable receive interrupt; Enable receive mode start
IRET
Figure Flowchart Serial Port Programming (Mode
MSUN
June 1996 5-80
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PROGRAMMING Programming Serial Port Mode Operation (Continued)
START
Disable interrupts System initialization settings P0CON,#00H P0,#03H SIOCON,#02H SIOPND,#03H
port output; devices selected Mode select; enable receive interrupt; receive disable Clear pending Enable interrupts
MAIN
CALL
other
CALL
SIO_T_R
subroutine
T,MAIN
TRANS RECEIVE SIO_T_R
CALL
P0,#0FEH SIO,TRANS WAIT100µs P0,#01H P0,#0FDH SIOCON,#10H
Transmit data buffer Receive data buffer Select (enable) device TRANS data 1-byte output Disable device Select (enable) device Enable receive mode start receive operation 100-µs delay routine
WAIT100 PUSH R3,#32H LOOP DJNZ R3,LOOP receive interrupt service routine: SIOINT_R IRET P0,#02H SIOCON,#0EFH RECEIVE,SIO SIOPND,#02H
Disable device Receive disable Data restore Clear pending
MSUN
5-81
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PROGRAMMING Programming Serial Port Mode Operation
This example shows program KS88C4116 serial port operate 11-bit asynchronous transmit receive mode (mode Assuming main oscillator frequency 11.0592 MHz, program parameters are: multiprocessor communication required Baud rate 9600 (see formula below) mode (11-bit, asynchronous type, used) Timer/counter overflow output used shift clock (timer used) Program Function Description this formula calculate 9600 baud rate (assume clock 11.0592 MHz, T1CON.7 "0", 0FAH): 9600 Baud BSEL (256-TDH)
subroutine SIO_T_R transmits byte time; received data added SR_SUM when receive interrupt occurs.
START
SIO_T_R
SYSTEM INITIALIZATION
Transmit data byte (B_SIO_T)
Timer setting; control settings
CALL
SIOINT_R
CALL SIO_T_R
SR_SUM SR_SUM Clear pending
CALL IRET
Figure Flowchart Serial Port Programming (Mode
MSUN
June 1996 5-82
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
PROGRAMMING Programming Serial Port Mode Operation (Continued)
B_SIO_T SR_SUM
transmit buffer register Total value received data
START
System initialization settings TDL,#0FAH TDH,#0FAH T1MOD,#20H Load auto-reload value Disable timer counter gate function Select clock (CPU clock 11.0592 MHz) Select auto-reload operating mode (mode (Timer used this program) Select normal baud rate Disable timer interrupt Timer enable mode multiprocessing Receive enable; transmit interrupt enabled interrupt disabled Clear pending bits
T1CON,#32H SIOCON,#0D2H
SIOPND,#03H
Enable interrupts
MAIN
CALL
JOB1
CALL CALL
SIO_T JOB2
transmit subroutine
T,MAIN
SIO_T SIOINT_R
SIO,B_SIO_T
Transmit 1-byte data
receive interrupt service routine IRET SR_SUM,SIO SIOPND,#02H receive data SR_SUM Clear receive interrupt pending
MSUN
5-83
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
DATA CAPTURE
OVERVIEW pulse width modulation (PWM) module following components: 16-bit counter 2-bit prescaler 8-bit comparators 8-bit data registers (PWM0, PWM1) control register (PWMCON) counter overflow interrupt (IRQ1, vector B8H) output pins (PWM0, PWM1) 8-bit capture unit included module. capture unit controlled PWMCON register settings following components: 8-bit capture register (PWMCAP) Capture input (P3.6 /CAP, Capture input interrupt (IRQ1, vector BAH) FUNCTION DESCRIPTION counter 16-bit incrementing counter. start counter enable module, (ECTR) PWMCON register "1". counter stopped, retains current count value; when restarted, resumes counting from retained count value. 2-bit prescaler controls clock input frequency counter. Using prescaler settings, divide input clock (non-divided), two, three, four. prescaler output clock frequency counter. counter overflows when reaches FFFFH, then continues counting from zero. counter overflow interrupt enabled, IRQ1 interrupt (vector B8H) generated. interrupt enable PWMCON register (PWMINT). PWM0 data register, PWM0, located FEH, bank PWM1 data register, PWM1, bank address FDH. Both data registers read write addressable. loading specific values into respective data registers, modulate pulse width corresponding output pins, PWM0 PWM1. 8-bit circuits function identically: Each 8-bit data register 8-bit comparator. Each circuit compares unique data register value lower 8-bit value 16-bit counter. level output pins toggles high frequency equal counter clock, divided (28). duty cycle PWM0 PWM1 pins ranges from 99.6%, based corresponding data register values. determine circuit's duty cycle, 8-bit comparator sends output level high when data register value greater than lower 8-bit count value. output level when data register value less than equal lower 8-bit count value. output level PWM0 PWM1 pins remains level first counter clocks. Then, each waveform repeated continuously, same frequency duty cycle, until three events occurs: counter stopped counter clock frequency changed value written data register CONTROL REGISTER (PWMCON) control register module, PWMCON, located register address bank reset clears PWMCON register '00H'.
MSUN
June 1996 5-84
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
CONTROL REGISTER (PWMCON) FCH, Bank
ECTR PWMINT CAPINT TEST CAP1 CAP0
2-bit prescaler counter clock: divide divide divide three divide four
counter enable bit: Stop counter Start (resume) counting counteroverflow interrupt enable bit: Disable interrupt Enable interrupt
Capture function control bits: Disable capture function Capture falling edges Capture rising edges Capture both edges test mode enable bit: (for factory only) Capture interrupt enable bit: Disable capture interrupt Enable capture interrupt
Figure PWM/Capture Module Control Register (PWMCON)
COUNTER VALUE (HEX) COUNTER CLOCK MHz) PWMn PWMn PWMn CYCLE NOTES: counter clock value assumed timing values. PWM0 PWM1.
100H
200H
300H
PWMn
Figure Output Waveform Timing Diagram
MSUN
5-85
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
8-BIT PWM0, PWM1 REGISTERS
WHEN COUNT WHEN COUNT PWM0, PWM1 OUTPUT PINS
8-BIT 8-BIT PWM0, PWM1 COMPARA COMPARATORS
2-BIT PRESCALER
LOWER BITS 16-BIT COUNTER
UPPER BITS 16-BIT COUNTER PWMINT
IRQ1 (B8H)
ECTR
IRQ1 (BAH) CAP0 CAP1 CAPINT
INPUT
CAPTURE REGISTER
Figure PWM/Capture Module Functional Block Diagram
MSUN
June 1996 5-86
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
STAGGERED OUTPUTS PWM0 PWM1 outputs staggered order reduce overall noise level pulse width modulation circuits.
load same value both data registers, match condition (data register value lower 8-bit count value) occurs same clock cycle both circuits. this case, only PWM0 output will toggled
high clock edge following match signal. PWM1 output delayed counter clocks, subsequent clock cycles (see Figure 70).
COUNTER CLOCK
100H
PWM0 PWM1 2-CYCLE DELAY PWM1 MATCH OCCURS; PWM0 TOGGLES HIGH LEVEL
Figure PWM0 PWM1 Output Delay
MSUN
5-87
June 1996
KS88C4116 MICROCONTROLLER
PRODUCT SPECIFICATION
PROGRAMMING Programming Module Sample Specifications
This example shows program 8-bit pulse-width modulation (PWM) module. program parameters are: oscillation frequency main crystal PWM0 data working register PWM1 data working register sample program performs these actions: PWM1 frequency 11.719 R0F.0 "1", then PWM0 PWM0 PWM1 PWM1 Else PWM1 PWM1
PWMCON,#60H PWM0 PWM1
Select bank P.S. '01B' (Select 11.719-kHz frequency) Enable counter (start PWM); disable interrupt Clear PWM0 data register Clear PWM1 data register Select bank
BTJRT AA1:
Select bank AA1,R0F.0 PWM1 t,AA2 PWM0 PWM1 PWM1 PWM1 PWM1 PWM0 PWM0 PWM1 PWM1 PWM1 PWM1
AA2:
MSUN
June 1996 5-88
PRODUCT SPECIFICATION
KS88C4116 MICROCONTROLLER
DATA CAPTURE UNIT 8-bit data capture unit integrated with module. capture unit detects incoming signal edges used measure pulse width incoming signals. capture unit captures upper 8-bit value 16-bit counter when signal edge transition detected pin. captured value then dumped into PWMCAP
register (set bank FFH) where read. manipulating CAP0 CAP1 bits PWMCON register, edge detection rising edges, falling edges, both signal edge types. Signal edges captured also used generate interrupt. (CAPINT) PWMCON register capture interrupt enable bit.
capture interrupt level (IRQ1) KS88C4116 interrupt structure; vector address BAH. Level IRQ1 interrupts: overflow interrupt (vector B8H) capture interrupt (vector BAH). overflow interrupt always higher priority. Usin
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