ISL6334EVAL1Z LGA1366 ISL6612A ISL6622 ISL6596 ISL6620
|
|
|
Top Searches for this datasheet
ISL6334EVAL1Z - ISL6334EVAL1Z
LGA1366 - LGA1366
ISL6612A - ISL6612A
ISL6622 - ISL6622
ISL6596 - ISL6596
ISL6620 - ISL6620
Technical Brief
ISL6334EVAL1Z User Guide
Board Specifications
Intel VR11.1 compliant. 4-Phase, 130W, 400kHz, Load Line 0.8m. Socket: LGA1366, sensing, configured motherboard sensing. Layer Board: Top/Bottom 0.5oz plated, 1.5oz finished; Internal Layer 1oz. Dual footprint Intersil (ISL6612A, ISL6622) drivers (ISL6596/ISL6620) cost efficiency optimization. With minor re-work, board also operate drive high-side MOSFET drive low-side MOSFET. Dual footprint PowerPak DPAK MOSFET cost efficiency optimization.
FIGURE
Enable Switch
switch (SW2) provided EN_VTT signal control. "OFF" position, EN_VTT signal shorted ground ISL6334 disabled. Place "ON" position enable operation.
ISL6334EVAL1Z Board Brief Description
Control Power Supply
There ways provide 5VDC this evaluation board: through power connectors (J21) Banana connectors J0). used control silver power supply.
FIGURE
PGOOD Indicator Test Points
used indicate status VR_RDY (PGOOD) signal. When VR_RDY high, will light); otherwise will once applied.
FIGURE
Input Power Supply External Load Connector
12VDC input power supply connected board through 4-pin connector test points, TPVIN TPGND, provided input voltage measurement. connectors provided external load.
Test points provided VR_RDY, IMON, VR_HOT VR_FAN signals.
FIGURE
FIGURE
July 2010 TB486.0
CAUTION: These devices sensitive electrostatic discharge; follow proper Handling Procedures. 1-888-INTERSIL 1-888-468-3774 Intersil (and design) registered trademark Intersil Americas Inc. Copyright Intersil Americas Inc. 2010. Rights Reserved other trademarks mentioned property their respective owners.
Technical Brief
(Figure
code generated from Demo board (JP9 DEMO) tool (JP9 VTT).
Phase Count Control
R1P, R2P, R3P, RW2, RW3, used phase count, shown Table phase count different than must adjusted accordingly stability correct load line.
TABLE 4-Phase 3-Phase 2-Phase 1-Phase
Dynamic signal generated from LGA1366 external function generator. Static, fixed operation through SW5. Placing switch position, leads circuit operating mode.
NOTE: Don't care.
Available Design Assist Tools
FIGURE Layout Check list. Design Worksheet. VCORE IMON Calculator. Schematic available OrCAD format. Layout available Allegro format.
Contact Intersil's local office field support latest available information.
FIGURE
July 2010 TB486.0
ISL6334EVAL1Z Schematics
VCC5
Controller circuit
VCC5 VCC5
0.1u
VCC12
ISL6334
EN_PWR EN_VTT EN_VTT
100k
PWM1 1.82k ISEN1221 120p PWM2 120p PWM3 1.82k ISEN3CC30 0.15u VCORE3 RCI3
R5+R1=R334; Average OC=100uA IMON Trip 1.12V
VR_RDY GREEN 2N7002
VR_RDY PSI#
TP29 PSI#
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 PSI# VR_RDY RGND VSEN VDIFF COMP/FB
9.31k
RCI1
connection
CC10 0.15u 470n
VCORE1 RSI1
VCORE
PWM1 ISEN1ISEN1+
VR_RDY Csen
RGND VSEN
PWM2 ISEN2ISEN2+
1.82k CC20 0.15u 470n ISEN2VCORE2
RCI2
VCORE RSI2
390pF
R346
PWM3 ISEN3ISEN3+
Technical Brief
12.1k 12pF 150pF RSS2 1.30k R344
PWM4 ISEN4ISEN4+
120p 49.9k
VCORE RSI3
IMON VR_FAN VR_HOT
VR_FAN VR_HOT
470n
49.9k
PWM4 1.82k CC40 0.15u VCORE4 120p 470n RSI4 ISEN4DNP RCI4 VCORE
RFS2 TP15 901k 26.1k IMON ISENSE R345 ISENSE_DN 10.2k 33nF RMON RMOFS ROFS RFS1 100k RSS1
TCOMP
0.1u
6.8k
Placement needs correction
~27ns Time Constant
their traces should close current sensing network.
Expose these traces external layers
Phase Dropping Decoding
RSS1 RSS2 RFS1 RFS2
Number Operating Phases Configuration
4-PHASE 3-PHASE
VSS_SENSE_DIE
Place this close socket
2-PHASE 1-PHASE
DON'T CARE Vishay, NTHS0805N02N6801 Un-couppled Inductor Couppled Inductor Droop (R1+R5) compensation network must adjusted accordingly.
Intersil Corporation
Readington Road Somerville, 08876
Intersil Confidential
Size Date:
Title
ISL6334 Burnside 130W Board
Thursday, December 2007
Sheet
July 2010 TB486.0
FIGURE ISL6334 BURNSIDE 130W BOARD, CONTROLLER CIRCUIT
ISL6334EVAL1Z Schematics
(Continued)
Power Stage
VCC12 VCC5
Follow Intel Burside Layout Guideline Power Stage LGA1366 Socket well Input Line (1080 pre-preg stackup, layers) Dual footprint Expose Output Inductor Copper Dual footprint LFPAK/DPAK High-side (T/B) Low-Side (B/T) Phase1 (Thermistor) Phase3 Phase2 Phase4 Default 12VUG, LDO=LG. Hardware Options: 12VUG5VLG; LDO=UGLG; DRIVER
R1V12 RDL1
RDU1
VCC/PVCC UVCC/NC LVCC/VCC GDV/NC GND/4
BOOT UGATE PHASE LGATE
PHASE1
RGV1
QLT11
R3V12
RDL3
RDU3
VCC/PVCC UVCC/NC LVCC/VCC GND/4 GDV/NC
BOOT UGATE PHASE LGATE
PHASE3
R2V12
RDL2
RDU2
VCC/PVCC UVCC/NC LVCC/VCC GDV/NC GND/4
BOOT UGATE PHASE LGATE
PHASE2
R4V12 RDL4
RDU4
VCC/PVCC UVCC/NC LVCC/VCC GDV/NC
BOOT UGATE PHASE LGATE
0.1u
PHASE4
PWM4 RGV4
0.1u RPH1 VCC12 CO29 QUB1 4.7u 4.7u 4.7u PHASE1 QLT12 RPS1 ISEN1160nH 2SEPC330MW CO30 330u CO31 330u CO32 330u CO33 330u CO34 VCORE ISL6622CR/12CR PWM1
Technical Brief
VCC12 0.1u RPH3
Need footprint bigger hole T-core; Expose output copper Coupled Inductors
4.7u 4.7u 4.7u 680uF
CO35 330u
CO36 330u
CO37 330u
CO38 330u
CO47 330u
ISL6622CR/12CR
QUB3
PHASE3 QLT32 RPS3 ISEN3L3 160nH QLT31
PWM3 RGV3
Rail1 VCC12 ISL6622CR/12CR 0.1u RPH2 QUB2 4.7u 4.7u 4.7u 680uF Rail2 160nH PHASE2 RPS2 QLT22 ISEN2L2 CO19 CO10
CO11
CO12
CO13
CO14
CO15
CO16
CO17
CO18
Rail4 CO20 CO21 CO22 CO23 CO24 CO25 CO26 CO27
PWM2 RGV2
QLT21
Rail3 CO28 RPH4 VCC12 CO39 CO40 CO41
Rail5 CO42 CO43 CO44
Rail4 CO45
Rail4 CO46
V_CORE
ISL6622CR/12CR
QUB4
4.7u
4.7u
4.7u
TP10
TP50
TP100
Place these hoods different positions scope probe ground
RPS4 ISEN4Size Title 160nH
PHASE4
Intersil Corporation
Readington Road Somerville, 08876
QLT41
QLT42
Intersil Confidential
ISL6334 Burnside 130W Board
Wednesday, December 2007
Date:
Sheet
July 2010 TB486.0
FIGURE ISL6334 BURNSIDE 130W BOARD, POWER STAGE
ISL6334EVAL1Z Schematics
(Continued)
Place These FETs Side Intel Burnside Design
VCC12 VCC12
generator, LGA1366 socket input connectors
VCC5 VCC5 ISL43240 VTT_VID0 VTT_VID1 VTT_VID2 VTT_VID3 COM1 COM2 COM3 COM4 VCC5 C107 0.1u TP20 VID0 TP21 VID1 TP22 VID2 TP23 VID3
Increase Resistor Value improve efficiency.
QUT1
QUT3
Intel Request, needed
DEMO
PHASE1 PHASE1 VCC12 PHASE3 VCC12 DIP-8
VID0 VID1 VID2 VID3
PHASE2
PHASE2
QLB21
QLB22
QLB41
QLB42
TP68 U100 AB35
DEMO
R101 VCC5
PWR_OK PS_ON# -12V
DIP-4
100k
+5VSB +12V1A +12V1B
VTTPWRGOOD
R100 EN_VTT VR_RDY RDIEP VSEN VSS_SENSE_DIE
ONLY "ON" code allowed
VTT_VID0 VTT_VID1 VTT_VID2 VTT_VID3 VTT_VID4 VTT_VID5
AL10 AM10 AN10 AR18 LGA1366_SOCKET
VCC_SENSE_DIE
VSS_SENSE_DIE VCORE
RDIEN
RGND VSEN
VTT_VID6 VTT_VID7 ISENSE ISENSE_DN
RLCP RLCN RGND
PSI#
QUT2
QUT4
PHASE4
Place These FETs Bottom Side Intel Burnside Design (Depending Upon Layout, might drop this)
PHASE1 PHASE1 PHASE3 QLB12 PHASE3 QLB31 QLB11 QLB32
VTT_VID4 VTT_VID5 VTT_VID6 VTT_VID7 VCC5
ISL43240 COM1 COM2 COM3 COM4 VCC5 C108 0.1u TP24 VID4 TP25 VID5 TP26 VID6 TP27 VID7
Technical Brief
VID4 VID5 VID6 VID7
Code
PHASE2
PHASE2
PHASE4
PHASE4
TP28 ENABLE
24-Pin Connector +3.3V +3.3VA +3.3VB +3.3VC +5VA +5VB +5VC +5VD GND0 GND1 GND2 GND3 GND4 GND5 GND6 VCC12 Power Connector +12V GND0
EN_VTT C106
TPGND Vin_GND
TPVIN
VCC5
NEED FOOTPRINT
Intersil/VTT Interposer DCLL Measurement
Intersil Corporation
Readington Road Somerville, 08876 Size Title
AR17
AR18 AR17 test points
Intersil Confidential
ISL6334 Burnside 130W Board
Tuesday, January 2008
Date:
Sheet
July 2010 TB486.0
FIGURE ISL6334 BURNSIDE 130W BOARD
ISL6334EVAL1Z Schematics
(Continued)
AM10
AL10
AC33 AC34 AC35 AC36 AC37 AC38
AA33 AA34 AA35 AA36 AA37 AA38 AA39 AA40 AA41
AA10 AA11
AB33 AB34 AB35 AB36 AB37 AB38 AB39 AB40 AB41 AB42 AB43
AB10 AB11
U100-2 1366LGA_6
AM10 AM11 AM12 AM13 AM14 AM15 AM16 AM17 AM18 AM19 AM20 AM21 AM22 AM23 AM24 AM25 AM26 AM27 AM28 AM29 AM30 AM31 AM32 AM33 AM34 AM35 AM36 AM37 AM38 AM39 AM40 AM41 AM42 AM43
AL10 AL11 AL12 AL13 AL14 AL15 AL16 AL17 AL18 AL19 AL20 AL21 AL22 AL23 AL24 AL25 AL26 AL27 AL28 AL29 AL30 AL31 AL32 AL33 AL34 AL35 AL36 AL37 AL38 AL39 AL40 AL41 AL42 AL43
AB35
VID3
VID1 VID0
AV10 AV11 AV12 AV13 AV14 AV15 AV16 AV17 AV18 AV19 AV20 AV21 AV22 AV23 AV24 AV25 AV26 AV27 AV28 AV29 AV30 AV31 AV32 AV33 AV34 AV35 AV36 AV37 AV38 AV39 AV40 AV41 AV42 AV43 AU10 AU11 AU12 AU13 AU14 AU15 AU16 AU17 AU18 AU19 AU20 AU21 AU22 AU23 AU24 AU25 AU26 AU27 AU28 AU29 AU30 AU31 AU32 AU33 AU34 AU35 AU36 AU37 AU38 AU39 AU40 AU41 AU42 AU43
VID7 VID2 VID4 VID6 VID5
AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 AN30 AN31 AN32 AN33 AN34 AN35 AN36 AN37 AN38 AN39 AN40 AN41 AN42 AN43 AP10 AP11 AP12 AP13 AP14 AP15 AP16 AP17 AP18 AP19 AP20 AP21 AP22 AP23 AP24 AP25 AP26 AP27 AP28 AP29 AP30 AP31 AP32 AP33 AP34 AP35 AP36 AP37 AP38 AP39 AP40 AP41 AP42 AP43
U100-3 1366LGA_6 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AK31 AK32 AK33 AK34 AK35 AK36 AK37 AK38 AK39 AK40 AK41 AK42 AK43 AJ10 AJ11 AJ33 AJ34 AJ35 AJ36 AJ37 AJ38 AJ39 AJ40 AJ41 AJ42 AJ43
1366LGA_6 U100-7 AC39 AC40 AC41 AC42 AC43 AC10 AC11 AD33 AD34 AD35 AD36 AD37 AD38 AD39 AD40 AD41 AD42 AD43 AD10 AD11 AE33 AE34 AE35 AE36 AE37 AE38 AE39 AE40 AE41 AE42 AE43 AE10 AE11
VTTPWRGOOD
AN10
ISENSE_DN ISENSE
AW42 AW41 AW40 AW39 AW38 AW37
BA10 BA11 BA12 BA13 BA14 BA15 BA16 BA17 BA18 BA19 BA20
1366LGA_6
VR_READY VSS_SENSE VCC_SENSE VSS_NORTH VCC_NORTH
AT10 AT11 AT12 AT13 AT14 AT15 AT16 AT17 AT18 AT19 AT20 AT21 AT22 AT23 AT24 AT25 AT26 AT27 AT28 AT29 AT30 AT31 AT32 AT33 AT34 AT35 AT36 AT37 AT38 AT39 AT40 AT41 AT42 AT43
BA35 BA36 BA37 BA38 BA39 BA40
AR10 AR11 AR12 AR13 AR14 AR15 AR16 AR17 AR18 AR19 AR20 AR21 AR22 AR23 AR24 AR25 AR26 AR27 AR28 AR29 AR30 AR31 AR32 AR33 AR34 AR35 AR36 AR37 AR38 AR39 AR40 AR41 AR42 AR43
BA24 BA25 BA26 BA27 BA28 BA29 BA30
AW36 AW35 AW34 AW33 AW32 AW31 AW30 AW29 AW28 AW27 AW26 AW25 AW24 AW23 AW22 AW21 AW20 AW19 AW18 AW17 AW16 AW15 AW14 AW13 AW12 AW11 AW10 AY42 AY41 AY40 AY39 AY38 AY37 AY36 AY35 AY34 AY33 AY32 AY31 AY30 AY29 AY28 AY27 AY26 AY25 AY24 AY23 AY22
PROCHOT#
AG10 AG11 AG33 AG34 AG35 AG36 AG37 AG38 AG39 AG40 AG41 AG42 AG43
AH10 AH11 AH33 AH34 AH35 AH36 AH37 AH38 AH39 AH40 AH41 AH42 AH43
AF10 AF11 AF43 AF42 AF41 AF40 AF39 AF38 AF37 AF36 AF35 AF34 AF33
AY19 AY20 AY21
U100-4 1366LGA_6
1366LGA_6
U100-1 AY10 AY11 AY12 AY13 AY14 AY15 AY16 AY17 AY18
Technical Brief
AR17 AR18
U100-5
U100-6 1366LGA_6
Intersil Corporation
July 2010 TB486.0
Size Custom Date:
Title
LGA1366 SOCKET
Sheet
Tuesday, January 2008
FIGURE LGA1366 SOCKET PINOUT
Technical Brief
ISL6334EVAL1Z Board Layout
FIGURE SILKSCREEN
July 2010 TB486.0
Technical Brief
ISL6334EVAL1Z Board Layout (Continued)
FIGURE COMPONENT SIDE
July 2010 TB486.0
Technical Brief
ISL6334EVAL1Z Board Layout (Continued)
FIGURE INTERNAL PLANE
July 2010 TB486.0
Technical Brief
ISL6334EVAL1Z Board Layout (Continued)
FIGURE INTERNAL ETCH
July 2010 TB486.0
Technical Brief
ISL6334EVAL1Z Board Layout (Continued)
FIGURE INTERNAL ETCH
July 2010 TB486.0
Technical Brief
ISL6334EVAL1Z Board Layout (Continued)
FIGURE INTERNAL PLANE
July 2010 TB486.0
Technical Brief
ISL6334EVAL1Z Board Layout (Continued)
FIGURE SOLDER SIDE BOTTOM
July 2010 TB486.0
Technical Brief
ISL6334EVAL1Z Board Layout (Continued)
FIGURE SILKSCREEN BOTTOM
Intersil Corporation reserves right make changes circuit design, software and/or specifications time without notice. Accordingly, reader cautioned verify that Application Note Technical Brief current before proceeding.
information regarding Intersil Corporation products, www.intersil.com
July 2010 TB486.0
Other recent searches
SN74LVT162244A - SN74LVT162244A SN74LVT162244A Datasheet
SN54LVT162244A - SN54LVT162244A SN54LVT162244A Datasheet
SL6320FRL - SL6320FRL SL6320FRL Datasheet
SH7670 - SH7670 SH7670 Datasheet
SCCS038B - SCCS038B SCCS038B Datasheet
PJ-049 - PJ-049 PJ-049 Datasheet
MIC59300 - MIC59300 MIC59300 Datasheet
IDT49FCT5805 - IDT49FCT5805 IDT49FCT5805 Datasheet
ENN7489 - ENN7489 ENN7489 Datasheet
DS52-0002 - DS52-0002 DS52-0002 Datasheet
Privacy Policy | Disclaimer
© 2013 Datasheets.org.uk